Midterm Exam
 Midterm exam March 8
 5pm – 7pm in MK405
 Cover everything from the beginning of class until
“Behavioral Design”
 Close book, close notes
 No makeup exam will be provided
 Midterm review class on March 3
 Today’s class is NOT covered in the midterm exam
ECE 351 Digital Systems Design
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Recap from the first half of course
 Structural VHDL design
 Components to describe combinatorial logic
 Signal assignments
 Behavioral VHDL design
 Processes to describe sequential logic
 System buffer
 Sync/async system design
 State machines to describe time-dependent system
behaviors
 Second half of course
 Applications of these design methodology
 Relevant design issues
ECE 351 Digital Systems Design
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ECE 351
Digital Systems Design
Medium Scale Integrated Circuits - 1
Wei Gao
Spring 2016
3
Integrated Circuit Scaling
 Integrated Circuit Scales
SSI - Small Scale Integrated Circuits
Example
# of Transistors
Individual Gates
10's
MSI - Medium Scale Integrated Circuits MUX, Decoder
100's
LSI - Large Scale Integrated Circuits
RAM, ALU's
1k - 10k
VLSI - Very Large Scale Integrated
Circuits
microprocessors
100k - 1M
ULSI - Ultra Large Scale Integrated
Circuits
Modern
microprocessors
> 1M
SoC - System on Chip
Microcomputers
SoP - System on Package
Different
technology
blending
VLSI: designs that cannot
be done using schematics
or by hand
ECE 351 Digital Systems Design
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Digital Systems within MSI
 Encoders
 Multiplexers/Demultiplexers
 Tri-state buffer
 Comparators
 Adders/Substractors
 Multipliers/Dividers
ECE 351 Digital Systems Design
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Encoder
 An encoder has 2n inputs and n outputs
 It assumes that one and only one input will be
asserted
 Depending on which input is asserted, an output
code will be generated
ex) truth table of binary encoder
Input
0001
0010
0100
1000
Output
00
01
10
11
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Encoder
 An encoder output is a simple OR structure that
looks at the incoming signals
ex)
4-to-2 encoder
I3 I2 I1 I0 Y1 Y0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
Y1 = I3 + I2
Y0 = I3 + I1
ECE 351 Digital Systems Design
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Encoder in VHDL
 Simply enumerate
each of the input case
and the corresponding
output
 8-to-3 binary encoder
modeled with
Behavioral VHDL
entity encoder_8to3_binary is
generic (t_delay : time := 1.0 ns);
port (I
: in STD_LOGIC_VECTOR (7 downto 0);
Y
: out STD_LOGIC_VECTOR (2 downto 0) );
end entity encoder_8to3_binary;
architecture encoder_8to3_binary_arch of encoder_8to3_binary is
begin
ENCODE : process (I)
begin
case (I) is
when "00000001" => Y <= "000";
when "00000010" => Y <= "001";
when "00000100" => Y <= "010";
when "00001000" => Y <= "011";
when "00010000" => Y <= "100";
when "00100000" => Y <= "101";
when "01000000" => Y <= "110";
when "10000000" => Y <= "111";
when others => Y <= "ZZZ";
end case;
end process ENCODE;
end architecture encoder_8to3_binary_arch;
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Priority Encoders
 A generic encoder does not know what to do when
multiple input bits are asserted
 To handle this case, we need to include prioritization
 If a bit with higher priority is asserted, all the other asserted bits
are shadowed
 We decide the list of priority (usually MSB to LSB) where
the truth table can be written as follows:
ex)
4-to-2 encoder
ECE 351 Digital Systems Design
I3 I2 I1 I0 Y1 Y0
1 x x x 1 1
0 1 x x 1 0
0 0 1 x 0 1
0 0 0 1 0 0
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Priority Encoders
 We can then write expressions for an intermediate
stage of priority bits “H” (i.e., Highest Priority):
I3 I2 I1 I0 Y1 Y0
1 x x x 1 1
0 1 x x 1 0
0 0 1 x 0 1
0 0 0 1 0 0
H3 = I3
H2 = I2∙I3’
H1 = I1∙I2’∙I3’
H0 = I0∙I1’∙I2’∙I3’
 The value of “H” only depends on the bit with highest
priority
 The final output stage then becomes:
Y1 = H3 + H2
Y0 = H3 + H1
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Multiplexer
 Gates are combinational logics which generate an
output depending on the current inputs
 What if we wanted to create a “Digital Switch” to
pass along the input signal?
 This type of circuit is called a “Multiplexer”
ex) truth table of Multiplexer
Sel
0
1
Out
A
B
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Implementation of Multiplexer
 We can use the behavior of an AND gate to build this
circuit:
X∙0 = 0
X∙1 = X
“Block Signal”
“Pass Signal”
 We can then use the behavior of an OR gate at the
output state to combine the signals into one output
 A 0 input has no effect
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Demultiplexer
 This is the exact opposite of a MUX
 A single input will be routed to a particular output
pin depending on the Select setting
ex) truth table of Demultiplexer
Sel
0
Y0 Y1
In 0
1
0 In
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Implementation of Demultiplexer
 We can again use the behavior of an AND gate to
“pass” or “block” the input signal
 An AND gate is used for each DEMUX output
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With More Selections
 Multiple bits for the selecting signals
 Combining AND/OR gates with “reverse” encoders
 Ensure that at any time, only one AND gate is “enabled”
I3 I2 I1 I0 Y1 Y0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
1
1
0
1
0
1
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Tri-State Buffers
 Provides either a Pass-Through or High Impedance
Output depending on Enable Line
 High Impedance (Z) allows the circuit to be connected to a
line with multiple circuits sending/receiving
 Using two Tri-State Buffers creates a "Bus
Transceiver"
 This is used for "Multi-Drop" Buses (i.e., many
Drivers/Receivers on the same bus)
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Tri-State Buffers
 Example
ex) truth table of Tri-State Buffer
ENB
0
1
Out
Z
In
ex) truth table of Bus Transceiver
Tx/Rx
0
1
ECE 351 Digital Systems Design
Mode
Receive from Bus (Rx)
Drive Bus (Tx)
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Tri-State Buffers in VHDL
 The High Impedance 'Z' is a resolved value in the
STD_LOGIC data type defined in Package STD_LOGIC
-Z&0=0
-Z&1=1
-Z&L=L
-Z&H=H
TRISTATE: process (In1, ENB)
begin
if (ENB = '1') then
Out1 <= 'Z';
else
Out1 <= In1;
end if;
end process TRISTATE;
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Comparators
 A circuit that compares digital values (i.e., Equal,
Greater Than, Less Than)
 We are considering Digital Comparators (Analog
comparators also exist)
 Typically there will be 3-outputs, of which only one is
asserted
 Whether a bit is EQ, GT, or LT is a Boolean expression
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Comparators
 A 2-Bit Digital Comparator would look like:
AB
0 0
0 1
1 0
1 1
(A=B)
(A>B)
(A<B)
EQ
1
0
0
1
GT
0
0
1
0
LT
0
1
0
0
ECE 351 Digital Systems Design
EQ = (A⊕B)'
GT = A·B'
LT = A'·B
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Non-Iterative Comparators
 “Iterative”: a circuit make up of identical blocks. The
first block performs its operation which produces a
result used in the 2nd block and so on.
 This can be thought of as a "Ripple" effect
 Iterative circuits tend to be slower due to the ripple, but
take less area
 Non-Iterative circuits consist of combinational logic
executing at the same time
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Non-Iterative Comparators
 "Equality“
 Since each bit in a vector must be equal, the outputs of each
bit's compare can be AND'd
 For a 4-bit comparator:
• EQ = (A3⊕B3)' · (A2⊕B2)' · (A1⊕B1)' · (A0⊕B0)‘
 "Greater Than“
 We can start at the MSB (n) and check whether An>Bn.
• If it is, we are done and can ignore the rest of the LSB's.
• If it is NOT, but they are equal, we need to check the next MSB bit
 4-bit comparator:
• GT = (A3·B3') +
Ensuring that (A3⊕B3)' · (A2·B2') +
(A3⊕B3)' · (A2⊕B2)' · (A1·B1') +
the previous
bit was equal (A3⊕B3)' · (A2⊕B2)' · (A1⊕B1)' · (A0·B0')
ECE 351 Digital Systems Design
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Non-Iterative Comparators
 "Less Than“
 Since we assume that if the vectors are either EQ, GT, or LT,
we can create LT using:
• LT = EQ' · GT‘
 Iterative Comparators
 We can build an iterative comparator by passing signals
between identical modules from MSB to LSB
 ex) module for 1-bit comparator
EQout = (A⊕B)' · EQin
 EQout is fed into the EQin port of the next LSB module
ECE 351 Digital Systems Design
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Comparator – Structural Model
begin
-- "Equal" Circuitry
XN0 : xnor2 port map (In1(0), In2(0), Bit_Equal(0));
-- 1st level of XNOR tree
XN1 : xnor2 port map (In1(1), In2(1), Bit_Equal(1));
XN2 : xnor2 port map (In1(2), In2(2), Bit_Equal(2));
XN3 : xnor2 port map (In1(3), In2(3), Bit_Equal(3));
AN0 : and4 port map (Bit_Equal(0), Bit_Equal(1), Bit_Equal(2), Bit_Equal(3), Eq); -- 2nd level of "Equal" Tree
AN1 : and4 port map (Bit_Equal(0), Bit_Equal(1), Bit_Equal(2), Bit_Equal(3), Eq_temp);
-- "Greater Than" Circuitry
IV0 : inv1 port map (In2(0), In2_n(0));
-- creating In2'
IV1 : inv1 port map (In2(1), In2_n(1));
IV2 : inv1 port map (In2(2), In2_n(2));
IV3 : inv1 port map (In2(3), In2_n(3));
AN2 : and2 port map (In1(3), In2_n(3), In1_and_In2_n(3)); -- creating In1 & In2'
AN3 : and2 port map (In1(2), In2_n(2), In1_and_In2_n(2));
AN4 : and2 port map (In1(1), In2_n(1), In1_and_In2_n(1));
AN5 : and2 port map (In1(0), In2_n(0), In1_and_In2_n(0));
AN6 : and2 port map (Bit_Equal(3), In1_and_In2_n(2), Bit_GT(2));
AN7 : and3 port map (Bit_Equal(3), Bit_Equal(2), In1_and_In2_n(1), Bit_GT(1));
AN8 : and4 port map (Bit_Equal(3), Bit_Equal(2), Bit_Equal(1), In1_and_In2_n(0), Bit_GT(0));
OR0 : or4 port map (In1_and_In2_n(3), Bit_GT(2), Bit_GT(1), Bit_GT(0), GT);
OR1 : or4 port map (In1_and_In2_n(3), Bit_GT(2), Bit_GT(1), Bit_GT(0), GT_temp);
-- "Less Than" Circuitry
ND0 : nor2 port map (EQ_temp, GT_temp, LT);
end architecture comparator_4bit_arch;
ECE 351 Digital Systems Design
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Comparator – Behavioral Model
entity comparator_4bit is
port (In1, In2 : in STD_LOGIC_VECTOR (3 downto 0);
EQ, LT, GT : out STD_LOGIC);
end entity comparator_4bit;
architecture comparator_4bit_arch of comparator_4bit is
begin
COMPARE : process (In1, In2)
begin
EQ <= '0'; LT <= '0'; GT <= '0';
-- initialize outputs to '0'
if (In1 = In2) then EQ <= '1'; end if; -- Equal
if (In1 < In2) then LT <= '1'; end if; -- Less Than
if (In1 > In2) then GT <= '1'; end if; -- Greater Than
end process COMPARE;
end architecture comparator_4bit_arch;
ECE 351 Digital Systems Design
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Summary
 Implementing the basic system components of MSI
using VHDL
 Combinatorial logic
 Structural model vs. behavioral model
 Encoder
 Multiplexer / Demultiplexer
 Tri-state buffer
 Comparator
 Iterative vs. non-iterative
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