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APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: 781/329-4700 • Fax: 781/461-3113 • www.analog.com
ADN2892 Evaluation Board
by Dongfeng Zhao
INTRODUCTION
This application note describes the ADN2892 evaluation board. The ADN2892 limiting amplifier works
as a data quantizer, Gigabit Ethernet (GbE), and Fibre
Channel optical receivers. Supporting a signal data
rate from a minimum of 1 Gbps up to maximum of
4.25 Gbps, the ADN2892 has better than 4 mV p-p typical
input sensitivity and works well with input level up to
2 V p-p. The ADN2892 also provides loss of signal (LOS)
and received signal strength indicator (RSSI) features.
This makes the ADN2892 an ideal limiting amplifier for
all SFF-8472-compliant SFP transceivers. In addition,
the ADN2892 has an on-chip selectable low-pass filter
(cutoff frequency is at 1.5 GHz) to filter out the relaxation
oscillation coming out of a cheap CD laser used in a
legacy 1 Gbps Fibre Channel transmitters. The reduced
BW will also improve the optical Rx sensitivity at the
lower data rates, such as 1xFC.
The ADN2892 evaluation board uses standard FR-4
material. Both the input/output differential transmission
line pairs use 50  characteristic impedance. Each pair
keeps the line length from SMA connector to a respective signal pad within a 3 mils difference to preserve
signal integrity.
The evaluation board uses 3.3 V power supply.
Table 1. Switch Functions
Switches
Functions
Default Setting
Options
S1
S2
S3
S4
S5
S6
PD_Cath
RSSI
Squelch
ThrAdj
BW_SEL
LOS_INV
AVDD
10 k + 0.0 F
GND
100 k
GND
GND
NC
NC
AVCC
1 k
AVCC
AVCC
Quick Start Guide
Please refer to Figure 1 for each of the following steps:
1. Set the switch from S1 to S6 to the factory default
setting shown in Figure 1 where the Switch S3 disables the squelch function by connecting to ground.
S1 and S2 set the RSSI function, and S4 sets the LOS
threshold resistor (default setting is 100 k). S5 and
S6 set to ground to disable the BW_SEL and LOS_INV
functions.
2. Apply a 3.3 V power to test points VCC (red) and GND
(black). The test points are located on the right-hand
side of the evaluation board.
3. Connect PIN and NIN (two SMA connectors located at
the bottom of the board) to a PRBS pattern generator
to get a PRBS signal. It is important to use a pair of
matched length, 50  cables.
Figure 1. The Switch Factory Default Settings of the ADN2892 Evaluation Board
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4. Connect OUTP and OUTN (two SMA connectors located
at the top of the board) to an oscilloscope using a pair
of matched length, 50  cables.
to GND. This on-chip circuit eliminates the need of an
external RSSI circuitry to get a SFF-8472-compliant
optical receiver.
5. Apply a PRBS data pattern signal (any data rate from
155 Mbps to 4.25 Gbps) to the ADN2892. A signal with
amplitude >100 mV p-p is a good signal for an initial
test. The ADN2892 will present its output at the OUTP
and OUTN SMA connectors.
To evaluate the ADN2892 RSSI circuit, Switch S1 must
be at the factory default setting position shown in
Figure 1. This setting provides power supply to the
ADN2892 PD_VCC pin and the on-chip RSSI circuitry.
The PD_Cathode pin connects to a PD cathode and
provides a current supply. The yellow test point on the
evaluation board provides the bias voltage to the PD. The
current provided from the PD_Cathode pin is mirrored
to the RSSI_OUT pin.
ADN2892 EVALUATION BOARD OUTLINES
Power Supply
The ADN2892 evaluation board requires a 3.3 V, 10%
nominal power supply. This supply should be brought
to the board through the test points VCC (red) and
GND (black).
Set S2 to the factory default setting position. The voltage
is available at the RSSI_OUT test point. In this configuration, the RSSI_Output current is converted to a voltage
via a 10 k resistor.
PIN/NIN Inputs
The ADN2892 gets a differential or single-ended signal
through the SMA connectors PIN and NIN. When applying
a single-ended signal, one of the differential input SMA
connectors should be terminated with a 50  terminator.
When Switch S2 sets at the upper position, the output
current is available at the RSSI_OUT test point (gray).
Squelch Mode
Driving the squelch input pad to logic high will disable
the limiting amplifier outputs. So, for normal evaluation
operation, Switch S3 should be at the factory default
setting position (Logic 0). Otherwise, set it to the upper
position (Logic 1) to disable the ADN2892 outputs.
With an ac signal coupling, ADN2892 supports not only
CML but also LVDS, LVPECL, and LVCMOS. Ceramic
capacitors C1 and C2 provide the ac-coupling path to
the signal input. To match the 50  transmission line,
the ADN2892 has on-chip 50  termination resistors
internally connected to the ADN2892 input pins.
BW_SEL Mode
Driving the BW_SEL input to logic high will enable the
internal 1.5 GHz low-pass filter. Switch S5 should be left
in the factory default setting position (Logic 0) for normal
operation up to 4.25 Gbps or at the upper position
(Logic 1) to enable the on-chip low-pass filter.
Data Outputs
The OUTP and OUTN outputs are CML outputs. Through
0.1 µF ceramic capacitors, the CML output signal is
ac-coupled to the SMA connector OUTP and OUTN. The
ADN2892 has on-chip 50  termination resistors connected to its CML output pins.
LOS_INV Mode
LOS_INV is an input pin with a 100 k on-chip pull-down
resistor. Switch S6 should be left in the factory default
setting position (Logic 0) for normal LOS operation or
the upper position (Logic 1) to enable the LOS_INV
mode. Set LOS_INV level high or low to change the
interpreter of the LOS function. The function matrix of
LOS_INV input and LOS output are as follows:
Loss of Signal Detector (LOS)
The ADN2892 has an on-chip loss of signal (LOS)
detector. The LOS asserts when the input level drops
below a user-programmed threshold voltage. The
threshold is set by selecting a resistor value between
the THRADJ pin and GND. On the ADN2892 evaluation board, the S4 switch can select resistors between
a 100 k (factory default setting position) or a 1 k
(switched to upper-most position). If an input signal
level drops below the preset threshold, the LOS output
will be Logic 1. LOS test point (green) connects to the
LOS output pin.
Table 2. Function Matrix
Received Signal Strength Indicator (RSSI)
The ADN2892 has an RSSI circuit to indicate a received
optical average power. Biased a photodiode, the
ADN2892 RSSI circuit senses the current supplied to
the photodiode, and outputs a current proportional to
the average amount of the photodiode current with a
1:1 ratio. A resistor placed between the RSSI_OUT to
GND converts the output current to a voltage referenced
LOS_INV
Level
LOS
Level
Function
Low
High
Low
High
Low
Loss of Input Signal
Input Signal Exists
Input Signal Exists
Loss of Input Signal
High
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Output Eye Measurements
Figure 2 shows the ADN2892 differential output with a
jitter-free, 10 mV p-p differential, 4.25 Gbps, 223 -1 PRBS
pattern input signal.
Figure 3 shows the ADN2892 differential output with a
jitter-free, 2 V p-p differential, 2.488 Gbps, 223 -1 PRBS
pattern input signal.
Figure 3. ADN2892 Output with 2 V p-p
Differential Input
Figure 2. ADN2892 Output with 10 mV p-p
Differential Input
BLU TP
NC
S1
C10
0.1�F
GRY TP
0.1�F PIN
C2
0.1�F NIN
AVEE
VCC
C7
0.1�F
R3
100k�
C6
C9
0.1�F 0.1�F
JP2
1k�
+
SQUELCH
CONNECT
EXPOSED
PAD TO
GND
2
3
11
10
4
9
THRADJ
S4
13
12
5
WHT TP
14
C11
0.1�F
C8
C14
10�F 0.01�F
6
7
DRVCC
VCC
OUTP C3
0.1�F
OUTN C4
0.1�F
OUTN
VCC
R1
10k� GRN TP
S5
S6
VCC
VCC
C15
C18
0.01�F 0.01�F
–3–
OUTP
DRVEE
C19
C17
0.01�F 0.01�F
Figure 4. ADN2892 Evaluation Board Schematic
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C12
0.01�F
8
LOS
NIN
C1
15
LOS_INV
PIN
16
R2
10k�
VCC
S3
1
BW_SEL
AVCC
RSSI_OUT
VCC
NC
S2
VIO TP
PD_VCC
C13
470pF
PD_CATHODE
YEL TP
VCC
C16
0.01�F
AN05279–0–5/05(0)
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