APPLICATIONS Cellular base station receivers Transmit observation receivers Radio link downconverters NIC MNLG VPOS MNLE MNOP MNON COMM MNGM FUNCTIONAL BLOCK DIAGRAM RF frequency range of 500 MHz to 1700 MHz IF frequency range of 30 MHz to 450 MHz Power conversion gain: 8.3 dB SSB noise figure of 9.9 dB SSB noise figure with 5 dBm blocker of 23 dB Input IP3 of 25.2 dBm Input P1dB of 10.6 dBm Typical LO drive of 0 dBm Single-ended, 50 Ω RF and LO input ports High isolation SPDT LO input switch Single-supply operation: 3.3 V to 5 V Exposed paddle, 6 mm × 6 mm, 36-lead LFCSP VPOS FEATURES MNIN LOI2 MNCT VGS2 COMM VGS1 VPOS VGS0 COMM LOSW VPOS PWDN COMM VPOS ADL5358 DVCT COMM LOI1 07885-001 NIC DVLG VPOS DVLE DVON DVOP COMM VPOS DVIN DVGM Data Sheet 500 MHz to 1700 MHz, Dual-Balanced Mixer, LO Buffer, IF Amplifier, and RF Balun ADL5358 NOTES 1. NIC = NO INTERNAL CONNECTION. Figure 1. GENERAL DESCRIPTION The ADL5358 uses a highly linear, doubly balanced, passive mixer core along with integrated RF and local oscillator (LO) balancing circuitry to allow single-ended operation. The ADL5358 incorporates the RF baluns, allowing for optimal performance over a 500 MHz to 1700 MHz RF input frequency range. Performance is optimized for RF frequencies from 500 MHz to 1200 MHz using a high-side LO and RF frequencies from 1200 MHz to 1700 MHz using a low-side LO. The balanced passive mixer arrangement provides good LO-to-RF leakage, typically better than −20 dBm, and excellent intermodulation performance. The balanced mixer core also provides extremely high input linearity, allowing the device to be used in demanding cellular applications where in-band blocking signals may otherwise result in the degradation of dynamic performance. A high linearity IF buffer amplifier follows the passive mixer core to yield a typical power conversion gain of 8.3 dB and can be used with a wide range of output impedances. Rev. A The ADL5358 provides two switched LO paths that can be used in TDD applications where it is desirable to ping-pong between two local oscillators. LO current can be externally set using a resistor to minimize dc current commensurate with the desired level of performance. For low voltage applications, the ADL5358 is capable of operation at voltages down to 3.3 V with substantially reduced current. Under low voltage operation, an additional logic pin is provided to power down (<300 µA) the circuit when desired. The ADL5358 is fabricated using a BiCMOS high performance IC process. The device is available in a 6 mm × 6 mm, 36-lead LFCSP and operates over a −40°C to +85°C temperature range. An evaluation board is also available. Table 1. Passive Mixers RF Frequency (MHz) 500 to 1700 1200 to 2500 Single Mixer ADL5367 ADL5365 Single Mixer and IF Amp ADL5357 ADL5355 Dual Mixer and IF Amp ADL5358 ADL5356 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2009–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADL5358 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 3.3 V Performance ...................................................................... 15 Applications ....................................................................................... 1 Spurious Performance ............................................................... 16 General Description ......................................................................... 1 Circuit Description......................................................................... 17 Functional Block Diagram .............................................................. 1 RF Subsystem .............................................................................. 17 Revision History ............................................................................... 2 LO Subsystem ............................................................................. 18 Specifications..................................................................................... 3 Applications Information .............................................................. 19 5 V Performance ........................................................................... 4 Basic Connections ...................................................................... 19 3.3 V Performance ........................................................................ 4 IF Port .......................................................................................... 19 Absolute Maximum Ratings............................................................ 5 Bias Resistor Selection ............................................................... 19 ESD Caution .................................................................................. 5 Mixer VGS Control DAC .......................................................... 19 Pin Configuration and Function Descriptions ............................. 6 Evaluation Board ............................................................................ 21 Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 23 5 V Performance ........................................................................... 7 Ordering Guide .......................................................................... 23 REVISION HISTORY 3/16—Rev. 0 to Rev. A Changes to Figure 1 .......................................................................... 1 Changes to Figure 2 and Table 6 ..................................................... 6 Changes to Figure 52 ...................................................................... 17 Changes to Figure 54 ...................................................................... 21 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 23 11/09—Revision 0: Initial Version Rev. A | Page 2 of 24 Data Sheet ADL5358 SPECIFICATIONS VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, ZO = 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted. Table 2. Parameter RF INPUT INTERFACE Return Loss Input Impedance RF Frequency Range OUTPUT INTERFACE Output Impedance IF Frequency Range DC Bias Voltage 1 LO INTERFACE LO Power Return Loss Input Impedance LO Frequency Range POWER-DOWN (PWDN) INTERFACE 2 PWDN Threshold Logic 0 Level Logic 1 Level PWDN Response Time PWDN Input Bias Current 1 2 Test Conditions/Comments Min Tunable to >20 dB over a limited bandwidth Typ Unit 1700 dB Ω MHz 450 5.5 Ω||pF MHz V 20 50 500 Differential impedance, f = 200 MHz Externally generated Max 230||0.75 30 3.3 −6 5.0 0 13 50 530 +10 1670 1.0 0.4 1.4 Device enabled, IF output to 90% of its final level Device disabled, supply current < 5 mA Device enabled Device disabled Apply supply voltage from external circuit through choke inductors. PWDN function is intended for use with VS ≤ 3.6 V only. Rev. A | Page 3 of 24 160 230 0 70 dBm dB Ω MHz V V V ns ns µA µA ADL5358 Data Sheet 5 V PERFORMANCE VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, VGS0 = VGS1 = VGS2 = 0 V, and ZO = 50 Ω, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE Power Conversion Gain Voltage Conversion Gain SSB Noise Figure SSB Noise Figure Under Blocking Input Third-Order Intercept (IIP3) Input Second-Order Intercept (IIP2) Input 1 dB Compression Point (IP1dB) LO-to-IF Leakage LO-to-RF Leakage RF-to-IF Isolation IF/2 Spurious IF/3 Spurious IF Channel-to-Channel Isolation POWER SUPPLY Positive Supply Voltage Quiescent Current Test Conditions/Comments Min Typ Max Unit Including 4:1 IF port transformer and PCB loss ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω differential 7.6 8.3 14.6 9.9 23 8.6 dB dB dB dB 22 25.2 dBm 57 dBm 10.6 −33 −31 −43 −72 −79 54 dBm dBm dBm dBc dBc dBc dB 5 dBm blocker present ±10 MHz from wanted RF input, LO source filtered fRF1 = 899.5 MHz, fRF2 = 900.5 MHz, fLO = 1103 MHz, each RF tone at −10 dBm fRF1 = 900 MHz, fRF2 = 950 MHz, fLO = 1103 MHz, each RF tone at −10 dBm Unfiltered IF output −10 dBm input power −10 dBm input power 4.75 LO supply IF supply Total Quiescent Current 5 170 180 350 5.25 V mA mA mA 3.3 V PERFORMANCE VS = 3.3 V, IS = 200 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.2 kΩ, R2 = R5 = 400 Ω, VGS0 = VGS1 = VGS2 = 0 V, and ZO = 50 Ω, unless otherwise noted. Table 4. Parameter DYNAMIC PERFORMANCE Power Conversion Gain Voltage Conversion Gain SSB Noise Figure Input Third-Order Intercept (IIP3) Input Second-Order Intercept (IIP2) Input 1 dB Compression Point (IP1dB) POWER INTERFACE Supply Voltage Quiescent Current Total Quiescent Current Test Conditions/Comments Min Including 4:1 IF port transformer and PCB loss ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω differential fRF1 = 899.5 MHz, fRF2 = 900.5 MHz, fLO = 1103 MHz, each RF tone at −10 dBm fRF1 = 950 MHz, fRF2 = 900 MHz, fLO = 1103 MHz, each RF tone at −10 dBm 3.0 Resistor programmable Device disabled Rev. A | Page 4 of 24 Typ Max Unit 8.3 14.6 8.9 19.3 dB dB dB dBm 47.2 dBm 6.75 dBm 3.3 200 300 3.6 V mA µA Data Sheet ADL5358 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Supply Voltage, VS RF Input Level LO Input Level MNOP, MNON, DVOP, DVON Bias VGS2, VGS1, VGS0, LOSW, PWDN Internal Power Dissipation θJA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 60 sec) Rating 5.5 V 20 dBm 13 dBm 6.0 V 5.5 V 2.2 W 22°C/W 150°C −40°C to +85°C −65°C to +150°C 260°C ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 5 of 24 ADL5358 Data Sheet 36 35 34 33 32 31 30 29 28 VPOS MNGM COMM MNON MNOP MNLE VPOS MNLG NIC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 ADL5358 TOP VIEW (Not to Scale) 27 26 25 24 23 22 21 20 19 LOI2 VGS2 VGS1 VGS0 LOSW PWDN VPOS COMM LOI1 NOTES 1. NIC = NO INTERNAL CONNECTION. 2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND. 07885-002 VPOS DVGM COMM DVOP DVON DVLE VPOS DVLG NIC 10 11 12 13 14 15 16 17 18 MNIN MNCT COMM VPOS COMM VPOS COMM DVCT DVIN Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2 3, 5, 7, 12, 20, 34 4, 6, 10, 16, 21, 30, 36 8 9 11 13, 14 Mnemonic MNIN MNCT COMM VPOS Description RF Input for Main Channel. Internally matched to 50 Ω. This pin must be ac-coupled. Center Tap for Main Channel Input Balun. Bypass this pin to ground using low inductance capacitor. Device Common (DC Ground). Positive Supply Voltage. DVCT DVIN DVGM DVOP, DVON 15 17 18, 28 19 22 DVLE DVLG NIC LOI1 PWDN 23 24, 25, 26 27 29 31 32, 33 LOSW VGS0, VGS1, VGS2 LOI2 MNLG MNLE MNOP, MNON 35 0 MNGM EPAD Center Tap for Diversity Channel Input Balun. Bypass to ground using low inductance capacitor. RF Input for Diversity Channel. Internally matched to 50 Ω. This pin must be ac-coupled. Diverstiy Amplifier Bias Setting. Connect a 1.3 kΩ resistor to ground for typical operation. Diversity Channel Differential Open-Collector Outputs. DVOP and DVON should be pulled-up to VCC using external inductors. Diversity Channel IF Return. This pin must be grounded. Diverstiy Channel LO Buffer Bias Setting. Connect a 1 kΩ resistor to ground for typical operation. No Internal Connection. Local Oscillator Input 1. Internally matched to 50 Ω. This pin must be ac-coupled. Connect to Ground for Normal Operation. Connect this pin to 3 V for disable mode when using VPOS < 3.6 V. PWDN pin must be grounded when VPOS > 3.6 V. Local Oscillator Input Selection Switch. Set LOSW high to select LOI1 or set LOSW low to select LOI2. Gate to Source Control Voltages. For typical operation, set VGS0, VGS1, and VGS2 to low logic level. Local Oscillator Input 2. Internally matched to 50 Ω. This pin must be ac-coupled. Main Channel LO Buffer Bias Setting. Connect a 1 kΩ resistor to ground for typical operation. Main Channel IF Return. This pin must be grounded. Main Channel Differential Open-Collector Outputs. MNOP and MNON should be pulled-up to VCC using external inductors. Main Amplifier Bias Setting. Connect a 1.3 kΩ resistor to ground for typical operation. Exposed Pad. The exposed pad must be connected to ground. Rev. A | Page 6 of 24 Data Sheet ADL5358 TYPICAL PERFORMANCE CHARACTERISTICS 5 V PERFORMANCE VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, VGS0 = VGS1 = VGS2 = 0 V, ZO = 50 Ω, unless otherwise noted. 70 400 65 TA = –40°C TA = –40°C 360 INPUT IP2 (dBm) TA = +25°C TA = +85°C 340 320 55 TA = +25°C 750 800 850 900 950 1000 1050 1100 1150 1200 RF FREQUENCY (MHz) 40 700 750 800 850 900 950 1000 1050 1100 1150 1200 RF FREQUENCY (MHz) Figure 6. Input IP2 vs. RF Frequency Figure 3. Supply Current vs. RF Frequency 12 14 11 13 10 INPUT P1dB (dBm) CONVERSION GAIN (dB) TA = +85°C 50 45 07885-003 300 700 60 07885-006 SUPPLY CURRENT (mA) 380 TA = –40°C 9 TA = +25°C 8 TA = +25°C 12 TA = +85°C 11 10 TA = –40°C 7 TA = +85°C 750 800 850 900 950 1000 1050 1100 1150 1200 RF FREQUENCY (MHz) 8 700 07885-004 5 700 750 800 850 900 950 1000 1050 1100 1150 1200 RF FREQUENCY (MHz) 07885-007 9 6 Figure 7. Input P1dB vs. RF Frequency Figure 4. Power Conversion Gain vs. RF Frequency 14 31 13 TA = –40°C SSB NOISE FIGURE (dB) TA = +25°C 25 23 TA = +85°C 21 19 700 TA = +85°C 12 TA = +25°C 11 10 9 TA = –40°C 8 7 750 800 850 900 950 1000 1050 1100 1150 1200 RF FREQUENCY (MHz) 6 700 750 800 850 900 950 1000 1050 1100 1150 1200 RF FREQUENCY (MHz) Figure 8. SSB Noise Figure vs. RF Frequency Figure 5. Input IP3 vs. RF Frequency Rev. A | Page 7 of 24 07885-008 27 07885-005 INPUT IP3 (dBm) 29 ADL5358 Data Sheet VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, VGS0 = VGS1 = VGS2 = 0 V, ZO = 50 Ω, unless otherwise noted. 62 400 61 VPOS = 5.25V 60 59 360 VPOS = 5.0V 340 VPOS = 4.75V INPUT IP2 (dBm) SUPPLY CURRENT (mA) 380 58 VPOS = 5.25V VPOS = 5.0V 57 56 55 320 VPOS = 4.75V 54 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) 52 –40 –30 –20 –10 07885-009 300 –40 –30 –20 –10 30 40 50 60 70 80 70 80 70 80 13 4.75V 5.0V 5.25V 12 INPUT P1dB (dBm) 9.0 8.5 8.0 VPOS = 5.25V VPOS = 5.0V 11 10 VPOS = 4.75V 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) 8 –40 –30 –20 –10 07885-010 7.0 –40 –30 –20 –10 10 20 30 40 50 60 TEMPERATURE (°C) Figure 13. Input P1dB vs. Temperature Figure 10. Power Conversion Gain vs. Temperature 29 12.0 28 11.5 27 0 07885-013 9 7.5 SSB NOISE FIGURE (dB) VPOS = 5.25V 26 25 VPOS = 5.0V 24 VPOS = 4.75V 23 22 11.0 VPOS = 5.25V 10.5 10.0 9.5 VPOS = 4.75V VPOS = 5.0V 9.0 8.5 0 10 20 30 40 50 TEMPERATURE (°C) 60 70 80 8.0 –40 –30 –20 –10 07885-011 21 –40 –30 –20 –10 0 10 20 30 40 50 60 TEMPERATURE (°C) Figure 11. Input IP3 vs. Temperature Figure 14. SSB Noise Figure vs. Temperature Rev. A | Page 8 of 24 07885-014 CONVERSION GAIN (dB) 20 Figure 12. Input IP2 vs. Temperature 10.0 INPUT IP3 (dBm) 10 TEMPERATURE (°C) Figure 9. Supply Current vs. Temperature 9.5 0 07885-012 53 Data Sheet ADL5358 VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, VGS0 = VGS1 = VGS2 = 0 V, ZO = 50 Ω, unless otherwise noted. 400 70 65 TA = –40°C 360 INPUT IP2 (dBm) TA = +25°C 340 60 TA = +25°C TA = –40°C 55 TA = +85°C 50 TA = +85°C 320 30 80 130 180 230 280 330 380 430 IF FREQUENCY (MHz) 40 07885-015 300 30 80 180 230 280 330 380 430 380 430 380 430 IF FREQUENCY (MHz) Figure 15. Supply Current vs. IF Frequency Figure 18. Input IP2 vs. IF Frequency 11 13 TA = –40°C 10 12 TA = +85°C 9 INPUT P1dB (dBm) CONVERSION GAIN (dB) 130 07885-018 45 8 TA = +25°C 7 TA = +85°C 6 11 10 TA = +25°C TA = –40°C 9 8 5 30 80 130 180 230 280 330 380 430 IF FREQUENCY (MHz) 7 07885-016 4 30 80 130 180 230 280 330 IF FREQUENCY (MHz) Figure 16. Power Conversion Gain vs. IF Frequency 07885-019 SUPPLY CURRENT (mA) 380 Figure 19. Input P1dB vs. IF Frequency 30 14 29 13 TA = –40°C 27 TA = +25°C 26 25 24 TA = +85°C 23 22 12 11 10 9 8 20 30 80 130 180 230 280 330 IF FREQUENCY (MHz) 380 430 6 30 80 130 180 230 280 330 IF FREQUENCY (MHz) Figure 17. Input IP3 vs. IF Frequency Figure 20. SSB Noise Figure vs. IF Frequency Rev. A | Page 9 of 24 07885-020 7 21 07885-017 INPUT IP3 (dBm) SSB NOISE FIGURE (dB) 28 ADL5358 Data Sheet VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, VGS0 = VGS1 = VGS2 = 0 V, ZO = 50 Ω, unless otherwise noted. 11.0 12.0 10.5 11.5 TA = +85°C TA = –40°C 9.5 INPUT P1dB (dBm) CONVERSION GAIN (dB) 10.0 9.0 8.5 8.0 TA = +25°C 7.5 10.5 TA = +25°C 10.0 TA = –40°C TA = +85°C 7.0 11.0 9.5 –6 –4 –2 0 2 4 6 8 10 LO POWER (dBm) 9.0 07885-021 6.0 –6 –4 –2 0 2 4 6 8 10 LO POWER (dBm) 07885-024 6.5 Figure 24. Input P1dB vs. LO Power Figure 21. Power Conversion Gain vs. LO Power –60 30 29 –65 28 IF/2 SPURIOUS (dBc) TA = –40°C 26 25 24 TA = +25°C TA = +85°C 23 –70 –75 TA = +25°C –80 TA = +85°C 22 –85 21 TA = –40°C –6 –4 –2 0 2 4 6 8 10 LO POWER (dBm) –90 700 07885-022 20 750 800 850 900 950 1000 1050 1100 1150 1200 RF FREQUENCY (MHz) 07885-025 INPUT IP3 (dBm) 27 Figure 25. IF/2 Spurious vs. RF Frequency Figure 22. Input IP3 vs. LO Power –65 64 –67 62 –69 TA = –40°C IF/3 SPURIOUS (dBc) TA = +25°C 58 56 TA = +85°C 54 –71 TA = +25°C TA = –40°C –73 –75 –77 –79 TA = +85°C –81 52 –6 –4 –2 0 2 4 6 LO POWER (dBm) 8 10 –85 700 750 800 850 900 950 1000 1050 1100 1150 1200 RF FREQUENCY (MHz) Figure 26. IF/3 Spurious vs. RF Frequency Figure 23. Input IP2 vs. LO Power Rev. A | Page 10 of 24 07885-026 –83 50 07885-023 INPUT IP2 (dBm) 60 Data Sheet ADL5358 VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, ZO = 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted. 100 500 12 400 9 300 6 200 3 100 0 60 40 20 7.5 8.0 8.5 9.0 9.5 10.0 CONVERSION GAIN (dB) 0 30 07885-027 0 7.0 130 180 230 280 330 380 430 IF FREQUENCY (MHz) Figure 27. Conversion Gain Distribution Figure 30. IF Output Impedance (R Parallel, C Equivalent) 100 10 MEAN = 25.2 STANDARD DEVIATION = 0.71 12 14 RF RETURN LOSS (dB) 80 PERCENTAGE (%) –3 80 07885-030 RESISTANCE (Ω) PERCENTAGE (%) 80 CAPACITANCE (pF) MEAN = 8.47 STANDARD DEVIATION = 0.66% 60 40 16 18 20 22 24 26 20 18 21 24 27 30 33 INPUT IP3 LO (dBm) 30 700 07885-028 15 750 850 900 950 1000 1050 1100 1150 1200 RF FREQUENCY (MHz) Figure 28. Input IP3 Distribution Figure 31. RF Return Loss, Fixed IF 100 8 MEAN = 10.66 STANDARD DEVIATION = 0.96 9 80 LO RETURN LOSS (dB) 10 60 40 SELECTED 11 12 13 UNSELECTED 14 15 20 0 7 8 9 10 11 INPUT P1dB (dBm) 12 13 Figure 29. Input P1dB Distribution 17 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 LO FREQUENCY (GHz) Figure 32. LO Return Loss, Selected and Unselected Rev. A | Page 11 of 24 07885-032 16 07885-029 PERCENTAGE (%) 800 07885-031 28 0 ADL5358 Data Sheet VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, ZO = 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted. –24 60 55 –26 TA = +25°C TA = +85°C LO-TO-RF LEAKAGE (dBm) LO SWITCH ISOLATION (dB) 65 TA = –40°C 50 –28 TA = –40°C –30 –32 TA = +25°C –34 TA = +85°C 45 750 800 850 900 950 1000 1050 1100 1150 1200 RF FREQUENCY (MHz) –38 900 07885-033 40 700 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 LO FREQUENCY (MHz) Figure 33. LO Switch Isolation vs. RF Frequency 07885-036 –36 Figure 36. LO-to-RF Leakage vs. LO Frequency –20 0 –25 2XLO LEAKAGE (dBm) RF-TO-IF ISOLATION (dB) –5 –30 TA = +85°C –35 TA = +25°C –40 –45 TA = –40°C –50 –10 –15 2XLO-TO-RF –20 –25 –55 800 850 900 950 1000 1050 1100 1150 1200 RF FREQUENCY (MHz) 07885-034 750 –30 900 Figure 34. RF-to-IF Isolation vs. RF Frequency 1000 1050 1100 1150 1200 1250 1300 1350 1400 LO FREQUENCY (MHz) Figure 37. 2XLO Leakage vs. LO Frequency –20 0 –10 –25 3XLO LEAKAGE (dBm) TA = –40°C –30 –35 TA = +25°C –40 TA = +85°C –45 –20 –30 3XLO-TO-RF –40 –50 –60 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 LO FREQUENCY (MHz) Figure 35. LO-to-IF Leakage vs. LO Frequency –70 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 LO FREQUENCY (MHz) Figure 38. 3XLO Leakage vs. LO Frequency Rev. A | Page 12 of 24 07885-038 3XLO-TO-IF –50 900 07885-035 LO-TO-IF LEAKAGE (dBm) 950 07885-037 2XLO-TO-IF –60 700 Data Sheet ADL5358 14 30 8 13 25 7 12 6 11 5 10 3 700 VGS = 000 VGS = 011 VGS = 100 VGS = 110 750 800 SSB NOISE FIGURE (dB) 20 15 10 5 9 850 900 950 8 1000 1050 1100 1150 1200 0 –30 RF FREQUENCY (MHz) 45 12 40 11 35 10 30 9 25 8 20 –20 –15 –10 –5 0 5 10 BLOCKER POWER (dBm) Figure 42. SSB Noise Figure vs. 10 MHz Offset Blocker Level Figure 39. Power Conversion Gain and SSB Noise Figure vs. RF Frequency for Various VGS Settings 13 –25 07885-042 4 SSB NOISE FIGURE (dB) 9 07885-039 CONVERSION GAIN (dB) VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, VGS0 = VGS1 = VGS2 = 0 V, ZO = 50 Ω, unless otherwise noted. 300 280 SUPPLY CURRENT (mA) 15 850 900 950 10 1000 1050 1100 1150 1200 14 28 INPUT IP3 12 24 NOISE FIGURE 10 8 CONVERSION GAIN 6 20 16 12 4 8 4 1000 1100 1200 1300 1400 1500 1600 07885-041 900 LO BIAS RESISTOR VALUE (Ω) Figure 41. Power Conversion Gain, SSB Noise Figure, and Input IP3 vs. LO Bias Resistor Value 700 800 900 1000 1100 1200 1300 1400 1500 1600 BIAS RESISTOR VALUE (Ω) Figure 43. LO and IF Supply Current vs. IF and LO Bias Resistor Value 28 18 CONVERSION GAIN AND SSB NOISE FIGURE (dB) 32 INPUT IP3 (dBm) CONVERSION GAIN AND SSB NOISE FIGURE (dB) 16 800 LO RESISTOR SUPPLY CURRENT 100 600 Figure 40. Input P1dB and Input IP3 vs. RF Frequency for Various VGS Settings 700 160 120 RF FREQUENCY (MHz) 2 600 180 07885-043 800 200 INPUT IP3 16 24 14 20 16 12 NOISE FIGURE 12 10 INPUT IP3 (dBm) 750 220 8 8 CONVERSION GAIN 4 6 4 600 700 800 900 0 1000 1100 1200 1300 1400 1500 1600 IF BIAS RESISTOR VALUE (Ω) Figure 44. Power Conversion Gain, SSB Noise Figure, and Input IP3 vs. IF Bias Resistor Value Rev. A | Page 13 of 24 07885-044 6 700 IF RESISTOR SUPPLY CURRENT 240 140 VGS = 000 VGS = 011 VGS = 100 VGS = 110 07885-040 7 INPUT IP3 (dB) INPUT P1dB (dB) 260 ADL5358 Data Sheet VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, VGS0 = VGS1 = VGS2 = 0 V, ZO = 50 Ω, unless otherwise noted. TA = –40°C 59 TA = +25°C 58 57 TA = +85°C 56 55 54 53 700 750 800 850 900 950 1000 1050 1100 1150 1200 RF FREQUENCY (MHz) 07885-045 IF CHANNEL-TO-CHANNEL ISOLATION (dB) 60 Figure 45. IF Channel-to-Channel Isolation vs. RF Frequency Rev. A | Page 14 of 24 Data Sheet ADL5358 3.3 V PERFORMANCE VS = 3.3 V, IS = 200 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.2 kΩ, R2 = R5 = 400 Ω, VGS0 = VGS1 = VGS2 = 0 V, ZO = 50 Ω, unless otherwise noted. 220 60 215 55 TA = –40°C INPUT IP2 (dBm) 210 205 TA = +25°C 200 750 800 850 900 950 45 TA = +85°C 40 35 TA = +85°C 190 700 1000 1050 1100 1150 1200 RF FREQUENCY (MHz) 30 700 750 800 850 900 950 1000 1050 1100 1150 1200 RF FREQUENCY (MHz) Figure 46. Supply Current vs. RF Frequency at 3.3 V Figure 49. Input IP2 vs. RF Frequency at 3.3 V 11 10 10 9 TA = –40°C 9 TA = +25°C 7 TA = +85°C 6 TA = +25°C 7 6 TA = –40°C 5 750 800 850 900 950 1000 1050 1100 1150 1200 RF FREQUENCY (MHz) 4 700 07885-047 5 700 TA = +85°C 8 750 800 850 900 950 1000 1050 1100 1150 1200 RF FREQUENCY (MHz) Figure 47. Power Conversion Gain vs. RF Frequency at 3.3 V 07885-050 8 INPUT P1dB (dBm) CONVERSION GAIN (dB) TA = +25°C 50 07885-049 195 07885-046 SUPPLY CURRENT (mA) TA = –40°C Figure 50. Input P1dB vs. RF Frequency at 3.3 V 14 26 13 24 12 20 18 TA = +25°C TA = +85°C 16 TA = +85°C 11 TA = +25°C 10 9 8 7 TA = –40°C 6 14 750 800 850 900 950 1000 1050 1100 1150 1200 RF FREQUENCY (MHz) 4 700 750 800 850 900 950 1000 1050 1100 1150 1200 RF FREQUENCY (MHz) Figure 51. SSB Noise Figure vs. RF Frequency at 3.3 V Figure 48. Input IP3 vs. RF Frequency at 3.3 V Rev. A | Page 15 of 24 07885-051 5 12 700 07885-048 INPUT IP3 (dBm) SSB NOISE FIGURE (dB) TA = –40°C 22 ADL5358 Data Sheet SPURIOUS PERFORMANCE All spur tables are (N × fRF) − (M × fLO) and were measured using the standard evaluation board. Mixer spurious products are measured in dBc from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement system = −100 dBm. 5 V Performance VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, VGS0 = VGS1 = VGS2 = 0 V, and ZO = 50 Ω, unless otherwise noted. M 0 0 1 2 3 4 5 6 N 7 8 9 10 11 12 13 14 −52.4 −74.8 <−100 <−100 <−100 <−100 1 −28.0 0.0 −73.1 <−100 <−100 <−100 <−100 <−100 2 −21.5 −70.8 −78.2 <−100 <−100 <−100 <−100 <−100 <−100 <−100 3 −59.0 −42.4 −90.2 −91.1 <−100 <−100 <−100 <−100 <−100 <−100 <−100 4 −44.2 −67.8 −77.6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 5 −71.2 −65.5 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 6 7 8 9 10 11 12 13 14 −86.2 −91.0 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 3.3 V Performance VS = 3.3 V, IS = 200 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.2 kΩ, R2 = R5 = 400 Ω, VGS0 = VGS1 = VG2 = 0 V, and ZO = 50 Ω, unless otherwise noted. M 0 0 1 2 3 4 5 6 N 7 8 9 10 11 12 13 14 1 −33.3 −46.3 0.0 −68.2 −61.5 −99.9 −90.6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 2 −23.7 −64.4 −78.4 −95.2 <−100 <−100 <−100 <−100 <−100 <−100 3 −49.1 −39.4 −81.2 −75.7 <−100 <−100 <−100 <−100 <−100 <−100 <−100 4 −41.3 −71.2 −71.8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 5 −82.9 −73.1 −94.6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 6 7 8 9 10 11 12 13 14 −86.1 −88.8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 Rev. A | Page 16 of 24 Data Sheet ADL5358 CIRCUIT DESCRIPTION The ADL5358 consists of two primary components: the radio frequency (RF) subsystem and the local oscillator (LO) subsystem. The combination of design, process, and packaging technology allows the functions of these subsystems to be integrated into a single die, using mature packaging and interconnection technologies to provide a high performance, low cost design with excellent electrical, mechanical, and thermal properties. In addition, the need for external components is minimized, optimizing cost and size. The RF subsystem consists of integrated, low loss RF baluns, passive MOSFET mixers, sum termination networks, and IF amplifiers. The LO subsystem consists of an SPDT-terminated FET switch and two multistage limiting LO amplifiers. The purpose of the LO subsystem is to provide a large, fixed amplitude balanced signal to drive the mixer independent of the level of the LO input. MNIN LOI2 MNCT VGS2 COMM VGS1 VPOS VGS0 COMM LOSW VPOS PWDN COMM VPOS ADL5358 DVCT COMM LOI1 07885-001 NOTES 1. NIC = NO INTERNAL CONNECTION. NIC DVLG VPOS DVLE DVON DVOP COMM DVGM VPOS DVIN Because the mixer is inherently broadband and bidirectional, it is necessary to properly terminate all the idler (M × N product) frequencies generated by the mixing process. Terminating the mixer avoids the generation of unwanted intermodulation products and reduces the level of unwanted signals at the input of the IF amplifier, where high peak signal levels can compromise the compression and intermodulation performance of the system. This termination is accomplished by the addition of a sum network between the IF amplifier and the mixer and in the feedback elements in the IF amplifier. The IF amplifier is a balanced feedback design that simultaneously provides the desired gain, noise figure, and input impedance that is required to achieve the overall performance. The balanced opencollector output of the IF amplifier, with impedance modified by the feedback within the amplifier, permits the output to be connected directly to a high impedance filter, differential amplifier, or an analog-to-digital input while providing optimum secondorder intermodulation suppression. The differential output impedance of the IF amplifier is approximately 200 Ω. If operation in a 50 Ω system is desired, the output can be transformed to 50 Ω by using a 4:1 transformer. NIC MNLG VPOS MNLE MNOP MNON COMM MNGM VPOS A simplified schematic of the device is shown in Figure 52. The resulting balanced RF signal is applied to a passive mixer that commutates the RF input with the output of the LO subsystem. The passive mixer is essentially a balanced, low loss switch that adds minimum noise to the frequency translation. The only noise contribution from the mixer is due to the resistive loss of the switches, which is in the order of a few ohms. The intermodulation performance of the design is generally limited by the IF amplifier. The IP3 performance can be optimized by adjusting the IF current with an external resistor. Figure 41, Figure 43, and Figure 44 illustrate how various IF and LO bias resistors affect the performance with a 5 V supply. Additionally, dc current can be saved by increasing either or both resistors. It is permissible to reduce the dc supply voltage to as low as 3.3 V, further reducing the dissipated power of the part. No performance enhancement is obtained by reducing the value of these resistors, and excessive dc power dissipation may result. Figure 52. Simplified Schematic RF SUBSYSTEM The single-ended, 50 Ω RF input is internally transformed to a balanced signal using a low loss (<1 dB) unbalanced-to-balanced (balun) transformer. This transformer is made possible by an extremely low loss metal stack, which provides both excellent balance and dc isolation for the RF port. Although the port can be dc connected, it is recommended that a blocking capacitor be used to avoid running excessive dc current through the part. The RF balun can easily support an RF input frequency range of 500 MHz to 1700 MHz. Rev. A | Page 17 of 24 ADL5358 Data Sheet LO SUBSYSTEM The LO amplifier is designed to provide a large signal level to the mixer to obtain optimum intermodulation performance. The resulting amplifier provides extremely high performance centered on an operating frequency of 1100 MHz. The best operation is achieved with either high-side LO injection for RF signals in the 500 MHz to 1200 MHz range or low-side injection for RF signals in the 1200 MHz to 1700 MHz range. Operation outside these ranges is permissible, and conversion gain is extremely wideband, easily spanning 500 MHz to 1700 MHz, but intermodulation is optimal over the aforementioned ranges. The ADL5358 has two LO inputs permitting multiple synthesizers to be rapidly switched with extremely short switching times (<40 ns) for frequency agile applications. The two inputs are applied to a high isolation SPDT switch that provides a constant input impedance, regardless of whether the port is selected, to avoid pulling the LO sources. This multiple section switch also ensures high isolation to the off input, minimizing any leakage from the unwanted LO input that may result in undesired IF responses. The single-ended LO input is converted to a fixed amplitude differential signal using a multistage, limiting LO amplifier. This results in consistent performance over a range of LO input power. Optimum performance is achieved from −6 dBm to +10 dBm, but the circuit continues to function at considerably lower levels of LO input power. The performance of this amplifier is critical in achieving a high intercept passive mixer without degrading the noise floor of the system. This is a critical requirement in an interferer rich environment, such as cellular infrastructure, where blocking interferers can limit mixer performance. The bandwidth of the intermodulation performance is somewhat influenced by the current in the LO amplifier chain. For dc current sensitive applications, it is permissible to reduce the current in the LO amplifier by raising the value of the external bias control resistor. For dc current critical applications, the LO chain can operate with a supply voltage as low as 3.3 V, resulting in substantial dc power savings. In addition, when operating with supply voltages below 3.6 V, the ADL5358 has a power-down mode that permits the dc current to drop to <300 µA. The logic inputs are designed to work with any logic family that provides a Logic 0 input level of less than 0.4 V and a Logic 1 input level that exceeds 1.4 V. All logic inputs are high impedance up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection circuitry permits operation up to 5.5 V, although a small bias current is drawn. Rev. A | Page 18 of 24 Data Sheet ADL5358 APPLICATIONS INFORMATION BASIC CONNECTIONS BIAS RESISTOR SELECTION The ADL5358 mixer is designed to downconvert radio frequencies (RF) primarily between 500 MHz and 1700 MHz to lower intermediate frequencies (IF) between 30 MHz and 450 MHz. Figure 53 depicts the basic connections of the mixer. It is recommended to ac-couple the RF and LO input ports to prevent non-zero dc voltages from damaging the RF balun or LO input circuit. The RFIN matching network consists of a series 8 pF capacitor to provide the optimized RF input return loss for the desired frequency band. The IF bias resistors (R1 and R4) and LO bias resistors (R2 and R5) are used to adjust the bias current of the integrated amplifiers at the IF and LO terminals. It is necessary to have a sufficient amount of current to bias both the internal IF and LO amplifiers to optimize dc current vs. optimum IIP3 performance. Figure 41, Figure 43, and Figure 44 provide the reference for the bias resistor selection when lower power consumption is preferred at the expense of conversion gain and IP3 performance. IF PORT The ADL5358 features three logic control pins, VGS0 (Pin 24), VGS1 (Pin 25), and VGS2 (Pin 26), that allow programmability for internal gate-to-source voltages for optimizing mixer performance over desired frequency bands. The evaluation board defaults VGS0, VGS1, and VGS2 to ground. Power conversion gain, NF, IIP3, and input P1dB can be optimized, as shown in Figure 39 and Figure 40. The mixer differential IF interface requires pull-up choke inductors to bias the open-collector outputs and to set the output match. The shunting impedance of the choke inductors used to couple dc current into the IF amplifier should be selected to provide the desired output return loss. The real part of the output impedance is approximately 200 Ω, as seen in Figure 30, which matches many commonly used SAW filters without the need for a transformer. This results in a voltage conversion gain that is approximately 6 dB higher than the power conversion gain, as shown in Table 3. When a 50 Ω output impedance is needed, use a 4:1 impedance transformer, as shown in Figure 53. MIXER VGS CONTROL DAC Rev. A | Page 19 of 24 ADL5358 Data Sheet R10 MAIN_OUTP MAIN_OUTN C32 C33 T1 C19 C17 C27 C8 C21 L2 L1 R3 C25 VCC R1 C22 C18 VCC R2 VCC 36 35 30 31 32 33 34 28 29 C9 C16 MAIN_IN Z1 1 27 2 26 LO2 Z2 R12 C3 R16 VCC R7 C2 25 3 C34 R13 R8 R14 R17 24 4 R11 R15 VCC 5 23 6 22 R19 21 7 C6 VCC C26 C7 ADL5358 8 C15 20 C11 DIV_IN LO1 19 9 Z3 C14 Z4 11 10 12 16 15 14 13 18 17 VCC VCC + C10 C23 VCC R4 VCC C24 R5 C13 GND L5 R6 C1 L4 C12 C28 C20 C29 T2 DIV_OUTN C30 R9 C31 Figure 53. Typical Application Circuit Rev. A | Page 20 of 24 07885-153 DIV_OUTP Data Sheet ADL5358 EVALUATION BOARD Table 7 describes the various configuration options of the evaluation board. The evaluation board layout is shown in Figure 55 and Figure 56. An evaluation board is available for the family of double balanced mixers. The standard evaluation board schematic is shown in Figure 54. The evaluation board is fabricated using Rogers® RO3003 material. R10 MAIN_OUTP MAIN_OUTN C32 C33 T1 C19 C17 C27 C8 C21 L1 L2 R3 C25 C18 VCC R1 C22 VCC R2 NIC MNLG VPOS MNLE MNOP MNON COMM MNGM VPOS VCC C9 C16 LOI2 MNIN MAIN_IN Z1 LO2 R12 Z2 VGS2 MNCT C3 VCC R7 C2 COMM VPOS VGS1 R13 VGS0 R8 C34 R14 ADL5358 COMM VCC C6 R16 R17 LOSW TOP VIEW (Not to Scale) R11 VPOS PWDN COMM VPOS DVCT COMM R15 C7 VCC C11 LOI1 DVIN DIV_IN R19 C15 LO1 NIC DVLG VPOS DVLE DVON DVOP COMM DVGM Z4 VPOS Z3 C26 C14 VCC + VCC C10 R5 C23 R4 VCC VCC GND C24 L5 R6 C1 C13 L4 C12 C28 C20 C29 T2 DIV_OUTP DIV_OUTN R9 C31 07885-154 C30 NOTES 1. NIC = NO INTERNAL CONNECTION. Figure 54. Evaluation Board Schematic Rev. A | Page 21 of 24 ADL5358 Data Sheet Table 7. Evaluation Board Configuration C14, C16, R15, LOSW R19, PWDN R1, R2, R4, R5, R7, R8, R11 to R14, R16, R17, C34 RF Main and Diversity Input Interface. Main and diversity input channels are ac-coupled through C9 and C11. Z1 to Z4 provide additional component placement for external matching/filter networks. C2, C3, C6, and C7 provide bypassing for the center taps of the main and diversity on-chip input baluns. IF Main and Diversity Output Interface. The open collector IF output interfaces are biased through pull-up choke inductors L1, L2, L4, and L5, with R3 and R6 available for additional supply bypassing. T1 and T2 are 4:1 impedance transformers used to provide a single-ended IF output interface with C27 and C28 providing center-tap bypassing. C17, C19, C20, C29, C30, C31, C32, and C33 ensure an ac-coupled output interface. Remove R9 and R10 for balanced output operation. LO Interface. C14 and C16 provide ac coupling for the LOI1 and LOI2 local oscillator inputs. LOSW selects the appropriate LO input for both mixer cores. R15 provides a pull-down to ensure LOI2 is enabled when the LOSW jumper is removed. Jumper can be removed to allow LOSW interface to be exercised using an external logic generator. PWDN Interface. When the PWDN 2-pin shunt is inserted, the ADL5358 is powered down. When R19 is open, it pulls the PWDN logic low and enables the device. Jumper can be removed to allow PWDN interface to be exercised using an external logic generator. Grounding the PWDN pin is allowed during nominal operation but is not permitted when supply voltages exceed 3.3 V. Bias Control. R16 and R17 form a voltage divider to provide a 3 V for logic control, bypassed to ground through C34. R7, R8, R11, R12, R13, and R14 provide resistor programmability of VGS0, VGS1, and VGS2. Typically, these nodes can be hardwired for nominal operation. Grounding these pins is allowed for nominal operation. R2 and R5 set the bias point for the internal LO buffers. R1 and R4 set the bias point for the internal IF amplifiers. Default Conditions C1, C8, C12, C21 = 150 pF (Size 0402), C10 = 4.7 μF (Size 3216), C13, C15, C18 = 0.1 μF (Size 0402) C22, C23, C24, C25, C26 = 10 pF (Size 0402) Z1, Z3 = open (Size 0402), Z2, Z4 = open (Size 0402), C2, C7 = 10 pF (Size 0402), C3, C6 = 0.01 μF (Size 0402), C9, C11 = 8 pF (Size 0402) T1, T2 = TC4-1T+ (Mini-Circuits), C17, C19, C20, C29 to C33 = 0.001 μF (Size 0402), C27, C28 = 150 pF (Size 0402), L1, L2, L4, L5 = 330 nH (Size 0805), R3, R6, R9, R10 = 0 Ω (Size 0402) C14, C16 = 10 pF (Size 0402), R15 = 10 kΩ (Size 0402), LOSW = 2-pin shunt R19 = 10 kΩ (Size 0402), PWDN = 2-pin shunt R1, R4 = 1.3 kΩ (Size 0402), R2, R5 = 1 kΩ (Size 0402), R7, R8, R11 = 0 Ω (Size 0402), R12, R13, R14 = open (Size 0402), R16 = 10 kΩ (Size 0402), R17 = 15 kΩ (Size 0402), C34 = 1 nF (Size 0402) 07885-057 T1, T2, C17, C19, C20, C27 to C33, L1, L2, L4, L5, R3, R6, R9, R10 Description Power Supply Decoupling. Nominal supply decoupling consists of a 0.01 μF capacitor to ground in parallel with 10 pF capacitors to ground positioned as close to the device as possible. 07885-056 Components C1, C8, C10, C12, C13, C15, C18, C21, C22, C23, C24, C25, C26 Z1 to Z4, C2, C3, C6, C7, C9, C11 Figure 55. Evaluation Board Top Layer Figure 56. Evaluation Board Bottom Layer Rev. A | Page 22 of 24 Data Sheet ADL5358 OUTLINE DIMENSIONS PIN 1 INDICATOR 6.10 6.00 SQ 5.90 36 28 27 1 PIN 1 INDICATOR 0.50 BSC EXPOSED PAD 3.85 3.70 SQ 3.55 19 0.80 0.75 0.70 SEATING PLANE 0.30 0.23 0.18 9 18 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 10 BOTTOM VIEW 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-1. 01-26-2010-A TOP VIEW 0.75 0.60 0.50 Figure 57. 36-Lead Lead Frame Chip Scale Package [LFCSP] 6 mm × 6 mm Body and 0.75 mm Package Height (CP-36-4) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADL5358ACPZ-R7 ADL5358-EVALZ 1 Temperature Range −40°C to +85°C Package Description 36-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS Compliant Part. Rev. A | Page 23 of 24 Package Option CP-36-4 ADL5358 Data Sheet NOTES ©2009–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07885-0-3/16(A) Rev. A | Page 24 of 24