700 MHz to 3000 MHz Dual Passive ADRF6612 Data Sheet
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GND CPOUT REFIN MUXOUT IFOUT+ IFOUT– VCC11 46 45 44 48 47 43 42 39 38 41 40 37 GND LDO3 2 DNC LDO4 FUNCTIONAL BLOCK DIAGRAM GND 1 PLL REF BUFFER PFD/CP FRACTIONAL DIVIDER GND 6 VCO VCO ÷1 TO 32 EXTVCOIN+ 4 EXTVCOIN– 5 16 17 18 19 22 23 VCC10 33 VCC9 32 VCC8 36 RFBCT1 35 RFIN1 31 VCC7 30 LDO2 26 25 RFIN2 RFBCT2 29 VCC6 28 VCC5 27 VCC4 20 21 24 GND 15 VCC3 DNC 14 IFOUT2– Multiband/multistandard cellular base station diversity receivers Wideband radio link diversity downconverters Multimode cellular extenders and picocells 13 SCLK APPLICATIONS SPI CONTROL SDIO DIV 3.3V LDO VCC2 DECL5 12 SPI 2.5V LDO LDO1 DECL4 11 VCO LDO LOOUT– DECL3 10 ADRF6612 PLL 3.3V LDO LOOUT+ DECL1 8 DECL2 9 CS VCC1 7 34 Figure 1. GENERAL DESCRIPTION The ADRF6612 is a dual radio frequency (RF) mixer and intermediate frequency (IF) amplifier with an integrated phaselocked loop (PLL) and voltage controlled oscillators (VCOs). The ADRF6612 uses revolutionary broadband square wave limiting local oscillator (LO) amplifiers to achieve an unprecedented RF bandwidth of 700 MHz to 3000 MHz. Unlike narrow-band sine wave LO amplifier solutions, the LO can be applied above or below the RF input over an extremely wide bandwidth. Energy storage elements are not utilized in the LO amplifier, thus dc current consumption also decreases with decreasing LO frequency. The ADRF6612 utilizes highly linear, doubly balanced passive mixer cores with integrated RF and LO balancing circuits to allow single-ended operation. Integrated RF baluns allow optimal performance over the 700 MHz to 3000 MHz RF input frequency. The balanced passive mixer arrangement provides outstanding LO to RF and LO to IF leakages, excellent RF to IF isolation, and excellent intermodulation performance over the full RF bandwidth. The balanced mixer cores provide extremely high input linearity, allowing the device to be used in demanding Rev. A wideband applications where in band blocking signals may otherwise result in the degradation of dynamic range. Noise performance under blocking is comparable to narrow-band passive mixer designs. High linearity IF buffer amplifiers follow the passive mixer cores, yielding typical power conversion gains of 9 dB, and can be matched to a wide range of output impedances. The PLL architecture supports both integer-N and fractional-N operation and can generate the entire LO frequency range of 200 MHz to 2700 MHz using an external reference input frequency anywhere in the range of 12 MHz to 320 MHz. An external loop filter provides flexibility in trading off phase noise vs. acquisition time. To reduce fractional spurs in fractional-N mode, a sigma-delta (Σ-Δ) modulator controls the post-VCO programmable divider. The VCO consists of multiple VCO cores. All features of the ADRF6612 are controlled via a 3-wire SPI resulting in optimum performance and minimum external components. The ADRF6612 is fabricated using a BiCMOS, high performance IC process. The device is available in a 7 mm × 7 mm, 48-lead LFCSP package and operates over a −40°C to +85°C temperature range. An evaluation board is available. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 12199-001 VCO IFOUT2+ GND 3 MUX RF frequency: 700 MHz to 3000 MHz, continuous LO input frequency: 200 MHz to 2700 MHz, high-side or lowside injection IF range: 40 MHz to 500 MHz Power conversion gain of 9.0 dB Single sideband (SSB) noise figure of 11.3 dB Input IP3 of 30 dBm Input P1dB of 10.6 dBm Typical LO input drive of 0 dBm Single-ended, 50 Ω RF port Single-ended or balanced LO input port Serial port interface (SPI) control on all functions Exposed pad, 7 mm × 7 mm, 48-lead LFCSP VCC12 FEATURES VCOVTUNE Data Sheet 700 MHz to 3000 MHz Dual Passive Receive Mixer with Integrated PLL and VCO ADRF6612 ADRF6612 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Spurious Performance ............................................................... 29 Applications ....................................................................................... 1 Circuit Description......................................................................... 31 Functional Block Diagram .............................................................. 1 RF Subsystem .............................................................................. 31 General Description ......................................................................... 1 External LO Generation ............................................................ 31 Revision History ............................................................................... 2 Internal LO Generation ............................................................. 31 Specifications..................................................................................... 3 Applications Information .............................................................. 35 RF Specifications .......................................................................... 3 Basic Connections Pin Description ............................................. 36 Synthesizer/PLL Specifications ................................................... 4 Mixer Optimization ....................................................................... 37 VCO Specifications, Open-Loop................................................ 7 RF Input Balun Insertion Loss Optimization ......................... 37 Logic Input and Power Specifications ....................................... 8 IIP3 Optimization ...................................................................... 37 Digital Logic Specifications ......................................................... 9 VGS Programming ..................................................................... 38 Absolute Maximum Ratings.......................................................... 10 Low-Pass Filter Programming .................................................. 38 Thermal Resistance .................................................................... 10 Register Summary .......................................................................... 40 ESD Caution ................................................................................ 10 Register Details ............................................................................... 41 Pin Configuration and Function Descriptions ........................... 11 Evaluation Board ............................................................................ 52 Typical Performance Characteristics ........................................... 13 Outline Dimensions ....................................................................... 57 Mixer, High Performance Mode............................................... 13 Ordering Guide .......................................................................... 57 Mixer, High Efficiency Mode.................................................... 22 Synthesizer................................................................................... 23 REVISION HISTORY 5/2016—Rev. 0 to Rev. A Changes to Table 19 ........................................................................ 32 Changes to Address: 0x22, Reset: 0x000A, Name: VCO_CTRL1 Section and Table 34....................................................................... 45 Updated Outline Dimensions ....................................................... 57 Changes to Ordering Guide .......................................................... 57 12/2014—Revision 0: Initial Version Rev. A | Page 2 of 57 Data Sheet ADRF6612 SPECIFICATIONS RF SPECIFICATIONS TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, ZO = 50 Ω, frequency of the reference (fREF) = 122.88 MHz, fREF power = 4 dBm, fPFD = 1.536 MHz, low-side LO injection, optimum RF balun (RFB) and low-pass filter (LPF) settings, unless otherwise noted. Table 1. High Performance Mode Parameter RF INTERFACE Return Loss Input Impedance RF Frequency Range (fRF) IF OUTPUT INTERFACE Output Impedance IF Frequency Range DC Bias Voltage 1 EXTERNAL LO INPUT External LO Power Input Return Loss Input Impedance External VCO Input Frequency LO Frequency Range DYNAMIC PERFORMANCE Power Conversion Gain Voltage Conversion Gain SSB Noise Figure IF Output Phase Noise Under Blocking Input Third-Order Intercept (IIP3) Input Second-Order Intercept (IIP2) Input 1 dB Compression Point (P1dB) LO to IF Output Leakage LO to RF Input Leakage RF to IF Output Isolation IF/2 Spurious IF/3 Spurious POWER INTERFACE VCC12, VCC7, VCC2, VCC1 Supply Voltage Quiescent Current VCC3, VCC4, VCC5, VCC6, VCC8, VCC9, VCC10, VCC11, IFOUT1+, IFOUT1−, IFOUT2+, IFOUT2− Supply Voltage Quiescent Current LO OUTPUT (LOOUT+, LOOUT−) Frequency Range Output Level Output Impedance 1 Test Conditions/Comments Min Tunable to >20 dB broadband via serial port Typ Differential impedance, f = 200 MHz Externally generated 0 −11 50 250 250 4:1 IF port transformer and printed circuit board (PCB) loss removed ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω 10 dBm blocker present 10 MHz above desired RF input, fRF = 1900 MHz, fBLOCK = 1910 MHz, fLO = 1697 MHz, IF = 203 MHz, IFBLOCKER = 213 MHz fRF1 = 1900 MHz, fRF2 = 1901 MHz, fLO = 1697 MHz, each RF tone at −10 dBm fRF1 = 1900 MHz, fRF2 = 1950 MHz, fLO = 1697 MHz, each RF tone at −10 dBm Unfiltered IF output −10 dBm input power −10 dBm input power Rev. A | Page 3 of 57 500 IFOUTx± −5 Supply voltage must be applied from the external circuit through choke inductors. 3000 dB Ω MHz 300||1.5 40 Adjustable via SPI in four steps, in 50 Ω balanced load Balanced Unit 17.9 50 700 External VCO input supports divide by 1, 2, 4, 8, 16, and 32 Low-side or high-side LO, internally or externally generated Max +5 5700 2850 Ω||pF MHz V dBm dB Ω MHz MHz 9.0 dB 15.0 11.3 −153 dB dB dBc/Hz 30 dBm 60 dBm 10.6 −35 −45 −22 −72 −69 dBm dBm dBm dB dBc dBc 3.55 3.7 260 3.85 V mA 3.55 5 214 5.25 V mA 2700 +7 MHz dBm Ω 200 −5 50 ADRF6612 Data Sheet TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, ZO = 50 Ω, fREF = 122.88 MHz, fREF power = 4 dBm, fPFD = 1.536 MHz, low-side LO injection, optimum RFB and LPF settings, unless otherwise noted. Table 2. High Efficiency Mode Parameter DYNAMIC PERFORMANCE Power Conversion Gain Voltage Conversion Gain SSB Noise Figure Input Third-Order Intercept (IIP3) Test Conditions/Comments Min Typ 4:1 IF port transformer and PCB loss removed ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω fRF1 = 1900 MHz, fRF2 = 1901 MHz, fLO = 1697 MHz, each RF tone at −10 dBm fRF1 = 1900 MHz, fRF2 = 1950 MHz, fLO = 1697 MHz, each RF tone at −10 dBm Input Second-Order Intercept (IIP2) Input 1 dB Compression Point (P1dB) LO to IF Output Leakage LO to RF Input Leakage RF to IF Output Isolation IF/2 Spurious IF/3 Spurious POWER INTERFACE VCC12, VCC7, VCC2, VCC1 Supply Voltage Quiescent Current VCC3, VCC4, VCC5, VCC6, VCC8, VCC9, VCC10, VCC11, IFOUT1+, IFOUT1−, IFOUT2+, IFOUT2− Supply Voltage Quiescent Current Unfiltered IF output −10 dBm input power −10 dBm input power Max Unit 8.7 14.7 10.7 20.5 dB dB dB dBm 53 dBm 8.2 −45.0 −52.0 −22.8 −58 −58 dBm dBm dBm dB dBc dBc 3.55 3.7 260 3.85 V mA 3.55 3.7 210 5.25 V mA SYNTHESIZER/PLL SPECIFICATIONS High performance mode, TA = 25°C, measured on LO output, fLO = 1700 MHz, ZO = 50 Ω, fREF =122.88 MHz, fPFD = 1.536 MHz, fREF power = 4 dBm, CSCALE = 8 mA, bleed = 0 µA, ABLDLY = 0.9 ns, integer mode loop filter, unless otherwise noted. Table 3. Integer Mode Parameter SYNTHESIZER SPECIFICATIONS Frequency Range Figure of Merit (FOM) 1 Phase and Frequency Detector (PFD) Frequency (fPFD) Reference Spurs CHARGE PUMP Pump Current Output Compliance Range REFERENCE CHARACTERISTICS REFIN Input Frequency REFIN Input Capacitance Reference Divider Value MUXOUT Output Level MUXOUT Duty Cycle Test Conditions/Comments Synthesizer specifications referenced to 1 × LO Internally generated LO PREFIN = 6.5 dBm Min Typ 200 Max Unit 2700 MHz dBc/Hz/Hz MHz −223 0.8 fPFD = 1.536 MHz 1 × fPFD 4 × fPFD >4 × fPFD 70 −105 −105 −90 Programmable to 250 µA, 500 µA, …, 8 mA 8 0.7 dBc dBc dBc 8.75 2.5 mA V 320 MHz pF REFIN, MUXOUT pins 12 4 Programmable to 0.5, 1, 2, 3, …, 2047 VOL (lock detect output selected) VOH (lock detect output selected) Reference output selected Rev. A | Page 4 of 57 0.5 2047 0.25 2.7 50 V V % Data Sheet Parameter VCO_0 Phase Noise, Locked Integrated Phase Noise VCO_1 Phase Noise, Locked Integrated Phase Noise VCO_2 Phase Noise, Locked Integrated Phase Noise VCO_3 Phase Noise, Locked Integrated Phase Noise 1 ADRF6612 Test Conditions/Comments Min Typ Max Unit fLO = 5.1 GHz 1 kHz offset 50 kHz offset 100 kHz offset 1 MHz offset 10 MHz offset 40 MHz offset 1 kHz to 40 MHz integration bandwidth −87 −94.9 −103.3 −132.9 −154.1 −155.2 0.87 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz °rms fLO = 4.45 GHz 1 kHz offset 50 kHz offset 100 kHz offset 1 MHz offset 10 MHz offset 40 MHz offset 1 kHz to 40 MHz integration bandwidth −90 −98.4 −106.5 −136.1 −154.8 −155.5 0.63 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz °rms fLO = 3.8 GHz 1 kHz offset 50 kHz offset 100 kHz offset 1 MHz offset 10 MHz offset 40 MHz offset 1 kHz to 40 MHz integration bandwidth −90 −98.1 −109.8 −137.1 −155.7 −156.2 0.61 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz °rms fLO = 3.2 GHz 1 kHz offset 50 kHz offset 100 kHz offset 1 MHz offset 10 MHz offset 40 MHz offset 1 kHz to 40 MHz integration bandwidth −89 −97.2 −107 −136.2 −155.7 −157.3 0.64 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz °rms The FOM is computed as phase noise (dBc/Hz) − 10Log10(fPFD) − 20Log10(fLO/fPFD). The FOM was measured across the full LO range, with fREF = 122.88 MHz and fREF power = 6.5 dBm with a 1.536 MHz fPFD. The FOM was computed at 50 kHz offset. Rev. A | Page 5 of 57 ADRF6612 Data Sheet High performance mode, TA = 25°C, measured on LO output, fLO = 1700 MHz, ZO = 50 Ω, fREF =122.88 MHz, fPFD = 30.72 MHz, fREF power = 4 dBm, CSCALE = 250 µA, bleed = 93.75 µA, ABLDLY = 0 ns, fractional mode loop filter, unless otherwise noted. Table 4. Fractional Mode Parameter SYNTHESIZER SPECIFICATIONS FOM 1 REFERENCE CHARACTERISTICS VCO_0 Phase Noise, Locked Integrated Phase Noise VCO_1 Phase Noise, Locked Integrated Phase Noise VCO_2 Phase Noise, Locked Integrated Phase Noise VCO_3 Phase Noise, Locked 1 Test Conditions/Comments Synthesizer specifications referenced to 1 × LO PREFIN = 6.5 dBm REFIN, MUXOUT pins fLO = 2.55 GHz 1 kHz offset 50 kHz offset 100 kHz offset 1 MHz offset 10 MHz offset 40 MHz offset 1 kHz to 40 MHz integration bandwidth Min Typ Max Unit 219 dBc/Hz/Hz −92.5 −97.4 −109.7 −137.6 −153.6 −155.5 0.36 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz °rms fLO = 2.22 GHz 1 kHz offset 50 kHz offset 100 kHz offset 1 MHz offset 10 MHz offset 40 MHz offset 1 kHz to 40 MHz integration bandwidth fLO = 1.9 GHz 1 kHz offset 50 kHz offset 100 kHz offset 1 MHz offset 10 MHz offset 40 MHz offset 1 kHz to 40 MHz integration bandwidth −93.6 −101.8 −112.5 −140.5 −154.3 −155.3 0.32 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz °rms −94.2 −101.7 −112.4 −141.3 −155.8 −156.8 0.32 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz °rms fLO = 1.6 GHz 1 kHz offset 50 kHz offset 100 kHz offset 1 MHz offset 10 MHz offset 40 MHz offset 1 kHz to 40 MHz integration bandwidth −93.1 −99.8 −110.9 −140.2 −155.7 −157.2 0.33 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz °rms The FOM is computed as phase noise (dBc/Hz) − 10Log10(fPFD) − 20Log10(fLO/fPFD). The FOM was measured across the full LO range, with fREF = 122.88 MHz and fREF power = 6.5 dBm with a 30.72 MHz fPFD. The FOM was computed at 45 kHz offset. Rev. A | Page 6 of 57 Data Sheet ADRF6612 VCO SPECIFICATIONS, OPEN-LOOP High performance mode, TA = 25°C, measured on LO output, unless otherwise noted. Table 5. Parameter VCO_0 PHASE NOISE VCO_1 PHASE NOISE VCO_2 PHASE NOISE VCO_3 PHASE NOISE Test Conditions/Comments fVCO = 5.15 GHz 1 kHz offset 50 kHz offset 100 kHz offset 1 MHz offset 10 MHz offset 40 MHz offset fVCO = 4.3 GHz 1 kHz offset 50 kHz offset 100 kHz offset 1 MHz offset 10 MHz offset 40 MHz offset fVCO = 3.8 GHz 1 kHz offset 50 kHz offset 100 kHz offset 1 MHz offset 10 MHz offset 40 MHz offset fVCO = 3.2 GHz 1 kHz offset 50 kHz offset 100 kHz offset 1 MHz offset 10 MHz offset 40 MHz offset Rev. A | Page 7 of 57 Min Typ Max Unit −50 −104.4 −112.6 −137.7 −154 −155.1 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −54 −106.1 −115 −138.9 −155.8 −155.2 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −53.6 −106.6 −114.6 −140.8 −155.4 −156.3 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −48.5 −106 −115.3 −140.2 −157.7 −156.3 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz ADRF6612 Data Sheet LOGIC INPUT AND POWER SPECIFICATIONS TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, ZO = 50 Ω, fREF = 122.88 MHz, fREF power = 4 dBm, fPFD = 1.536 MHz, low-side LO injection, optimum RFB and LPF settings, unless otherwise noted. Table 6. Parameter LOGIC INPUTS Input High Voltage, VIH Input Low Voltage, VIL Input Current, IINH/IINL POWER SUPPLIES High Performance Mode Voltage Range VCC3, VCC4, VCC5, VCC6, VCC8, VCC9, VCC10, VCC11, IFOUT1+, IFOUT1−, IFOUT2+, IFOUT2− VCC12, VCC7, VCC2, VCC1 Power Dissipation High Efficiency Mode Voltage Range VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7, VCC8, VCC9, VCC10, VCC11,VCC12, IFOUT1+, IFOUT1−, IFOUT2+, IFOUT2− Power Dissipation Test Conditions/Comments SCLK, SDIO, CS Min Typ 1.4 0 Max Unit 3.3 0.7 V V µA 0.1 4.75 5 5.25 V 3.55 3.7 5.25 V Internal LO mode (internal PLL) External LO output enabled External LO output disabled 2.7 2.5 3.55 Internal LO mode (internal PLL) External LO output enabled External LO output disabled Rev. A | Page 8 of 57 3.7 2.0 1.8 W W 3.85 V W W Data Sheet ADRF6612 DIGITAL LOGIC SPECIFICATIONS Table 7. Parameter Input Voltage High Input Voltage Low Output Voltage High Output Voltage Low Serial Clock Period Setup Time Between Data and Rising Edge of SCLK Hold Time Between Data and Rising Edge of SCLK Setup Time Between Falling Edge of CS and SCLK Hold Time Between Rising Edge of CS and SCLK Minimum Period for SCLK to Be in a Logic High State Minimum Period for SCLK to Be in a Logic Low State Maximum Delay Between Falling Edge of SCLK and Output Data Valid for a Read Operation Maximum Delay Between CS Deactivation and SDIO Bus Return to High Impedance Test Conditions/Comments Min 1.4 IOH = −100 µA IOL = 100 µA 2.3 Typ Max 5 ns 0.2 38 8 8 10 10 10 10 tH tCLK tACCESS tLOW tDH 231 Units V V V V ns ns ns ns ns ns ns ns 0.70 tZ tHIGH tDS tS Symbol VIH VIL VOH VOL tCLK tDS tDH tS tH tHIGH tLOW tACCESS CS DON'T CARE DON'T CARE tZ SDIO DON'T CARE A6 A5 A4 A3 A2 A1 A0 R/W D15 D14 D13 Figure 2. Setup and Hold Timing Measurements Rev. A | Page 9 of 57 D3 D2 D1 D0 DON'T CARE 12199-002 SCLK ADRF6612 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Parameter Supply Voltage (VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7, VCC8, VCC9, VCC10, VCC11,VCC12, IFOUT1+, IFOUT1−, IFOUT2+, IFOUT2−) Digital Input/Output (SCLK, SDIO, CS) RFINx EXTVCOIN+, EXTVCOIN− Maximum Junction Temperature Operating Temperature Range Storage Temperature Range θJC is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating −0.5 V to +5.5 V Table 9. Thermal Resistance Package Type 48-Lead LFCSP −0.3 V to +3.6 V 20 dBm 13 dBm 150°C −40°C to +85°C −65°C to +150°C ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 10 of 57 θJC 1.62 Unit °C/W Data Sheet ADRF6612 48 47 46 45 44 43 42 41 40 39 38 37 GND CPOUT VCC12 LDO4 LDO3 REFIN MUXOUT VCC11 DNC IFOUT1+ IFOUT1– GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADRF6612 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 RFBCT1 RFIN1 VCC10 VCC9 VCC8 VCC7 LDO2 VCC6 VCC5 VCC4 RFIN2 RFBCT2 NOTES 1. DNC = DO NOT CONNECT. 2. THE EXPOSED PAD MUST BE CONNECTED TO A GROUND PLANE WITH LOW THERMAL IMPEDANCE. 12199-003 LOOUT+ LOOUT– LDO1 VCC2 SDIO SCLK CS VCC3 DNC IFOUT2+ IFOUT2– GND 13 14 15 16 17 18 19 20 21 22 23 24 GND 1 VCOVTUNE 2 GND 3 EXTVCOIN+ 4 EXTVCOIN– 5 GND 6 VCC1 7 DECL1 8 DECL2 9 DECL3 10 DECL4 11 DECL5 12 Figure 3. Pin Configuration Table 10. Pin Function Descriptions Pin No. 1 2 3, 6 4, 5 7 8, 9 10, 11 12 13, 14 15 16 17 18 19 20, 41 21, 40 22, 23 24, 37 25 26 27, 28, 29 30 31 32, 33, 34 35 36 38, 39 42 Mnemonic GND VCOVTUNE GND EXTVCOIN+, EXTVCOIN− VCC1 DECL1, DECL2 DECL3, DECL4 DECL5 LOOUT+, LOOUT− LDO1 VCC2 SDIO SCLK CS VCC3, VCC11 DNC IFOUT2+, IFOUT2− GND, GND RFBCT2 RFIN2 VCC4, VCC5, VCC6 LDO2 VCC7 VCC8, VCC9, VCC10 RFIN1 RFBCT1 IFOUT1−, IFOUT1+ MUXOUT Description Common Ground Connection for External Loop Filter. Control Voltage for Internal VCO. Common Ground for External VCO. Inputs from External VCO to Internal Divider. 3.7 V VCO Supply. LDO Output Decouplers for VCO. External Decouplers for VCO Buffer. External Decoupler for VCO Circuitry. Differential Outputs of Internally Generated LO. External Decoupling for Internal 2.5 V SPI Port LDO. 3.7 V Supply for Programmable SPI Port. Serial Data Input/Output for Programmable SPI Port. Clock for Programmable SPI Port. SPI Chip Select, Asserted Low. 5 V Biases for Channel 1 and Channel 2 IF. Do Not Connect. Do not connect this pin externally. Channel 2 Differential IF Outputs. Ground Connections for Channel 1 and Channel 2 IF Stage. Balun Center Tap Connection for Channel 2 RF Input. Channel 2 RF Input. 5 V Supplies for Mixer LO Amplifiers. External Decoupling for Internal 3.3 V PLL/Divider LDO. 3.7 V Supply for Mixer LO Divider Chain. 5 V Supplies for Mixer LO Amplifiers. Channel 1 RF Input. Balun Center Tap Connection for Channel 1 RF Input. Channel 1 Differential IF Outputs. Internal Multiplexer Output. Rev. A | Page 11 of 57 ADRF6612 Pin No. 43 44 45 46 47 48 Mnemonic REFIN LDO3 LDO4 VCC12 CPOUT GND EPAD Data Sheet Description Reference Input for Internal PLL (Single-Ended, CMOS). External Decoupling for Internal 2.5 V PLL LDO. External Decoupling for Internal 3.3 V PLL LDO. 3.7 V Supply for Internal PLL. Charge Pump Output. Common Ground for External Charge Pump. Exposed Pad. The exposed pad must be connected to a ground plane with low thermal impedance. Rev. A | Page 12 of 57 Data Sheet ADRF6612 TYPICAL PERFORMANCE CHARACTERISTICS MIXER, HIGH PERFORMANCE MODE TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, ZO = 50 Ω, fREF = 122.88 MHz, fREF power = 4 dBm, low-side LO injection, optimum RFB and LPF settings, unless otherwise noted. For integer mode: fPFD = 1.536 MHz, CSCALE = 8 mA, bleed = 0 µA, ABLDLY = 0.9 ns. For fractional mode: fPFD = 30.72 MHz, CSCALE = 250 µA, bleed = 93.75 µA, ABLDLY = 0.0 ns. 2.8 2.4 85 80 75 2.2 2.0 1.8 1.6 70 65 60 55 50 45 1.4 30 700 12199-004 35 1.0 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 RF FREQUENCY (MHz) Figure 4. Power Dissipation vs. RF Frequency over Three Temperatures Figure 7. Input IP2 vs. RF Frequency over Three Temperatures 11.0 15 10.5 10.0 13 INPUT P1dB (dBm) 9.0 8.0 7.5 7.0 6.5 5.5 5.0 4.5 TA TA TA TA TA TA = –40°C, HIGH-SIDE LO = +25°C, HIGH-SIDE LO = +85°C, HIGH-SIDE LO = –40°C, LOW-SIDE LO = +25°C, LOW-SIDE LO = +85°C, LOW-SIDE LO 4.0 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 RF FREQUENCY (MHz) RF FREQUENCY (MHz) Figure 8. Input P1dB vs. RF Frequency over Three Temperatures 18 38 17 36 16 SSB NOISE FIGURE (dB) 34 32 30 28 26 24 22 20 12 TA TA TA TA TA TA = –40°C, HIGH-SIDE LO = +25°C, HIGH-SIDE LO = +85°C, HIGH-SIDE LO = –40°C, LOW-SIDE LO = +25°C, LOW-SIDE LO = +85°C, LOW-SIDE LO 10 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 RF FREQUENCY (MHz) Figure 6. Input IP3 vs. RF Frequency over Three Temperatures –40°C LOCKED –40°C EXTERNAL LO +25°C LOCKED +25°C EXTERNAL LO +85°C LOCKED +85°C EXTERNAL LO 15 14 13 12 11 10 9 8 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 12199-006 14 9 5 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 40 16 11 7 Figure 5. Power Conversion Gain vs. RF Frequency over Three Temperatures, IF Balun and Board Loss Removed 18 TA = –40°C, HIGH-SIDE LO TA = +25°C, HIGH-SIDE LO TA = +85°C, HIGH-SIDE LO TA = –40°C, LOW-SIDE LO TA = +25°C, LOW-SIDE LO TA = +85°C, LOW-SIDE LO 12199-008 6.0 12199-305 CONVERSION GAIN (dB) 9.5 8.5 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 12199-007 40 1.2 RF FREQUENCY (MHz) INPUT IP3 (dBm) TA = –40°C, HIGH-SIDE LO TA = +25°C, HIGH-SIDE LO TA = +85°C, HIGH-SIDE LO TA = –40°C, LOW-SIDE LO TA = +25°C, LOW-SIDE LO TA = +85°C, LOW-SIDE LO RF FREQUENCY (MHz) 12199-109 POWER DISSIPATION (W) 2.6 90 TA = –40°C, HIGH-SIDE LO TA = +25°C, HIGH-SIDE LO TA = +85°C, HIGH-SIDE LO TA = –40°C, LOW-SIDE LO TA = +25°C, LOW-SIDE LO TA = +85°C, LOW-SIDE LO INPUT IP2 (dBm) 3.0 Figure 9. SSB Noise Figure vs. RF Frequency over Three Temperatures Rev. A | Page 13 of 57 ADRF6612 Data Sheet 70 2.7 68 66 64 62 2.1 1.9 1.7 RF RF RF RF RF RF 0 10 20 9.0 40 50 60 70 80 8.0 50 RF RF RF RF RF RF 40 –40 –30 –20 –10 0 10 20 = 900MHz, LOW-SIDE LO = 1900MHz, LOW-SIDE LO = 2500MHz, LOW-SIDE LO = 900MHz, HIGH-SIDE LO = 1900MHz, HIGH-SIDE LO = 2500MHz, HIGH-SIDE LO 30 40 50 60 70 80 TEMPERATURE (°C) Figure 13. Input IP2 vs. Temperature for Three RF Frequencies 15 = 900MHz, LOW-SIDE LO = 1900MHz, LOW-SIDE LO = 2500MHz, LOW-SIDE LO = 900MHz, HIGH-SIDE LO = 1900MHz, HIGH-SIDE LO = 2500MHz, HIGH-SIDE LO 14 13 INPUT P1dB (dBm) CONVERSION GAIN (dB) 8.5 52 42 30 RF RF RF RF RF RF 54 44 Figure 10. Power Dissipation vs. Temperature for Three RF Frequencies 9.5 56 46 TEMPERATURE (°C) 10.0 58 48 = 900MHz, LOW-SIDE LO = 1900MHz, LOW-SIDE LO = 2500MHz, LOW-SIDE LO = 900MHz, HIGH-SIDE LO = 1900MHz, HIGH-SIDE LO = 2500MHz, HIGH-SIDE LO 1.5 –40 –30 –20 –10 60 12199-013 INPUT IP2 (dBm) 2.3 12199-010 POWER DISSIPATION (W) 2.5 7.5 7.0 6.5 6.0 5.5 RF RF RF RF RF RF = 900MHz, LOW-SIDE LO = 1900MHz, LOW-SIDE LO = 2700MHz, LOW-SIDE LO = 900MHz, HIGH-SIDE LO = 1900MHz, HIGH-SIDE LO = 2700MHz, HIGH-SIDE LO 12 11 10 9 5.0 8 4.5 7 4.0 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) 5 –40 –30 –20 –10 12199-011 3.0 –40 –30 –20 –10 18 34 17 33 32 SSB NOISE FIGURE (dB) 29 28 27 26 25 40 50 60 70 80 RF = 900MHz RF = 1900MHz RF = 2500MHz = 900MHz, LOW-SIDE LO = 1900MHz, LOW-SIDE LO = 2500MHz, LOW-SIDE LO = 900MHz, HIGH-SIDE LO = 1900MHz, HIGH-SIDE LO = 2500MHz, HIGH-SIDE LO 20 –40 –30 –20 –10 0 10 20 15 14 13 12 11 10 9 30 40 50 60 70 80 TEMPERATURE (°C) Figure 12. Input IP3 vs. Temperature for Three RF Frequencies 8 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 12199-115 RF RF RF RF RF RF 12199-012 INPUT IP3 (dBm) 30 21 30 16 31 22 20 Figure 14. Input P1dB vs. Temperature for Three RF Frequencies 35 23 10 TEMPERATURE (°C) Figure 11. Power Conversion Gain vs. Temperature for Three RF Frequencies 24 0 12199-314 6 3.5 Figure 15. SSB Noise Figure vs. Temperature for Three RF Frequencies Rev. A | Page 14 of 57 ADRF6612 2.55 85 2.50 80 75 RF = 2500MHz, HIGH-SIDE LO RF = 2500MHz, LOW-SIDE LO 2.45 70 2.40 RF = 1900MHz, HIGH-SIDE LO RF = 1900MHz, LOW-SIDE LO 2.30 2.25 50 RF RF RF RF RF RF 35 30 12199-016 120 160 200 240 280 320 360 400 440 480 80 IF FREQUENCY (MHz) 10.0 RF RF RF RF RF RF 9.5 9.0 8.5 15 900MHz, LOW-SIDE LO 1900MHz, LOW-SIDE LO 2500MHz, LOW-SIDE LO 900MHz, HIGH-SIDE LO 1900MHz, HIGH-SIDE LO 2500MHz, HIGH-SIDE LO 14 13 7.5 7.0 6.5 6.0 5.5 80 120 160 200 240 280 320 360 400 440 480 Figure 19. Input IP2 vs. IF Frequency for Three RF Frequencies INPUT P1dB (dBm) 8.0 = = = = = = 40 = 900MHz, LOW-SIDE LO = 1900MHz, LOW-SIDE LO = 2500MHz, LOW-SIDE LO = 900MHz, HIGH-SIDE LO = 1900MHz, HIGH-SIDE LO = 2500MHz, HIGH-SIDE LO IF FREQUENCY (MHz) Figure 16. Power Dissipation vs. IF Frequency for Three RF Frequencies CONVERSION GAIN (dB) 55 40 2.15 2.10 40 60 45 RF = 900MHz, HIGH-SIDE LO RF = 900MHz, LOW-SIDE LO 2.20 65 12199-019 2.35 INPUT IP2 (dBm) POWER DISSIPATION (W) Data Sheet RF RF RF RF RF RF = 900MHz, LOW-SIDE LO = 1900MHz, LOW-SIDE LO = 2500MHz, LOW-SIDE LO = 900MHz, HIGH-SIDE LO = 1900MHz, HIGH-SIDE LO = 2500MHz, HIGH-SIDE LO 12 11 10 9 5.0 8 4.5 7 4.0 120 160 200 240 280 320 360 400 440 480 IF FREQUENCY (MHz) 5 40 12199-017 Figure 20. Input P1dB vs. IF Frequency for Three RF Frequencies 18 36 34 17 32 16 SSB NOISE FIGURE (dB) 26 24 22 20 18 16 14 12 10 40 RF RF RF RF RF RF 80 = = = = = = 900MHz, LOW-SIDE LO 1900MHz, LOW-SIDE LO 2500MHz, LOW-SIDE LO 900MHz, HIGH-SIDE LO 1900MHz, HIGH-SIDE LO 2500MHz, HIGH-SIDE LO 120 160 200 240 280 –40°C, LOW SIDE LO +25°C, LOW SIDE LO +85°C, LOW SIDE LO –40°C, HIGH-SIDE LO +25°C, HIGH-SIDE LO +85°C, HIGH-SIDE LO 15 14 13 12 11 10 9 320 360 400 440 480 IF FREQUENCY (MHz) Figure 18. Input IP3 vs. IF Frequency for Three RF Frequencies 8 50 12199-018 INPUT IP3 (dBm) 28 120 160 200 240 280 320 360 400 440 480 IF FREQUENCY (MHz) Figure 17. Power Conversion Gain vs. IF Frequency for Three RF Frequencies 30 80 100 150 200 250 300 IF FREQUENCY (MHz) 350 400 450 12199-121 80 12199-020 6 3.5 3.0 40 Figure 21. SSB Noise Figure vs. IF Frequency for Three RF Frequencies Rev. A | Page 15 of 57 Data Sheet –8 –24 –28 –32 –36 –40 LO FREQUENCY (MHz) 12199-025 300 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 TA = –40°C TA = +25°C TA = +85°C 300 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 LO FREQUENCY (MHz) Figure 26. LO to RF Leakage vs. LO Frequency over Three Temperatures 12199–024 2 × LO LEAKAGE (dBm) Figure 23. IF/3 Spurious vs. RF Frequency over Three Temperatures 0 –4 –8 –12 –16 –20 –24 –28 –32 –36 –40 –44 –48 –52 –56 –60 –64 –68 12199-026 LO TO RF LEAKAGE (dBm) Figure 25. LO to IF Leakage vs. LO Frequency over Three Temperatures 12199-123 IF/3 SPURIOUS (dB) –20 –52 RF FREQUENCY (MHz) RF TO IF ISOLATION (dBc) –16 –48 –50 TA = –40°C, HIGH-SIDE LO –52 TA = +25°C, HIGH-SIDE LO –54 TA = +85°C, HIGH-SIDE LO –56 TA = –40°C, LOW-SIDE LO –58 TA = +25°C, LOW-SIDE LO –60 TA = +85°C, LOW-SIDE LO –62 –64 –66 –68 –70 –72 –74 –76 –78 –80 –82 –84 –86 –88 –90 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 RF FREQUENCY (MHz) –12 –44 Figure 22. IF/2 Spurious vs. RF Frequency over Three Temperatures 0 TA = –40°C, HIGH-SIDE LO –2 TA = +25°C, HIGH-SIDE LO –4 TA = +85°C, HIGH-SIDE LO –6 –8 TA = –40°C, LOW-SIDE LO –10 TA = +25°C, LOW-SIDE LO –12 TA = +85°C, LOW-SIDE LO –14 –16 –18 –20 –22 –24 –26 –28 –30 –32 –34 –36 –38 –40 –42 –44 –46 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 TA = –40°C TA = +25°C TA = +85°C 0 –4 –8 –12 –16 –20 –24 –28 –32 –36 –40 –44 –48 –52 –56 –60 –64 TA = –40°C TA = +25°C TA = +85°C 2 × LO TO RF 2 × LO TO IF 300 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 LO FREQUENCY (MHz) Figure 24. RF to IF Isolation vs. RF Frequency over Three Temperatures 12199-027 RF FREQUENCY (MHz) 0 –4 LO TO IF LEAKAGE (dBm) –50 TA = –40°C, HIGH-SIDE LO –52 TA = +25°C, HIGH-SIDE LO –54 TA = +85°C, HIGH-SIDE LO –56 TA = –40°C, LOW-SIDE LO –58 TA = +25°C, LOW-SIDE LO –60 TA = +85°C, LOW-SIDE LO –62 –64 –66 –68 –70 –72 –74 –76 –78 –80 –82 –84 –86 –88 –90 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 12199-022 IF/2 SPURIOUS (dB) ADRF6612 Figure 27. 2 × LO Leakage vs. LO Frequency (2 × LO to RF and 2 × LO to IF) Rev. A | Page 16 of 57 0 –4 –8 –12 –16 –20 –24 –28 –32 –36 –40 –44 –48 –52 –56 –60 –64 ADRF6612 100 TA = –40°C TA = +25°C TA = +85°C MEAN: 7.94 SD: 0.07% PERCENT (%) 80 3 × LO TO RF 60 40 3 × LO TO IF 300 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 LO FREQUENCY (MHz) 0 7.70 7.75 7.80 7.85 7.90 7.95 8.00 8.05 8.10 34 35 CONVERSION GAIN (dB) Figure 28. 3 × LO Leakage vs. LO Frequency (3 × LO to RF and 3 × LO to IF) 12199-131 20 12199-028 3 × LO LEAKAGE (dBm) Data Sheet Figure 31. Conversion Gain Distribution 100 0 HIGH-SIDE LO LOW-SIDE LO MEAN: 31.23 SD: 0.34% –5 PERCENT (%) RETURN LOSS (dBm) 80 –10 –15 –20 60 40 –25 20 1000 2000 1500 2500 RF FREQUENCY (MHz) 3000 0 27 12199-129 –35 500 28 30 31 32 33 INPUT IP3 (dBm) Figure 29. RF Port Return Loss, Fixed IF LO Return Loss Figure 32. Input IP3 Distribution 100 0 –5 MEAN: 10.59 SD: 0.39% 80 PERCENT (%) –10 –15 60 40 –20 –30 100 600 1100 1600 2100 FREQUENCY (MHz) 2600 Figure 30. LO Return Loss 0 10.0 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 INPUT P1dB (dBm) Figure 33. Input P1dB Distribution Rev. A | Page 17 of 57 10.9 11.0 12199-133 20 –25 12199-130 RETURN LOSS (dB) 29 12199-132 –30 ADRF6612 Data Sheet 80 8 900 6 700 600 500 4 CIN1 (pF) 400 300 2 200 100 0 50 100 150 200 250 300 350 400 450 0 500 65 60 55 50 45 40 35 30 25 20 700 12199-334 0 70 FREQUENCY (MHz) Figure 37. IF Channel-to-Channel Isolation vs. RF Frequency over Three Temperatures 10 9 INPUT IP3 (dBm) 7 6 5 4 2 1 =0 =2 =4 =6 =8 = 10 = 12 = 14 0 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 RF FREQUENCY (MHz) 12199-035 CONVERSION GAIN (dB) 8 BAL_COUT BAL_COUT BAL_COUT BAL_COUT BAL_COUT BAL_COUT BAL_COUT BAL_COUT 40 39 38 37 36 35 34 33 32 31 30 29 28 27 BAL_COUT = 0 26 BAL_COUT = 2 25 BAL_COUT = 4 24 BAL_COUT = 6 BAL_COUT = 8 23 BAL_COUT = 10 22 BAL_COUT = 12 21 BAL_COUT = 14 20 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 RF FREQUENCY (MHz) Figure 35. Conversion Gain vs. RF Frequency for All RFB Settings, VGS and LPF Use Optimum Settings 19 18 17 15 18 =0 =2 =4 =6 =8 = 10 = 12 = 14 17 16 14 13 12 11 10 9 8 7 =0 =2 =4 =6 =8 = 10 = 12 = 14 14 13 12 11 9 6 5 700 15 BAL_COUT BAL_COUT BAL_COUT BAL_COUT BAL_COUT BAL_COUT BAL_COUT BAL_COUT 10 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 RF FREQUENCY (MHz) 12199-036 INPUT P1dB (dBm) 16 BAL_COUT BAL_COUT BAL_COUT BAL_COUT BAL_COUT BAL_COUT BAL_COUT BAL_COUT Figure 38. Input IP3 vs. RF Frequency for All RFB Settings, VGS and LPF Use Optimum Settings SSB NOISE FIGURE (dB) 20 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 RF FREQUENCY (MHz) Figure 34. IF Output Impedance (R Parallel C Equivalent) 3 TA = –40°C, HIGH-SIDE LO TA = +25°C, HIGH-SIDE LO TA = +85°C, HIGH-SIDE LO TA = –40°C, LOW-SIDE LO TA = +25°C, LOW-SIDE LO TA = +85°C, LOW-SIDE LO Figure 36. Input P1dB vs. RF Frequency for All RFB Settings, VGS and LPF Use Optimum Settings 8 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 RF FREQUENCY (MHz) Figure 39. SSB Noise Figure vs. RF Frequency for All RFB Settings, VGS and LPF Use Optimum Settings Rev. A | Page 18 of 57 12199-139 RIN1 (Ω) 800 75 12199-038 1000 12199-137 1100 IF CHANNEL-TO-CHANNEL ISOLATION (dBc) 10 1200 Data Sheet ADRF6612 15.0 10 14.5 9 13.0 INPUT P1dB (dBm) 13.5 7 6 5 4 VGS = 0 VGS = 1 VGS = 2 VGS = 3 VGS = 4 VGS = 5 VGS = 6 VGS = 7 1 9.0 8.5 8.0 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 RF FREQUENCY (MHz) Figure 43. Input P1dB vs. RF Frequency for All VGS Settings, RFB and LPF Use Optimum Settings 14.0 13.5 SSB NOISE FIGURE (dB) 13.0 VGS = 0 VGS = 1 VGS = 2 VGS = 3 VGS = 4 VGS = 5 VGS = 6 VGS = 7 RF FREQUENCY (MHz) 11.0 10.5 RF FREQUENCY (MHz) Figure 44. SSB Noise Figure vs. RF Frequency for All VGS Settings, RFB and LPF Use Optimum Settings 15 =0 =2 =4 =6 14 13 8.0 12 INPUT P1dB (dBm) 8.5 7.5 7.0 6.5 6.0 5.5 LPF LPF LPF LPF =0 =2 =4 =6 11 10 9 5.0 8 4.5 7 4.0 3.0 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 RF FREQUENCY (MHz) Figure 42. Conversion Gain vs. RF Frequency for All LPF Settings, RFB and VGS Use Optimum Settings 5 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 RF FREQUENCY (MHz) Figure 45. Input P1dB vs. RF Frequency for All LPF Settings, RFB and VGS Use Optimum Settings Rev. A | Page 19 of 57 12199-149 6 3.5 12199-146 CONVERSION GAIN (dB) 11.5 9.0 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 Figure 41. Input IP3 vs. RF Frequency for All VGS Settings, RFB and LPF Use Optimum Settings 9.0 12.0 9.5 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 LPF LPF LPF LPF 12.5 VGS = 0 VGS = 1 VGS = 2 VGS = 3 VGS = 4 VGS = 5 VGS = 6 VGS = 7 10.0 12199-141 INPUT IP3 (dBm) Figure 40. Conversion Gain vs. RF Frequency for All VGS Settings, RFB and LPF Use Optimum Settings 9.5 11.0 10.5 9.5 RF FREQUENCY (MHz) 10.0 11.5 10.0 0 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 700 12.0 12199-043 2 12.5 12199-144 3 12199-040 CONVERSION GAIN (dB) 14.0 8 VGS = 0 VGS = 1 VGS = 2 VGS = 3 VGS = 4 VGS = 5 VGS = 6 VGS = 7 18 14 13 12 11 =0 =2 =4 =6 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 8 700 IFMAIN = 3 IFMAIN = 4 IFMAIN = 5 IFMAIN = 6 IFMAIN = 7 IFMAIN = 8 IFMAIN = 9 IFMAIN = 10 IFMAIN = 11 IFMAIN = 12 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 RF FREQUENCY (MHz) Figure 49. SSB Noise Figure vs. RF Frequency for All LPF Settings, RFB and VGS Use Optimum Settings 40 IFMAIN = 13 IFMAIN = 14 IFMAIN = 15 35 2.4 2.3 2.2 2.1 2.0 1.9 30 25 20 IFMAIN = 3 IFMAIN = 4 IFMAIN = 5 IFMAIN = 6 IFMAIN = 7 IFMAIN = 8 IFMAIN = 9 15 1.8 0 –20 20 40 60 80 TEMPERATURE (°C) 10 –40 12199-347 IFLIN = 8 IFLIN = 9 IFLIN = 10 IFLIN = 11 IFLIN = 12 IFLIN = 13 IFLIN = 14 IFLIN = 15 80 34 32 INPUT IP3 (dBm) 0 1 2 3 4 5 6 7 2.30 2.28 2.26 2.24 30 28 26 2.22 2.20 24 2.18 2.16 –40 60 36 IFLIN = IFLIN = IFLIN = IFLIN = IFLIN = IFLIN = IFLIN = IFLIN = –20 0 20 40 60 80 TEMPERATURE (°C) 12199-348 POWER DISSIPATION (W) 2.32 40 Figure 50. Input IP3 vs. Temperature for IF Main Settings 2.38 2.34 20 0 TEMPERATURE (°C) Figure 47. Power Dissipation vs. Temperature for IF Main Settings 2.36 –20 IFMAIN = 10 IFMAIN = 11 IFMAIN = 12 IFMAIN = 13 IFMAIN = 14 IFMAIN = 15 Figure 48. Power Dissipation vs. Temperature for IF LIN Settings 22 –40 IFLIN = 0 IFLIN = 1 IFLIN = 2 IFLIN = 3 IFLIN = 4 IFLIN = 5 IFLIN = 6 IFLIN = 7 –20 IFLIN = 8 IFLIN = 9 IFLIN = 10 IFLIN = 11 IFLIN = 12 IFLIN = 13 IFLIN = 14 IFLIN = 15 0 20 40 60 80 TEMPERATURE (°C) Figure 51. Input IP3 vs. Temperature for IF LIN Settings Rev. A | Page 20 of 57 12199-351 1.7 –40 12199-150 9 12199-350 LPF LPF LPF LPF INPUT IP3 (dBm) POWER DISSIPATION (W) 2.5 15 10 Figure 46. Input IP3 vs. RF Frequency for All LPF Settings, RFB and VGS Use Optimum Settings 2.6 =0 =2 =4 =6 16 RF FREQUENCY (MHz) 2.7 LPF LPF LPF LPF 17 SSB NOISE FIGURE (dB) 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 700 Data Sheet 12199-147 INPUT IP3 (dBm) ADRF6612 Data Sheet ADRF6612 –60 –60 890MHz +10dBm 1910MHz +10dBm 2510MHz +10dBm –70 –90 –100 –110 –120 –130 –90 –100 –110 –120 –130 –140 –140 –150 –150 0.01 0.1 1 OFFSET FREQUENCY (MHz) 10 –160 0.001 Figure 52. Phase Noise at IF Output vs. Offset Frequency with 10 dBm Blocker in Integer Mode 0.01 0.1 1 OFFSET FREQUENCY (MHz) 10 12199-353 PHASE NOISE (dBc/Hz) –80 12199-352 PHASE NOISE (dBc/Hz) –80 –160 0.001 890MHz +10dBm 1910MHz +10dBm 2510MHz +10dBm –70 Figure 53. Phase Noise at IF Output vs. Offset Frequency with 10 dBm Blocker in Fractional Mode Rev. A | Page 21 of 57 ADRF6612 Data Sheet MIXER, HIGH EFFICIENCY MODE TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, ZO = 50 Ω, fREF = 122.88 MHz, fREF power = 4 dBm, fPFD = 1.536 MHz, low-side LO injection, optimum RFB and LPF settings, unless otherwise noted. 2.1 1.9 70 = –40°C, HIGH-SIDE LO = 25°C, HIGH-SIDE LO = 85°C, HIGH-SIDE LO = –40°C, LOW-SIDE LO = 25°C, LOW-SIDE LO = 85°C, LOW-SIDE LO 65 60 1.8 1.7 1.6 55 50 45 1.5 35 1.3 RF FREQUENCY (MHz) RF FREQUENCY (MHz) 13 12 11 INPUT P1dB (dBm) 12.0 TA = –40°C, HIGH_LO 11.5 TA = +25°C,HIGH_LO 11.0 TA = +85°C, HIGH_LO 10.5 TA = –40°C, LOW_LO TA = +25°C, LOW_LO 10.0 TA = +85°C, LOW_LO 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 Figure 57. Input IP2 vs. RF Frequency over Three Temperatures 31 29 6 17 16 23 21 19 17 15 13 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 RF FREQUENCY (MHz) 18 TA = –40°C, HIGH-SIDE LO TA = +25°C, HIGH-SIDE LO TA = +85°C, HIGH-SIDE LO TA = –40°C, LOW-SIDE LO TA = +25°C, LOW-SIDE LO TA = +85°C, LOW-SIDE LO 25 11 –40°C LOCKED –40°C EXTERNAL LO +25°C LOCKED +25°C EXTERNAL LO +85°C LOCKED +85°C EXTERNAL LO 15 14 13 12 11 10 9 9 7 5 700 7 Figure 58. Input P1dB vs. RF Frequency over Three Temperatures 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 RF FREQUENCY (MHz) Figure 56. Input IP3 vs. RF Frequency over Three Temperatures 8 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 12199-153 INPUT IP3 (dBm) 27 8 3 700 SSB NOISE FIGURE (dB) 33 9 4 Figure 55. Conversion Gain vs. RF Frequency over Three Temperatures 35 10 TA = –40°C, HIGH-SIDE LO TA = +25°C, HIGH-SIDE LO TA = +85°C, HIGH-SIDE LO TA = –40°C, LOW-SIDE LO TA = +25°C, LOW-SIDE LO TA = +85°C, LOW-SIDE LO 5 12199-152 CONVERSION GAIN (dB) Figure 54. Power Dissipation vs. RF Frequency over Three Temperatures 12199-155 RF FREQUENCY (MHz) 30 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 12199-151 1.2 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 TA = –40°C, HIGH-SIDE LO TA = +25°C, HIGH-SIDE LO TA = +85°C, HIGH-SIDE LO TA = –40°C, LOW-SIDE LO TA = +25°C, LOW-SIDE LO TA = +85°C, LOW-SIDE LO 12199-357 40 1.4 RF FREQUENCY (MHz) 12199-156 POWER DISSIPATION (W) 2.0 TA TA TA TA TA TA INPUT IP2 (dBm) 2.2 Figure 59. SSB Noise Figure vs. RF Frequency over Three Temperatures Rev. A | Page 22 of 57 Data Sheet ADRF6612 SYNTHESIZER VS = high performance mode, TA = 25°C, measured on LO output, fLO = 1700 MHz, ZO = 50 Ω, fREF = 122.88 MHz, fPFD = 1.536 MHz, fREF power = 4 dBm, integer mode loop filter, unless otherwise noted. –60 –80 –100 –120 –140 –160 –180 10k 100k 1M 10M 100M OFFSET FREQUENCY (Hz) Figure 60. VCO_0 Open-Loop Phase Noise vs. Offset Frequency, fVCO_0 = 5.1 GHz, Divide by Two Selected, VCOVTUNE = 1.5 V –140 –150 0.01 0.1 1 10 100 –140 –160 10k 100k 1M 10M 100M –70 LO_DIV = /2 LO_DIV = /4 LO_DIV = /8 –80 –90 –100 –110 –120 –130 –140 –150 –160 0.001 0.01 0.1 1 10 100 OFFSET FREQUENCY (MHz) 12199-061 CLOSED-LOOP PHASE NOISE (dBc/Hz) –120 OFFSET FREQUENCY (Hz) Figure 64. VCO_1 Closed-Loop Phase Noise for Various LO_DIV Dividers vs. Offset Frequency, fVCO_1 = 4.5 GHz Figure 61. VCO_1 Open-Loop Phase Noise vs. Offset Frequency, fVCO_1 = 4.5 GHz, Divide by Two Selected, VCOVTUNE = 1.5 V –60 CLOSED-LOOP PHASE NOISE (dBc/Hz) –40 –60 –80 –100 –120 –140 –160 10k 100k 1M 10M 100M OFFSET FREQUENCY (Hz) Figure 62. VCO_2 Open-Loop Phase Noise vs. Offset Frequency, fVCO_2 = 3.8 GHz, Divide by Two Selected, VCOVTUNE = 1.5 V –70 LO_DIV = /2 LO_DIV = /4 LO_DIV = /8 –80 –90 –100 –110 –120 –130 –140 –150 –160 0.001 12199-159 OPEN-LOOP PHASE NOISE (dBc/Hz) –130 OFFSET FREQUENCY (MHz) 12199-158 OPEN-LOOP PHASE NOISE (dBc/Hz) –100 1k –110 –120 –60 –80 –180 –90 –100 Figure 63. VCO_0 Closed-Loop Phase Noise for Various LO_DIV Dividers vs. Offset Frequency, fVCO_0 = 5.1 GHz –60 1k –80 –160 0.001 –40 –180 LO_DIV = /2 LO_DIV = /4 LO_DIV = /8 0.01 0.1 1 OFFSET FREQUENCY (MHz) 10 100 12199-062 1k –70 12199-060 CLOSED-LOOP PHASE NOISE (dBc/Hz) –60 12199-157 OPEN-LOOP PHASE NOISE (dBc/Hz) –40 Figure 65. VCO_2 Closed-Loop Phase Noise for Various LO_DIV Dividers vs. Offset Frequency, fVCO_2 = 3.8 GHz Rev. A | Page 23 of 57 ADRF6612 Data Sheet –60 –80 –100 –120 –140 –160 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (Hz) Figure 66. VCO_3 Open-Loop Phase Noise vs. Offset Frequency, fVCO_3 = 3.2 GHz, Divide by Two Selected, VCOVTUNE = 1.5 V LO_DIV = /2 LO_DIV = /4 LO_DIV = /8 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 0.001 0.01 0.1 1 10 100 OFFSET FREQUENCY (MHz) 12199-066 CLOSED-LOOP PHASE NOISE (dBc/Hz) –60 12199-163 OPEN-LOOP PHASE NOISE (dBc/Hz) –40 Figure 69. VCO_3 Closed-Loop Phase Noise for Various LO_DIV Dividers vs. Offset Frequency, fVCO_3 = 3.2 GHz –200 –200 –40°C +25°C +85°C –40°C +25°C +85°C –205 FOM (dBc/Hz/Hz) FOM (dBc/Hz/Hz) –205 –210 –215 –210 –215 –220 –220 –225 1630 1830 2030 2230 2430 2630 2830 LO FREQUENCY (MHz) Figure 67. PLL Figure of Merit (FOM) vs. LO Frequency, Integer Mode –230 1430 1630 1830 2030 2230 2430 2630 Figure 70. PLL Figure of Merit (FOM) vs. LO Frequency, Fractional Mode Offset = 45 kHz, Bleed = 125 µA OPEN-LOOP PHASE NOISE (dBc/Hz) –40 1kHz OFFSET –60 –80 –100 100kHz OFFSET –120 500kHz OFFSET –140 10MHz OFFSET –40°C +25°C +85°C –100 50kHz OFFSET –110 200kHz OFFSET –120 –130 1MHz OFFSET –140 40MHz OFFSET –150 –160 –180 1430 1630 1830 2030 2230 2430 2630 LO FREQUENCY (MHz) 2830 Figure 68. Open-Loop Phase Noise vs. LO Frequency, Divide by Two Selected Rev. A | Page 24 of 57 –170 1430 1630 1830 2030 2230 2430 2630 LO FREQUENCY (MHz) Figure 71. Open-Loop Phase Noise vs. LO Frequency, Divide by Two Selected 2830 12199-168 –160 12199-165 OPEN-LOOP PHASE NOISE (dBc/Hz) –40°C +25°C +85°C –20 2830 LO FREQUENCY (MHz) –90 0 12199-470 –230 1430 12199-367 –225 Data Sheet –70 ADRF6612 –80 –40°C +25°C +85°C –80 50 kHz OFFSET –100 –100 PHASE NOISE (dBc/Hz) 100kHz OFFSET –110 –120 500kHz OFFSET –130 –140 –130 1MHz OFFSET –140 40MHz OFFSET 1630 1830 2030 2230 2430 2630 LO FREQUENCY (MHz) –170 1430 12199-069 –170 1430 2030 2230 2430 2630 Figure 75. Integer Loop Filter Phase Noise, Divide by Two Selected, Offset = 50 kHz, 200 kHz, 1 MHz, and 40 MHz 1.4 –40°C +25°C +85°C –40°C +25°C +85°C 1.2 INTEGRATED PHASE NOISE, WITHOUT SPURS (°rms) 1.2 1830 LO FREQUENCY (Hz) Figure 72. Integer Loop Filter Phase Noise, Divide by Two Selected, Offset = 1 kHz, 100 kHz, 500 kHz, and 10 MHz 1.4 1630 12199-072 –160 –160 LO_DIV = /2 1.0 0.8 0.6 0.4 0.2 LO_DIV = /2 1.0 0.8 0.6 0.4 0.2 LO_DIV = /4 3360 3860 4360 LO_DIV = /8 4860 5360 VCO FREQUENCY (MHz) 0 2860 12199-070 0 2860 Figure 73. 10 kHz to 40 MHz Integrated Phase Noise vs. VCO Frequency, Divide by Two, Four, and Eight, Including Spurs –105 –115 3860 4360 4860 5360 VCO FREQUENCY (MHz) 12199-071 –125 3360 4360 4860 5360 –75 –40°C LO_DIV = /8 +25°C LO_DIV = /8 +85°C LO_DIV = /8 –95 –135 2860 3860 Figure 76. 10 kHz to 40 MHz Integrated Phase Noise vs. VCO Frequency, Divide by Two, Four, and Eight, Excluding Spurs REFERENCE SPURS (dBc), 2 × PFD OFFSET –85 3360 VCO FREQUENCY (MHz) –75 –40°C LO_DIV = /2 +25°C LO_DIV = /2 +85°C LO_DIV = /2 –40°C LO_DIV = /4 +25°C LO_DIV = /4 +85°C LO_DIV = /4 LO_DIV = /8 LO_DIV = /4 12199-073 INTEGRATED PHASE NOISE, WITH SPURS (°rms) 200 kHz OFFSET –120 –150 10 MHz OFFSET –150 –110 Figure 74. fPFD Reference Spurs vs. VCO Frequency, 1 × PFD Offset, Measured at LO Output, Integer Mode –85 –95 –105 –115 –40°C LO_DIV = /2 +25°C LO_DIV = /2 +85°C LO_DIV = /2 –40°C LO_DIV = /4 +25°C LO_DIV = /4 +85°C LO_DIV = /4 –125 –135 2860 3360 3860 4360 –40°C LO_DIV = /8 +25°C LO_DIV = /8 +85°C LO_DIV = /8 4860 5360 VCO FREQUENCY (MHz) Figure 77. fPFD Reference Spurs vs. VCO Frequency, 2 × PFD Offset, Measured at LO Output, Integer Mode Rev. A | Page 25 of 57 12199-074 PHASE NOISE (dBc/Hz) –90 REFERENCE SPURS (dBc), 1 × PFD OFFSET –40°C +25°C +85°C –90 1kHz OFFSET ADRF6612 –105 –115 –125 3860 3360 4360 4860 5360 VCO FREQUENCY (MHz) –95 –105 –115 –125 –135 2860 –60 REFERENCE SPURS (dBc), 2 × PFD OFFSET –70 –75 –80 –85 1830 2030 2230 2430 2630 2830 LO FREQUENCY (MHz) –64 –66 –68 –70 –72 –74 –76 –78 –74 –76 –78 –80 –82 –84 –86 –88 –90 1430 1630 1830 2030 2230 2430 2630 2830 LO FREQUENCY (MHz) Figure 80. fPFD Reference Spurs vs. LO Frequency, 3 × PFD Offset, Measured at LO Output, Fractional Mode Rev. A | Page 26 of 57 1830 2030 2230 2430 2630 2830 Figure 82. fPFD Reference Spurs vs. LO Frequency, 2 × PFD Offset, Measured at LO Output, Fractional Mode REFERENCE SPURS (dBc), 4 × PFD OFFSET –40°C +25°C +85°C 12199-380 REFERENCE SPURS (dBc), 3 × PFD OFFSET –70 1630 LO FREQUENCY (MHz) Figure 79. fPFD Reference Spurs vs. LO Frequency, 1 × PFD Offset, Measured at LO Output, Fractional Mode –72 5360 –40°C +25°C +85°C –62 –80 1430 12199-379 REFERENCE SPURS (dBc), 1 × PFD OFFSET –65 1630 4860 Figure 81. fPFD Reference Spurs vs. VCO Frequency, 4 × PFD Offset, Measured at LO Output, Integer Mode –40°C +25°C +85°C –90 1430 4360 VCO FREQUENCY (MHz) Figure 78. fPFD Reference Spurs vs. VCO Frequency, 3 × PFD Offset, Measured at LO Output, Integer Mode –60 3860 3360 12199-382 –135 2860 –85 –40°C LO_DIV = /8 +25°C LO_DIV = /8 +85°C LO_DIV = /8 12199-078 –95 –40°C LO_DIV = /2 +25°C LO_DIV = /2 +85°C LO_DIV = /2 –40°C LO_DIV = /4 +25°C LO_DIV = /4 +85°C LO_DIV = /4 –40°C +25°C +85°C –76 –78 –80 –82 –84 –86 –88 –90 1430 1630 1830 2030 2230 2430 2630 2830 LO FREQUENCY (MHz) Figure 83. fPFD Reference Spurs vs. LO Frequency, 4 × PFD Offset, Measured at LO Output, Fractional Mode 12199-383 –85 –75 –40°C LO_DIV = /8 +25°C LO_DIV = /8 +85°C LO_DIV = /8 REFERENCE SPURS (dBc), 4 × PFD OFFSET –40°C LO_DIV = /2 +25°C LO_DIV = /2 +85°C LO_DIV = /2 –40°C LO_DIV = /4 +25°C LO_DIV = /4 +85°C LO_DIV = /4 12199-075 REFERENCE SPURS (dBc), 3 × PFD OFFSET –75 Data Sheet Data Sheet ADRF6612 0 IF AT –40°C IF AT +25°C IF AT +85°C LO AT –40°C LO AT +25°C LO AT +85°C –20 –10 –20 –40 ISOLATION (dB) –30 –60 –80 –40 –50 –60 –70 –100 –80 –120 –90 1630 1830 2030 2230 2430 2630 2830 LO FREQUENCY (MHz) –100 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 12199-387 –140 1430 12199-384 REFERENCE SPURS (dBc), 1 × PFD OFFSET 0 RF FREQUENCY (MHz) Figure 84. fPFD Reference Spurs vs. LO Frequency, Divide by Two Selected, 1 × PFD Offset, Measured on LO Output and IF Output Figure 87. RF to LO Output Feedthrough, LO_DRV_LVL = 0 10 1520 LO_DRV_LVL = 0 AT –40°C LO_DRV_LVL = 0 AT +25°C LO_DRV_LVL = 0 AT +85°C 8 LO_DRV_LVL = 1 AT –40°C LO_DRV_LVL = 1 AT +25°C LO_DRV_LVL = 1 AT +85°C 1515 4 LO FREQUENCY (MHz) LO AMPLITUDE (dBm) 3 2 0 –2 –4 –6 1510 1505 1500 1495 1490 –8 850 1350 1850 2350 1485 2850 LO FREQUENCY (MHz) 1480 0 20 30 40 50 60 70 80 90 100 LOCK TIME (ms) Figure 85. LO Amplitude vs. LO Frequency, LO_DRV_LVL = 0, 1, 2, and 3 Figure 88. LO Frequency Settling Time, Integer Mode Loop Filter, Integer Mode 1520 225 LO_DRV_LVL = 3 AT LO_DRV_LVL = 3 AT LO_DRV_LVL = 3 AT LO_DRV_LVL = 2 AT LO_DRV_LVL = 2 AT LO_DRV_LVL = 2 AT 1515 LO FREQUENCY (MHz) 205 –40°C +25°C +85°C –40°C +25°C +85°C 195 185 175 165 155 135 125 350 LO_DRV_LVL = 1 AT LO_DRV_LVL = 1 AT LO_DRV_LVL = 1 AT LO_DRV_LVL = 0 AT LO_DRV_LVL = 0 AT LO_DRV_LVL = 0 AT 850 1350 1505 1500 1495 1490 –40°C +25°C +85°C –40°C +25°C +85°C 1485 1850 2350 LO FREQUENCY (MHz) Figure 86. Supply Current for VCC7 vs. LO Frequency, LO_DRV_LVL = 0, 1, 2, and 3 2850 1480 12199-386 145 1510 0 0.5 1.0 1.5 2.0 2.5 3.0 LOCK TIME (ms) 3.5 4.0 4.5 5.0 12199-389 215 VCC7 SUPPLY CURRENT (mA) 10 12199-388 –12 350 LO_DRV_LVL = 3 AT –40°C LO_DRV_LVL = 3 AT +25°C LO_DRV_LVL = 3 AT +85°C 12199-500 LO_DRV_LVL = 2 AT –40°C LO_DRV_LVL = 2 AT +25°C LO_DRV_LVL = 2 AT +85°C –10 Figure 89. LO Frequency Settling Time, Fractional Loop Filter, Fractional Mode Rev. A | Page 27 of 57 ADRF6612 2.5 Data Sheet –60 VTUNE +85°C VTUNE –40°C –70 –80 PFD SPURS (dBc) VTUNE (V) 2.0 3.18GHz 3.81GHz 4.45GHz 5.08GHz 1.5 1.0 –90 –100 –110 –120 0.5 1830 2030 2230 2430 2630 2830 LO FREQUENCY (MHz) Figure 90. VTUNE vs. LO Frequency for Lock at Cold Drift to Hot 2.5 VTUNE +85°C VTUNE –40°C 1.5 1.0 0.5 0 1430 1630 1830 2030 2230 2430 2630 2830 LO FREQUENCY (MHz) 12199-188 VTUNE (V) 2.0 Figure 91. VTUNE vs. LO Frequency for Lock at Hot Drift to Cold Rev. A | Page 28 of 57 –140 –100 –80 –60 –40 –20 0 20 40 60 80 100 OFFSET FREQUENCY (MHz) Figure 92. PFD Spurs vs. Offset Frequency for 4 VCOs, Integer Mode 12199-189 1630 12199-187 0 1430 –130 Data Sheet ADRF6612 SPURIOUS PERFORMANCE (N × fRF) − (M × fLO) spur measurements were made using the standard evaluation board. Mixer spurious products are measured in dBc from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement system = −100 dBm. High Performance Mode VS = high performance mode, TA = 25°C, ZO = 50 Ω, fREF = 122.88 MHz, fREF power = 4 dBm, fPFD = 1.536 MHz, low-side LO injection, optimum RFB and LPF settings, unless otherwise noted. Table 11. RF = 900 MHz, LO = 697 MHz M 0 N 0 1 2 3 4 5 6 7 8 9 −35.5 −55.3 −88.2 <−100 <−100 <−100 1 −27.1 0.0 −68.9 −88.4 −56.6 −43.6 −66.7 −53.5 2 −32.1 −52.5 −68.8 <−100 <−100 <−100 <−100 <−100 <−100 3 −39.1 −18.4 −73.4 −79.5 <−100 <−100 <−100 <−100 <−100 4 −27.0 −56.6 −64.9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 5 −54.2 −43.6 <−100 −94.1 <−100 <−100 <−100 <−100 <−100 <−100 6 −48.5 −66.7 −68.3 <−100 <−100 <−100 <−100 <−100 <−100 <−100 7 −69.3 −53.5 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 8 −65.6 −87.4 −80.6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 9 −73.5 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 5 6 7 8 9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 7 8 9 <−100 −92.5 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 Table 12. RF = 1900 MHz, LO = 1697 MHz M 0 N 0 1 2 3 4 5 6 7 8 9 −30.2 −70.8 <−100 1 −37.0 0.0 −71.9 <−100 <−100 2 −31.2 −47.9 −81.6 −93.5 <−100 3 −64.2 −52.1 −81.2 −75.2 <−100 <−100 4 −74.4 −67.2 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 Table 13. RF = 2500 MHz, LO = 2297 MHz M 0 N 0 1 2 3 4 5 6 7 8 9 −29.0 −81.0 1 −40.7 0.0 −87.3 <−100 2 −44.1 −49.4 −75.4 −91.9 <−100 3 −58.7 −79.0 −74.7 <−100 <−100 4 5 −84.7 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 Rev. A | Page 29 of 57 6 <−100 <−100 <−100 <−100 ADRF6612 Data Sheet High Efficiency Mode VS = high efficiency mode, TA = 25°C, ZO = 50 Ω, fREF = 122.88 MHz, fREF power = 4 dBm, fPFD = 1.536 MHz, low-side LO injection, optimum RFB and LPF settings, unless otherwise noted. Table 14. RF = 900 MHz, LO = 697 MHz M 0 N 0 1 2 3 4 5 6 7 8 9 −37.7 −70.3 −86.4 <−100 <−100 <−100 1 −30.4 0.0 −66.4 −81.0 <−100 <−100 <−100 <−100 2 −34.1 −52.6 −68.8 −96.4 −97.9 <−100 <−100 <−100 <−100 3 −46.7 −19.2 −71.9 −74.7 <−100 <−100 <−100 <−100 <−100 4 −29.6 −61.6 −59.9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 5 −57.4 −44.3 −93.0 −85.0 <−100 <−100 <−100 <−100 <−100 <−100 6 −51.2 −64.0 −67.8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 7 −74.7 −53.6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 8 −62.7 −91.8 −79.0 <−100 <−100 <−100 <−100 <−100 <−100 <−100 9 −73.2 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 7 8 9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 7 8 9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 Table 15. RF = 1900 MHz, LO = 1697 MHz M 0 N 0 1 2 3 4 5 6 7 8 9 −30.5 −71.5 <−100 1 −41.4 0.0 −67.7 <−100 <−100 2 −35.1 −46.9 −74.6 −89.9 <−100 3 −69.0 −52.2 −71.3 −67.7 <−100 <−100 4 −74.4 −63.6 <−100 <−100 <−100 <−100 5 <−100 <−100 <−100 <−100 <−100 <−100 6 <−100 <−100 <−100 <−100 <−100 <−100 Table 16. RF = 2500 MHz, LO = 2297 MHz 0 N 0 1 2 3 4 5 6 7 8 9 −29.1 −75.6 1 −42.3 0.0 −88.8 −59.4 2 −48.6 −48.6 −71.6 −86.2 −77.0 3 −59.4 −70.8 −66.9 <−100 <−100 4 −77.0 <−100 <−100 <−100 <−100 M 5 <−100 <−100 <−100 <−100 Rev. A | Page 30 of 57 6 <−100 <−100 <−100 <−100 Data Sheet ADRF6612 CIRCUIT DESCRIPTION The ADRF6612 consists of two primary components: the RF subsystem and the LO subsystem. The combination of design, process, and packaging technology allows the functions of these subsystems to be integrated into a single die, using mature packaging and interconnection technologies to provide a high performance device with excellent electrical, mechanical, and thermal properties. The wideband frequency response and flexible frequency programming simplifies the receiver design, saves on-board space, and minimizes the need for external components. The RF subsystem consists of an integrated, tunable, low loss RF balun, a double balanced, passive MOSFET mixer, a tunable sum termination network, and an IF amplifier. The LO subsystem consists of a multistage, limiting LO amplifier. The purpose of the LO subsystem is to provide a large, fixed amplitude, balanced signal to drive the mixer independent of the level of the LO input. A schematic of the device is shown in Figure 94. EXTERNAL LO GENERATION The ADRF6612 LO can be generated by an externally applied source or by using the internal PLL synthesizer. To select the external LO mode, write the value 011 to Register 0x22, Bits[2:0] and apply the differential LO signal to Pin 4 (EXTVCOIN+) and Pin 5 (EXTVCOIN−). Internal dividers allow the externally applied LO signal to be divided before this signal arrives at the mixer LO input. The divider value is set by Register 0x21, Bits[5:3] and has possible values of 1, 2, 4, and 8. With the divider set to 1, the externally applied LO input frequency range is 250 MHz to 2850 MHz. When using a divider value of other than 1, the maximum externally applied LO frequency is 5700 MHz. The external LO input pins present a broadband differential 50 Ω input impedance. The EXTVCOIN+ and EXTVCOIN− input pins must be ac-coupled. When not in use, EXTVCOIN+ and EXTVCOIN− can be left unconnected. INTERNAL LO GENERATION RF SUBSYSTEM The single-ended, 50 Ω RF input is internally transformed to a balanced signal using a tunable, low loss, unbalanced-to-balanced (balun) transformer. This transformer is made possible by an extremely low loss metal stack, which provides both excellent balance and dc isolation for the RF port. Although the port can be dc connected, it is recommended to use a blocking capacitor to avoid running excessive dc current through the device. The RF balun can easily support an RF input frequency range of 700 MHz to 3000 MHz. This balun is tuned over the frequency range by a SPI controlled switched capacitor network at the output of the RF balun. The resulting balanced RF signal is applied to a passive mixer that commutates the RF input in accordance with the output of the LO subsystem. The passive mixer is a balanced, low loss switch that adds minimum noise to the frequency translation. The only noise contribution from the mixer is due to the resistive loss of the switches, which is in the order of a few ohms. The IF amplifier is a balanced feedback design that simultaneously provides the desired gain, noise figure, and input impedance that is required to achieve the overall performance. The balanced open-collector output of the IF amplifier, with an impedance modified by the feedback within the amplifier, permits the output to be connected directly to a high impedance filter, a differential amplifier, or an analog-to-digital converter (ADC) input while providing optimum second-order intermodulation suppression. The differential output impedance of the IF amplifier is approximately 200 Ω. If operation in a 50 Ω system is desired, the output can be transformed to 50 Ω by using a 4:1 transformer or an LC impedance matching network. Reference Input Circuitry The ADRF6612 includes an on-chip PLL for LO synthesis. The PLL, shown in Figure 93, consists of a reference input and input dividers, a PFD, a charge pump, VCOs, and a programmable fractional/integer divider with a 2× prescaler. The reference path takes in a reference clock and divides it by a factor of 1 to 8191 before passing it to the PFD. The PFD compares this signal to the divided down signal from the VCO. Depending on the PFD polarity selected, the PFD sends an up or down signal to the charge pump if the VCO signal is slow or fast compared to the reference frequency. The charge pump sends a current pulse to the off-chip loop filter to increase or decrease the tuning voltage (VCOVTUNE). In band (within the band of the loop filter) phase noise performance is typically limited by the reference source. Due to the inherent phase noise reduction when performing frequency division, improved in band phase noise performance can be achieved with higher reference divide values. However, the divide chain adds its own small amount of phase noise, so there is a limit on how much improvement can be gained by increasing the divider value. Rev. A | Page 31 of 57 ADRF6612 Data Sheet CPOUT REFIN 1 TO 8191 (REG 0x21[11:0]) VCOVTUNE LOOP FILTER R8 R10 CHARGE PUMP PFD R7 C18 C20 C22 C23 GNDCP MIXER 1 LO MIXER 2 LO 2× PRESCALER LO DIVIDER (1, 2, 4, 8, 16, 32) (REG 0x22[5:3]) EXTERNAL LO INPUT 12199-090 FRAC N = INT + MOD (REG 0x02, REG 0x03, REG 0x04) Figure 93. LO Generation Block Diagram Loop Filters Defining a loop filter for the ADRF6612 depends on several dynamics, these being the PLL REFIN and PFD frequency and desired PFD and fractional spur levels. Higher reference and PFD frequencies spread the PFD spurs over a wider bandwidth (wider separation between spurs), but also lead to higher levels of spurs coupling through the reference divider chain. Lower reference and PFD frequencies lower the spacing between PFD spurs, but the spur levels can be significantly improved by using lower frequencies. At lower PFD frequencies, it may also be possible to achieve the desired synthesizer frequency step size using the integer divider mode, therefore eliminating the risk of fractional spurs. Table 17 shows the recommended loop filter components and dynamic loop settings when using integer mode and PFD frequencies at less than 10 MHz. Table 17. Integer Mode Loop Filter Components and PLL Dynamic Settings Loop Filter Components C18 R7 C20 R8 C22 R10 C23 CSCALE Bleed Current ABDLY PLL Dynamic Settings 1500 pF 910 Ω 33 nF 1.8 kΩ 560 pF 20 kΩ 39 pF 8000 µA 0 µA 0.9 nS Table 18. Fractional Mode Loop Filter Components and PLL Dynamic Settings Loop Filter Components C18 R7 C20 R8 C22 R10 C23 CSCALE Bleed Current ABDLY PLL Dynamic Settings 1000 pF 700 Ω 33 nF 1.8 kΩ 560 pF 20 kΩ 39 pF 500 µA 93.75 µA 0 nS VCOs and Dividers The ADRF6612 has four internal VCOs. Considering the range of these VCOs, the fixed 2× prescaler after the VCO, and the LO_DIV (1, 2, 4, 8, 16, and 32) range, the total LO range allows RF generation of 200 MHz to 2700 MHz. Table 19. VCO Range VCO_SEL (Register 0x22, Bits[2:0])1 000 001 010 011 1 If a smaller frequency step size is desired, the ADRF6612 can be used in fractional mode. The 16-bit FRAC_DIV and MOD_DIV values available in the ADRF6612 mean that small step sizes can be achieved with high PFD frequencies. PFD spurs may be higher in amplitude, but are spaced further apart. Fractional spurs may be present as well. Frequency Range (GHz) 1 VCO_0 = 4.6 to 5.7 VCO_1 =4.02 to 4.6 VCO_2 =3.5 to 4.02 VCO_3 =2.85 to 3.5 For VCO_0, VCO_1, VCO_2, and VCO_3, set VTUNE_DAC_SLOPE (Register 0x49, Bits[13:9]) = 11 (decimal), VTUNE_DAC_OFFSET (Register 0x49, Bits[8:0]) = 184 (decimal), VCO_LDO_R2 (Register 0x22, Bits[11:8]) = 0 (decimal), and VCO_LDO_R4 (Register 0x22, Bits[15:12]) = 5 (decimal). The N-divider divides down the differential VCO signal to the PFD frequency. The N-divider can be configured for fractional mode or integer mode by addressing the DIV_MODE bit (Register 0x02, Bit 15). The default configuration is set for fractional mode. Rev. A | Page 32 of 57 Data Sheet ADRF6612 The following equations can be used to determine the N value and the PLL frequency: f PFD = f VCO 2 ×N N = INT + The time it takes to lock the PLL after the last register is written can be broken down into two parts: VCO band calibration and loop settling. FRAC MOD f LO = f PFD × 2 × N LO_DIVIDER where: fPFD is the phase frequency detector frequency. fVCO is the voltage controlled oscillator frequency. N is the fractional divide ratio. INT is the integer divide ratio programmed in Register 0x02. FRAC is the fractional divide ratio programmed in Register 0x03. MOD is the modulus divide ratio programmed in Register 0x04. fLO is the LO frequency going to the mixer core when the loop is locked. LO_DIVIDER is the final divider block that divides the VCO frequency down by 1, 2, 4, or 8 before it reaches the mixer (see Table 20). This control is located in the LO_DIV bits (Register 0x22, Bits[5:3]). Table 20. LO Divider LO_DIV (Register 0x22, Bits[5:3]) 00 01 10 11 Register 0x03 (FRAC_DIV in Table 25), or Register 0x04 (MOD_DIV in Table 25). When one of these registers is programmed, an internal VCO calibration is initiated, which is the last step in locking the PLL. LO_DIVIDER 1 2 4 8 The lock detect signal is available as one of the selectable outputs through the MUXOUT pin; a logic high indicates that the loop is locked. The MUXOUT pin is controlled by the REF_MUX_SEL bits (Register 0x21, Bits[14:13]); the PLL lock detect signal is the default configuration. To ensure that the PLL locks to the desired frequency, follow the proper write sequence of the PLL registers. The PLL registers must be configured accordingly to achieve the desired frequency, and the last writes must be to Register 0x02 (INT_DIV in Table 25), After the last register is written, the PLL automatically performs a VCO band calibration to choose the correct VCO band. This calibration takes approximately 5120 PFD cycles. For a 40 MHz fPFD, this corresponds to 128 µs. After calibration is complete, the feedback action of the PLL causes the VCO to eventually lock to the correct frequency. The speed with which this locking occurs depends on the nonlinear cycle-slipping behavior, as well as the small-signal settling of the loop. For an accurate estimation of the lock time, download the ADIsimPLL™ tool, which correctly captures these effects. In general, higher bandwidth loops tend to lock faster than lower bandwidth loops. Additional LO Controls To access the LO signal going to the mixer core through the LOOUT+ and LOOUT− pins (Pin 13 and Pin 14), enable the LO_DRV_EN bit in Register 0x01, Bit 7. This setting offers direct monitoring of the LO signal to the mixer for debug purposes; or the LO signal can be used to daisy-chain many devices synchronously. One ADRF6612 can serve as the master where the LO signal is sourced, and the subsequent slave devices share the same LO signal from the master. This flexibility substantially eases the LO requirements of a system with multiple LOs. The LO output drive level is controlled by the LO_DRV_LVL bits (Register 0x22, Bits[7:6]). Table 21 shows the available drive levels. Table 21. LO Drive Levels LO_DRV_LVL (Register 0x22, Bits[7:6]) 00 01 10 11 Rev. A | Page 33 of 57 Amplitude (dBm) −4 0.5 3 4.5 VCC11 VCC10 VCC9 VCOVTUNE CPOUT REFIN MUXOUT DNC IFOUT1+ IFOUT1– DECL1 DECL2 Data Sheet VCC12 ADRF6612 46 41 34 33 2 47 43 42 40 39 38 8 9 EXPOSED PAD 10 DECL3 VCO BUFFER LDO 11 DECL4 VCO BAND SWITCH LDO 12 DECL5 PLL CHARGE PUMP 3.3V LDO 45 LDO4 35 RFIN1 36 RFBCT1 VCO LDO VCC1 7 REFIN DIVIDER VCC2 16 LOCK DETECT VCC3 20 VPTAT SCAN VCC4 27 PFD VCC5 28 VCO VCC7 31 VCO N-DIVIDER DIVIDE BY 1 TO 32 VCC8 32 SPI CONTROL VCO INT N-DIVIDER 2.5V LDO EXTVCOIN+ 4 GND 14 21 22 23 15 30 LDO2 GND 13 LDO1 GND 19 Figure 94. Simplified Schematic Rev. A | Page 34 of 57 IFOUT2– GND 18 IFOUT2+ GND 17 DNC 48 LOOUT– 37 LOOUT+ 24 CS 6 LO DIV 3.3V LDO SCLK 3 SPI 2.5V LDO SDIO 1 GND EXTVCOIN– 5 26 RFIN2 25 RFBCT2 44 LDO3 12199-091 VCC6 29 Data Sheet ADRF6612 APPLICATIONS INFORMATION It is recommended to ac couple the RF and LO input ports to prevent nonzero dc voltages from damaging the RF balun or LO input circuit. A RFIN capacitor value of 22 pF is recommended. The ADRF6612 mixer is designed to downconvert radio frequencies (RF) primarily between 700 MHz and 2800 MHz to lower intermediate frequencies (IF) between 30 MHz and 450 MHz. Figure 95 depicts the basic connections of the mixer. +5V 330nH 330nH 150pF (0402) IFOUT1 22pF (0402) REFIN 47 2 43 40 39 38 DECL2 42 DECL1 REFIN 3.16kΩ (0402) IFOUT1– 1000pF (0402) 2700pF (0402) CPOUT VCC9 33 34 8 10pF (0402) 10µF (0603) 0.1µF (0402) 10pF (0402) VCC5 0.1µF (0402) 10pF (0402) VCC7 10µF (0603) 0.1µF (0402) 10pF (0402) VCC8 10µF (0603) LOIN 0.1µF (0402) 100pF (0402) 100pF (0402) VCO BAND SWITCH LDO 12 27 PLL CHARGE PUMP 3.3V LDO 45 28 10pF (0402) EXTVCOIN+ EXTVCOIN– 29 VCO 31 VCO DIVIDE BY 1 TO 32 36 26 25 SPI CONTROL VCO INT N-DIVIDER 2.5V LDO 4 5 3 6 10µF (0603) 100pF (0402) 10µF (0603) 100pF (0402) 10µF (0603) 100pF (0402) 10µF (0603) DECL5 LDO4 RFIN1 22pF (0402) RFIN1 N-DIVIDER 32 1 100pF (0402) DECL4 PFD 35 VCC6 10µF (0603) 11 DECL3 24 37 48 17 18 GND 19 13 14 100pF (0402) 22 23 21 44 SPI 2.5V LDO LO DIV 3.3V LDO 15 30 RFBCT1 RFIN2 10pF (0402) 10nF (0603) RFIN2 10pF (0402) 10nF (0603) 10pF (0402) 10µF (0603) LDO3 100pF (0402) 100pF (0402) 100pF (0402) 22pF (0402) RFBCT2 LDO2 10pF (0402) VCO BUFFER LDO LDO1 0.1µF (0402) VPTAT 20 SCAN VCC4 10µF (0603) LOCK DETECT IFOUT2– 0.1µF (0402) VCC3 16 IFOUT2+ 10µF (0603) VCC2 DNC 10pF (0402) LOOUT– 0.1µF (0402) CS 10µF (0603) 10µF (0603) REFIN DIVIDER LOOUT+ 10pF (0402) VCO LDO 7 SCLK 0.1µF (0402) 100pF (0402) 10 SDIO 10µF (0603) 10µF (0603) 9 EXPOSED PAD VCC1 100pF (0402) 10µF (0603) 10µF (0603) 150pF (0402) LOOUT IFOUT2 150pF (0402) 330nH +5V Figure 95. Basic Connections Diagram Rev. A | Page 35 of 57 330nH 150pF (0402) 12199-082 41 150pF (0402) 50Ω (0402) IFOUT1+ 22pF (0402) DNC 46 VCC10 10pF (0402) VCC11 0.1µF (0402) 10kΩ (0402) 150pF (0402) 10pF (0402) VCC12 10µF (0603) 6.8pF (0402) VCOVTUNE 0.1µF (0402) 10µF (0603) 10pF (0402) 10kΩ (0402) MUXOUT 0.1µF (0402) 10µF (0603) 10pF (0402) 0.1µF (0402) 10µF (0603) ADRF6612 Data Sheet BASIC CONNECTIONS PIN DESCRIPTION Table 22. Basic Connections Pin No. 5 V Power Mnemonic Description Basic Connection Decouple to GND with a 10 µF, a 0.1 µF, and a 10 pF capacitor as close to the pin as possible. 7 16 20, 41 27, 28, 29, 32, 33, 34 31 46 Internal LDO Nodes VCC1 VCC2 VCC3, VCC11 VCC4, VCC5, VCC6, VCC8, VCC9, VCC10 VCC7 VCC12 5 V VCO supply 5 V supply for SPI port 5 V biases for IF Channel 2 and IF Channel 1 5 V supplies for mixer LO amplifier 5 V supply for mixer LO divider chain 5 V supply for internal PLL Decouple to GND with a 10 µF and a 100 pF capacitor, as close to the pin as possible. 8, 9 10, 11, 12 15 DECL1, DECL2 DECL3, DECL4, DECL5 LDO1 30 LDO2 44 LDO3 45 LDO4 VCO LDO outputs External decoupling for VCO circuitry External decoupling for internal 2.5 V SPI LDO External decoupling for internal 3.3 V PLL/divider LDO External decoupling for internal 2.5 V PLL LDO External decoupling for internal 3.3 V PLL LDO GND 1 3, 6 24, 37 48 SPI 17 18 19 Connect directly to the PCB ground through a low impedance connection. GND GND GND GND External loop filter ground Common ground for external loop filter If stage, Channel 2 and Channel 1 ground External charge pump ground SDIO SCLK CS SPI port data input/output SPI port clock SPI port chip select External VCO or LO inputs DC block with 100 pF capacitors. 13, 14 22, 23 EXTVCOIN+, EXTVCOIN− LOOUT+, LOOUT− IFOUT2+, IFOUT2− Differential LO outputs Channel 2 differential IF outputs 25 RFBCT2 26 36 RFIN2 RFBCT1 35 38, 39 RFIN1 IFOUT1−, IFOUT1+ Internal mixer bias control for Channel 2 RF input Channel 2 single-ended RF input Internal mixer bias control for Channel 1 RF input Channel 1 single-ended RF input Channel 1 differential IF outputs DC block with 100 pF capacitors. Bias to 5 V supply with 330 nH inductors and dc block with 150 pF capacitors. Decouple to GND with a 10 pF and a 10 nF capacitor, as close to the pin as possible. DC block with a 22 pF capacitor. Decouple to GND with a 10 pF and a 10 nF capacitor, as close to the pin as possible. DC block with a 22 pF capacitor. Bias to 5 V supply with 330 nH inductors and dc block with 150 pF capacitors. VCOVTUNE REFIN CPOUT Control voltage for internal VCO External reference for internal PLL Charge pump output Output from external loop filter. MUXOUT Output for various internal analog signals, including PLL lock detect and VPTAT Do not connect Can be read directly from the pin; the user must be careful of loading effects, not a low impedance output. RF, Mixer, IF Path 4, 5 PLL/VCO 2 43 47 Other 42 21, 40 DNC Rev. A | Page 36 of 57 Input to external loop filter. Data Sheet ADRF6612 MIXER OPTIMIZATION As shown in Figure 96 and Figure 97, this tuning range can be further optimized by adding capacitance across the RF input in conjunction with tuning BAL_COUT. This can help to increase the low frequency range of the device significantly. 0 35 30 25 20 15 IFA_LIN = 0 IFA_LIN = 1 IFA_LIN = 2 IFA_LIN = 3 IFA_LIN = 4 IFA_LIN = 5 IFA_LIN = 6 IFA_LIN = 7 –2 10 5 –6 –8 0 –10 0 4 6 8 10 12 14 16 IFA_MAIN –12 Figure 98. IIP3 vs. Main (IFA_MAIN) and Linearity Bias (IFA_LIN) Level at IF Frequency = 50 MHz –14 35 –16 1300 30 1700 2100 2500 2900 RF FREQUENCY (MHz) Figure 96. Return Loss; Optimum COUT vs. Tuning Capacitor on RFIN Using a High Side LO 0 25 20 15 IFA_LIN = 0 IFA_LIN = 1 IFA_LIN = 2 IFA_LIN = 3 IFA_LIN = 4 IFA_LIN = 5 IFA_LIN = 6 IFA_LIN = 7 –2 10 –4 5 –6 –8 0 –10 4 6 8 10 12 14 16 Figure 99. IIP3 vs. Main (IFA_MAIN) and Linearity Bias (IFA_LIN) Level at IF Frequency = 100 MHz –14 35 –16 900 4pF 5.6pF 6.8pF 1300 30 1700 2100 RF FREQUENCY (MHz) 2500 2900 Figure 97. Return Loss; Optimum COUT vs. Tuning Capacitor on RFIN Using a Low Side LO IIP3 OPTIMIZATION 25 IIP3 (dBm) NO CAP 1pF 2pF 3.3pF 12199-097 –20 500 2 IFA_MAIN –12 –18 0 IFA_LIN = 8 IFA_LIN = 9 IFA_LIN = 10 IFA_LIN = 11 IFA_LIN = 12 IFA_LIN = 13 IFA_LIN = 14 12199-401 900 4pF 5.6pF 6.8pF IIP3 (dBm) –20 500 NO CAP 1pF 2pF 3.3pF 12199-096 –18 RETURN LOSS (dB) 2 In applications in which performance is critical, the ADRF6612 offers IIP3 optimization. The IF amplifier bias current can be reduced to trade performance vs. power consumption. This saves on the overall power at the expense of degraded performance. Figure 98 to Figure 101 show the IIP3 sweeps for all combinations of IFA main bias and linearity bias. The IIP3 vs. IFA main bias and linearity bias figures show both a surface and a contour plot in one figure. The contour plot is located directly underneath the surface plot. The best approach for reading the figure is to localize the 20 15 IFA_LIN = 0 IFA_LIN = 1 IFA_LIN = 2 IFA_LIN = 3 IFA_LIN = 4 IFA_LIN = 5 IFA_LIN = 6 IFA_LIN = 7 10 5 0 0 2 4 IFA_LIN = 8 IFA_LIN = 9 IFA_LIN = 10 IFA_LIN = 11 IFA_LIN = 12 IFA_LIN = 13 IFA_LIN = 14 6 8 IFA_MAIN 10 12 14 16 12199-402 RETURN LOSS (dB) –4 IFA_LIN = 8 IFA_LIN = 9 IFA_LIN = 10 IFA_LIN = 11 IFA_LIN = 12 IFA_LIN = 13 IFA_LIN = 14 12199-400 At lower input frequencies, more capacitance is needed. This increase is achieved by programming higher codes into BAL_COUT. At high frequencies, less capacitance is required; therefore, lower BAL_COUT codes are appropriate. peaks on the surface plot, which indicate maximum IIP3, and to follow the same color pattern to the contour plot to determine the optimized IFA main bias and linearity bias settings. IIP3 (dBm) RF INPUT BALUN INSERTION LOSS OPTIMIZATION Figure 100. IIP3 vs. Main (IFA_MAIN) and Linearity Bias (IFA_LIN) Level at IF Frequency = 150 MHz Rev. A | Page 37 of 57 ADRF6612 Data Sheet VGS PROGRAMMING 35 The ADRF6612 allows programmability for internal gate-to-source voltages for optimizing mixer performance over the desired frequency bands. The ADRF6612 default VGS setting is 0. Both channels of the ADRF6612 are programmed together using the same VGS setting. Power conversion gain, input IP3 NF, and input P1dB can be optimized, as shown in Figure 40, Figure 41, Figure 43, and Figure 44. 30 20 15 IFA_LIN = 0 IFA_LIN = 1 IFA_LIN = 2 IFA_LIN = 3 IFA_LIN = 4 IFA_LIN = 5 IFA_LIN = 6 IFA_LIN = 7 10 5 0 0 2 4 IFA_LIN = 8 IFA_LIN = 9 IFA_LIN = 10 IFA_LIN = 11 IFA_LIN = 12 IFA_LIN = 13 IFA_LIN = 14 6 8 IFA_MAIN LOW-PASS FILTER PROGRAMMING 10 12 14 16 12199-403 IIP3 (dBm) 25 Figure 101. IIP3 vs. Main (IFA_MAIN) and Linearity Bias (IFA_LIN) Level at IF Frequency = 200 MHz The ADRF6612 allows programmability for the low-pass filter terminating the mixer output. This filter helps to block sum term mixing products at the expense of some noise figure and gain and can significantly increase input IP3. The ADRF6612 default LPF setting is 0. Both channels of the ADRF6612 are programmed together using the same LPF settings. Power conversion gain, input IP3, NF, and input P1dB can be optimized, as shown in Figure 42, Figure 45, Figure 46, and Figure 49. Rev. A | Page 38 of 57 Data Sheet ADRF6612 Table 23. Recommended Optimum Settings for High Performance Mode (in Decimal) RF Frequency (MHz) 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 LO Frequency (MHz) 497 597 697 797 897 997 1097 1197 1297 1397 1497 1597 1697 1797 1897 1997 2097 2197 2297 2397 2497 2597 2697 2797 IFA_MAINBIAS 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 IFA_LINBIAS 11 11 11 11 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 BAL_COUT 14 14 10 10 10 10 10 6 6 4 4 4 4 4 4 4 2 2 2 2 2 2 0 0 LPF 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 VGS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BAL_COUT 14 14 10 10 10 10 10 6 6 4 4 4 4 4 4 4 2 2 2 2 2 2 0 0 LPF 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 VGS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 24. Recommended Optimum Settings for High Efficiency Mode (in Decimal) RF Frequency (MHz) 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 LO Frequency (MHz) 497 597 697 797 897 997 1097 1197 1297 1397 1497 1597 1697 1797 1897 1997 2097 2197 2297 2397 2497 2597 2697 2797 IFA_MAINBIAS 5 5 5 5 5 5 5 7 7 7 7 7 7 7 7 7 13 13 13 13 13 13 13 13 IFA_LINBIAS 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 Rev. A | Page 39 of 57 ADRF6612 Data Sheet REGISTER SUMMARY Table 25. Register Summary Reg. Name Bits Bit 7 0x00 SOFT_RESET [15:8] [7:0] [15:8] LO_LDO_EN [7:0] LO_DRV_EN [15:8] DIV_MODE [7:0] 0x01 ENABLES 0x02 INT_DIV 0x03 FRAC_DIV 0x04 MOD_DIV 0x10 IF_BIAS 0x20 CP_CTRL 0x4A VCO_BUF_LDO 0x7C VARIATION1 0x7D VARIATION2 0x7E VARIATION3 0x7F VARIATION4 Bit 5 Bit 4 LO2_ENP BALUN_EN VCOBUF_LDO_EN REF_BUF_EN Bit 3 UNUSED BLEED_POLARITY UNUSED Bit 2 SOFT_RESET[15:8] SOFT_RESET[7:0] LO1_ENP DIV2P5_EN VCO_EN DIV_EN INT_DIV[14:8] INT_DIV[7:0] [15:8] [7:0] [15:8] [7:0] [15:8] IFA_LIN_HIEFFP IFA_MAIN_HIEFFP IFA_LINSLOPE [7:0] IFA_LINBIAS[1:0] IFA_LINBIAS_EN [15:8] [7:0] 0x21 PFD_CTRL1 [15:8] [7:0] 0x22 VCO_CTRL1 [15:8] [7:0] 0x30 BALUN_CTRL [15:8] [7:0] 0x40 PFD_CTRL2 [15:8] [7:0] 0x42 DITH_CTRL1 [15:8] [7:0] 0x43 DITH_CTRL2 [15:8] [7:0] 0x44 SYNTH_FCNTN_CTRL [15:8] [7:0] 0x45 VCO_CTRL2 [15:8] [7:0] 0x46 VCO_CTRL3 [15:8] [7:0] 0x47 VCO_CNTR_CTRL [15:8] [7:0] 0x48 VCO_CNTR_RB [15:8] [7:0] 0x49 VTUNE_DAC_CTRL Bit 6 CP_EN RW LO_PATH_EN LDO_3P3_EN 0x0000 RW 0x0058 RW 0x0250 RW 0x0600 RW IFA_MAINSLOPE IFA_MAINBIAS IFA_LINBIAS[3:2] IFA_MAINBIAS_EN CSCALE REF_MUX_SEL PFD_POLARITY REFSEL[7:0] LO_DIV VGS UNUSED ABLDLY[2:0] [15:8] [7:0] [15:8] [7:0] [15:8] IS_RESET [7:0] [15:8] [7:0] [15:8] IS_RESET [7:0] [15:8] [7:0] PWRUPRX VCO_LDO_EN FRAC_DIV[15:8] FRAC_DIV[7:0] MOD_DIV[15:8] MOD_DIV[7:0] BAL_COUT VCO_CNTR_DONE Reset 0x0000 R VCO_LDO_R4 VCO_BAND_SRC Bit 0 0x02B5 RW 0x0026 RW BLEED LO_DRV_LVL UNUSED UNUSED[1:0] Bit 1 REFSEL[11:8] 0x0003 RW VCO_LDO_R2 VCO_SEL LPF RESERVED ABLDLY[3] CLKEDGE 0x000A RW CPCTRL UNUSED[11:4] UNUSED[3:0] DITH_EN DITH_MAG DITH_VAL_H DITH_VAL_L[15:8] DITH_VAL_L[7:0] UNUSED[9:2] DIV_SDM_DIS VCOCNT_CG_DIS BANDCAL_CG_DIS SDM_CG_DIS SDM_DIVD_CLR BANDCAL_DIVD_CLR UNUSED BAND UNUSED VCO_BAND UNUSED[11:4] UNUSED[3:0] VCO_CNTR_REFCNT VCO_CNTR_CLR VCO_CNTR_EN VCO_CNTR_RB[15:8] VCO_CNTR_RB[7:0] UNUSED VTUNE_DAC_SLOPE VTUNE_DAC_OFFSET[7:0] UNUSED VCOBUF_LDO_R4 VCO_SW_CAL BE_VER SIF_VER 0x0000 RW 0x0010 RW 0x000E RW 0x0001 RW 0x0000 RW 0x0020 RW 0x0000 RW 0x0000 RW 0x0000 R VTUNE_DAC_OFFSET[8] 0x0000 RW 0x0000 RW VCOBUF_LDO_R2 VARIANT 0x0000 R FE_VER PART_ID[11:8] 0x2001 R PART_ID[7:0] VCO_SW_CAL BE_VER SIF_VER VARIANT 0x0001 R FE_VER PART_ID[11:8] PART_ID[7:0] Rev. A | Page 40 of 57 0x2001 R Data Sheet ADRF6612 REGISTER DETAILS Address: 0x00, Reset: 0x0000, Name: SOFT_RESET Table 26. Bit Descriptions for SOFT_RESET Bits [15:0] Bit Name SOFT_RESET Settings 0 Description Soft reset bit Any write to this register will assert soft reset command Reset 0x0 0x0 Access R R Address: 0x01, Reset: 0x0000, Name: ENABLES Table 27. Bit Descriptions for ENABLES Bits 15 14 13 12 11 [10:9] Bit Name LO_LDO_EN LO2_ENP BALUN_EN LO1_ENP DIV2P5_EN PWRUPRX Settings 0x0 0x1 0x2 0x3 8 7 LO_PATH_EN LO_DRV_EN Description Power up LO LDO LO 2 enable Input Balun enable LO 1 enable Enable dividers 2.5 V LDO Power up Rx Power down both mixer channels Power up mixer Channel 1 Power up mixer Channel 2 Power up both mixer channels External LO path enable LO driver enable Rev. A | Page 41 of 57 Reset 0x0 0x0 0x0 0x0 0x0 0x0 Access RW RW RW RW RW RW 0x0 0x0 RW RW ADRF6612 Bits 6 5 4 3 2 1 0 Bit Name VCOBUF_LDO_EN REF_BUF_EN VCO_EN DIV_EN CP_EN VCO_LDO_EN LDO_3P3_EN Data Sheet Settings Description VCO buffer LDO enable Reference buffer enable Power up VCOs Power up dividers Power up charge pump Power up VCO LDO Power up 3.3 V LDO Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access RW RW RW RW RW RW RW Reset 0x0 Access RW 0x58 RW Reset 0x250 Access RW Reset 0x600 Access RW Address: 0x02, Reset: 0x0058, Name: INT_DIV Table 28. Bit Descriptions for INT_DIV Bits 15 Bit Name DIV_MODE Settings 0 1 [14:0] INT_DIV Description Set fractional/integer mode Fractional Integer Set divider INT value Address: 0x03, Reset: 0x0250, Name: FRAC_DIV Table 29. Bit Descriptions for FRAC_DIV Bits [15:0] Bit Name FRAC_DIV Settings Description Set divider FRAC value Address: 0x04, Reset: 0x0600, Name: MOD_DIV Table 30. Bit Descriptions for MOD_DIV Bits [15:0] Bit Name MOD_DIV Settings Description Set divider MOD value Rev. A | Page 42 of 57 Data Sheet ADRF6612 Address: 0x10, Reset: 0x02B5, Name: IF_BIAS Table 31. Bit Descriptions for IF_BIAS Bits 15 14 [13:12] [11:10] [9:6] 5 [4:1] 0 Bit Name IFA_LIN_HIEFFP IFA_MAIN_HIEFFP IFA_LINSLOPE IFA_MAINSLOPE IFA_LINBIAS IFA_LINBIAS_EN IFA_MAINBIAS IFA_MAINBIAS_EN Settings Description Linearity RDAC: 0 = high performance mode, 1 = high efficiency mode Main RDAC: 0 = high performance mode, 1 = high efficiency mode Linearity Slope Adj for IF amps (IPMix) Main Slope Adj for IF amps (IPMix) Linearity Bias Adj for IF amps (IPMix) Enable internal Linearity Bias Adj for IF amps (IPMix) Main Bias Adj for IF Amps (IPMix) Enable internal Main Bias Adj for IF amps (IPMix) Reset 0x0 0x0 0x0 0x0 0xa 0x1 0xa 0x1 Access RW RW RW RW RW RW RW RW Reset 0x0 0x0 0x0 0x26 Access RW RW RW RW Address: 0x20, Reset: 0x0026, Name: CP_CTRL Table 32. Bit Descriptions for CP_CTRL Bits [15:14] [13:8] 7 [6:0] Bit Name UNUSED CSCALE BLEED_POLARITY BLEED Settings Description Unused Charge pump current adjust Charge pump bleed current polarity Charge pump bleed Rev. A | Page 43 of 57 ADRF6612 Data Sheet Address: 0x21, Reset: 0x0003, Name: PFD_CTRL1 Table 33. Bit Descriptions for PFD_CTRL1 Bits 15 [14:13] Bit Name UNUSED REF_MUX_SEL Settings 000 001 010 011 100 101 110 111 12 PFD_POLARITY 0 1 [11:0] REFSEL Description Unused REF output divide ratio/VPTAT/SCAN/LOCK_DET LOCK_DET VPTAT REFCLK REFCLK/2 REFCLKx2 REFCLK/8 REFCLK/4 SCAN PFD polarity POS NEG REF input divide ratio Rev. A | Page 44 of 57 Reset 0x0 0x0 Access RW RW 0x0 RW 0x3 RW Data Sheet ADRF6612 Address: 0x22, Reset: 0x000A, Name: VCO_CTRL1 15 14 13 12 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 0 1 0 0 [15:12] VCO_LDO_R4 (R/W) VCO LDO R4 control setting [2:0] VCO_SEL (R/W) Select VCO core/external LO 000: VCO_0 = 4.6 GHz to 5.7 GHz. 001: VCO_1 = 4.02 GHz to 4.6 GHz. 010: VCO_2 = 3.5 GHz to 4.02 GHz. 011: VCO_3 = 2.85 GHz to 3.5 GHz. 100: None. 101: None. 110: External LO/VCO. 111: None. [11:8] VCO_LDO_R2 (R/W) VCO LDO R2 control setting [7:6] LO_DRV_LVL (R/W) External LO am plitude 00: -0.8 dBm /15 m A. 01: 4.6 dBm /28 m A. 10: 7.5 dBm /40 m A. 11: 9.2 dBm /49 m A. [5:3] LO_DIV (R/W) LO_DIV 00: DIV1. 01: DIV2. 10: DIV4. 11: DIV8. Table 34. Bit Descriptions for VCO_CTRL1 Bits [15:12] [11:8] [7:6] Bit Name VCO_LDO_R4 VCO_LDO_R2 LO_DRV_LVL Settings 00 01 10 11 [5:3] LO_DIV 00 01 10 11 [2:0] VCO_SEL 000 001 010 011 100 101 110 111 Description VCO LDO R4 control setting VCO LDO R2 control setting External LO amplitude −0.8 dBm/15 mA 4.6 dBm/28 mA 7.5 dBm/40 mA 9.2 dBm/49 mA LO_DIV DIV1 DIV2 DIV4 DIV8 Select VCO core/external LO VCO_0 = 4.6 GHz to 5.7 GHz VCO_1 = 4.02 GHz to 4.6 GHz VCO_2 = 3.5 GHz to 4.02 GHz VCO_3 = 2.85 GHz to 3.5 GHz None None External LO/VCO None Rev. A | Page 45 of 57 Reset 0x0 0x0 0x0 Access RW RW RW 0x1 RW 0x2 RW ADRF6612 Data Sheet Address: 0x30, Reset: 0x0000, Name: BALUN_CTRL Table 35. Bit Descriptions for BALUN_CTRL Bits [15:14] [13:11] [10:8] [7:4] [3:0] Bit Name UNUSED VGS LPF BAL_COUT RESERVED Settings Description Unused Mixer VGS bias Mixer output IF low-pass filter Set balun COUT (both channels) Reserved, set to 0x0 Reset 0x0 0x0 0x0 0x0 0x0 Access RW RW RW RW RW Reset 0x0 0x0 Access RW RW Address: 0x40, Reset: 0x0010, Name: PFD_CTRL2 Table 36. Bit Descriptions for PFD_CTRL2 Bits [15:9] [8:5] Bit Name UNUSED ABLDLY Settings 00 01 10 11 Description Unused Set antibacklash delay 0 ns 0.5 ns 0.75 ns 0.9 ns Rev. A | Page 46 of 57 Data Sheet Bits [4:2] Bit Name CPCTRL ADRF6612 Settings 000 001 010 011 100 101 110 111 [1:0] CLKEDGE 00 01 10 11 Description Set charge pump control Both ON Pump DWN Pump UP Tristate PFD Reset 0x4 Access RW Set PFD edge sensitivity Div and REF DWN edge Div DWN edge, REF UP edge Div UP edge, REF DWN edge Div and REF UP edge 0x0 RW Reset 0x0 0x1 Access RW RW 0x3 0x0 RW RW Reset 0x1 Access RW Address: 0x42, Reset: 0x000E, Name: DITH_CTRL1 Table 37. Bit Descriptions for DITH_CTRL1 Bits [15:4] 3 Bit Name UNUSED DITH_EN Settings 0 1 [2:1] 0 DITH_MAG DITH_VAL_H Description Unused register bits Set dither enable Disable Enable Dither magnitude High bit of 17 bit dither value Address: 0x43, Reset: 0x0001, Name: DITH_CTRL2 Table 38. Bit Descriptions for DITH_CTRL2 Bits [15:0] Bit Name DITH_VAL_L Settings Description Low 16 bits of 17 bit dither value Rev. A | Page 47 of 57 ADRF6612 Data Sheet Address: 0x44, Reset: 0x0000, Name: SYNTH_FCNTN_CTRL Table 39. Bit Descriptions for SYNTH_FCNTN_CTRL Bits [15:6] 5 4 3 2 1 0 Bit Name UNUSED DIV_SDM_DIS VCOCNT_CG_DIS BANDCAL_CG_DIS SDM_CG_DIS SDM_DIVD_CLR BANDCAL_DIVD_CLR Settings Description Unused Disable SDM divider Disable BIST clock Disable bandcal clock Disable SDM clock SDM_DIVD_CLR BANDCAL_DIVD_CLR Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access RW RW RW RW RW RW RW Reset 0x0 0x0 Access RW RW 0x20 RW Address: 0x45, Reset: 0x0020, Name: VCO_CTRL2 Table 40. Bit Descriptions for VCO_CTRL2 Bits [15:8] 7 Bit Name UNUSED VCO_BAND_SRC Settings 0 1 [6:0] BAND Description Unused Set VCO band source Automatic Manual Set VCO band Rev. A | Page 48 of 57 Data Sheet ADRF6612 Address: 0x46, Reset: 0x0000, Name: VCO_CTRL3 Table 41. Bit Descriptions for VCO_CTRL3 Bits [15:8] 7 [6:0] Bit Name UNUSED VCO_CNTR_DONE VCO_BAND Settings Description Unused Read back BIST counter status Read back output of bandcap mux Reset 0x0 0x0 0x0 Access RW R R Reset 0x0 0x0 0x0 0x0 Access RW RW RW RW Reset 0x0 Access R Address: 0x47, Reset: 0x0000, Name: VCO_CNTR_CTRL Table 42. Bit Descriptions for VCO_CNTR_CTRL Bits [15:4] [3:2] 1 0 Bit Name UNUSED VCO_CNTR_REFCNT VCO_CNTR_CLR VCO_CNTR_EN Settings Description Unused BIST counter integration interval Clear BIST counter Enable BIST counter Address: 0x48, Reset: 0x0000, Name: VCO_CNTR_RB Table 43. Bit Descriptions for VCO_CNTR_RB Bits [15:0] Bit Name VCO_CNTR_RB Settings Description Read back output of BIST counter Rev. A | Page 49 of 57 ADRF6612 Data Sheet Address: 0x49, Reset: 0x0000, Name: VTUNE_DAC_CTRL Table 44. Bit Descriptions for VTUNE_DAC_CTRL Bits [15:14] [13:9] [8:0] Bit Name UNUSED VTUNE_DAC_SLOPE VTUNE_DAC_OFFSET Settings Description Unused Set VTUNE PTAT DAC Set VTUNE ZTAT DAC Reset 0x0 0x0 0x0 Access RW RW RW Reset 0x0 0x0 0x0 Access RW RW RW Reset 0x0 0x0 0x0 0x0 0x0 Access R R R R R Address: 0x4A, Reset: 0x0000, Name: VCO_BUF_LDO Table 45. Bit Descriptions for VCO_BUF_LDO Bits [15:8] [7:4] [3:0] Bit Name UNUSED VCOBUF_LDO_R4 VCOBUF_LDO_R2 Settings Description Unused VCOBUF LDO R4 control VCOBUF LDO R2 control Address: 0x7C, Reset: 0x0000, Name: VARIATION1 Table 46. Bit Descriptions for VARIATION1 Bits 15 14 [13:8] [7:4] [3:0] Bit Name IS_RESET VCO_SW_CAL VARIANT BE_VER FE_VER Settings Description IS reset VCO switch calibration Experimental variant Back end of line revision Front end of line revision Rev. A | Page 50 of 57 Data Sheet ADRF6612 Address: 0x7D, Reset: 0x2001, Name: VARIATION2 Table 47. Bit Descriptions for VARIATION2 Bits [15:12] [11:0] Bit Name SIF_VER PART_ID Settings Description Serial interface version Product ID Reset 0x2 0x1 Access R R Reset 0x0 0x0 0x0 0x0 0x1 Access R R R R R Reset 0x2 0x1 Access R R Address: 0x7E, Reset: 0x0001, Name: VARIATION3 Table 48. Bit Descriptions for VARIATION3 Bits 15 14 [13:8] [7:4] [3:0] Bit Name IS_RESET VCO_SW_CAL VARIANT BE_VER FE_VER Settings Description IS reset VCO switch calibration Experimental variant Back end of line revision Front end of line revision Address: 0x7F, Reset: 0x2001, Name: VARIATION4 Table 49. Bit Descriptions for VARIATION4 Bits [15:12] [11:0] Bit Name SIF_VER PART_ID Settings Description Serial interface version Product ID Rev. A | Page 51 of 57 Rev. A | Page 52 of 57 Figure 102. Evaluation Board, Main Circuitry VCC_LO N P 1 AGND N P VCC_IF RED C16 0.1UF C19 0.1UF C6 0.1UF C3 0.1UF C2 0.1UF VCC_IF C92 10UF (VCCIF1) (VCCIF2) VCC_LO RED VCC_IF VCC_IF (VCC5SPI) VCC_SYNTH (VCC5VCO) VCC_SYNTH (VCC5PLL) VCC_SYNTH 1 AGND C8 10UF GND4 BLK 1 C5 10UF AGND C11 100PF LDO2P5SPI AGND 2 3 4 5 1 100PF 1 C23 39PF VCOTUNE R41 0 C107 10UF 0 R35 AGND C100 100PF AGND 4 PRI AGND C108 100PF LDO2P5PLL C14 10UF T2 C103 100PF 100PF 100PF 0 R97 6 TC1-1-43A+ AT224-1 AGND 4 AGND C57 100PF AGND AGND 100PF 100PF 1 2 3 4 5 6 7 8 9 10 11 12 C58 10UF C33 150PF AGND C32 150PF AGND L1 330NH L2 330NH CPOUT PLL_REF_IN 1000PF C54 GND VCOVTUNE GND EXTVCOIN+ EXTVCOINGND VCC1 DECL1 DECL2 DECL3 DECL4 DECL5 AGND LDO3P3DIV AGND C30 0.1UF C31 C28 VCC_IF AGND AGND R19 50 C24 TBD0805 DNI AGND 2 3 4 5 AGND C105 10UF AGND VCC_SYNTH C15 100PF PLL REF IN AGND C29 0.1UF VCC_IF PLL_REF_IN JOHNSON142-0701-851 1 CPOUT BLU LDO3P3PLL 3 SEC 1 AGND AGND PRI R98 0 1 C89 C104 10UF 100PF AGND C102 10UF C27 C25 C18 1500PF AGND C101 100PF 3 SEC 1 AGND R7 910 TC1-1-43A+ AT224-1 6 AGND C26 10UF T1 EXT VCO OUTPUT C20 .033UF R8 1.8K C22 560PF R10 20K VTUNE BLU JOHNSON142-0701-851 C82 LO_OUT AGND 2 3 4 5 ALL 100PF DECOUPLING CAPS SHOULD BE AS N P 1 1 AGND EXT_LOIN JOHNSON142-0701-851 GND3 BLK AGND CLOSE AS POSSIBLE TO THE PINS ON THE CHIP AGND C1 10UF VCC_SYNTH RED VCC_SYNTH AGND C17 100PF AGND C21 100PF AGND C12 100PF AGND C9 100PF AGND C7 100PF AGND 1 AGND GND2 BLK R96 1K DNI VCC_IF 1 ADRF6612ACPZ U1 AGND C35 150PF AGND C34 150PF 330NH L4 330NH L3 R93 1K DNI LDO2P5SPI VCC_SYNTH DATA CLK LE VCC_IF GND1 BLK VCC_SYNTH LDO3P3PLL LDO2P5PLL PAD 48 47 46 45 44 43 42 41 40 39 38 37 1 R95 1K DNI TP5 BLU 150PF C37 150PF C36 150PF C39 150PF C38 AGND 36 35 34 33 32 31 30 29 28 27 26 25 R94 1K DNI 1 3 2 1 TP4 BLU AGND C42 22PF C43 22PF VCC_LO VCC_LO VCC_LO VCC_SYNTH LDO3P3DIV VCC_LO VCC_LO VCC_LO T5 C44 10000PF MUXOUT C40 10PF 4 6 4 6 AGND C45 10000PF AGND AGND C59 150PF TC4-1W+ 3 2 1 T4 TC4-1W+ C60 150PF C41 10PF RFBCT1 RFIN1 VCC10 VCC9 VCC8 VCC7 LDO2 VCC6 VCC5 VCC4 RFIN2 RFBCT2 EP GND CPOUT VCC12 LDO4 LDO3 REFIN MUXOUT VCC11 DNC IFOUT1+ IFOUT1GND LOOUT+ LOOUTLDO1 VCC2 SDIO SCLK CS_N VCC3 DNC IFPOUT2+ IFOUT2GND 13 14 15 16 17 18 19 20 21 22 23 24 DNI AGND 2 0 R37 AGND 4 5 IF2N IF2N JOHNSON142-0701-851 0 DNI R40 3 5 IF2P 1 3 AGND 2 DNI AGND 2 3 3 3 AGND JOHNSON142-0701-851 1 IF2P AGND 2 PINS 27,28,29,32,33,34 CLOSE AS POSSIBLE TO AGND IF OUTPUT 2 R16 0 4 SHOULD BE LOCATED AS RF_IN2 JOHNSON142-0701-851 1 R18 0 DNI 3 AGND RF_IN1 JOHNSON142-0701-851 1 1 2 AGND 2 DNI JOHNSON142-0701-851 MUX_OUT 2 AGND IF1N JOHNSON142-0701-851 1 IF1N CR3 SML-210MTT86 R36 2K 0 R39 IF OUTPUT 1 IF1P JOHNSON142-0701-851 1 IF1P THESE SIX 10PF CAPS AGND R15 0 AGND R17 0 DNI 0 R38 3 4 4 4 4 4 5 5 5 5 AGND C50 10PF 5 AGND C49 10PF AGND C48 10PF AGND C47 10PF AGND C46 10PF AGND C10 10PF AGND C4 10PF C91 0.1UF C90 0.1UF C56 0.1UF C55 0.1UF C53 0.1UF C52 0.1UF C51 0.1UF VCC_LO (VCC2LO4) VCC_LO (VCC2LO3) VCC_LO (VCC2LO2) VCC_LO (VCC5DIV) VCC_SYNTH (VCC1LO2) VCC_LO (VCC1LO3) VCC_LO (VCC1LO4) An evaluation board is available for the ADRF6612. The standard evaluation board schematic is presented in Figure 102. The USB interface circuitry schematic is presented in Figure 104. The evaluation board layout is shown in Figure 105 and Figure 106. 12199-092 C A 1 ADRF6612 Data Sheet EVALUATION BOARD The evaluation board is fabricated using Rogers® 3003 material. Table 50 details the configuration for the mixer characterization. The evaluation board software is available on the ADRF6612 product page. 0.1UF C61 3V3_USB DGND 0.1UF C63 897-43-005-00-100001 GND PINS SNS1 2 DGND 0.1UF C64 0.1UF C65 DECOUPLING FOR U1 AGND SNS 1 DGND 0.1UF C66 0.1UF C69 10PF C67 C68 3V3_USB DGND 0.1UF 0.1UF 14 12 13 11 10 9 8 7 6 5 4 3 2 G4 G3 DGND 3V3_USB 1 C62 DGND G2 G1 5 4 52 GND RESET_N PA3_WU2 AVCC R28 2K R27 2K RESERVED IFCLK GND VCC AGND DMINUS A1 U2 8 VCC A0 C72 0.1UF 10PF C73 DGND A2 6 5 SCL SDA 7 WC_N GND 4 24LC64-I-SN 3 2 1 3V3_USB DGND CTL0_FLAGA CTL1_FLAGB CTL2_FLAGC VCC PA0_INT0_N PA1_INT1_N PA2_SLOE PA4_FIFOADR0 DPLUS PA5_FIFOADR1 PA6_PKTEND PA7_FLAGD_SLCS_N 29 30 31 32 33 34 35 36 37 38 39 40 41 42 U4 3V3_USB AGND CY7C68013A-56LTXC 44 XTALIN XTALOUT AVCC RDY1_SLWR RDY0_SLRD 55 VCC 17 SDA 16 3 PAD PAD 15 VCC 3V3_USB PB0_FD0 18 2 54 CLKOUT 3V3_USB 53 GND 19 1 50 PD6_FD14 P2 51 PD7_FD15 PB1_FD1 20 PB2_FD2 21 PB3_FD3 5V_USB DGND 49 PD5_FD13 C71 24 22PF 56 GND SCL 48 PD4_FD12 23 PB4_FD4 22 DGND 25 1 VCC CASE 4 2 26 DGND 3 PB7_FD7 43 WAKEUP GND 28 C70 PD1_FD9 GND 47 PD3_FD11 PB5_FD5 46 PD2_FD10 PB6_FD6 45 PD0_FD8 VCC 27 3V3_USB 22PF DGND CR2 2K R29 100K R30 0.1UF C74 3V3_USB SML-210MTT86 Y1 DGND R31 JP1 JP2 JP3 5V_USB JPR0402 1 JPR0402 1 JPR0402 1 0.1UF C75 100K SML-210MTT86 Rev. A | Page 53 of 57 DGND CR1 2K R32 2 2 2 C Figure 103. Evaluation Board, Legacy USB Interface A C A 24.000000MEGHZ DGND DGND 330PF DNI DGND TBD0402 C76 DNI R25 1K 3V3_USB 1UF C77 DGND DNI 1K R24 U3 IN1 OUT1 1K R22 2 1 DGND DGND DGND DNI IN2 OUT2 6 3 SD_N FB PAD GND PAD 5 8 7 ADP3334ACPZ DGND DNI 330PF TBD0402 C78 78.7K R33 3V3_USB 1000PF C80 DGND DNI 330PF TBD0402 C79 140K R21 LE DATA CLK 1 1 BLK DNI DGND TP2 DGND 1UF C81 TP1 BLK DNI Data Sheet ADRF6612 12199-093 R9 100K DNI R100 100K DNI R99 TBD0603 DNI VSS 4 DGND A0 A1 A2 SCL WP 8 VCC SDA 5 DGND 24LC32A-I/MS E014160 JEDEC_TYPE=MSOP8 1 2 3 6 7 U11 DNI DATA TP6 1 JPR0402 DNI JP6 2 DATA_SDP 0 R6 0 R34 DNI DNI TP7 JP4 2 CLK_SDP JPR0402 DNI CLK 1 Figure 104. Evaluation Board, ADI SDP-S USB Interface Rev. A | Page 54 of 57 DGND DGND 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 P7 DNI FX8-120S-SV(21) TP8 VCC_SYNTH JP5 2 LE_SDP LE 1 JPR0402 DNI 0 R1 DNI DGND 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 P7 FX8-120S-SV(21) ADRF6612 Data Sheet 12199-094 Data Sheet ADRF6612 Table 50. Evaluation Board Configuration C3, C4, C5, C28, C29, C30, L1, L2, L3, L4, R20, R21, R22, R23, T1, T2 C17 R1, R2 Description Power supply decoupling. Nominal supply decoupling consists of a 0.1 µF capacitor to ground in parallel with a 10 pF capacitor to ground positioned as close to the device as possible. Default Conditions C1, C2, C26, C27 = 0.1 µF (size 0402), C8, C11, C12, C13, C14, C15, C18, C19, C20, C23 = 10 pF (size 0402) RF input interface. The input channels are ac-coupled through C6 and C24. C7 and C25 provide bypassing for the center tap of the RF input baluns. IF output interface. The open-collector IF output interfaces are biased through pull-up choke inductors L1, L2, L3, and L4. T1 and T2 are 4:1 impedance transformers used to provide single-ended IF output interfaces, with C5 and C30 providing center-tap bypassing. Remove R21 and R22 for balanced output operation. LO interface. C17 provides ac coupling for the LOIP local oscillator input. Bias control. R1and R2 set the bias point for the internal IF amplifier. C6, C24 = 22 pF (size 0402), C7, C25 = 22 pF (size 0402) C3, C4, C5, C28, C29, C30 = 120 pF (size 0402), L1, L2, L3, L4 = 470 nH (size 0603), R20, R23 = open, R21, R22 = 0 Ω (size 0402), T1, T2 = TC4-1W+ (Mini-Circuits®) C17 = 22 pF (size 0402) R1, R2 = 910 Ω (size 0402) 12199-205 Components C1, C2, C8, C11, C12, C13, C14, C15, C18, C19, C20, C23, C26, C27 C6, C7, C24, C25 Figure 105. Evaluation Board, Top Layer Rev. A | Page 55 of 57 Data Sheet 12199-206 ADRF6612 Figure 106. Evaluation Board, Bottom Layer Rev. A | Page 56 of 57 Data Sheet ADRF6612 OUTLINE DIMENSIONS 0.30 0.25 0.18 PIN 1 INDICATOR 37 36 48 1 0.50 BSC 5.70 5.60 SQ 5.50 EXPOSED PAD TOP VIEW 0.80 0.75 0.70 END VIEW PKG-004452 SEATING PLANE 0.50 0.40 0.30 24 13 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF PIN 1 INDICATOR 0.20 MIN 5.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-4. 02-29-2016-A 7.10 7.00 SQ 6.90 Figure 107. 48-Lead Lead Frame Chip Scale Package [LFCSP] 7 mm × 7 mm Body and 0.75 mm Package Height (CP-48-13) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADRF6612ACPZ-R7 ADRF6612-EVALZ 1 Temperature Range −40°C to +85°C Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS Compliant Part. ©2014–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12199-0-5/16(A) Rev. A | Page 57 of 57 Package Option CP-48-13
