MOSIS REPORT:
Final Project
Flip-flop Design with Option of Set/Reset, Clear
or Enable
COURSE NO: ECE 491
DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
UNIVERSITY OF TENNESSEE, TN-37996
SPRING 2007
ABSTRACT:
A flip-flop design with either a set/reset, clear, or enable is presented. Since students
were given the option, several variations will be discussed. The two flip-flops designed
by students were a JK flip-flop and a D flip-flop. Students used truth tables and
Karnaugh maps to help with the design and layout of their flip-flops. Multiple loads were
simulated to test the rise time, fall time, delay, and functionality of the circuit.
INTRODUCTION:
Flip-flops are a fundamental element of digital logic and can be used in state machines,
counters, memory, and other synchronous logic circuits. They are the basic storage
element and can be used to prevent race conditions as the output values of the flip-flop
only change on the clock edge. Flip-flops are most often created by cascading two latches
together in a master-slave configuration. The input therefore doesn’t propagate through
both latches as one latch is always in a hold phase. The slave latch is clocked on the
opposite phase of the master latch, so it isn’t activated until the clock changes state.
Flip-flops can be designed and reproduced with standard NAND/NOR/NOT logic, but
they can also be designed at the transistor level and as a result use fewer circuit
components. This has the effect of smaller rise & fall times for the flip-flop.
DESIGN APPROACH:
A J-K biphase CMOS master-slave schematic is shown in Figure 1. It uses cross-coupled
NOR gates that act as latches and has output buffers which are just inverters that reduce
the effect higher capacitive loads have on rise & fall times. Output values change on the
falling edge of the clock. The W/L ratios are given to apply to any process, though our
minimum length was 0.6 μm. The ratios for the latches are smaller than the NMOS drive
transistors so the drive transistors will dominate during state transitions.
Figure 1: JK Flip-Flop Design Circuit
The enable works by controlling when the clock changes through an additional NAND
gate. The output of the NAND is fed into an inverter to produce an AND of the Enable
and Clk inputs. The “true” clock signals from the perspective of the flip-flop are taken
directly from the output of the NAND and NOT gates.
Figure 2 : Enable Logic
The master-slave D flip-flop can be made using nand gates and an inverter. The D flipflop is designed from the truth table. The truth table of a D flip-flop states that when the
clock is on the falling edge and the D is set to zero, Q should be zero. When the clock is
on the falling edge and D is set to one, Q should be one. Table 1 shows the truth table for
a D flip-flop. This table works only for this particular version of the D flip-flip. If there
was an inverter after the CLK and before the other inverter the table would be different
and the change would be on the rising side of the clock. The following circuit (figure 3)
was used to design a D flip-flop with a set/reset. For the inverters in the circuit that did
not have specific width and length ratios, inverters built earlier in the semester were used.
Everything else was built using the same ratios specified.
Figure 3: Schematic of D flip-flop
LAYOUT DESIGN:
The next phase of design was drawing the layout of the transistors for the silicon
masks. The W/L ratios were respected for this, and the active regions for the crosscoupled NOR gates were combined to reduce their size. The wiring still ends up taking
most of the space in the layout, and some of this could be reduced by combining more
active regions still, as seen in the NAND and inverter for the Clk and Enable inputs. The
output buffers use a little larger W/L (actual 15μm/0.6μm and 10μm/0.6μm) that allows
the flip-flop to drive a larger load. Overall, the layout essentially mimics the positioning
seen in the schematic.
The total layout area is approximately 90μm x 90μm. A DRC check was ran to
ensure that no errors in design were violated. The extracted view of the layout was then
created to check parasitic capacitances and perform post-layout Spectre simulation. The
LVS tool was also used to see if the layout mapped correctly back to the schematic,
which it did and the netlists matched.
Figure 4 : CMOS J-K Flip-Flop Layout
Figure 5 : CMOS J-K Flip-Flop Layout Extraction
Figure 6 : LVS Output
SIMULATION RESULTS
Simulation results from the extracted layout are shown below in Figure 7. When
compared to results done to just the schematic, there is a larger dip seen between the
initial indeterminate state of Q and when the output is first initialized with a set. This tells
me that the window of time between state transitions is a little longer in my layout than
for the schematic simulation.
Figure 7 : Post-Layout Spectre Simulation
After correct operation was ensured, I checked the rise and fall times of the flipflop by measuring the time it took for the output value to change from 30% value to 70%
value (1.5V to 3.5V for rise, 3.5V to 1.5V for fall). The rise and fall times for no load are
seen below.
Capacitive loads of 0.5pF, 1pF, 10pF, and 15pF were added to the Q output of
the flip-flop to determine how well the output buffers worked for the circuit.
The capacitive load simulates adding another element to the circuit, such as
another flip-flop used in a counter. The 10pF and 15pF loads were chosen to simulate the
capacitances commonly seen for a pad frame, and the lower capacitances could represent
interconnects. The delay vs. load curve for each of these measurements is plotted in
Figure 9.
Delay vs Load
12
10
R2 = 1
8
Load (pF)
Rise Delay
Fall Delay
(ns)
(ns)
15
10.18
7.666
10
6.77
5.0428
1
0.716
0.55
0.5
0.401
0.328
0
0.069
0.085
R2 = 0.9999
6
4
Rise
Fall
2
0
0
5
10
Load (pF)
Figure 8 : Delay vs Load Curve For Rise & Fall Times
15
20
The R2 value for both the curves is very close to 1, indicating that the relationship
between capacitive load and the resulting rise and fall delay times is virtually linear. The
fall delay is generally longer than that for the rise, so there is a small mismatch in the nchannel and p-channel transistor W/Ls for the flip-flop.
Propagation Delay (ns)
Load (pF)
Rise
Fall
15
8.18
7.21
10
7.98
7.187
1
1.776
1.899
0.5
1.389
1.584
CHIP TEST RESULTS
A photograph of the actual chip is shown in Figure 8. Figure 9 shows what the
actual tests have given as results. The problem is that there is no good result. The reason
for this is that it seems there was a mistake done in the padframe creating a low resistance
path to ground. Therefore, the actual results are inconclusive. This proves however, that
even though the padframe seems like a minor detail it is one of the most important to get
right.
CONCLUSION
This project was to prove whether students could design and layout a simple
digital circuit into a fairly standard process. Even though actual results are not seen, it
was still an essential learning experience. Everyone has to start doing something small
and this is a great first experience to actually laying out a circuit. In that method, this
project is a success.
MOSIS REPORT:
Final Project
Flip-flop Design with Option of Set/Reset
COURSE NO: ECE 491
DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
UNIVERSITY OF TENNESSEE, TN-37996
SPRING 2007
ABSTRACT
This report consists of a detailed description of a D flip-flop with a set-reset. A brief
explanation of how the D flip-flop works and its truth table are examined. The effects of
the set/reset are then explained. Finally, the results are displayed and analyzed.
INTRODUCTION
The final project for VLSI was designed to display student’s knowledge of Cadence.
After working with Cadence all semester students must use what they have learned and
build either a JK flip-flop, D flip-flop, or T flip-flop. In addition, they should add an
enable, set/reset, or clear to the circuit. The waveforms should show that the flip-flop is
functional and that the addition works correctly.
The flip-flop chosen by the author was a D flip-flop. The reasoning for this was that the
simple master-slave design would be easy to implement but still more complicated than
just building a JK flip-flop. In addition a set/reset was added to the system. Also, to test
if the D flip-flop was operating correctly an enable was also used.
DESIGN
The master-slave D flip-flop can be made using nand gates and an inverter. The flip-flop
shown in Fig. 2-1 is a representation using nand gates. This gate view of the D flip-flop
could be easily broken down into a transistor view if necessary.
Figure 2-1: D Flip-Flop
The D flip-flop is designed from the truth table. The truth table of a D flip-flop states
that when the clock is on the falling edge and the D is set to zero, Q should be zero.
When the clock is on the fallingedge and D is set to one, Q should be one. Table 1 shows
the truth table for a D flip-flop. This table works only for this particular version of the D
flip-flip. If there was an inverter after the CLK and before the other inverter the table
would be different and the change would be on the rising side of the clock.
Table 1: D flip-flop Truth Table
D
CLK
Q Q_not
0 Falling Edge 0
1
1 Falling Edge 1
0
The following circuit was used to design a D flip-flop with a set/reset. For the inverters
in the circuit that did not have specific width and length ratios, inverters built earlier in
the semester were used. Everything else was built using the same ratios specified. Refer
to Table 2 for the ratios used.
Figure 2-2: Schematic of D flip-flop
Table 2: Transistor Ratios
Transistor W/L ratio
Buffer1
15/0.6
Buffer2
10/0.6
Inv1
5/0.6
Inv2
2/0.6
Inv3
Inv4
CLK
10/0.6
CLK_not
10/0.6
N1
5/0.6
N2
10/0.6
N3
10/0.6
N4
5/0.6
N5
5/0.6
N6
5/0.6
N7
10/0.6
N8
10/0.6
SIMULATION RESULTS
The set-reset works in such a way that, regardless of the action of the clock and D, ‘set’
high will force the output to be high and ‘reset’ will force the output to be low. Refer to
Fig 3-3 for the schematic in Cadence. This figure should be very similar the previous Fig
2-2. This is because the designer wanted the schematic to be simple to follow.
Figure 3-3: Cadence Schematic
The waveforms produced in Cadence using this schematic are shown in Fig. 3-4. Since
the circuit is an asynchronous set/reset there will be a delay in the D change and the
set/reset will happen on the falling edge. This means that when set is high while the
clock is on, Q will be high only as long as the set is high. If the set is high while the
clock is off, Q will stay high until the next falling edge of the clock. The reset will set
any current value to zero. This has no dependency on the clock and should not have
much of a delay.
Figure 3-4: Waveforms from Schematic
The layout of the circuit was also simulated. The layout was the most time consuming
section of the project. Layout of the circuit should be based on the schematic. Also,
while designing the layout one think to keep in mind is size. The size is important
because the smaller the circuit layout, the more circuitry that can fit on the integrated
circuit. The layout is displayed in Fig. 3-5.
Figure 3-5: Layout Design of D flip-flop
After the layout is designed, need to be extracted and compared to the schematic to show
that they match exactly. The comparison is done using LVS. The extraction will also be
simulated, like the schematic, and a waveform will be generated. The simulation will
only happen if the LVS matches. The LVS is attached in Appendix A. Refer to Fig. 3-6
for the extracted layout.
Figure 3-6: Extracted Layout
The waveform from the extracted layout was exactly the same as the one from the
schematic. Refer to Fig. 3-4 for the waveforms.
The rise time and fall time can be calculated from the outputs Q and Q_not. The rise
time is calculated at t+70% and fall time is calculated at t30%. This is found from the
waveforms. Refer to Fig. 3-8 for the waveforms used to find the rise and fall time.
Figure 3-8: Rise time and Fall time of Output
The rise time: t30%=20.48nS t70%=20.53nS
The fall time: t-30%=20.76nS t-70%=20.81nS
Capacitance is added onto the output of Q and Q_not. The capacitance added to the
circuit was 1pF. This will effect the rise and fall time of the output. Refer to Fig. 3-9 for
the new Q and Q_not.
Figure 3-9: Rise and Fall time of Output with 1pF cap
The rise time: t30%=21.45nS t70%=22.46nS
The fall time: t-30%=21.45nS t-70%=22.35nS
Another value of capacitance was added to the output of the circuit. The new capacitance
added was 500fF. This capacitance replaced the first 1pF. This will effect the rise and
fall time of the output. Refer to Fig. 3-10 for the new rise and fall time of the output.
Figure 3-10: Rise and Fall time with 500fF cap
The rise time: t30%=20.91nS t70%=21.51nS
The fall time: t-30%=21.14nS t-70%=21.6nS
Refer to Table 3 for more rise time and fall times.
Cap
Value
0pF
Table 3: Rise time and Fall time due to Cap
Rise Time
Fall Time
30%
70%
-30%
-70%
20.48nS
0.5pF
1pF
20.91nS
21.45nS
20.53n
S
21.51n
S
22.46n
20.76nS
20.81n
S
21.14nS
21.45nS
21.6nS
22.35n
S
1.5pF
21.65nS
2pF
22nS
23.4nS
24.34n
S
21.75nS
22.06nS
S
23.12n
S
23.89n
S
The values can be plotted to show how the output capacitance affects the overall rise time
and fall time. Refer to Fig. 3-11 to the graph of the delay vs. the load capacitance. These
values were found on the first curve, the first change from zero to Vdd.
Figure 3-11: Delay vs. Load Capacitance
The total delay was found by subtracting the rise time t70% and t30% and comparing it to
the capacitance. A figure showing this comparison can be found in Fig. 3-12.
Figure 3-12: Total Delay vs. Load Capacitance
One application for an asynchronous D flip-flop with a set/reset would be memory. Such
ideas as SRAM and other computer memory are built from D flip-flops.
TEST RESULTS
A photograph of the actual chip is shown in Figure 4-1. Figure 4-2 shows what
the actual tests have given as results. The problem is that there is no good result. The
reason for this is that it seems there was a mistake done in the padframe creating a low
resistance path to ground. Therefore, the actual results are inconclusive. This proves
however, that even though the padframe seems like a minor detail it is one of the most
important to get right.
CONCLUSION
This lab allows students to apply what they learned in class and in their lab.
The student must understand transistor level interactions, the truth table, and how the
flip-flop works. The layout of the flip-flop is based off the schematic. The output of the
schematic and waveform needs to match as well as the LVS. The rise time and fall time
is important in these type systems. The rise time and fall time is affected by the load
capacitance. By changing the load capacitance, a comparison can be made between the
load capacitance and delay.