25 MHz Direct Digital Synthesizer,
Waveform Generator
AD9832-KGD
Known Good Die
FEATURES
GENERAL DESCRIPTION
25 MHz speed
On-chip SIN lookup table
On-chip, 10-bit DAC
Serial loading
Power-down option
Temperature range: −40°C to +85°C
200 mW power consumption
Known good die (KGD): these die are fully guaranteed to
data sheet specifications
The AD9832-KGD is a numerically controlled oscillator
employing a phase accumulator, a sine look-up table, and a 10bit digital-to-analog converter (DAC) integrated on a single
CMOS chip. Modulation capabilities are provided for phase
modulation and frequency modulation.
Clock rates up to 25 MHz are supported. Frequency accuracy can
be controlled to one part in 4 billion. Modulation is effected by
loading registers through the serial interface.
A power-down bit lets the user power down the AD9832-KGD
when it is not in use, the power consumption being reduced to
5 mW (5 V) or 3 mW (3 V).
APPLICATIONS
Frequency stimulus/waveform generation
Frequency phase tuning and modulation
Low power RF/communications systems
Liquid and gas flow measurement
Sensory applications: proximity, motion, and defect
detection
Test and medical equipment
Similar DDS products can be found at www.analog.com/DDS.
Additional application and technical information can be found
in the AD9832 data sheet.
FUNCTIONAL BLOCK DIAGRAM
DVDD
FSELECT
BIT
FSELECT
AVDD
AGND
REFOUT
FS ADJUST
REFIN
SELSRC
ON-BOARD
REFERENCE
MUX
MCLK
DGND
FULL-SCALE
CONTROL
SYNC
FREQ0 REG
12
MUX
PHASE
ACCUMULATOR
(32 BIT)
FREQ1 REG
SIN
ROM
10-BIT DAC
COMP
IOUT
PHASE0 REG
PHASE1 REG
AD9832-KGD
MUX
PHASE2 REG
SYNC
PHASE3 REG
SYNC
16-BIT DATA REGISTER
SYNC
8 MSBs
8 LSBs
DEFER REGISTER
SELSRC
CONTROL REGISTER
DECODE LOGIC
FSELECT/PSEL REGISTER
MUX
PSEL0
BIT
MUX
PSEL1
BIT
FSYNC
SCLK
PSEL0 PSEL1
SDATA
11672-001
SERIAL REGISTER
Figure 1.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD9832-KGD
Known Good Die
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................6
Applications ....................................................................................... 1
ESD Caution...................................................................................6
General Description ......................................................................... 1
Pad Configuration and Function Descriptions .............................7
Functional Block Diagram .............................................................. 1
Outline Dimensions ..........................................................................8
Revision History ............................................................................... 2
Die Specifications and Assembly Recommendations ..............8
Specifications..................................................................................... 3
Ordering Guide .............................................................................8
Timing Characteristics ................................................................ 5
REVISION HISTORY
7/13—Rev. 0 to Rev. A
Changes to Ordering Guide ............................................................ 8
6/13—Revision 0: Initial Version
Rev. A | Page 2 of 8
Known Good Die
AD9832-KGD
SPECIFICATIONS
VDD = +5 V ± 5%; AGND = DGND = 0 V; TA = TMIN to TMAX; REFIN = REFOUT; RSET = 3.9 kΩ; RLOAD = 300 Ω for IOUT, unless otherwise
noted. Also, see Figure 2.
Table 1.
Parameter 1
SIGNAL DAC SPECIFICATIONS
Resolution
Update Rate (fMAX)
IOUT Full Scale
Output Compliance
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
DDS SPECIFICATIONS 2
Dynamic Specifications
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range (SFDR) 3
Narrow Band (±50 kHz)
Wideband (±2 MHz)
Clock Feedthrough
Wake-Up Time 4
Power-Down Option
VOLTAGE REFERENCE
Internal Reference @ 25°C
TMIN to TMAX
REFIN Input Impedance
Reference Temperature Coefficient (TC)
REFOUT Output Impedance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINH
Input Capacitance, CIN
POWER SUPPLIES
AVDD
DVDD
IAA
IDD
IAA + IDD 5
Low Power Sleep Mode
AD9832-KGD
Unit
Test Conditions/Comments
10
25
4
4.5
1.35
Bits
MSPS nom
mA nom
mA max
V max
3 V power supply
±1
±0.5
LSB typ
LSB typ
50
−53
dB min
dBc max
−72
−70
−50
−60
1
Yes
dBc min
dBc min
dBc min
dBc typ
ms typ
1.21
1.21 ± 7%
10
100
300
V typ
V min/V max
MΩ typ
ppm/°C typ
Ω typ
VDD − 0.9
0.9
10
10
V min
V max
µA max
pF max
2.97/5.5
2.97/5.5
5
2.5 + 0.4/MHz
15
24
350
V min/V max
V min/V max
mA max
mA typ
mA max
mA max
µA max
fMCLK = 25 MHz, fOUT = 1 MHz
fMCLK = 25 MHz, fOUT = 1 MHz
fMCLK = 6.25 MHz, fOUT = 2.11 MHz
5 V power supply
3 V power supply
5 V power supply
5 V power supply
3 V power supply
5 V power supply
Operating temperature range is −40°C to +85°C.
100% production tested.
fMCLK = 6.25 MHz, frequency word = 0x5671C71C, and fOUT = 2.11 MHz.
4
To reduce the wake-up time at low power supplies and low temperature, the use of an external reference is suggested.
5
Measured with the digital inputs static and equal to 0 V or DVDD. The AD9832-KGD is tested with a capacitive load of 50 pF. The part can operate with higher
capacitive loads, but the magnitude of the analog output will be attenuated. For example, a 5 MHz output signal is attenuated by 3 dB when the load capacitance equals
85 pF.
1
2
3
Rev. A | Page 3 of 8
AD9832-KGD
Known Good Die
RSET
3.9kΩ
10nF
ON-BOARD
REFERENCE
12
SIN
ROM
REFIN
FS
ADJUST
FULL-SCALE
CONTROL
10-BIT DAC
COMP
AVDD
10nF
IOUT
300Ω
50pF
AD9832-KGD
Figure 2. Test Circuit by Which Specifications Were Tested
Rev. A | Page 4 of 8
11672-002
REFOUT
Known Good Die
AD9832-KGD
TIMING CHARACTERISTICS
VDD = +5 V ± 5%; AGND = DGND = 0 V, unless otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t11A1
1
Limit at TMIN to TMAX (B Version)
40
16
16
50
20
20
15
20
SCLK − 5
15
5
8
8
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
Test Conditions/Comments
MCLK period
MCLK high duration
MCLK low duration
SCLK period
SCLK high duration
SCLK low duration
FSYNC to SCLK falling edge setup time
FSYNC to SCLK hold time
Data setup time
Data hold time
FSELECT, PSEL0, PSEL1 setup time before MCLK rising edge
FSELECT, PSEL0, PSEL1 setup time after MCLK rising edge
See the Pad Configuration and Function Descriptions section.
Timing Diagrams
t1
11672-003
MCLK
t2
t3
Figure 3. Master Clock
t5
t4
SCLK
t7
t8
t6
FSYNC
t10
D15
D14
D2
D1
D0
D15
Figure 4. Serial Timing
MCLK
t11A
t11
FSELECT
PSEL0, PSEL1
VALID DATA
VALID DATA
Figure 5. Control Timing
Rev. A | Page 5 of 8
VALID DATA
11672-005
SDATA
D14
11672-004
t9
AD9832-KGD
Known Good Die
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
AVDD to AGND
DVDD to DGND
AVDD to DVDD
AGND to DGND
Digital I/O Voltage to DGND
Analog I/O Voltage to AGND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
ESD Rating
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−40°C to +85°C
−65°C to +150°C
150°C
215°C
220°C
>4500 V
Rev. A | Page 6 of 8
Known Good Die
AD9832-KGD
PAD CONFIGURATION AND FUNCTION DESCRIPTIONS
20
19
18
17 16
1
15
2
3
14
13
4
12
5
7
8
9
10
11672-006
11
6
Figure 6. Pad Configuration
Table 4. Pad Function Descriptions
Pad No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
X-Axis(µm)
−1130
−1132.1
−1132.1
−1130
−1130
−1130
−763.2
−351.7
+343.9
+771.8
+1130
+1130
+1130
+1130
+1130
+801
+618.2
+226.6
−408.1
−851.5
Y-Axis(µm)
+790.1
+402.9
+232
−240.4
−415
−767.9
−1105
−1105
−1105
−1105
−747.2
−354
+169
+346.9
+787.6
+1105
+1105
+1102.9
+1102.9
+1102.9
Mnemonic
REFOUT
DVDD
DVDD
DGND
DGND
MCLK
SCLK
SDATA
FSYNC
FSELECT
PSEL1
PSEL0
AGND
AGND
IOUT
AVDD
AVDD
COMP
FS ADJUST
REFIN
Pad Type
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Description
Voltage Reference Output.
Positive Power Supply for the Digital Section.
Positive Power Supply for the Digital Section.
Digital Ground
Digital Ground
Digital Clock Input
Serial Clock, Logic Input
Serial Data In, Logic Input
Data Synchronization Signal, Logic Input.
Frequency Select Input
Phase Select Input
Phase Select Input
Analog Ground
Analog Ground
Current Output
Positive Power Supply for the Analog Section
Positive Power Supply for the Analog Section
Compensation Pin
Full-Scale Adjust Control.
Voltage Reference Input.
Rev. A | Page 7 of 8
AD9832-KGD
Known Good Die
OUTLINE DIMENSIONS
2.600
SQ
20
19
0.280
18
17 16
1
15
2
3
14
13
4
12
5
11
6
8
9
TOP VIEW
(CIRCUIT SIDE)
10
0.092 × 0.092
SIDE VIEW
06-21-2013-A
7
Figure 7. 20-Pad Bare Die [CHIP]
(C-20-1)
Dimensions shown in millimeters
DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS
Table 5. Die Specifications
Parameter
Chip Size
Scribe Line Width
Die Size
Thickness
Bond Pad
Bond Pad Composition
Backside
Passivation
1
Value
2600 × 2600
100 × 150
2500 × 2450
280
92 × 92
98.5% Al, 1% Si, 0.5% Cu
Bare
Nitride
Unit1
μm
μm
mm (maximum)
μm
μm (minimum)
%
N/A
N/A
N/A means not applicable.
Table 6. Assembly Recommendations
Assembly Component
Die Attach
Bonding Method
Bonding Sequence
Recommendation
No special requirements
Gold ball or aluminum wedge
Pads 4 & 5 First
ORDERING GUIDE
Model
AD9832-KGD-CHIPS
Temperature Range
−40°C to +85°C
Package Description
20-Pad Bare Die [CHIP]
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11672-0-7/13(A)
Rev. A | Page 8 of 8
Package Option
C-20-1