Enhanced Product
Complete Quad, 16-Bit, High Accuracy,
Serial Input, Bipolar Voltage Output DAC
AD5764-EP
FEATURES
GENERAL DESCRIPTION
Complete quad, 16-bit digital-to-analog converter (DAC)
Programmable output range: ±10 V, ±10.2564 V, or ±10.5263 V
±2 LSB maximum INL error, ±1 LSB maximum DNL error
Low noise: 60 nV/√Hz
Settling time: 10 µs maximum
Integrated reference buffers
Output control during power-up/brownout
Programmable short-circuit protection
Simultaneous updating via LDAC
Asynchronous CLR to zero code
Digital offset and gain adjust
Logic output control pins
DSP-/microcontroller-compatible serial interface
Temperature range: −55°C to +105°C
iCMOS process technology1
The AD5764-EP is a quad, 16-bit, serial input, bipolar voltage
output DAC that operates from supply voltages of ±11.4 V to
±16.5 V. The nominal full-scale output range is ±10 V. The
AD5764-EP provides integrated output amplifiers, reference
buffers, and proprietary power-up/power-down control circuitry.
The device also features a digital I/O port that is programmed via
the serial interface. The AD5764-EP incorporates digital offset
and gain adjust registers per channel.
ENHANCED PRODUCT FEATURES
Supports defense and aerospace applications (AQEC standard)
Extended temperature range: −55°C to +105°C
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available on request
APPLICATIONS
The AD5764-EP uses a serial interface that operates at clock rates
of up to 30 MHz and is compatible with DSP and microcontroller
interface standards. Double buffering allows the simultaneous
updating of all DACs. The input coding is programmable to either
twos complement or offset binary format. The asynchronous clear
function clears the data register to either bipolar zero or zero scale
depending on the coding used. The AD5764-EP is ideal for both
closed-loop servo control and open-loop control applications. The
AD5764-EP is available in a 32-lead TQFP and offers guaranteed
specifications over the −55°C to +105°C industrial temperature
range. See Figure 1 for the functional block diagram.
Additional application and technical information can be found
in the AD5764 data sheet.
Industrial automation
Open-loop/closed-loop servo control
Process control
Data acquisition systems
Automatic test equipment
Automotive test and measurement
High accuracy instrumentation
1
The AD5764-EP is a high performance converter that offers
guaranteed monotonicity, integral nonlinearity (INL) of ±2 LSB,
low noise, and 10 µs settling time. During power-up (when the
supply voltages are changing), VOUTx is clamped to 0 V via a
low impedance path.
Table 1. Related Devices
Part No.
AD5764R
AD5744R
Description
AD5764 with internal voltage reference
Complete quad, 14-bit, high accuracy, serial input,
bipolar voltage output DAC with internal voltage
reference
For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels, iCMOS® is a technology
platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies, allowing dramatic reductions in power consumption and package
size, and increased ac and dc performance.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5764-EP
Enhanced Product
TABLE OF CONTENTS
Features .............................................................................................. 1
Timing Characteristics .................................................................6
Enhanced Product Features ............................................................ 1
Absolute Maximum Ratings ............................................................9
Applications ....................................................................................... 1
ESD Caution...................................................................................9
General Description ......................................................................... 1
Pin Configuration and Function Descriptions........................... 10
Revision History ............................................................................... 2
Typical Performance Characteristics ........................................... 12
Functional Block Diagram .............................................................. 3
Outline Dimensions ....................................................................... 17
Specifications..................................................................................... 4
Ordering Guide .......................................................................... 17
AC Performance Characteristics ................................................ 5
REVISION HISTORY
12/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
Enhanced Product
AD5764-EP
FUNCTIONAL BLOCK DIAGRAM
PGND
AVDD
AVSS
AVDD
AVSS
REFGND
DVCC
DGND
16
SDIN
SCLK
SYNC
REFERENCE
BUFFERS
AD5764-EP
INPUT
SHIFT
REGISTER
AND
CONTROL
LOGIC
INPUT
REG A
DATA
REG A
RSTOUT
REFAB
16
RSTIN
VOLTAGE
MONITOR
AND
CONTROL
ISCC
G1
DAC A
VOUTA
G2
GAIN REG A
AGNDA
OFFSET REG A
SDO
INPUT
REG B
DATA
REG B
16
G1
DAC B
VOUTB
G2
GAIN REG B
AGNDB
OFFSET REG B
D0
D1
INPUT
REG C
DATA
REG C
16
G1
DAC C
VOUTC
G2
GAIN REG C
AGNDC
OFFSET REG C
BIN/2sCOMP
INPUT
REG D
DATA
REG D
16
G1
DAC D
VOUTD
G2
GAIN REG D
AGNDD
OFFSET REG D
REFERENCE
BUFFERS
LDAC
Figure 1.
Rev. 0 | Page 3 of 20
REFCD
11843-001
CLR
AD5764-EP
Enhanced Product
SPECIFICATIONS
AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGNDx = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V;
DVCC = 2.7 V to 5.25 V, RLOAD = 10 kΩ, CLOAD = 200 pF. Temperature range: −55°C to +105°C; typical at +25°C. All specifications
TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
ACCURACY
Resolution
Relative Accuracy (INL)
Differential Nonlinearity (DNL)
Bipolar Zero Error
Max
Unit
±2
±1
±2
Bits
LSB
LSB
mV
Bipolar Zero Temperature Coefficient (TC) 1
Zero-Scale Error
±2
±3
ppm FSR/°C
mV
Zero-Scale TC1
Gain Error
±2
±0.02
ppm FSR/°C
% FSR
±2
0.5
ppm FSR/°C
LSB
±10
7
±1% for specified performance
Typically 100 MΩ
Typically ±30 nA
1
V
MΩ
µA
V
−10.5263
−14
+10.5263
+14
AVDD/AVSS = ±11.4 V, VREFIN = 5 V
AVDD/AVSS = ±16.5 V, VREFIN = 7 V
±1
V
V
ppm FSR/
500 hours
ppm FSR/
1000 hours
mA
mA
200
1000
0.3
pF
pF
Ω
0.8
±1
10
V
V
µA
pF
Per pin
Per pin
V
V
V
V
µA
pF
DVCC = 5 V ± 5%, sinking 200 µA
DVCC = 2.7 V to 3.6 V, sinking 200 µA
DVCC = 5 V ± 5%, sourcing 200 µA
DVCC = 2.7 V to 3.6 V, sourcing 200 µA
SDO only
SDO only
Gain TC1
DC Crosstalk1
REFERENCE INPUT1
Reference Input Voltage
DC Input Impedance
Input Current
Reference Range
OUTPUT CHARACTERISTICS1
Output Voltage Range 2
Min
Typ
16
5
1
Output Voltage Drift vs. Time
±13
±15
Short-Circuit Current
Load Current
Capacitive Load Stability
RLOAD = ∞
RLOAD = 10 kΩ
DC Output Impedance
DIGITAL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current
Pin Capacitance
DIGITAL OUTPUTS (D0, D1, SDO)1
Output Low Voltage, VOL
Output High Voltage, VOH
High Impedance Leakage Current
High Impedance Output Capacitance
10
Test Conditions/Comments
Outputs unloaded
Guaranteed monotonic
At 25°C; error at other temperatures
obtained using bipolar zero TC
At 25°C; error at other temperatures
obtained using zero-scale TC
At 25°C; error at other temperatures
obtained using gain TC
RISCC = 6 kΩ; see Figure 31
For specified performance
DVCC = 2.7 V to 5.25 V, JEDEC compliant
2
0.4
0.4
DVCC − 1
DVCC − 0.5
±1
5
Rev. 0 | Page 4 of 20
Enhanced Product
Parameter
POWER REQUIREMENTS
AVDD/AVSS
DVCC
Power Supply Sensitivity1
∆VOUT/∆ΑVDD
AIDD
AISS
DICC
Power Dissipation
1
2
AD5764-EP
Min
Typ
±11.4
2.7
Max
Unit
±16.5
5.25
V
V
3.75
−3
1.4
dB
mA/channel
mA/channel
mA
mW
−85
275
Test Conditions/Comments
Outputs unloaded
Outputs unloaded
VIH = DVCC, VIL = DGND, 750 µA typical
±12 V operation, output unloaded
Guaranteed by design and characterization; not production tested.
Output amplifier headroom requirement is 1.4 V minimum.
AC PERFORMANCE CHARACTERISTICS
AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGNDx = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V;
DVCC = 2.7 V to 5.25 V, RLOAD = 10 kΩ, CLOAD = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE 1
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
Digital Feedthrough
Output Noise
0.1 Hz to 10 Hz
0.1 Hz to 100 kHz
1/f Corner Frequency
Output Noise Spectral Density
Complete System Output Noise Spectral
Density 2
1
2
Min
Typ
Max
Unit
Test Conditions/Comments
8
2
5
8
10
µs
µs
V/µs
nV-sec
mV p-p
dB
nV-sec
nV-sec
nV-sec
Full-scale step to ±1 LSB
512 LSB step settling
37
80
8
2
2
0.1
45
1
60
80
Guaranteed by design and characterization; not production tested.
Includes noise contributions from integrated reference buffers, 16-bit DAC, and output amplifier.
Rev. 0 | Page 5 of 20
LSB p-p
µV rms
kHz
nV/√Hz
nV/√Hz
Effect of input bus activity on DAC
outputs
Measured at 10 kHz
Measured at 10 kHz
AD5764-EP
Enhanced Product
TIMING CHARACTERISTICS
AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGNDx = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V;
DVCC = 2.7 V to 5.25 V, RLOAD = 10 kΩ, CLOAD = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter 1, 2, 3
t1
t2
t3
t4
t5 4
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15 5, 6
t16
t17
t18
Limit at TMIN, TMAX
33
13
13
13
13
90
2
9
1.7
480
17
500
10
17
2
25
13
2
170
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs min
ns min
ns min
ns max
µs max
ns min
µs max
ns max
ns min
µs max
ns min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24th SCLK falling edge to SYNC rising edge
Minimum SYNC high time
Data setup time
Data hold time
SYNC rising edge to LDAC falling edge (all DACs updated)
SYNC rising edge to LDAC falling edge (single DAC updated)
LDAC pulse width low
LDAC falling edge to DAC output response time
DAC output settling time
CLR pulse width low
CLR pulse activation time
SCLK rising edge to SDO valid
SYNC rising edge to SCLK falling edge
SYNC rising edge to DAC output response time (LDAC = 0)
LDAC falling edge to SYNC rising edge
Guaranteed by design and characterization; not production tested.
All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
See Figure 3, Figure 4, and Figure 5.
4
Standalone mode only.
5
Measured with the load circuit of Figure 2.
6
Daisy-chain mode only.
1
2
3
200µA
VOH (MIN) OR
VOL (MAX)
CL
50pF
200µA
IOH
Figure 2. Load Circuit for SDO Timing Diagram
Rev. 0 | Page 6 of 20
11843-005
TO SDO
PIN
IOL
Enhanced Product
AD5764-EP
Timing Diagrams
t1
SCLK
1
24
2
t2
t3
t6
t4
t5
SYNC
t8
t7
SDIN
DB0
DB23
t10
t9
LDAC
t10
t18
t12
t11
VOUTx
LDAC = 0
t12
t17
VOUTx
t13
CLR
t14
11843-002
VOUTx
Figure 3. Serial Interface Timing Diagram
t1
SCLK
24
t3
t6
48
t2
t5
t16
t4
SYNC
t7
SDIN
t8
DB23
DB0
INPUT WORD FOR DAC N
DB23
DB0
t15
INPUT WORD FOR DAC N – 1
DB23
SDO
UNDEFINED
DB0
INPUT WORD FOR DAC N
t9
t10
11843-003
LDAC
Figure 4. Daisy-Chain Timing Diagram
Rev. 0 | Page 7 of 20
AD5764-EP
Enhanced Product
SCLK
24
48
SYNC
DB23
DB0
DB23
DB0
NOP CONDITION
INPUT WORD SPECIFIES
REGISTER TO BE READ
DB0
DB23
SDO
SELECTED REGISTER DATA
CLOCKED OUT
UNDEFINED
Figure 5. Readback Timing Diagram
Rev. 0 | Page 8 of 20
11843-004
SDIN
Enhanced Product
AD5764-EP
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Table 5.
Parameter
AVDD to AGNDx, DGND
AVSS to AGNDx, DGND
DVCC to DGND
Digital Inputs to DGND
Digital Outputs to DGND
REFAB, REFCD to AGNDx, PGND
VOUTA, VOUTB, VOUTC, VOUTD
to AGNDx
AGNDx to DGND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ max)
32-Lead TQFP
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature
Soldering
Rating
−0.3 V to +17 V
+0.3 V to −17 V
−0.3 V to +7 V
−0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
−0.3 V to DVCC + 0.3 V
−0.3 V to AVDD + 0.3 V
AVSS to AVDD
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−0.3 V to +0.3 V
−55°C to +105°C
−65°C to +150°C
150°C
65°C/W
12°C/W
JEDEC industry standard
J-STD-020
Rev. 0 | Page 9 of 20
AD5764-EP
Enhanced Product
REFAB
REFCD
NC
REFGND
NC
AVSS
AVDD
BIN/2sCOMP
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32 31 30 29 28 27 26 25
24
AGNDA
23
VOUTA
22
VOUTB
21
AGNDB
20
AGNDC
LDAC 6
19
VOUTC
D0 7
18
VOUTD
D1 8
17
AGNDD
SYNC 1
PIN 1
SCLK 2
SDIN 3
AD5764-EP
SDO 4
TOP VIEW
(Not to Scale)
CLR 5
NC = NO CONNECT
11843-006
ISCC
AVSS
PGND
AVDD
DVCC
DGND
RSTIN
10 11 12 13 14 15 16
RSTOUT
9
Figure 6. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
Mnemonic
SYNC
2
SCLK
3
4
5
SDIN
SDO
CLR
6
LDAC
7, 8
D0, D1
9
RSTOUT
10
RSTIN
11
12
13, 31
14
15, 30
16
DGND
DVCC
AVDD
PGND
AVSS
ISCC
17
18
AGNDD
VOUTD
19
VOUTC
20
AGNDC
Description
Active Low Input. This pin is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred in on the falling edge of SCLK.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This input operates at
clock speeds up to 30 MHz.
Serial Data Input. Data must be valid on the falling edge of SCLK.
Serial Data Output. This pin is used to clock data from the serial register in daisy-chain or readback mode.
Negative Edge Triggered Input. Asserting this pin sets the data register to 0x0000. This logic input has an
internal pull-up device. Therefore, this pin can be left floating and defaults to a Logic 1 condition.
Load DAC. This logic input is used to update the data register and, consequently, the analog outputs. When
LDAC is tied permanently low, the addressed data register is updated on the rising edge of SYNC. If LDAC is held
high during the write cycle, the DAC input shift register is updated, but the update of the output is delayed
until the falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling
edge of LDAC. The LDAC pin must not be left unconnected.
Digital I/O Port. These pins can be inputs or outputs that are configurable and readable over the serial interface.
When configured as inputs, D0 and D1 have weak internal pull-ups to DVCC. When configured as outputs, D0 and
D1 are referenced by DVCC and DGND.
Reset Logic Output. This pin is the output from the on-chip voltage monitor and is used in the reset circuit. If
desired, this pin can be used to control other system components.
Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to this input
clamps the DAC outputs to 0 V. In normal operation, RSTIN should be tied to Logic 1. Register values remain
unchanged.
Digital Ground.
Digital Supply Voltage (2.7 V to 5.25 V).
Positive Analog Supply Voltage (11.4 V to 16.5 V).
Ground Reference Point for the Analog Circuitry.
Negative Analog Supply Voltage (−11.4 V to −16.5 V).
Resistor Connection for Pin Programmable Short-Circuit Current. This pin is used with an optional external
resistor to AGND to program the short-circuit current of the output amplifiers.
Ground Reference Pin for DAC D Output Amplifier.
Analog Output Voltage of DAC D. This buffered output has a nominal full-scale output range of ±10 V. The
output amplifier is capable of directly driving a 10 kΩ, 200 pF load.
Analog Output Voltage of DAC C. This buffered output has a nominal full-scale output range of ±10 V. The
output amplifier is capable of directly driving a 10 kΩ, 200 pF load.
Ground Reference Pin for DAC C Output Amplifier.
Rev. 0 | Page 10 of 20
Enhanced Product
Pin No.
21
22
Mnemonic
AGNDB
VOUTB
23
VOUTA
24
25
AGNDA
REFAB
26
REFCD
27, 29
28
32
NC
REFGND
BIN/2sCOMP
AD5764-EP
Description
Ground Reference Pin for DAC B Output Amplifier.
Analog Output Voltage of DAC B. This buffered output has a nominal full-scale output range of ±10 V. The
output amplifier is capable of directly driving a 10 kΩ, 200 pF load.
Analog Output Voltage of DAC A. This buffered output has a nominal full-scale output range of ±10 V. The
output amplifier is capable of directly driving a 10 kΩ, 200 pF load.
Ground Reference Pin for DAC A Output Amplifier.
External Reference Voltage Input for Channel A and Channel B. Reference input range is 1 V to 7 V. This pin
programs the full-scale output voltage. VREFIN = 5 V for specified performance.
External Reference Voltage Input for Channel C and Channel D. Reference input range is 1 V to 7 V. This pin
programs the full-scale output voltage. VREFIN = 5 V for specified performance.
No Connect.
Reference Ground Return for the Reference Generator and Buffers.
This pin determines the DAC coding. This pin should be hardwired to either DVCC or DGND. When the pin is
hardwired to DVCC, the input coding is offset binary. When the pin is hardwired to DGND, the input coding is
twos complement.
Rev. 0 | Page 11 of 20
AD5764-EP
Enhanced Product
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
TA = 25°C
AVDD/AVSS = ±15V
VREFIN = 5V
0.8
0.6
0.6
DNL ERROR (LSB)
INL ERROR (LSB)
0.4
0.2
0
–0.2
–0.4
0.4
0.2
0
–0.2
–0.4
–0.6
–0.6
–0.8
–0.8
0
10000
20000
30000
40000
50000
60000
DAC CODE
–1.0
11843-007
–1.0
TA = 25°C
AVDD/AVSS = ±12V
VREFIN = 5V
0.8
0
20000
30000
40000
50000
60000
DAC CODE
Figure 7. Integral Nonlinearity Error vs. Code,
AVDD/AVSS = ±15 V
Figure 10. Differential Nonlinearity Error vs. Code,
AVDD/AVSS = ±12 V
1.0
TA = 25°C
0.8 AVDD/AVSS = ±12V
VREFIN = 5V
0.6
0.6
TA = 25°C
AVDD/AVSS = ±15V
VREFIN = 5V
0.4
INL ERROR (LSB)
0.4
INL ERROR (LSB)
10000
11843-012
1.0
0.2
0
–0.2
0.2
0
–0.2
–0.4
–0.6
–0.4
0
10000
20000
30000
40000
50000
60000
DAC CODE
–0.6
–55
11843-008
–1.0
0.6
TA = 25°C
AVDD/AVSS = ±15V
VREFIN = 5V
0.4
INL ERROR (LSB)
0.4
0.2
0
–0.2
–0.4
–0.6
105
TA = 25°C
AVDD/AVSS = ±12V
VREFIN = 5V
0.2
0
–0.2
–0.4
–1.0
0
10000
20000
30000
40000
50000
60000
DAC CODE
Figure 9. Differential Nonlinearity Error vs. Code,
AVDD/AVSS = ±15 V
–0.6
–55
–40
25
85
TEMPERATURE (°C)
Figure 12. Integral Nonlinearity Error vs. Temperature,
AVDD/AVSS = ±12 V
Rev. 0 | Page 12 of 20
105
11843-112
–0.8
11843-011
DNL ERROR (LSB)
85
Figure 11. Integral Nonlinearity Error vs. Temperature,
AVDD/AVSS = ±15 V
1.0
0.6
25
TEMPERATURE (°C)
Figure 8. Integral Nonlinearity Error vs. Code,
AVDD/AVSS = ±12 V
0.8
–40
11843-111
–0.8
Enhanced Product
AD5764-EP
0.2
0.15
TA = 25°C
VREFIN = 5V
0.10
0.1
DNL ERROR (LSB)
DNL ERROR (LSB)
0.05
0
–0.1
–0.2
0
–0.05
–0.10
–0.15
TA = 25°C
AVDD/AVSS = ±15V
VREFIN = 5V
25
–40
85
105
TEMPERATURE (°C)
–0.25
11.4
11843-113
–0.4
–55
–0.20
12.4
13.4
14.4
15.4
16.4
SUPPLY VOLTAGE (V)
Figure 13. Differential Nonlinearity Error vs. Temperature,
AVDD/AVSS = ±15 V
11843-025
–0.3
Figure 16. Differential Nonlinearity Error vs. Supply Voltage
0.2
0.8
TA = 25°C
AVDD/AVSS = ±16.5V
0.6
0.1
0
INL ERROR (LSB)
DNL ERROR (LSB)
0.4
–0.1
–0.2
0.2
0
–0.2
–0.4
–0.6
TA = 25°C
AVDD/AVSS = ±12V
VREFIN = 5V
85
105
TEMPERATURE (°C)
–1.0
1
4
5
6
7
Figure 17. Integral Nonlinearity Error vs. Reference Voltage,
AVDD/AVSS = ±16.5 V
0.5
0.4
TA = 25°C
VREFIN = 5V
TA = 25°C
AVDD/AVSS = ±16.5V
0.3
0.4
0.2
DNL ERROR (LSB)
0.3
0.2
0.1
0
0.1
0
–0.1
–0.2
–0.1
–0.3
12.4
13.4
14.4
15.4
16.4
SUPPLY VOLTAGE (V)
11843-023
INL ERROR (LSB)
3
REFERENCE VOLTAGE (V)
Figure 14. Differential Nonlinearity Error vs. Temperature,
AVDD/AVSS = ±12 V
–0.2
11.4
2
11843-027
25
–40
11843-114
–0.4
–55
–0.8
Figure 15. Integral Nonlinearity Error vs. Supply Voltage
–0.4
1
2
3
4
5
6
7
REFERENCE VOLTAGE (V)
Figure 18. Differential Nonlinearity Error vs. Reference Voltage,
AVDD/AVSS = ±16.5 V
Rev. 0 | Page 13 of 20
11843-031
–0.3
AD5764-EP
Enhanced Product
0.6
0.6
VREFIN = 5V
TA = 25°C
0.4 AVDD/AVSS = ±16.5V
0.5
BIPOLAR ZERO ERROR (mV)
0.2
0
TUE (mV)
–0.2
–0.4
–0.6
–0.8
–1.0
0.4
AVDD/AVSS = ±15V
0.3
0.2
0.1
AVDD/AVSS = ±12V
–1.2
0
1
2
3
4
5
6
7
REFERENCE VOLTAGE (V)
–0.1
–55
11843-035
–1.6
25
–40
85
105
TEMPERATURE (°C)
Figure 19. Total Unadjusted Error vs. Reference Voltage,
AVDD/AVSS = ±16.5 V
11843-122
–1.4
Figure 22. Bipolar Zero Error vs. Temperature
0.8
14
VREFIN = 5V
TA = 25°C
VREFIN = 5V
0.7
13
0.6
GAIN ERROR (mV)
|IDD|
IDD/ISS (mA)
12
11
10
|ISS|
0.5
AVDD/AVSS = ±15V
0.4
0.3
AVDD/AVSS = ±12V
0.2
0.1
9
12.4
13.4
14.4
15.4
16.4
AVDD/AVSS (V)
–0.1
–55
11843-037
8
11.4
25
–40
85
105
TEMPERATURE (°C)
11843-123
0
Figure 23. Gain Error vs. Temperature
Figure 20. IDD/ISS vs. AVDD/AVSS
0.5
0.0014
TA = 25°C
VREFIN = 5V
0.0013
DVCC = 5V
0.0012
0.3
0.0011
AVDD/AVSS = ±12V
0.2
DICC (mA)
ZERO-SCALE ERROR (mV)
0.4
AVDD/AVSS = ±15V
0.0010
0.0009
0.1
0.0008
DVCC = 3V
0
–40
25
85
TEMPERATURE (°C)
105
0.0006
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VLOGIC (V)
Figure 24. DICC vs. Logic Input Voltage
Figure 21. Zero-Scale Error vs. Temperature
Rev. 0 | Page 14 of 20
4.5
5.0
11843-041
–0.1
–55
11843-121
0.0007
Enhanced Product
7000
TA = 25°C
VREFIN = 5V
RISCC = 6kΩ
AVDD/AVSS = ±15V
TA = 25°C
VREFIN = 5V
AVDD/AVSS = ±15V
5000
AVDD/AVSS = ±12V
4000
3000
2000
0
–5
0
5
10
SOURCE/SINK CURRENT (mA)
11843-042
1
–1000
–10
1µs/DIV
CH1 3.00V
Figure 25. Source and Sink Capability of Output Amplifier
with Positive Full Scale Loaded
10000
–120mV
–4
TA = 25°C
VREFIN = 5V
RISCC = 6kΩ
–6
8000
–8
AVDD/AVSS = ±15V
7000
–10
6000
–12
VOUT (mV)
AVDD/AVSS = ±12V
5000
4000
–14
–16
3000
–18
2000
–20
1000
–22
0
–24
–1000
–12
CH1
Figure 27. Full-Scale Settling Time
–7
–2
3
8
SOURCE/SINK CURRENT (mA)
11843-043
OUTPUT VOLTAGE DELTA (µV)
9000
M1.00µs
11843-044
1000
Figure 26. Source and Sink Capability of Output Amplifier
with Negative Full Scale Loaded
AVDD/AVSS = ±12V
VREFIN = 5V
TA = 25°C
0x8000 TO 0x7FFF
500ns/DIV
–26
–2.0–1.5–1.0–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
TIME (µs)
Figure 28. Major Code Transition Glitch Energy, AVDD/AVSS = ±12 V
Rev. 0 | Page 15 of 20
11843-047
OUTPUT VOLTAGE DELTA (µV)
6000
AD5764-EP
AD5764-EP
Enhanced Product
10
AVDD/AVSS = ±15V
MIDSCALE LOADED
VREFIN = 0V
SHORT-CIRCUIT CURRENT (mA)
M1.00s
CH4
26µV
8
7
6
5
4
3
2
1
0
0
20
40
60
80
100
RISCC (kΩ)
Figure 31. Short-Circuit Current vs. RISCC
Figure 29. Peak-to-Peak Noise (100 kHz Bandwidth)
T
AVDD/AVSS = ±12V
VREFIN = 5V
TA = 25°C
RAMP TIME = 100µs
LOAD = 200pF||10kΩ
1
2
CH1 10.0V BW CH2 10.0V
CH3 10.0mV BW
M100µs
A CH1
T 29.60%
7.80mV
11843-055
3
Figure 30. VOUT vs. AVDD/AVSS on Power-Up
Rev. 0 | Page 16 of 20
120
11843-050
50µV/DIV
11843-048
4
CH4 50.0µV
AVDD/AVSS = ±15V
TA = 25°C
VREFIN = 5V
9
Enhanced Product
AD5764-EP
OUTLINE DIMENSIONS
0.75
0.60
0.45
1.20
MAX
9.00 BSC SQ
25
32
24
1
PIN 1
7.00
BSC SQ
TOP VIEW
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
SEATING
PLANE
17
8
16
9
VIEW A
VIEW A
0.80
BSC
LEAD PITCH
ROTATED 90° CCW
0.45
0.37
0.30
COMPLIANT TO JEDEC STANDARDS MS-026-AB A
020607-A
1.05
1.00
0.95
0.15
0.05
(PINS DOWN)
0° MIN
Figure 32. 32-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD5764SSUZ-EP-RL7
1
INL
±2 LSB max
Temperature Range
−55°C to +105°C
Z = RoHS Compliant Part.
Rev. 0 | Page 17 of 20
Package Description
32-Lead TQFP
Package Option
SU-32-2
AD5764-EP
Enhanced Product
NOTES
Rev. 0 | Page 18 of 20
Enhanced Product
AD5764-EP
NOTES
Rev. 0 | Page 19 of 20
AD5764-EP
Enhanced Product
NOTES
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11843-0-12/13(0)
Rev. 0 | Page 20 of 20