Quad, 16-Bit DAC with 5 ppm/°C
On-Chip Reference in 14-Lead TSSOP
AD5666-EP
The AD5666-EP has an on-chip reference with an internal gain of 2.
The AD5666-EP-2 has a 2.5 V, 5 ppm/°C reference, giving a fullscale output of 5 V. The on-board reference is off at power-up,
allowing the use of an external reference. The internal reference
is turned on by writing to the DAC.
FEATURES
Enhanced product features
Supports defense and aerospace applications (AQEC)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available on request
Low power, quad 16-bit DAC
14-lead TSSOP
On-chip 1.25 V/2.5 V, 5 ppm/°C reference
Power down to 400 nA at 5 V, 200 nA at 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale or midscale
3 power-down functions
Hardware LDAC with LDAC override function
CLR function to programmable code
SDO daisy-chaining option
Rail-to-rail operation
The part incorporates a power-on reset circuit that ensures that
the DAC output powers up to 0 V (POR pin low) or to midscale
(POR pin high) and remains powered up at this level until a valid
write takes place. The part contains a power-down feature that
reduces the current consumption of the device to 400 nA at 5 V
and provides software-selectable output loads while in power-down
mode for any or all DAC channels.
The outputs of all DACs can be updated simultaneously using the
LDAC function, with the added functionality of user-selectable DAC
channels to simultaneously update. There is also an asynchronous
CLR that clears all DACs to a software-selectable code—0 V,
midscale, or full scale.
The AD5666-EP uses a versatile 3-wire serial interface that operates
at clock rates of up to 50 MHz and is compatible with standard
SPI, QSPI, MICROWIRE, and DSP interface standards. The onchip precision output amplifier enables rail-to-rail output swing.
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Additional application and technical information can be found
in the AD5666 data sheet.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
GENERAL DESCRIPTION
The AD5666-EP is a low power, quad 16-bit, buffered voltageoutput DAC. The part operates from a single 2.7 V to 5.5 V supply
and is guaranteed monotonic by design.
Quad, 16-bit DAC.
On-chip 2.5 V, 5 ppm/°C reference.
Available in 14-lead TSSOP.
Selectable power-on reset to 0 V or midscale.
Power-down capability. When powered down, the DAC
typically consumes 200 nA at 3 V and 400 nA at 5 V.
FUNCTIONAL BLOCK DIAGRAM
VREFIN/VREFOUT
VDD
AD5666-EP
1.25V/2.5V
REF
LDAC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
BUFFER
VOUTA
SCLK
SYNC
INTERFACE
LOGIC
BUFFER
VOUTB
BUFFER
VOUTC
DIN
BUFFER
VOUTD
SDO
LDAC CLR
POR
GND
09511-001
POWER-DOWN
LOGIC
POWER-ON
RESET
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
AD5666-EP
TABLE OF CONTENTS
Features .............................................................................................. 1 Timing Characteristics .................................................................6 Applications ....................................................................................... 1 Absolute Maximum Ratings ............................................................8 General Description ......................................................................... 1 ESD Caution...................................................................................8 Product Highlights ........................................................................... 1 Pin Configuration and Function Descriptions..............................9 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ........................................... 10 Revision History ............................................................................... 2 Outline Dimensions ....................................................................... 16 Specifications..................................................................................... 3 Ordering Guide .......................................................................... 16 AC Characteristics........................................................................ 5 REVISION HISTORY
11/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD5666-EP
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE 2
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Zero-Code Error Drift
Full-Scale Error
Gain Error
Gain Temperature Coefficient
Offset Error
DC Power Supply Rejection Ratio
DC Crosstalk (External Reference)
Min
16
1
±2
−0.2
±2.5
±1
–80
10
DC Crosstalk (Internal Reference)
OUTPUT CHARACTERISTICS 3
Output Voltage Range
Capacitive Load Stability
DC Output Impedance
Short-Circuit Current
Power-Up Time
REFERENCE INPUTS
Reference Input Voltage
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT
Output Voltage
Reference Temperature Coefficient3
Reference Output Impedance
LOGIC INPUTS3
Input Current
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
LOGIC OUTPUTS (SDO)3
Output Low Voltage, VOL
Output High Voltage, VOH
High Impedance Leakage Current
High Impedance Output Capacitance
B Grade 1
Typ
Max
±21
±1
14
−1
±1
±14
Unit
Bits
LSB
LSB
mV
μV/°C
% FSR
% FSR
ppm
mV
dB
μV
5
10
25
μV/mA
μV
μV
10
μV/mA
0
VDD
2
10
0.5
30
4
VDD
20
0
55
VDD
14.6
2.495
V
nF
nF
Ω
mA
μs
V
μA
V
kΩ
See Figure 6
Guaranteed monotonic by design (see Figure 7)
All 0s loaded to DAC register (see Figure 13)
All 1s loaded to DAC register (see Figure 12)
Of FSR/°C
VDD ± 10%
Due to full-scale output change, RL = 2 kΩ to
GND or VDD
Due to load current change
Due to powering down (per channel)
Due to full-scale output change, RL = 2 kΩ to
GND or VDD
Due to load current change
RL = ∞
RL = 2 kΩ
VDD = 5 V
Coming out of power-down mode VDD = 5 V
VREF = VDD = 5.5 V
Per DAC channel
2.505
V
ppm/°C
kΩ
At ambient
±3
0.8
μA
V
V
pF
All digital inputs
VDD = 5 V
VDD = 5 V
0.4
V
ISINK = 2 mA
ISOURCE = 2 mA
±0.25
μA
pF
±5
7.5
2
3
VDD − 1
2
Test Conditions/Comments
Rev. 0 | Page 3 of 16
AD5666-EP
Parameter
POWER REQUIREMENTS
VDD
IDD (Normal Mode) 4
VDD = 4.5 V to 5.5 V
VDD = 4.5 V to 5.5 V
IDD (All Power-Down Modes) 5
VDD = 4.5 V to 5.5 V
Min
B Grade 1
Typ
Max
Unit
Test Conditions/Comments
5.5
V
0.7
1.3
0.9
1.6
mA
mA
All digital inputs at 0 or VDD, DAC active,
excludes load current
VIH = VDD and VIL = GND
Internal reference off
Internal reference on
0.4
1
μA
VIH = VDD and VIL = GND
4.5
1
Temperature range is −40°C to +105°C, typical at 25°C.
Temperature range is −55°C to +125°C, typical at 25°C. Linearity calculated using a reduced code range of 512 to 65,024. Output unloaded.
3
Guaranteed by design and characterization; not production tested.
4
Interface inactive. All DACs active. DAC outputs unloaded.
5
All four DACs powered down.
2
Rev. 0 | Page 4 of 16
AD5666-EP
AC CHARACTERISTICS
VDD =2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter 1
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Reference Feedthrough
SDO Feedthrough
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
Output Noise
1
2
Min
Typ
6
1.5
4
−90
3
0.1
0.5
2.5
3
340
−80
120
100
15
Max
10
Unit
μs
V/μs
nV-sec
dB
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
kHz
dB
nV/√Hz
nV/√Hz
μV p-p
Test Conditions/Comments 2
¼ to ¾ scale settling to ±2 LSB
1 LSB change around major carry (see Figure 29)
VREF = 2 V ± 0.1 V p-p, frequency = 10 Hz to 20 MHz
Daisy-chain mode; SDO load is 10 pF
VREF = 2 V ± 0.2 V p-p
VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz
DAC code = 0x8400, 1 kHz
DAC code = 0x8400, 10 kHz
0.1 Hz to 10 Hz
Guaranteed by design and characterization; not production tested.
Temperature range is −55°C to + 125°C, typical at 25°C.
Rev. 0 | Page 5 of 16
AD5666-EP
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 3 and
Figure 4. VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
t1 1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16 2
t172
t182
t192
2
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns max
ns min
ns min
ns min
Test Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC-to-SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
LDAC pulse width low
SCLK falling edge to LDAC rising edge
CLR pulse width low
SCLK falling edge to LDAC falling edge
CLR pulse activation time
SCLK rising edge to SDO valid
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge
Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
Daisy-chain mode only.
2mA
TO OUTPUT
PIN
IOL
VOH (MIN)
CL
50pF
2mA
IOH
09511-002
1
Limit at TMIN, TMAX
VDD = 2.7 V to 5.5 V
20
8
8
13
4
4
0
15
13
0
10
15
5
0
300
22
5
8
0
Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications
Rev. 0 | Page 6 of 16
AD5666-EP
t10
t1
t9
SCLK
t8
t2
t3
t4
t7
SYNC
t6
t5
DB31
DIN
DB0
t14
t11
LDAC1
t12
LDAC2
t13
09511-003
CLR
1ASYNCHRONOUS LDAC UPDATE MODE
2SYNCHRONOUS LDAC UPDATE MODE
Figure 3. Serial Write Operation
t1
SCLK
32
t7
t3
t4
64
t18
t2
t17
SYNC
t8
t9
DIN
DB31
DB0
DB0
DB31
INPUT WORD FOR DAC N + 1
INPUT WORD FOR DAC N
t16
DB31
SDO
UNDEFINED
DB0
INPUT WORD FOR DAC N
t19
09511-004
t11
LDAC
Figure 4. Daisy-Chain Timing Diagram
Rev. 0 | Page 7 of 16
AD5666-EP
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
VDD to GND
Digital Input Voltage to GND
VOUT to GND
VREFIN/VREFOUT to GND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ MAX)
TSSOP Package
Power Dissipation
θJA Thermal Impedance
Reflow Soldering Peak Temperature
SnPb
Pb Free
Rating
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−55°C to +125°C
−65°C to +150°C
150°C
(TJ MAX − TA)/θJA
150.4°C/W
240°C
260°C
Rev. 0 | Page 8 of 16
AD5666-EP
LDAC
1
14
SCLK
SYNC
2
13
DIN
VDD
3
12
GND
VOUTA
4
VOUTC
5
POR
6
9
CLR
VREFIN/VREFOUT
7
8
SDO
AD5666-EP
TOP VIEW
(Not to Scale)
11
VOUTB
10
VOUTD
09511-005
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 5. 14-Lead TSSOP (RU-14) Pin Configuration
Table 5. 14-Lead TSSOP (RU-14) Pin Function Descriptions
Pin No.
Mnemonic
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LDAC
SYNC
VDD
VOUTA
VOUTC
POR
VREFIN/VREFOUT
SDO
CLR
VOUTD
VOUTB
GND
DIN
SCLK
Rev. 0 | Page 9 of 16
AD5666-EP
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
10
8
0.6
DNL ERROR (LSB)
6
4
2
0
–2
0.4
0.2
0
–0.2
–0.4
–4
55000
60000
65000
55000
60000
65000
55000
60000
65000
CODE
Figure 6. INL
09511-009
50000
50000
50000
45000
40000
35000
30000
25000
5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k
CODE
20000
0
09511-006
–10
15000
–1.0
0
–0.8
–8
5000
–0.6
–6
10000
INL ERROR (LSB)
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
0.8
VDD = VREF = 5V
TA = 25°C
Figure 9. DNL—AD5666-EP-2
10
1.0
0.8
6
INL ERROR (LSB)
0.6
0.4
0.2
0
–0.2
4
2
0
–2
–4
–0.4
–6
–0.6
–8
–0.8
09511-010
45000
CODE
Figure 7. DNL
Figure 10. INL—AD5666-EP-1
1.0
0.6
4
0.4
CODE
Figure 11. DNL—AD5666-EP-1
Figure 8. INL—AD5666-EP-2
Rev. 0 | Page 10 of 16
09511-011
45000
0
65000
60000
55000
09511-008
CODE
50000
45000
40000
35000
–1.0
30000
–0.8
25000
–8
–10
20000
–0.6
15000
–6
10000
–0.4
5000
–4
40000
–0.2
35000
–2
0
30000
0
0.2
25000
2
20000
DNL ERROR (LSB)
6
0
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
0.8
15000
8
5000
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
10000
10
INL ERROR (LSB)
40000
60k
35000
50k
30000
40k
25000
30k
CODE
20000
20k
15000
10k
09511-007
0
5000
0
–10
–1.0
10000
DNL ERROR (LSB)
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
8
VDD = VREF = 5V
TA = 25°C
AD5666-EP
1.0
0
TA = 25°C
VDD = 5V
–0.02
0.5
ZERO-SCALE ERROR
–0.04
GAIN ERROR
0
ERROR (mV)
ERROR (% FSR)
–0.06
–0.08
–0.10
–0.12
–0.14
–0.5
–1.0
–1.5
FULL-SCALE ERROR
–0.16
–2.0
–20
0
20
40
60
TEMPERATURE (°C)
80
100
–2.5
2.7
09511-030
–0.20
–40
Figure 12. Gain Error and Full-Scale Error vs. Temperature
3.2
3.7
4.2
VDD (V)
4.7
5.2
Figure 15. Zero-Scale Error and Offset Error vs. Supply Voltage
1.5
140
25°C
55°C
125°C
120
1.0
09511-045
OFFSET ERROR
–0.18
100
ZERO-SCALE ERROR
80
0.5
60
20
–0.5
70
60
50
40
30
20
10
0
–1.0
–1.5
OFFSET ERROR
–20
0
20
40
60
TEMPERATURE (°C)
80
100
09511-021
–2.0
–2.5
–40
0
Figure 13. Zero-Scale Error and Offset Error vs. Temperature
–0.03
0
0.03
0.06
IDD @ 3.6V (mA)
0.09
25°C
55°C
125°C
–0.03
0
0.03
0.06
IDD @ 5.5V (mA)
0.09
09511-028
HITS
ERROR (mV)
40
0
Figure 16. IDD Histogram with External Reference
1.0
50
0.5
40
30
HITS
FULL-SCALE ERROR
–0.5
20
–1.0
10
–2.0
2.7
3.2
3.7
4.2
VDD (V)
4.7
5.2
0
–0.02
0
0.02
IDD_REF_ON (mA)
0.04
Figure 17. IDD Histogram with Internal Reference
Figure 14. Gain Error and Full-Scale Error vs. Supply Voltage
Rev. 0 | Page 11 of 16
0.06
09511-029
–1.5
09511-031
ERROR (% FSR)
GAIN ERROR
0
AD5666-EP
0.5
TA = 25°C
DAC LOADED WITH
ZERO-SCALE
SINKING CURRENT
0.8
0.7
0.2
VDD = 3V
VREFOUT = 1.25V
IDD (mA)
ERROR VOLTAGE (V)
0.3
0.1
0
0.6
0.4
–0.2
0.3
VDD = 5V
VREFOUT = 2.5V
–0.3
VDD = VREF = 3V
0.5
–0.1
0.2
0.1
–8
–6
–4
–2
0
2
CURRENT (mA)
4
6
8
10
09511-019
–0.4
–0.5
–10
0
512
Figure 18. Headroom at Rails vs. Source and Sink
20512
30512
40512
CODE
50512
60512
1.0
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
FULL SCALE
0.9
VDD = VREFIN = 5.5V
0.8
3/4 SCALE
3
0.7
IDD (mA)
4
VOUT (V)
10512
Figure 21. Supply Current vs. Code
6
5
VDD = VREF = 5V
0.9
09511-014
0.4
1.0
DAC LOADED WITH
FULL-SCALE
SOURCING CURRENT
MIDSCALE
2
1/4 SCALE
0.6
VDD = VREFIN = 3.6V
0.5
0.4
0.3
1
0.2
–20
–10
0
10
CURRENT (mA)
20
0.1
30
09511-012
–1
–30
ZERO SCALE
0
–40
Figure 19. Source and Sink Current Capability with VDD = 5 V
0
20
40
60
TEMPERATURE (°C)
80
100
Figure 22. Supply Current vs. Temperature
1.0
4
3
–20
09511-015
0
TA = 25°C
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
0.9
0.8
FULL SCALE
IDD (mA)
2
MIDSCALE
1
0.6
0.5
0.4
1/4 SCALE
0.3
0
0.2
ZERO SCALE
–1
–30
–20
–10
0
10
CURRENT (mA)
20
30
Figure 20. Source and Sink Current Capability with VDD = 3 V
0
2.7
3.2
3.7
4.2
VDD (V)
4.7
Figure 23. Supply Current vs. Supply Voltage
Rev. 0 | Page 12 of 16
5.2
09511-016
0.1
09511-013
VOUT (V)
0.7
3/4 SCALE
AD5666-EP
4.0
TA = 25°C
VDD = VREF = 5V
TA = 25°C
3.5
3.0
2.5
IDD (mA)
VDD
2.0
1
VDD = 5V
1.5
1.0
2
0.5
0
1
2
3
VLOGIC (V)
4
5
6
09511-017
0
CH1 2.0V
CH2 1.0V
M100µs 125MS/s
A CH1
1.28V
09511-033
VOUT
VDD = 3V
8.0ns/pt
Figure 27. Power-On Reset to Midscale
Figure 24. Supply Current vs. Logic Input Voltage
SYNC
1
SCLK
3
VDD = VREF = 5V
TA = 25°C
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2kΩ
AND 200pF TO GND
VOUT
VOUT = 909mV/DIV
VDD = 5V
09511-018
TIME BASE = 4µs/DIV
CH1 5.0V
CH3 5.0V
VDD
1
MAX(C2)*
420.0mV
2
8.0ns/pt
09511-020
VOUT
M100µs 125MS/s
A CH1
1.28V
A CH1
1.4V
2.505
2.504
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.496
2.495
2.494
2.493
2.492
2.491
2.490
2.489
2.488
2.487
2.486
2.485
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
4ns/SAMPLE NUMBER
GLITCH IMPULSE = 3.55nV-s
1 LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)
0
64
128
192
256
320
SAMPLE
384
Figure 29. Digital-to-Analog Glitch Impulse
Figure 26. Power-On Reset to 0 V
Rev. 0 | Page 13 of 16
448
512
09511-022
VOUT (V)
VDD = VREF = 5V
TA = 25°C
CH2 500mV
M400ns
Figure 28. Exiting Power-Down to Midscale
Figure 25. Full-Scale Settling Time
CH1 2.0V
CH2 500mV
09511-034
2
1
AD5666-EP
2.5000
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
DAC LOADED WITH MIDSCALE
2.4995
2.4990
2.4980
10µV/DIV
VOUT (V)
2.4985
2.4975
2.4970
1
2.4965
2.4960
0
64
128
192
256
320
SAMPLE
384
448
512
09511-038
2.4950
09511-035
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
4ns/SAMPLE NUMBER
2.4955
5s/DIV
Figure 33. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference
Figure 30. Analog Crosstalk
2.4900
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
DAC LOADED WITH MIDSCALE
2.4895
2.4890
5µV/DIV
2.4880
2.4875
1
2.4870
2.4865
0
64
128
192
256
320
SAMPLE
384
448
512
09511-039
2.4855
09511-036
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
4ns/SAMPLE NUMBER
2.4860
4s/DIV
Figure 31. DAC-to-DAC Crosstalk
Figure 34. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference
800
700
1
600
500
400
300
0
100
Figure 32. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
VDD = 5V
VREFOUT = 2.5V
200
100
Y AXIS = 2µV/DIV
X AXIS = 4s/DIV
TA = 25°C
MIDSCALE LOADED
VDD = 3V
VREFOUT = 1.25V
1k
10k
FREQUENCY (Hz)
100k
Figure 35. Noise Spectral Density, Internal Reference
Rev. 0 | Page 14 of 16
1M
09511-040
OUTPUT NOISE (nV/ Hz)
VDD = VREF = 5V
TA = 25°C
DAC LOADED WITH MIDSCALE
09511-037
VOUT (V)
2.4885
AD5666-EP
–20
VDD = 5V
TA = 25°C
DAC LOADED WITH FULL SCALE
VREF = 2V ± 0.3Vp-p
CLR
–40
–50
VOUT D
VOLTAGE (V)
HARMONIC DISTORTION (dB)
–30
–60
–70
–80
VOUT B
2k
4k
6k
FREQUENCY (Hz)
8k
10k
TIME (ns)
Figure 36. Total Harmonic Distortion
Figure 38. Hardware CLR
16
5
VREF = VDD
TA = 25°C
MULTIPLYING BANDWIDTH (dB)
14
VDD = 3V
12
10
VDD = 5V
6
–5
–10
–15
–20
–25
–30
4
0
1
2
3
4
5
6
7
CAPACITANCE (nF)
8
9
10
Figure 37. Settling Time vs. Capacitive Load
–40
10k
100k
1M
FREQUENCY (Hz)
Figure 39. Multiplying Bandwidth
Rev. 0 | Page 15 of 16
10M
09511-044
–35
09511-042
TIME (µs)
VDD = 5V
TA = 25°C
0
8
09511-043
–100
09511-041
–90
AD5666-EP
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
0.65 BSC
1.20
MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
0.75
0.60
0.45
061908-A
1.05
1.00
0.80
Figure 40. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD5666SRU-EP-2RL7
1
Power-On
Reset to Code
Zero
Accuracy
±21 LSB INL
Internal
Reference
2.5 V
Temperature Range
−55°C to +125°C
Z = RoHS Compliant Part.
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09511-0-11/10(0)
Rev. 0 | Page 16 of 16
Package Description
14-Lead TSSOP
Package Option
RU-14