Quad, Current-Output,
Serial-Input 16-Bit DAC
AD5544-EP
Enhanced Product
2 mA full-scale current ± 20%, with VREF = ±10 V
0.9 µs settling time to ±0.1%
12 MHz multiplying bandwidth
Midscale glitch of −1 nV-sec
Midscale or zero-scale reset
4 separate, 4-quadrant multiplying reference inputs
SPI-compatible, 3-wire interface
Double-buffered registers enable
Simultaneous multichannel change
Internal power-on reset
Compact 28-lead SSOP
FUNCTIONAL BLOCK DIAGRAM
VREFA
VREFB
VREFC
VREFD
FEATURES
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
SDO
SDI
VDD
RFBA
INPUT
REGISTER R
DAC A
REGISTER R
DAC A
IOUTA
AGNDA
RFBB
16
INPUT
REGISTER R
DAC B
REGISTER R
DAC B
IOUTB
AGNDB
RFBC
INPUT
REGISTER R
DAC C
REGISTER R
DAC C
IOUTC
AGNDC
CS
Supports defense and aerospace applications (AQEC)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
1 assembly/test site
1 fabrication site
Enhanced product change notification
Qualification data available on request
CLK
RFBD
EN
DAC A
B
C
D
2:4
DECODE
DGND
INPUT
REGISTER R
DAC D
REGISTER R
DAC D
IOUTD
AGNDD
AD5544-EP
POWER-ON
RESET
RS
MSB
LDAC
AGNDF
VSS
10083-001
ENHANCED PRODUCT FEATURES
Figure 1.
APPLICATIONS
Automatic test equipment
Instrumentation
Digitally controlled calibration
GENERAL DESCRIPTION
The AD5544-EP quad, 16-bit, current output, digital-to-analog
converter (DAC) is designed to operate from a 2.7 V to
5.5 V supply range.
The applied external reference input voltage (VREFx) determines
the full-scale output current. Integrated feedback resistors (RFB)
provide temperature-tracking, full-scale voltage outputs when
combined with an external I-to-V precision amplifier.
A double-buffered serial data interface offers high speed, 3-wire,
SPI- and microcontroller-compatible inputs using serial data in
(SDI), a chip select (CS), and clock (CLK) signals. In addition, a
serial data out pin (SDO) allows for daisy chaining when multiple
packages are used. A common, level-sensitive, load DAC strobe
(LDAC) input allows the simultaneous update of all DAC outputs
from previously loaded input registers. Additionally, an internal
power-on reset forces the output voltage to 0 at system turn-on.
The MSB pin allows system reset assertion (RS) to force all registers
to zero code when MSB = 0 or to half-scale code when MSB = 1.
The AD5544-EP is packaged in the compact 28-lead SSOP.
Additional application and technical information can be found
in the AD5544 data sheet.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
AD5544-EP
Enhanced Product
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................5
Enhanced Product Features ............................................................ 1
ESD Caution...................................................................................5
Applications ....................................................................................... 1
Pin Configuration and Function Descriptions..............................6
Functional Block Diagram .............................................................. 1
Typical Performance Characteristics ..............................................8
General Description ......................................................................... 1
Outline Dimensions ....................................................................... 10
Revision History ............................................................................... 2
Ordering Guide .......................................................................... 10
Specifications..................................................................................... 3
Timing Diagrams.......................................................................... 4
REVISION HISTORY
4/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
Enhanced Product
AD5544-EP
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, VSS = 0 V, IOUTx = virtual GND, AGNDx = 0 V, VREFA = VREFB = VREFC = VREFD = 10 V, TA = full operating temperature
range of −55°C to +125°C, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE 1
Resolution
Relative Accuracy
Differential Nonlinearity
Output Leakage Current
Full-Scale Gain Error
Full-Scale Tempco 2
Feedback Resistor
REFERENCE INPUT
VREFx Range
Input Resistance
Input Resistance Match
Input Capacitance2
ANALOG OUTPUT
Output Current
Output Capacitance2
LOGIC INPUT AND OUTPUT
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance2
Logic Output Low Voltage
Logic Output High Voltage
INTERFACE TIMING2, 3
Clock Width High
Clock Width Low
CS to Clock Setup
Clock to CS Hold
Clock to SDO Propagation
Delay
Load DAC Pulse Width
Data Setup
Data Hold
Load Setup
Load Hold
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation
Power Supply Sensitivity
Symbol
Test Condition/Comments
N
INL
DNL
IOUTx
1 LSB = VREFx/216 = 153 µV when VREF = 10 V
GFSE
TCVFS
RFBx
VREFx
RREFx
RREFx
CREFx
Min
Data = 0x0000, TA = 25°C
Data = 0x0000, TA = 85°C
Data = 0xFFFF
VDD = 5 V
4
±0.75
1
6
Max
Unit
16
±1.5
±1.5
10
20
±4
Bits
LSB
LSB
nA
nA
mV
ppm/°C
kΩ
8
+15
8
V
kΩ
%
pF
2.5
mA
pF
0.8
4
V
V
µA
pF
V
V
tCH
tCL
tCSS
tCSH
tPD
25
25
0
25
2
ns
ns
ns
ns
ns
tLDAC
tDS
tDH
tLDS
tLDH
25
20
20
5
25
IOUTx
COUTx
VIL
VIH
IIL
CIL
VOL
VOH
VDD RANGE
IDD
ISS
PDISS
PSS
−15
4
Typ
Channel-to-channel
Data = 0xFFFF
Code dependent
6
0.35
5
1.25
35
2.4
1
10
0.4
IOL = 1.6 mA
IOH = 100 µA
20
ns
ns
ns
ns
ns
2.7
Logic inputs = 0 V
Logic inputs = 0 V, VSS = −5 V
Logic inputs = 0 V
∆VDD = ±5%
Rev. 0 | Page 3 of 12
0.001
5.5
5
9
1.25
0.006
V
µA
µA
mW
%/%
AD5544-EP
Enhanced Product
Parameter
AC CHARACTERISTICS 4
Output Voltage Settling Time
Reference Multiplying
Bandwidth (BW)
DAC Glitch Impulse
Feedthrough Error
Crosstalk Error
Digital Feedthrough
Total Harmonic Distortion
Output Spot Noise Voltage
Symbol
Test Condition/Comments
tS
BW − 3 dB
To ±0.1% of full scale, data = 0x0000 to 0xFFFF to 0x0000
VREFx = 5 V p-p, data = 0xFFFF, CFB = 2.0 pF,
0.9
12
µs
MHz
Q
VOUTx/VREFx
VOUTA/VREFB
VREFx = 8 V, data = 0x0000 to 0x8000 to 0x0000
Data = 0x0000, VREFx = 100 mV rms, f = 100 kHz
Data = 0x0000, VREFB = 100 mV rms, adjacent channel,
f = 100 kHz
CS = 1, fCLK = 1 MHz
VREFx = 5 V p-p, data = 0xFFFF, f = 1 kHz
f = 1 kHz, BW = 1 Hz
−1
−65
−90
nV-sec
dB
dB
0.6
−98
7
nV-sec
dB
nV/√Hz
Q
THD
eN
Min
Typ
Max
1
Unit
All static performance tests (except IOUTx) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5544 RFB terminal
is tied to the amplifier output. Typical values represent average readings measured at 25°C.
2
These parameters are guaranteed by design and not subject to production testing.
3
All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
4
All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier.
TIMING DIAGRAMS
A1
A0
D15
D14
D13
D12
D11
D10
D1
D0
INPUT
REG
LD
CLK
CS
tCSS
tDS
tDH
tCH
tCL
tCSH
tLDS
LDAC
tPD
tLDAC
SDO
Figure 2. Timing Diagram
Rev. 0 | Page 4 of 12
tLDH
10083-004
SDI
Enhanced Product
AD5544-EP
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VDD to GND
VSS to GND
VREFx to GND
Logic Input and Output to GND
V(IOUTx) to GND
AGNDx to DGND
Input Current to Any Pin Except Supplies
Package Power Dissipation
Thermal Resistance
28-Lead SSOP
32-Lead LFCSP
Maximum Junction Temperature (TJ Max)
Operating Temperature Range, Enhanced
Product (EP Version)
Storage Temperature Range
Lead Temperature
Vapor Phase, 60 Sec
Infrared, 15 Sec
Rating
−0.3 V, +8 V
+0.3 V, −7 V
−18 V, +18 V
−0.3 V, +8 V
−0.3 V, VDD + 0.3 V
−0.3 V, +0.3 V
±50 mA
(TJ max − TA)/θJA
θJA
100°C/W
32.5°C/W
150°C
−55°C to +125°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
ESD CAUTION
−65°C to +150°C
215°C
220°C
Rev. 0 | Page 5 of 12
AD5544-EP
Enhanced Product
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AGNDA 1
28
IOUTA 2
27
IOUTD
VREFA 3
26
VREFD
RFBA 4
25
RFBD
MSB 5
24
DGND
23
VSS
22
AGNDF
AD5544-EP
CS 8
TOP VIEW
(Not to Scale)
CLK 9
21
LDAC
20
SDO
NC
SDI 10
19
RFBB 11
18
RFBC
VREFB 12
17
VREF C
IOUTB 13
16
IOUTC
AGNDB 14
15
AGNDC
NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
10083-003
RS 6
VDD 7
AGNDD
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
2
3
Mnemonic
AGNDA
IOUTA
VREFA
4
5
6
RFBA
MSB
RS
7
8
VDD
CS
9
10
11
12
CLK
SDI
RFBB
VREFB
13
14
15
16
17
IOUTB
AGNDB
AGNDC
IOUTC
VREFC
18
19
20
RFBC
NC
SDO
21
LDAC
22
23
24
25
AGNDF
VSS
DGND
RFBD
Description
DAC A Analog Ground.
DAC A Current Output.
DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. This pin can be tied to the
VDD pin.
Establish the voltage output for DAC A by connecting to an external amplifier output.
MSB Pin. Set pin during a reset pulse (RS) or at system power-on if tied to ground or VDD.
Reset Pin, Active Low Input. Input registers and DAC registers are set to all 0s or half-scale code, determined by
the voltage on the MSB pin. Register data = 0x0000 when MSB = 0.
Positive Power Supply Input. Specified range of operation: 5 V ± 10%.
Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data to the
input register when CS/LDAC returns high. Does not affect LDAC operation.
Clock Input. Positive edge clocks data into the shift register.
Serial Data Input. Input data loads directly into the shift register.
Establish the voltage output for DAC B by connecting to an external amplifier output.
DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. This pin can be tied to the
VDD pin.
DAC B Current Output.
DAC B Analog Ground.
DAC C Analog Ground.
DAC C Current Output.
DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. This pin can be tied to the
VDD pin.
Establish the voltage output for DAC C by connecting to an external amplifier output.
No Connect. Do not connect to this pin.
Serial Data Output. Input data loads directly into the shift register. Data appears at SDO at 19 clock pulses for
the AD5544-EP after input at the SDI pin.
Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC registers.
Asynchronous active low input.
High Current Analog Force Ground.
Negative Bias Power Supply Input. Specified range of operation: −5.5 V to +0.3 V.
Digital Ground Pin.
Establish the voltage output for DAC D by connecting to an external amplifier output.
Rev. 0 | Page 6 of 12
Enhanced Product
Pin No.
26
Mnemonic
VREFD
27
28
IOUTD
AGNDD
AD5544-EP
Description
DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. This pin can be tied to the
VDD pin.
DAC D Current Output.
DAC D Analog Ground.
Rev. 0 | Page 7 of 12
AD5544-EP
Enhanced Product
TYPICAL PERFORMANCE CHARACTERISTICS
0.10
10
VDD = 5V
VREF = 10V
0.05
5
–0.05
GAIN ERROR (LSB)
–0.10
–0.15
–0.20
–0.25
–0.30
0
–5
–10
10083-006
–15
–0.35
–0.40
0
10,000
20,000
30,000 40,000
CODE
50,000
60,000
–20
–1500
70,000
–500
0
500
1000
1500
Figure 7. Gain Error vs. Op Amp Offset
–3.88
1.5
VDD = 5V
VREF = 10V
0x0FFF
–3.90
1.0
–3.92
0xF000
–3.94
0.5
0x7FFF
VOUT (V)
0x8000
0
–0.5
–3.96
–3.98
–4.00
–4.02
–4.04
10083-009
–1.0
–1500
–1000
–500
0
500
OP AMP OFFSET (µV)
1000
1500
10083–012
INL (LSB)
–1000
OP AMP OFFSET (µV)
Figure 4. DNL Error vs. Code, TA = 25°C
–1.5
–2000
10083-013
DNL ERROR (LSB)
0
–4.06
–4.08
2000
0.4
0.5
Figure 5. INL Error vs. Op Amp Offset
0.6
0.7
0.8
0.9
TIME (µs)
1.0
1.1
1.2
Figure 8. Midscale Transition
1.00
VDD = 5V
VREF = 10V
VDD = 5V
VREF = 10V
0.75
VOUT
0.50
5V/DIV
0x0FFF
0
–0.75
10083-018
0x8000
–0.50
–1.00
–1000
LDAC
0xF000
–0.25
10083-011
DNL (LSB)
0.25
–750
–500
–250
0
250
500
750
1000
OP AMP OFFSET (µV)
Figure 6. DNL Error vs. Op Amp Offset
Figure 9. Large Signal Settling Time
Rev. 0 | Page 8 of 12
Enhanced Product
AD5544-EP
0.1
4
100
VDD = 5V
VREF = 10V
90
0
0
80
70
–0.1
PSRR (dB)
–8
LDAC (V)
VOUT (V)
–4
–12
60
50
40
30
20
–16
2
4
6
8
0
100
10083-019
0
–20
10
TIME (µs)
1k
10k
100k
1M
FREQUENCY (Hz)
10083-020
10
–0.2
–2
Figure 12. Power Supply Rejection vs. Frequency
Figure 10. Small Signal Settling Time
300
10,000
250
SUPPLY CURRENT (µA)
ZERO SCALE
MIDSCALE
FULL SCALE
0x5555
100
10
200
150
100
1
1k
10k
100k
1M
CLOCK FREQUENCY (Hz)
10M
10083-017
50
10083-015
IDD (µA)
1000
0
100M
0
0.5
1.0
1.5
2.0
2.5
3.0
LOGIC INPUT (V)
3.5
4.0
4.5
Figure 13. Power Supply Current vs. Logic Input Voltage
Figure 11. Power Supply Current vs. Clock Frequency
Rev. 0 | Page 9 of 12
5.0
AD5544-EP
Enhanced Product
OUTLINE DIMENSIONS
10.50
10.20
9.90
15
28
5.60
5.30
5.00
1
8.20
7.80
7.40
14
0.65 BSC
0.38
0.22
SEATING
PLANE
8°
4°
0°
COMPLIANT TO JEDEC STANDARDS MO-150-AH
0.95
0.75
0.55
060106-A
0.05 MIN
COPLANARITY
0.10
0.25
0.09
1.85
1.75
1.65
2.00 MAX
Figure 4. 28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5544SRS-EP
Resolution (Bits)
16
INL LSB
±1.5
DNL LSB
±1.5
Temperature Range
−55°C to +125°C
Rev. 0 | Page 10 of 12
Package Description
28-Lead Shrink Small Outline Package [SSOP]
Package
Option
RS-28
Enhanced Product
AD5544-EP
NOTES
Rev. 0 | Page 11 of 12
AD5544-EP
Enhanced Product
NOTES
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10083-0-4/12(0)
Rev. 0 | Page 12 of 12