Evaluation Board User Guide
UG-070
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Setting Up the Evaluation Board for the ADCLK854
PACKAGE LIST
GENERAL DESCRIPTION
Evaluation board with components installed
Applicable documents (schematic and layout)
This user guide describes how to set up and use the evaluation
board for the ADCLK854. The ADCLK854 data sheet contains
full technical details about the specifications and operation of this
device and should be consulted when using the evaluation board.
08669-001
The ADCLK854 is a high performance clock fanout buffer.
The evaluation board is fabricated using a high quality Rogers®
dielectric material. Transmission line paths are kept as close to
100 Ω differentially as possible.
Figure 1. Evaluation Board
Please see the last page for an important warning and disclaimers.
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Evaluation Board User Guide
TABLE OF CONTENTS
Package List ....................................................................................... 1 Clock Outputs ................................................................................4 General Description ......................................................................... 1 Evaluation Board Schematic and Artwork.....................................5 Revision History ............................................................................... 2 ESD Caution...................................................................................8 Recommended Board Setup............................................................ 3 REVISION HISTORY
12/09—Revision 0: Initial Version
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UG-070
RECOMMENDED BOARD SETUP
The range of the peak-to-peak input voltage swing at CLK1 is
0.15 V to 1.8 V. Output jitter performance is degraded by input
slew rate, as shown in the ADCLK854 data sheet.
The recommended setup for the ADCLK854 evaluation board
is shown in Figure 2. VS is set to 1.8 V. The IN_SEL jumper
provides the desired input configuration. Logic 0 on the IN_SEL
pin selects the CLK0 and CLK0 inputs, and Logic 1 on the
IN_SEL pin selects the CLK1 and CLK1 inputs.
Table 1. Basic Equipment Required
Quantity
1
1
1
1
2
On the evaluation board, the CLK0 and CLK0 inputs are set up for
ac-coupled, differential operation to the ADCLK854. This input
configuration requires the user to provide the appropriate ac
swing to both inputs. Refer to the ADCLK854 data sheet and
the schematic (see Figure 4) for the input specifications.
Description
Single power supply
Signal source
High bandwidth oscilloscope
High bandwidth differential probe
Matched high speed cables
CLK1 is set up to evaluate with a single-ended source via the balun
on the evaluation board. In addition, series capacitors in the
path provide ac-coupled inputs to the ADCLK854.
POWER SUPPLY
1.8V
GND
VS
CLK1
CLK1
ADCLK854
EVALUATION
BOARD
OUTx
PROBE
OSCILLOSCOPE
OUTx
CLK0
08669-002
CLOCK
SOURCE
GND
CLK0
Figure 2. Recommended Setup for ADCLK854 Evaluation
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Evaluation Board User Guide
The outputs that go to the SMA connector may not have a full
output swing, and reflections may be observed.
CLOCK OUTPUTS
The ADCLK854 outputs are pin programmable up to 12
differential LVDS outputs or 24 single-ended 1.8 V CMOS
outputs. Jumpers CTRL_A, CTRL_B, CTRL_C, and SLEEP
are used to configure the outputs. See Table 2 and Figure 3
for jumper assignments.
Table 2. Output Pin Assignment
For high precision measurements, it is recommended to evaluate the
nonlaunched outputs on the evaluation board. The nonlaunched
outputs do not go to the SMA connectors. In this case, the
ADCLK854 is physically close to the output load and avoids the
issues of driving a 50 Ω cable. Note that CMOS is not designed
to operate in a 50 Ω environment.
Jumper
Name
CTRL_A
CTRL_B
CTRL_C
SLEEP
Jumper Setting
Logic 0 = LVDS; Logic 1 = CMOS
Logic 0 = LVDS; Logic 1 = CMOS
Logic 0 = LVDS; Logic 1 = CMOS
Logic 1 = sleep
The nonlaunched outputs have a full output swing with 100 Ω
differential trace impedance into a 100 Ω resistor to minimize
reflections. These outputs are set up to evaluate using a high
bandwidth differential probe and oscilloscope. See the
evaluation board schematic in Figure 4 for more details.
ADCLK854
VREF
VS/2
LVDS/
CMOS
OUT0 (OUT0A)
OUT0 (OUT0B)
CLK0
OUT1 (OUT1A)
CLK0
OUT1 (OUT1B)
CLK1
OUT2 (OUT2A)
CLK1
OUT2 (OUT2B)
IN_SEL
OUT3 (OUT3A)
CTRL_A
OUT3 (OUT3B)
LVDS/
CMOS
OUT4 (OUT4A)
OUT4 (OUT4B)
OUT5 (OUT5A)
OUT5 (OUT5B)
CTRL_B
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
LVDS/
CMOS
OUT8 (OUT8A)
OUT8 (OUT8B)
OUT9 (OUT9A)
OUT9 (OUT9B)
CTRL_C
OUT10 (OUT10A)
OUT10 (OUT10B)
SLEEP
OUT11 (OUT11B)
Figure 3. 1:12 Clock/Data Buffer Block Diagram
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08669-003
OUT11 (OUT11A)
Affected Outputs
Output 0 to Output 3
Output 4 to Output 7
Output 8 to Output 11
Output 0 to Output 11
GND
1
1
GND
2 3 4 5
CLK1
GND
2 3 4 5
CLK1B
2 3 4 5
1
GND
GND
C2
DNI
0
0.1UF
0.1UF
C3
R7
SEC
1
T1
C4
PRI
5
0
DNI
R6
4
3
MABA-007159-000000
0.1UF
GND
0
0
CLK0
R4
R5
C1
GND
0.1UF
C6
0.1UF
C5
100OHM DIFF MATCH
100OHM DIFF MATCH
GND11
0.1UF
1
1
1
R12
2 3 4 5
100
CLK0B
OUT11 1 OUT11B
49.9
DNI
R9
1
2
3
1
2
3
CTRL_B
CTRL_C
GND
VS
GND
VS
GND
VS
GND
VS
1.1K
R11
1.1K
R10
1.1K
R2
1.1K
R1
VS
1
R13
2
GND
1.1K
3
MOLEX22-28-4033
SLEEP
1
2
3
R8
CTRL_A
49.9
1
2
3
100OHM DIFF MATCH
VREF
IN_SEL
R14
R15
DNI
DNI
GND0
1 R3 2
100
GND
1
2
3
4
5
6
7
8
9
10
11
12
R16
100
VREF
CLK0B
CLK0
GND
CLK1B
CLK1
VS
OUT11B
OUT11
IN_SEL
CTRL_A
CTRL_B
1
1
1GND
OUT0 OUT0B
C7
GND
1
OUT2B
GND
GND3
100
R18
5 4 3 2
CP 48-6
GND
5 4 3 2
OUT10 1
100
1
GND
1
GND
GND
OUT9
GND
5 4 3 2
OUT9B 1
100
R20
1
OUT8
100
R21
5 4 3 2
1
OUT8B
1
NC
NC
OUT4
OUT4B
OUT5
OUT5B
VS
GND
OUT6
OUT6B
OUT7
OUT7B
R19 1
100
36
35
34
33
32
31
30
29
28
27
26
25
5 4 3 2
1GND
OUT3 OUT3B
OUT2
ADCLK854
R17
5 4 3 2
OUT10B 1
GND
C11
OUT1B
0.1UF
1
0.1UF
2 3 4 5
R22
100OHM DIFF MATCH
100OHM DIFF MATCH
100OHM DIFF MATCH
100OHM DIFF MATCH
GND
LABEL "VS (1.8V)"
VS
GND
GND
1
2
PWRCONN
0.1UF
C28
0.1UF
C27
0.1UF
C26
0.1UF
C25
1
OUT5
1
OUT6
GND
OUT6B
5 4 3 2
1
GND
5 4 3 2
GND
1
OUT5B
5 4 3 2
GND
5 4 3 2
25.602.2253.0
GND
GND
VS
BYPASS CAPACITORS (SUPPLY)
GND
VREF
VS
BYPASS CAPACITORS (DUT)
0.1UF
C36
OUT1
100OHM DIFF MATCH
PAD
0.1UF
C38
1
C9
100
100
0.1UF
GND
0.1UF
0.1UF
100OHM DIFF MATCH
100OHM DIFF MATCH
C12
C31
C32
C18
100OHM DIFF MATCH
0.1UF
C33
0.1UF
10UF
C13
100OHM DIFF MATCH
100OHM DIFF MATCH
100
100
48
47
46
45
44
43
42
41
40
39
38
37
C14
Figure 4. ADCLK854 Evaluation Board Schematic
1
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0.1UF
1
0.1UF
100
R23
OUT0
OUT0B
OUT1
OUT1B
GND
VS
OUT2
OUT2B
OUT3
OUT3B
GND
VS
13 CTRL_C
14 SLEEP
15 OUT10B
16 OUT10
17 GND
18 VS
19 OUT9B
20 OUT9
21 OUT8B
22 OUT8
23 GND
24 VS
1
100OHM DIFF MATCH
OUT4 OUT4B
C20
R24
R25
1
100
1
0.1UF
GND4
GND8
2 3 4 5
Evaluation Board User Guide
UG-070
EVALUATION BOARD SCHEMATIC AND ARTWORK
1
OUT7 OUT7B
GND7
1
08669-004
0.1UF
0.1UF
C42
0.1UF
C40
C29
Evaluation Board User Guide
08669-006
UG-070
08669-007
Figure 5. Top Trace Layer
Figure 6. Ground Plane Layer
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08669-008
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08669-009
Figure 7. VS Power Plane Layer
Figure 8. Bottom Trace Layer
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Evaluation Board User Guide
NOTES
ESD CAUTION
Evaluation boards are only intended for device evaluation and not for production purposes. Evaluation boards are supplied “as is” and without warranties of any kind, express,
implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. No license is granted by implication or otherwise under
any patents or other intellectual property by application or use of evaluation boards. Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Analog Devices reserves the
right to change devices or specifications at any time without notice. Trademarks and registered trademarks are the property of their respective owners. Evaluation boards are not
authorized to be used in life support devices or systems.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
UG08669-0-12/09(0)
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