<0.5 Ω CMOS, 1.65 V to 3.6 V,
Quad SPST Switches
ADG811/ADG812/ADG813
0.5 Ω typical on resistance
0.8 Ω maximum on resistance at 125°C
1.65 V to 3.6 V operation
Automotive temperature range: −40°C to +125°C
High current carrying capability: 300 mA continuous
Rail-to-rail switching operation
Fast switching times: <25 ns
Typical power consumption <0.1 μW
FUNCTIONAL BLOCK DIAGRAMS
S1
IN1
S1
IN1
D1
D1
S2
IN2
S2
IN2
D2
D2
ADG811
D2
ADG812
S3
IN3
ADG813
S3
IN3
S3
IN3
D3
S4
IN4
Cellular phones
MP3 players
Power routing
Battery-powered systems
PCMCIA cards
Modems
Audio and video signal routing
Communications systems
D1
S2
IN2
D3
APPLICATIONS
S1
IN1
D3
S4
IN4
S4
IN4
D4
D4
SWITCHES SHOWN FOR A LOGIC 1 INPUT
Figure 1.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG811/ADG812/ADG813 are low voltage CMOS devices
containing four independently selectable switches. These switches
offer ultralow on resistance of less than 0.8 Ω over the full
temperature range. The digital inputs can handle 1.8 V logic
with a 2.7 V to 3.6 V supply.
1.
2.
3.
4.
These devices contain four independent single-pole/singlethrow (SPST) switches. The ADG811 and ADG812 differ only
in that the digital control logic is inverted. The ADG811
switches are turned on with a logic low on the appropriate
control input, while a logic high is required to turn on the
switches of the ADG812. The ADG813 contains two switches
whose digital control logic is similar to the ADG811, while the
logic is inverted on the other two switches.
5.
6.
<0.8 Ω over full temperature range of −40°C to +125°C.
Single 1.65 V to 3.6 V operation.
Operational with 1.8 V CMOS logic.
High current handling capability (300 mA continuous
current at 3.3 V).
Low THD + N (0.02% typical).
Small 3 mm × 3 mm LFCSP package and 16-lead TSSOP
package.
Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. The
ADG813 exhibits break-before-make switching action.
The ADG811/ADG812/ADG813 are fully specified for 3.3 V,
2.5 V, and 1.8 V supply operation. The ADG811 is available in a
16-lead TSSOP package and a 16-lead LFCSP package, and the
ADG812/ADG813 are available in a 16-lead TSSOP package.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2009 Analog Devices, Inc. All rights reserved.
D4
04306-A-001
FEATURES
ADG811/ADG812/ADG813
TABLE OF CONTENTS
Features .............................................................................................. 1 Pin Configurations and Function Descriptions ............................7 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................8 General Description ......................................................................... 1 Test Circuits ..................................................................................... 11 Functional Block Diagrams ............................................................. 1 Terminology .................................................................................... 13 Product Highlights ........................................................................... 1 Outline Dimensions ....................................................................... 14 Revision History ............................................................................... 2 Ordering Guide .......................................................................... 15 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 6 ESD Caution .................................................................................. 6 REVISION HISTORY
11/09—Rev. A to Rev. B
Added 16-Lead LFCSP....................................................... Universal
Changes to Table 4 ............................................................................ 6
Changes to Pin Configurations and Function Description
Section ................................................................................................ 7
Moved Terminology Section ......................................................... 13
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 15
5/04—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Updated Package Choices ................................................. Universal
11/03—Revision 0: Initial Version
Rev. B | Page 2 of 16
ADG811/ADG812/ADG813
SPECIFICATIONS
VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted. Temperature range for the Y version is −40°C to +125°C.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between
Channels, ΔRON
On Resistance Flatness, RFLAT (ON)
+25°C
−40°C to +85°C
−40°C to +125°C
Unit
0 V to VDD
V
Ω typ
0.5
0.65
0.04
0.75
0.8
0.075
0.08
0.15
0.16
0.1
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
±0.2
±1
±0.2
±8
Drain Off Leakage, ID (Off )
±1
±0.2
±1
±8
±80
±15
±90
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
±80
tOFF
Break-Before-Make Time Delay, tBBM
(ADG813 Only)
VDD = 2.7 V, VS = 0 V to VDD, IS = 10 mA
nA typ
VDD = 3.6 V
VS = 0.6 V/3.3 V, VD = 3.3 V/0.6 V;
see Figure 20
nA max
nA typ
VS = 0.6 V/3.3 V, VD = 3.3 V/0.6 V;
see Figure 20
VS = VD = 0.6 V or 3.3 V; see Figure 21
VIN = VINL or VINH
6
V min
V max
μA typ
μA max
pF typ
21
25
4
5
17
ns typ
ns max
ns typ
ns max
ns typ
RL = 50 Ω, CL = 35 pF
VS = 1.5 V/0 V; see Figure 22
RL = 50 Ω, CL = 35 pF
VS = 1.5 V; see Figure 22
RL = 50 Ω, CL = 35 pF
VS1 = VS2 = 1.5 V; see Figure 23
VS = 1.5 V, RS = 0 Ω, CL = 1 nF;
see Figure 24
RL = 50 Ω, CL = 5 pF, f = 100 kHz;
see Figure 25
RL = 50 Ω, CL = 5 pF, f = 100 kHz;
see Figure 27
RL = 32 Ω, f = 20 Hz to 20 kHz,
VS = 2 V p-p
RL = 50 Ω, CL = 5 pF, f = 100 kHz
RL = 50 Ω, CL = 5 pF; see Figure 26
2
0.8
0.005
26
28
6
7
5
30
ns min
pC typ
Off Isolation
−67
dB typ
Channel-to-Channel Crosstalk
−90
dB typ
Total Harmonic Distortion (THD + N)
0.02
%
−0.05
90
30
35
60
dB typ
MHz typ
pF typ
pF typ
pF typ
0.003
μA typ
μA max
1.0
1
VDD = 2.7 V, VS = 0.5 V, IS = 10 mA
Ω max
Ω typ
Ω max
Charge Injection
Insertion Loss
−3 dB Bandwidth
CS (Off )
CD (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD
VDD = 2.7 V, VS = 0 V to VDD, IS = 10 mA;
see Figure 19
nA max
nA typ
nA max
±0.1
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS 1
tON
Ω max
Ω typ
Test Conditions/Comments
4
Guaranteed by design, but not subject to production test.
Rev. B | Page 3 of 16
VDD = 3.6 V
Digital inputs = 0 V or 3.6 V
ADG811/ADG812/ADG813
VDD = 2.5 V ± 0.2 V, GND = 0 V, unless otherwise noted. Temperature range for the Y version is −40°C to +125°C.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between
Channels, ΔRON
On Resistance Flatness, RFLAT (ON)
+25°C
−40°C to +85°C
−40°C to +125°C
Unit
0 V to VDD
V
Ω typ
0.65
0.72
0.04
0.8
0.88
0.08
0.085
0.23
0.24
0.16
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
±0.2
±1
±0.2
±6
Drain Off Leakage, ID (Off )
±1
±0.2
±1
±6
±35
±11
±70
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
±35
1.7
0.7
0.005
±0.1
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS 1
tON
tOFF
Break-Before-Make Time Delay, tBBM
(ADG813 Only)
6
22
27
4
6
18
29
30
7
8
5
nA typ
VDD = 2.7 V
VS = 0.6 V/2.4 V, VD = 2.4 V/0.6 V;
see Figure 20
nA max
nA typ
VS = VD = 0.6 V or 2.4 V; see Figure 21
V min
V max
μA typ
μA max
pF typ
VIN = VINL or VINH
ns typ
ns max
ns typ
ns max
ns typ
RL = 50 Ω, CL = 35 pF
VS = 1.5 V/ 0 V; see Figure 22
RL = 50 Ω, CL = 35 pF
VS = 1.5 V; see Figure 22
RL = 50 Ω, CL = 35 pF
VS1 = VS2 = 1.5 V; see Figure 23
VS = 1.25 V, RS = 0 Ω, CL = 1 nF;
see Figure 24
RL = 50 Ω, CL = 5 pF, f = 100 kHz;
see Figure 25
RL = 50 Ω, CL = 5 pF, f = 100 kHz;
see Figure 27
RL = 32 Ω, f = 20 Hz to 20 kHz,
VS = 1.5 V p-p
RL = 50 Ω, CL = 5 pF, f = 100 kHz
RL = 50 Ω, CL = 5 pF; see Figure 26
Off Isolation
−67
dB typ
Channel-to-Channel Crosstalk
−90
dB typ
Total Harmonic Distortion (THD + N)
0.022
%
−0.06
90
32
37
60
dB typ
MHz typ
pF typ
pF typ
pF typ
0.003
μA typ
μA max
Guaranteed by design, but not subject to production test.
Rev. B | Page 4 of 16
VS = 0.6 V/2.4 V, VD = 2.4 V/0.6 V;
see Figure 20
nA max
nA typ
nA max
ns min
pC typ
4
VDD = 2.3 V, VS = 0.55 V, IS = 10 mA
VDD = 2.3 V, VS = 0 V to VDD, IS = 10 mA
25
1.0
VDD = 2.3 V, VS = 0 V to VDD, IS = 10 mA;
see Figure 19
Ω max
Ω typ
Ω max
Charge Injection
Insertion Loss
−3 dB Bandwidth
CS (Off )
CD (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD
1
Ω max
Ω typ
Test Conditions/Comments
VDD = 2.7 V
Digital inputs = 0 V or 2.7 V
ADG811/ADG812/ADG813
VDD = 1.65 V to 1.95 V, GND = 0 V, unless otherwise noted. Temperature range for the Y version is −40°C to +125°C.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between
Channels, ΔRON
LEAKAGE CURRENTS
Source Off Leakage IS (Off )
Drain Off Leakage ID (Off )
Channel On Leakage ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
+25°C
−40°C to +85°C
−40°C to +125°C
Unit
0 V to VDD
V
Ω typ
1
1.4
2.5
0.1
2.2
4
2.2
4
±0.2
nA typ
±1
±0.2
±5
±30
±1
±0.2
±1
±5
±30
±9
±60
0.65VDD
0.35VDD
0.005
±0.1
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS 1
tON
tOFF
Break-Before-Make Time Delay, tBBM
(ADG813 Only)
6
27
35
6
8
20
36
37
9
10
5
nA max
nA typ
ns typ
ns max
ns typ
ns max
ns typ
RL = 50 Ω, CL = 35 pF
VS = 1.5 V/ 0 V; see Figure 22
RL = 50 Ω, CL = 35 pF
VS = 1.5 V; see Figure 22
RL = 50 Ω, CL = 35 pF
VS1 = VS2 = 1 V; see Figure 23
VS = 1 V, RS = 0 Ω, CL = 1 nF;
see Figure 24
RL = 50 Ω, CL = 5 pF, f = 100 kHz;
Figure 25
RL = 50 Ω, CL = 5 pF, f = 100 kHz;
see Figure 27
RL = 32 Ω, f = 20 Hz to 20 kHz,
VS = 1.2 V p-p
RL = 50 Ω, CL = 5 pF, f = 100 kHz
RL = 50 Ω, CL = 5 pF; see Figure 26
−67
dB typ
Channel-to-Channel Crosstalk
−90
dB typ
Total Harmonic Distortion (THD + N)
0.14
%
−0.08
90
32
38
60
dB typ
MHz typ
pF typ
pF typ
pF typ
0.003
μA typ
μA max
Rev. B | Page 5 of 16
VS = 0.6 V/1.65 V, VD = 1.65 V/0.6 V;
see Figure 20
VIN = VINL or VINH
Off Isolation
Guaranteed by design, but not subject to production test.
VDD = 1.95 V
VS = 0.6 V/1.65 V, VD = 1.65 V/0.6 V;
see Figure 20
V min
V max
μA typ
μA max
pF typ
ns min
pC typ
4
VDD = 1.65 V, VS = 0 V to VDD, IS = 10 mA
VDD = 1.65 V, VS = 0.7 V, IS = 10 mA
VS = VD = 0.6 V or 1.65 V; see Figure 21
15
1.0
VDD = 1.8 V, VS = 0 V to VDD, IS = 10 mA;
see Figure 19
nA max
nA typ
nA max
Charge Injection
Insertion Loss
–3 dB Bandwidth
CS (Off )
CD (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD
1
Ω max
Ω max
Ω typ
Test Conditions/Comments
VDD = 1.95 V
Digital inputs = 0 V or 1.95 V
ADG811/ADG812/ADG813
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
VDD to GND
Analog Inputs 1
Digital Inputs1
Peak Current, S or D
3.3 V Operation
2.5 V Operation
1.8 V Operation
Continuous Current, S or D
3.3 V Operation
2.5 V Operation
1.8 V Operation
Operating Temperature Range,
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
TSSOP Package
θJA Thermal Impedance
θJC Thermal Impedance
LFCSP Package
θJA Thermal Impedance
IR Reflow, Peak Temperature <20 sec
1
Rating
−0.3 V to +4.6 V
−0.3 V to VDD + 0.3 V
GND − 0.3 V to 4.6 V or
10 mA, whichever occurs first
(Pulsed at 1 ms, 10%
duty-cycle maximum)
500 mA
460 mA
420 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating may be applied at any one
time.
Table 5. ADG811/ADG812 Truth Table
300 mA
275 mA
250 mA
−40°C to +125°C
ADG811 IN
0
1
ADG812 IN
1
0
−65°C to +150°C
150°C
Table 6. ADG813 Truth Table
150°C/W
27°C/W
Logic
0
1
70°C/W
235°C
ESD CAUTION
Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
Rev. B | Page 6 of 16
Switch 1, Switch 4
Off
On
Switch Condition
On
Off
Switch 2, Switch 3
On
Off
ADG811/ADG812/ADG813
VDD
NC 2
12
NC
GND 3
11
S3
S4 4
D4 7
10
D3
IN4 8
9
IN3
S4 6
TOP VIEW
(Not to Scale)
NC = NO CONNECT
04306-A-002
GND 5
PIN 1
INDICATOR
ADG811
TOP VIEW
(Not to Scale)
12 S2
11 VDD
10 NC
9 S3
NOTES
1. NC = NO CONNECT.
2. CONNECT EXPOSED PAD TO GND.
Figure 2. ADG811/ADG812/ADG813 Pin Configuration (16-Lead TSSOP)
Figure 3. ADG811 Pin Configuration (16-Lead LFCSP)
Table 7. ADG811/ADG812/ADG813 Pin Configuration
(16-Lead TSSOP)
Table 8. ADG811 Pin Configuration
(16-Lead LFCSP)
Pin No.
1
2
Mnemonic
IN1
D1
Pin No.
1
Mnemonic
S1
3
S1
2
3
4
NC
GND
S4
4
5
6
NC
GND
S4
5
D4
7
D4
6
7
8
IN4
IN3
D3
8
9
10
IN4
IN3
D3
9
S3
11
S3
10
11
12
NC
VDD
S2
12
13
14
NC
VDD
S2
13
D2
15
D2
14
15
16
IN2
IN1
D1
16
IN2
Definition
Logic control input.
Drain Terminal. This pin may be an
input or output.
Source Terminal. This pin may be an
input or output.
No Connect.
Ground (0 V) reference.
Source Terminal. This pin may be an
input or output.
Drain Terminal. This pin may be an
input or output.
Logic Control Input.
Logic Control Input.
Drain Terminal. This pin may be an
input or output.
Source Terminal. This pin may be an
input or output.
No Connect.
Most Positive Power Supply Potential.
Source Terminal. This pin may be an
input or output.
Drain Terminal. This pin may be an
input or output.
Logic Control Input.
04306-027
13
NC 4
14 IN2
S1 1
13 D2
S2
ADG811/
ADG812/
ADG813
D3 8
D2
14
S1 3
IN3 7
IN2
15
D4 5
16
D1 2
IN4 6
IN1 1
15 IN1
16 D1
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
EPAD
Rev. B | Page 7 of 16
Definition
Source Terminal. This pin may be an
input or output.
No Connect.
Ground (0 V) Reference.
Source Terminal. This pin may be an
input or output.
Drain Terminal. This pin may be an
input or output.
Logic Control Input.
Logic Control Input.
Drain Terminal. This pin may be an
input or output.
Source Terminal. This pin may be an
input or output.
No Connect.
Most Positive Power Supply Potential.
Source Terminal. This pin may be an
input or output.
Drain Terminal. This pin may be an
input or output.
Logic Control Input.
Logic Control Input.
Drain Terminal. This pin may be an
input or output.
Connect exposed pad to GND.
ADG811/ADG812/ADG813
TYPICAL PERFORMANCE CHARACTERISTICS
0.60
1.2
VDD = 3.3V
TA = 25°C
0.55
VDD = 3V
1.0
VDD = 2.7V
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
0.50
0.45
0.40
VDD = 3.3V
VDD = 3.6V
0.35
0.8
+125°C
+85°C
0.6
0.4
+25°C
0.30
–40°C
0.2
0.25
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VD, VS (V)
0
Figure 4. On Resistance vs. VD (VS), VDD = 2.7 V to 3.6 V
0
1.0
1.5
2.0
2.5
3.0
VD, VS (V)
Figure 7. On Resistance vs. VD (VS) for Different Temperatures, VDD = 3.3 V
0.8
1.2
TA = 25°C
VDD = 2.5V
0.7
1.0
VDD = 2.3V
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
0.5
04306-A-006
0
04306-A-003
0.20
0.6
0.5
VDD = 2.5V
VDD = 2.7V
0.4
+125°C
0.8
+85°C
0.6
+25°C
0.4
–40°C
0.3
0
0.5
1.0
1.5
2.0
0
04306-A-004
0.2
2.5
VD, VS (V)
Figure 5. On Resistance vs. VD (VS), VDD = 2.5 V ± 0.2 V
0
1.0
1.5
2.0
2.5
VD, VS (V)
Figure 8. On Resistance vs. VD (VS) for Different Temperatures, VDD = 2.5 V
1.8
1.4
–40°C
VDD = 1.8V
TA = 25°C
1.6
1.2
VDD = 1.65V
+25°C
+125°C
ON RESISTANCE (Ω)
1.4
1.2
VDD = 1.8V
1.0
0.8
0.6
1.0
0.8
0.6
+85°C
0.4
VDD = 1.95V
0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
VD, VS (V)
Figure 6. On Resistance vs. VD (VS), VDD = 1.8 V ± 0.15 V
2.0
0
0
0.2
0.4
0.6
0.8
1.0
VD, VS (V)
1.2
1.4
1.6
1.8
04306-A-008
0.2
0.4
04306-A-005
ON RESISTANCE (Ω)
0.5
04306-A-007
0.2
Figure 9. On Resistance vs. VD (VS) for Different Temperatures, VDD = 1.8 V
Rev. B | Page 8 of 16
ADG811/ADG812/ADG813
10
120
VDD = 3.3V
0
TA = 25°C
100
IS (OFF)
–10
–20
80
QINJ (pC)
CURRENT (nA)
ID (OFF)
–30
ID, IS (ON)
–40
–50
VCC = 3.6V
60
40
VCC = 2.5V
–60
20
–70
20
40
60
80
100
120
140
TEMPERATURE (°C)
04306-A-009
0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VS (V)
Figure 10. Leakage Current vs. Temperature, VDD = 3.3 V
04306-A-012
VCC = 1.8V
–80
Figure 13. Charge Injection (QINJ) vs. Source Voltage (VS)
35
10
VDD = 2.5V
30
0
ID (OFF)
25
–10
IS (OFF)
TIME (ns)
CURRENT (nA)
VCC = 1.8V
tON
–20
ID, IS (ON)
–30
VCC = 2.5V
20
VCC = 3V
15
10
–40
VDD = 2.5V
VDD = 1.8V
tOFF
–50
5
–60
0
–40
20
40
60
80
100
120
140
TEMPERATURE (°C)
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 11. Leakage Current vs. Temperature, VDD = 2.5 V
04306-A-013
0
04306-A-010
VCC = 3V
Figure 14. tON/tOFF Times vs. Temperature
0
1
VDD = 1.8V
ID (OFF)
0
–10
–1
ATTENUATION (dB)
IS (OFF)
–30
ID, IS (ON)
–40
–3
TA = 25°C
VCC = 3.3V/2.5V/1.8V
–4
–5
–6
–7
–8
–50
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
–10
0.01
0.1
1
10
100
FREQUENCY (MHz)
Figure 15. On Response vs. Frequency
Figure 12. Leakage Current vs. Temperature, VDD = 1.8 V
Rev. B | Page 9 of 16
1000
04306-A-014
–9
–60
04306-A-011
CURRENT (nA)
–2
–20
ADG811/ADG812/ADG813
0.08
0
VDD = 2.5V
TA = 25°C
32Ω LOAD
1.5V p-p
–10
TA = 25°C
0.06
VCC = 3.3V/2.5V/1.8V
–30
THD+N (%)
ATTENUATION (dB)
–20
–40
–50
0.05
–60
0.04
–70
0.1
1
10
100
1000
FREQUENCY (MHz)
0.02
04306-A-015
–90
0.01
Figure 16. Crosstalk vs. Frequency
20
–30
–40
–50
–60
–70
–80
–90
1
10
100
FREQUENCY (MHz)
1000
04306-A-016
ATTENUATION (dB)
TA = 25°C
VCC = 3.3V/2.5V/1.8V
0.1
200
500
1k
2k
5k
10k
20k
Figure 18. Total Harmonic Distortion + Noise (THD + N) vs. Frequency
0
–100
0.01
100
FREQUENCY (Hz)
–10
–20
50
Figure 17. Off Isolation vs. Frequency
Rev. B | Page 10 of 16
04306-A-017
–80
ADG811/ADG812/ADG813
TEST CIRCUITS
IDS
V1
RON = V1/IDS
S
D
ID (OFF)
A
VS
VD
Figure 19. On Resistance
ID (ON)
S
NC
D
A
VD
Figure 21. On Leakage
Figure 20. Off Leakage
VDD
0.1μF
ADG811
VIN
VDD
S
VOUT
D
RL
VS
IN
50%
50%
50%
VIN
ADG812
CL
35pF
50Ω
50%
90%
90%
04306-A-021
VOUT
GND
tON
tOFF
Figure 22. Switching Times
VDD
0.1μF
VDD
S2
VIN
VOUT2
D2
RL2
50Ω
IN1, IN2
50%
VOUT1
RL1
50Ω
VIN
CL1
35pF
50%
0V
VOUT
80%
CL2
35pF
GND
80%
tBBM
tBBM
Figure 23. Break-Before-Make Time Delay, tBBM (ADG813 Only)
VDD
SW ON
VDD
RS
VS
S
SW OFF
VIN
D
VOUT
CL
1nF
IN
VOUT
ΔVOUT
QINJ = CL × ΔVOUT
GND
Figure 24. Charge Injection
Rev. B | Page 11 of 16
04306-A-022
VS2
D1
04306-A-023
VS1
S1
04306-A-020
A
04306-A-018
VS
D
04306-A-019
IS (OFF)
S
ADG811/ADG812/ADG813
VDD
0.1μF
NETWORK
ANALYZER
VDD
50Ω
S
50Ω
VS
D
RL
50Ω
OFF ISOLATION = 20 LOG
04306-A-024
GND
VDD
VOUT
VS
Figure 25. Off Isolation
VDD
0.1μF
NETWORK
ANALYZER
VDD
50Ω
S
VS
D
GND
INSERTION LOSS = 20 LOG
VDD
04306-A-025
RL
50Ω
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Figure 26. Bandwidth
VDD
0.1μF
NETWORK
ANALYZER
VOUT
VDD
S1
RL
50Ω
S2
D
50Ω
RL
50Ω
VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
VOUT
VS
Figure 27. Channel-to-Channel Crosstalk
Rev. B | Page 12 of 16
04306-A-026
GND
ADG811/ADG812/ADG813
TERMINOLOGY
IDD
Positive supply current.
CD, CS (On)
On switch capacitance. Measured with reference to ground.
VD, VS
Analog voltage on Terminal D, Terminal S.
CIN
Digital input capacitance.
RON
Ohmic resistance between D and S.
tON
Delay time between the 50% and the 90% points of the digital
input and switch on condition.
RFLAT (ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured over the specified
analog signal range.
tOFF
Delay time between the 50% and the 90% points of the digital
input and switch off condition.
ΔRON
On resistance match between any two channels, that is,
RON maximum − RON minimum.
tBBM
On or off time measured between the 80% points of both
switches, when switching from one to another.
IS (Off)
Source leakage current with the switch off.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during on-to-off switching.
ID (Off)
Drain leakage current with the switch off.
ID, IS (On)
Channel leakage current with the switch on.
VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.
IINL (IINH)
Input current of the digital input.
CS (Off)
Off switch source capacitance. Measured with reference to
ground.
CD (Off)
Off switch drain capacitance. Measured with reference to
ground.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another because of parasitic capacitance.
−3 dB Bandwidth
The frequency at which the output is attenuated by 3 dB.
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
THD + N
The ratio of the harmonic amplitudes plus noise of a signal to
the fundamental.
Rev. B | Page 13 of 16
ADG811/ADG812/ADG813
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
0.75
0.60
0.45
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 28. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
3.00
BSC SQ
0.60 MAX
13
16
12 (BOTTOM VIEW) 1
0.45
TOP
VIEW
2.75
BSC SQ
0.80 MAX
0.65 TYP
1.00
0.85
0.80
SEATING
PLANE
9
8
5
4
0.25 MIN
1.50 REF
0.05 MAX
0.02 NOM
0.30
0.23
0.18
*1.45
1.30 SQ
1.15
EXPOSED
PAD
0.50
BSC
12° MAX
PIN 1
INDICATOR
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.20 REF
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 29. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-2)
Dimensions shown in millimeters
Rev. B | Page 14 of 16
072208-A
PIN 1
INDICATOR
0.50
0.40
0.30
ADG811/ADG812/ADG813
ORDERING GUIDE
Model
ADG811YRU
ADG811YRU-REEL
ADG811YRU-REEL7
ADG811YRUZ 1
ADG811YCPZ-REEL1
ADG811YCPZ-REEL71
ADG812YRU
ADG812YRU-REEL
ADG812YRU-REEL7
ADG812YRUZ1
ADG812YRUZ-REEL71
ADG813YRU
ADG813YRU-REEL
ADG813YRU-REEL7
ADG813YRUZ1
1
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
16-Lead Thin Shrink Small Outline [TSSOP]
16-Lead Thin Shrink Small Outline [TSSOP]
16-Lead Thin Shrink Small Outline [TSSOP]
16-Lead Thin Shrink Small Outline [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
16-Lead Thin Shrink Small Outline [TSSOP]
16-Lead Thin Shrink Small Outline [TSSOP]
16-Lead Thin Shrink Small Outline [TSSOP]
16-Lead Thin Shrink Small Outline [TSSOP]
16-Lead Thin Shrink Small Outline [TSSOP]
16-Lead Thin Shrink Small Outline [TSSOP]
16-Lead Thin Shrink Small Outline [TSSOP]
16-Lead Thin Shrink Small Outline [TSSOP]
16-Lead Thin Shrink Small Outline [TSSOP]
Z = RoHS Compliant Part.
Rev. B | Page 15 of 16
Package Option
RU-16
RU-16
RU-16
RU-16
CP-16-2
CP-16-2
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
ADG811/ADG812/ADG813
NOTES
©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04306-0-11/09(B)
Rev. B | Page 16 of 16