1 pC Charge Injection, 100 pA Leakage,
CMOS, ±5 V/+5 V/+3 V, Quad SPST Switches
ADG611/ADG612/ADG613
1 pC charge injection
±2.7 V to ±5.5 V dual-supply operation
+2.7 V to +5.5 V single-supply operation
Automotive temperature range: −40°C to +125°C
100 pA maximum at 25°C leakage currents
85 Ω on resistance
Rail-to-rail switching operation
Fast switching times
16-lead TSSOP and SOIC packages
Typical power consumption: <0.1 μW
TTL-/CMOS-compatible inputs
APPLICATIONS
FUNCTIONAL BLOCK DIAGRAM
ADG611
ADG612
S1
IN1
ADG613
IN1
IN1
D1
D1
S2
S2
IN2
IN2
D2
S3
S3
IN3
S2
D2
S3
IN3
D3
D3
S4
S4
IN4
IN4
D1
IN2
D2
IN3
S1
S1
D3
S4
IN4
D4
D4
D4
NOTES
1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.
02753-001
FEATURES
Figure 1.
Automatic test equipment
Data acquisition systems
Battery-powered systems
Communications systems
Sample-and-hold systems
Audio signal routing
Relay replacement
Avionics
GENERAL DESCRIPTION
The ADG611/ADG612/ADG613 are monolithic CMOS devices
containing four independently selectable switches. These switches
offer ultralow charge injection of 1 pC over the full input signal
range and typical leakage currents of 10 pA at 25°C.
The devices are fully specified for ±5 V, +5 V, and +3 V supplies.
Each contains four independent single-pole, single-throw (SPST)
switches. The ADG611 and ADG612 differ only in that the digital
control logic is inverted. The ADG611 switches are turned on
with a logic low on the appropriate control input, whereas a
logic high is required to turn on the switches of the ADG612.
The ADG613 contains two switches with digital control logic
similar to that of the ADG611 and two switches in which the
logic is inverted.
Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. The
ADG613 exhibits break-before-make switching action. The
ADG611/ADG612/ADG613 are available in a small, 16-lead
TSSOP package, and the ADG611 is also available in a 16-lead
SOIC package.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
Ultralow charge injection (1 pC typically).
Dual ±2.7 V to ±5.5 V or single +2.7 V to +5.5 V operation.
Automotive temperature range: −40°C to +125°C.
Small, 16-lead TSSOP and SOIC packages.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved.
ADG611/ADG612/ADG613
TABLE OF CONTENTS
Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................6 Applications ....................................................................................... 1 ESD Caution...................................................................................6 Functional Block Diagram .............................................................. 1 Pin Configuration and Function Descriptions..............................7 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................8 Product Highlights ........................................................................... 1 Terminology .................................................................................... 10 Revision History ............................................................................... 2 Test Circuits ..................................................................................... 11 Specifications..................................................................................... 3 Applications Information .............................................................. 13 Dual-Supply Operation ............................................................... 3 Outline Dimensions ....................................................................... 14 Single-Supply Operation ............................................................. 4 Ordering Guide .......................................................................... 14 REVISION HISTORY
11/09—Rev. 0 to Rev. A
Changes to Analog Signal Range Parameter
and to On Resistance, RON Parameter, Table 1 .......................... 3
Change to Digital Input Capacitance, CIN Parameter, Table 2 .... 4
Changes to Table 4 and to Absolute Maximum Ratings Section...... 6
Added Table 5; Renumbered Sequentially .................................... 7
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 14
1/02—Revision 0: Initial Version
Rev. A | Page 2 of 16
ADG611/ADG612/ADG613
SPECIFICATIONS
DUAL-SUPPLY OPERATION
VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match
Between Channels, ΔRON
On-Resistance Flatness, RFLAT(ON)
LEAKAGE CURRENTS
Source Off Leakage, IS(OFF)
Drain Off Leakage, ID(OFF)
Channel On Leakage, ID(ON), IS(ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
+25°C
85
115
2
4
25
40
±0.01
±0.1
±0.01
±0.1
±0.01
±0.1
−40°C to +85°C
−40°C to +125°C1
Unit
Test Conditions/Comments
VSS to VDD
V
Ω typ
Ω max
Ω typ
VS = ±3 V, IS = −1 mA; see Figure 14
VS = ±3 V, IS = −1 mA; see Figure 14
VS = ±3 V, IS = −1 mA
140
160
5.5
6.5
55
60
±0.25
±2
±0.25
±2
± 0.25
±6
2.4
0.8
0.005
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 2
tON
tOFF
Break-Before-Make Time Delay, tBBM
2
45
65
25
40
15
75
90
45
50
10
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS(OFF)
CD(OFF)
CD(ON), CS(ON)
POWER REQUIREMENTS
IDD
−0.5
−65
−90
680
5
5
5
0.001
1.0
ISS
0.001
1.0
1
2
The temperature range for the Y version is −40°C to +125°C.
Guaranteed by design; not subject to production test.
Rev. A | Page 3 of 16
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
μA typ
μA max
μA typ
μA max
VS = ±3 V, IS = −1 mA
VS = ±3 V, IS = −1 mA
VS = ±3 V, IS = −1 mA
VDD = +5.5 V, VSS = −5.5 V
VD = ±4.5 V, VS = +4.5 V; see Figure 15
VD = ±4.5 V, VS = +4.5 V; see Figure 15
VD = ±4.5 V, VS = + 4.5 V; see Figure 15
VD = ±4.5 V, VS = + 4.5 V; see Figure 15
VD = VS = ±4.5 V; see Figure 16
VD = VS = ±4.5 V; see Figure 16
VIN = VINL or VINH
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17
RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17
RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17
RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.0 V; see Figure 18
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.0 V; see Figure 18
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19
RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 20
RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 21
RL = 50 Ω, CL = 5 pF; see Figure 22
f = 1 MHz
f = 1 MHz
f = 1 MHz
VDD = +5.5 V, VSS = −5.5 V
Digital inputs = 0 V or 5.5 V
Digital inputs = 0 V or 5.5 V
Digital inputs = 0 V or 5.5 V
Digital inputs = 0 V or 5.5 V
ADG611/ADG612/ADG613
SINGLE-SUPPLY OPERATION
VDD = 5 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match
Between Channels, ΔRON
LEAKAGE CURRENTS
Source Off Leakage, IS(OFF)
Drain Off Leakage, ID(OFF)
Channel On Leakage, ID(ON), IS(ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
+25°C
−40°C to +85°C
−40°C to +125°C1
Unit
Test Conditions/Comments
0 to VDD
V
Ω typ
Ω max
Ω typ
VS = 3.5 V, IS = −1 mA; see Figure 14
VS = 3.5 V, IS = −1 mA; see Figure 14
VS = 3.5 V, IS = −1 mA
210
290
3
350
380
10
12
13
±0.25
±2
±0.25
±0.25
±0.01
±0.1
±0.01
±0.1
±0.01
±0.1
±2
nA typ
nA max
nA typ
nA max
VS = 3.5 V, IS = −1 mA
VDD = 5.5 V
VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 15
VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 15
VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 15
VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 15
±6
nA typ
nA max
VS = VD = 1 V or 4.5 V; see Figure 16
VS = VD = 1 V or 4.5 V; see Figure 16
2.4
0.8
0.005
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 2
tON
tOFF
Break-Before-Make Time Delay, tBBM
2
70
100
25
40
25
130
150
45
50
10
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS(OFF)
CD(OFF)
CD(ON), CS(ON)
POWER REQUIREMENTS
IDD
1
−62
−90
680
5
5
5
0.001
1.0
1
2
The temperature range for the Y version is −40°C to +125°C.
Guaranteed by design; not subject to production test.
Rev. A | Page 4 of 16
Ω max
V min
V max
μA typ
μA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
μA typ
μA max
VIN = VINL or VINH
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17
RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17
RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17
RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.0 V; see Figure 18
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.0 V; see Figure 18
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19
RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 20
RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 21
RL = 50 Ω, CL = 5 pF; see Figure 22
f = 1 MHz
f = 1 MHz
f = 1 MHz
VDD = 5.5 V
Digital inputs = 0 V or 5.5 V
Digital inputs = 0 V or 5.5 V
ADG611/ADG612/ADG613
VDD = 3 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
LEAKAGE CURRENTS
Source Off Leakage, IS(OFF)
Drain Off Leakage, ID(OFF)
Channel On Leakage, ID(ON), IS(ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
+25°C
−40°C to +85°C
−40°C to +125°C1
Unit
380
420
0 to VDD
460
V
Ω typ
±0.25
±2
±0.25
±2
±0.25
±6
±0.01
±0.1
±0.01
±0.1
±0.01
±0.1
2.0
0.8
0.005
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 2
tON
tOFF
Break-Before-Make Time Delay, tBBM
2
130
185
40
55
50
230
260
60
65
10
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS(OFF)
CD(OFF)
CD(ON), CS(ON)
POWER REQUIREMENTS
IDD
1.5
−62
−90
680
5
5
5
0.001
1.0
1
2
The temperature range for the Y version is −40°C to +125°C.
Guaranteed by design; not subject to production test.
Rev. A | Page 5 of 16
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
μA typ
μA max
Test Conditions/Comments
VS = 1.5 V, IS = −1 mA; see Figure 14
VDD = 3.3 V
VS = 1 V/3 V, VD = 3 V/1 V; see Figure 15
VS = 1 V/3 V, VD = 3 V/1 V; see Figure 15
VS = 1 V/3 V, VD = 3 V/1 V; see Figure 15
VS = 1 V/3 V, VD = 3 V/1 V; see Figure 15
VS = VD = 1 V or 3 V; see Figure 16
VS = VD = 1 V or 3 V; see Figure 16
VIN = VINL or VINH
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17
RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17
RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17
RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 2 V; see Figure 18
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 2 V; see Figure 18
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19
RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 20
RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 21
RL = 50 Ω, CL = 5 pF; see Figure 22
f = 1 MHz
f = 1 MHz
f = 1 MHz
VDD = 3.3 V
Digital inputs = 0 V or 3.3 V
Digital inputs = 0 V or 3.3 V
ADG611/ADG612/ADG613
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted
Table 4.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
Peak Current, S or D
Continuous Current, S or D
3 V operation 85°C to 125°C
Operating Temperature Range
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
16-Lead TSSOP
16-Lead SOIC, 4-Layer Board
Lead Soldering
Lead Temperature, Soldering
(10 sec)
IR Reflow, Peak Temperature
(<20 sec)
(Pb-Free) Soldering
Reflow, Peak Temperature
Time at Peak Temperature
Rating
13 V
−0.3 V to +6.5 V
+0.3 V to −6.5 V
VSS − 0.3 V to VDD + 0.3 V
GND − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
20 mA (pulsed at 1 ms, 10%
duty cycle maximum)
10 mA
7.5 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
−40°C to +125°C
−65°C to +150°C
150°C
150.4°C/W
80.6°C/W
300°C
220°C
260(+0/−5)°C
20 sec to 40 sec
1
Overvoltages at IN, S, or D are clamped by internal diodes. The current
should be limited to the maximum ratings given.
Rev. A | Page 6 of 16
ADG611/ADG612/ADG613
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IN1 1
16
IN2
D1 2
15
D2
14
S2
13
VDD
S1 3
VSS 4
ADG611/
ADG612/
ADG613
TOP VIEW 12 NC
(Not to Scale)
11 S3
S4 6
D4 7
10
D3
IN4 8
9
IN3
NC = NO CONNECT
02753-002
GND 5
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
IN1
D1
S1
VSS
GND
S4
D4
IN4
IN3
D3
S3
NC
VDD
S2
D2
IN2
Description
Switch 1 Digital Control Input.
Drain Terminal of Switch 1. Can be an input or output.
Source Terminal of Switch 1. Can be an input or output.
Most Negative Power Supply Terminal. Tie this pin to GND when using the device with single-supply voltages.
Ground (0 V) Reference.
Source Terminal of Switch 4. Can be an input or output.
Drain Terminal of Switch 4. Can be an input or output.
Switch 4 Digital Control Input.
Switch 3 Digital Control Input.
Drain Terminal of Switch 3. Can be an input or output.
Source Terminal of Switch 3. Can be an input or output.
Not Internally Connected.
Most Positive Power Supply Terminal.
Source Terminal of Switch 2. Can be an input or output.
Drain Terminal of Switch 2. Can be an input or output.
Switch 2 Digital Control Input.
Table 6. ADG611/ADG612 Truth Table
ADG611 Input
0
1
ADG612 Input
1
0
Switch Condition
On
Off
Switch 1, Switch 4
Off
On
Switch 2, Switch 3
On
Off
Table 7. ADG613 Truth Table
Logic
0
1
Rev. A | Page 7 of 16
ADG611/ADG612/ADG613
TYPICAL PERFORMANCE CHARACTERISTICS
250
600
TA = 25°C
500
200
±3.3V
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
VDD = 5V
VSS = 0V
150
±2.7V
±4.5V
±3.0V
100
400
300
+125°C
+85°C
200
±5.5V
50
100
–40°C
+25°C
–4
–3
–2
–1
0
1
2
3
4
5
VD, VS (V)
0
02753-003
0
–5
0
VDD = 2.7V
2.5
3.0
3.5
4.0
4.5
5.0
IS(OFF)
LEAKAGE CURRENT (nA)
VDD = 3.0V
VDD = 3.3V
300
VDD = 4.5V
200
100
VDD = 5.0V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–1
ID(OFF)
–2
IS(ON), ID(ON)
–3
–4
–5
0
0
0
4.5
5.0
VD, VS (V)
–6
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 4. On Resistance vs. VD (VS), Single Supply
02753-007
400
250
2.0
VDD = +5V
VSS = –5V
1
02753-004
ON RESISTANCE (Ω)
500
1.5
Figure 6. On Resistance vs. VD (VS) for Various Temperatures, Single Supply
2
TA = 25°C
VSS = 0V
1.0
VD, VS (V)
Figure 3. On Resistance vs. VD (VS), Dual Supplies
600
0.5
02753-006
±5.0V
Figure 7. Leakage Current vs. Temperature, Dual Supplies
2
VDD = +5V
VSS = –5V
VDD = 5V
VSS = 0V
1
IS(OFF)
LEAKAGE CURRENT (nA)
150
+125°C
+85°C
100
+25°C
50
–3
–2
–1
0
VD, VS (V)
1
2
3
4
5
ID(OFF)
–2
–3
IS(ON), ID(ON)
–4
–6
02753-005
–4
–1
–5
–40°C
0
–5
0
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 5. On Resistance vs. VD (VS) for Various Temperatures, Dual Supplies
Rev. A | Page 8 of 16
Figure 8. Leakage Current vs. Temperature, Single Supply
02753-008
ON RESISTANCE (Ω)
200
ADG611/ADG612/ADG613
0
VDD = +3V
VSS = 0V
TA = 25°C
1.5
VDD = –5V
VSS = +5V
–10 T = 25°C
A
–20
VDD = +5V
VSS = 0V
0.5
0
–0.5
VDD = +5V
VSS = –5V
–1.0
–30
–40
–50
–60
–70
–1.5
–80
–4
–3
–2
–1
0
1
2
3
4
5
VS (V)
–90
0.3
02753-009
–2.0
–5
1k
0
VDD = +5V
–10 VSS = –5V
TA = 25°C
100
tON, VDD = +5V
–20
VSS = 0V
60
tON, VDD = +5V
40
tOFF, VDD = +5V
CROSSTALK (dB)
80
TIME (ns)
100
Figure 12. Off Isolation vs. Frequency
120
VSS = –5V
VSS = 0V
–30
–40
–50
–60
–70
–80
20
tOFF, VDD = +5V
–90
VSS = –5V
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
–100
0.3
02753-010
0
–40
VDD = –5V
VSS = +5V
–4
VDD = +5V
VSS = 0V
–6
–8
–10
–12
–14
1
10
100
FREQUENCY (MHz)
1k
02753-011
–16
–18
0.3
10
100
Figure 13. Crosstalk vs. Frequency
TA = 25°C
–2
1
FREQUENCY (MHz)
Figure 10. tON/tOFF Times vs. Temperature
ATTENUATION (dB)
10
FREQUENCY (MHz)
Figure 9. Charge Injection vs. Source Voltage
0
1
02753-012
QINJ (pC)
OFF ISOLATION (dB)
1.0
Figure 11. On Response vs. Frequency
Rev. A | Page 9 of 16
1k
02753-013
2.0
ADG611/ADG612/ADG613
TERMINOLOGY
VDD
Most positive power supply potential.
VINH
Minimum input voltage for Logic 1.
VSS
Most negative power supply potential.
IINL, IINH
Input current of the digital input.
IDD
Positive supply current.
CS(OFF)
Off switch source capacitance. Measured with reference
to ground.
ISS
Negative supply current.
CD(OFF)
Off switch drain capacitance. Measured with reference
to ground.
GND
Ground (0 V) reference.
CD(ON), CS(ON)
On switch capacitance. Measured with reference to ground.
S
Source terminal. Can be an input or output.
CIN
Digital input capacitance.
D
Drain terminal. Can be an input or output.
tON
Delay between applying the digital control input and the output
switching on (see Figure 17).
IN
Logic control input.
VD (VS)
Analog voltage on Terminal D and Terminal S.
tOFF
Delay between applying the digital control input and the output
switching off (see Figure 17).
RON
Ohmic resistance between Terminal D and Terminal S.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
ΔRON
On-resistance match between any two channels, that is,
RONMAX − RONMIN.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured over the specified
analog signal range.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
IS(OFF)
Source leakage current with the switch off.
On Response
Frequency response of the on switch.
ID(OFF)
Drain leakage current with the switch off.
Insertion Loss
Loss due to the on resistance of the switch.
ID(ON), IS(ON)
Channel leakage current with the switch on.
VINL
Maximum input voltage for Logic 0.
Rev. A | Page 10 of 16
ADG611/ADG612/ADG613
TEST CIRCUITS
IDS
V1
ID(OFF)
A
VD
VS
Figure 14. On Resistance
S
NC
A
VD
Figure 16. On Leakage
VSS
0.1µF
0.1µF
VDD
VSS
S
VS
ID(ON)
NC = NO CONNECT
Figure 15. Off Leakage
VDD
D
VOUT
ADG611
50%
50%
VIN
ADG612
50%
50%
VOUT
D
RL
300Ω
IN
CL
35pF
90%
VIN
90%
GND
tON
tOFF
02753-017
RON = V1/IDS
D
Figure 17. Switching Times
VSS
0.1µF
VDD
VSS
VS1
S1
D1
VS2
S2
D2
IN1,
IN2
RL2
300Ω
CL2
35pF
RL1
300Ω
VOUT2
CL1
35pF
VOUT1
VOUT1
VOUT2
ADG613
50%
0V
50%
90%
90%
0V
90%
90%
0V
GND
tBBM
tBBM
Figure 18. Break-Before-Make Time Delay
RS
VDD
VSS
VDD
VSS
S
D
VIN
ADG611
VIN
ADG612
VOUT
CL
1nF
VS
IN
GND
VOUT
Figure 19. Charge Injection
Rev. A | Page 11 of 16
ON
QINJ = CL × ΔVOUT
OFF
ΔVOUT
02753-019
VIN
VIN
02753-018
VDD
0.1µF
02753-016
S
A
02753-014
VS
IS(OFF)
D
02753-015
S
ADG611/ADG612/ADG613
VDD
VSS
0.1µF
VDD
NETWORK
ANALYZER
VSS
S
NETWORK
ANALYZER
VSS
S
50Ω
IN
VS
VS
D
D
RL
50Ω
GND
VOUT
VIN
OFF ISOLATION = 20 log
VOUT
VS
INSERTION LOSS = 20 log
Figure 20. Off Isolation
VDD
0.1µF
VDD
VSS
50Ω
D
S
VIN1
VS
VIN2
GND
RL
50Ω
CHANNEL-TO-CHANNEL CROSSTALK = 20 log |VS/VOUT|
VOUT
02753-021
D
S
Figure 21. Channel-to-Channel Crosstalk
Rev. A | Page 12 of 16
VOUT
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Figure 22. Bandwidth
VSS
0.1µF
RL
50Ω
GND
02753-020
VIN
NC
0.1µF
VDD
50Ω
50Ω
IN
VSS
0.1µF
02753-022
VDD
0.1µF
ADG611/ADG612/ADG613
APPLICATIONS INFORMATION
Figure 23 illustrates a photodetector circuit with programmable
gain. With the resistor values shown in this figure, gains in the
range of 2 to 16 can be achieved by using different combinations
of switches.
C1
R1
33kΩ
5V
D1
VOUT
2.5V
R2
510kΩ
5V
S1
R4
D1 240kΩ
R5
240kΩ
S2
R6
D2 120kΩ
R7
120kΩ
(LSB) IN1
IN2
S3
D3
R8
120kΩ
S4
D4
R9
120kΩ
R3
510kΩ
IN3
GND
2.5V
R9
120kΩ
GAIN RANGE: 2 TO 16
Figure 23. Photodetector Circuit with Programmable Gain
Rev. A | Page 13 of 16
02753-023
(MSB) IN4
ADG611/ADG612/ADG613
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.30
0.19
0.65
BSC
0.20
0.09
SEATING
PLANE
COPLANARITY
0.10
0.75
0.60
0.45
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 24. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
10.00 (0.3937)
9.80 (0.3858)
4.00 (0.1575)
3.80 (0.1496)
9
16
1
8
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
6.20 (0.2441)
5.80 (0.2283)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
0.50 (0.0197)
0.25 (0.0098)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
060606-A
COMPLIANT TO JEDEC STANDARDS MS-012-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 25. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
ADG611YRUZ 1
ADG611YRUZ-REEL1
ADG611YRUZ-REEL71
ADG611YRZ1
ADG612YRUZ1
ADG612YRUZ-REEL1
ADG612YRUZ-REEL71
ADG612WRUZ-REEL1
ADG613YRUZ1
ADG613YRUZ-REEL1
ADG613YRUZ-REEL71
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
Z = RoHS Compliant Part.
Rev. A | Page 14 of 16
Package Option
RU-16
RU-16
RU-16
R-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
ADG611/ADG612/ADG613
NOTES
Rev. A | Page 15 of 16
ADG611/ADG612/ADG613
NOTES
©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02753-0-11/09(A)
Rev. A | Page 16 of 16