SHARC+ Dual Core
DSP with ARM Cortex-A5
a
Silicon Anomaly List
ADSP-SC582/583/584/587/589/ADSP-21583/584/587
ABOUT ADSP-SC582/583/584/587/589/ADSP-21583/584/587 SILICON ANOMALIES
These anomalies represent the currently known differences between revisions of the SHARC®ADSP-SC582/583/584/587/589/ADSP21583/584/587 product(s) and the functionality specified in the ADSP-SC582/583/584/587/589/ADSP-21583/584/587 data sheet(s) and the
Hardware Reference book(s).
SILICON REVISIONS
A silicon revision number with the form "-x.x" is branded on all parts. The REVID bits <31:28> of the TAPC0_IDCODE register can be
used to differentiate the revisions as shown below.
Silicon REVISION
TAPC0_IDCODE.REVID
0.1
0x01
ANOMALY LIST REVISION HISTORY
The following revision history lists the anomaly list revisions and major changes for each anomaly list revision.
Date
Anomaly List Revision
Data Sheet Revision
Additions and Changes
06/26/2015
A
PrC
Initial Version
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NR004444A
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ADSP-SC582/583/584/587/589/ADSP-21583/584/587
Silicon Anomaly List
SUMMARY OF SILICON ANOMALIES
The following table provides a summary of ADSP-SC582/583/584/587/589/ADSP-21583/584/587 anomalies and the applicable silicon
revision(s) for each anomaly.
No.
ID
Description
0.1
1
20000002
Data forwarding from Rn/Sn(n = 0-15) to any DAG register may fail in presence of stalls for certain sequence of
instructions
x
2
20000003
Transacations to Certain SPU and SMPU MMR Regions Cause Erroneous Errors
x
3
20000005
Loading I12 register with invalid instruction address may result in unpredictable behavior when BTB is enabled
with software optimization
x
4
20000006
DM-PM priority may not be honored for the second Type-1 instruction in case of consecutive Type-1
instructions having DM-write and PM-read from same L2 or external memory address
x
5
20000007
Flush instruction may not work as expected under some conditions
x
6
20000009
IDLE instruction in the vicinity of Cacheable data access instruction may lead to unexpected results
x
7
20000010
DMA and Data cache access conflict may lead to unexpected results
x
8
20000013
Instruction cache functioning gets affected by un-cached external data access
x
9
20000016
Load of ASTATy to use in condition has more than 1 cycle effect latency
x
10
20000017
Parity status remains stuck if immediately after instruction parity error there is change-of-flow to non-L1
location
x
11
20000018
Speculative read accesses launched on pipeline flush may lead to system hang under some conditions
x
12
20000019
Certain range in DMC VISA space is not accessible
x
13
20000020
When L1 Cache is enabled, usage of Byte modifiers in a certain sequence of instructions may not work as
expected
x
14
20000021
Fast Interrupt mode in L1 Cache is not functional
x
15
20000022
Determining the success of an Exclusive Access (load or store) instruction based on the AZ flag of ASTAT
register is not reliable
x
16
20000023
Short word SIMD data should be short word aligned in L2 and external memories
x
17
20000024
Consecutive instructions having external memory access may lead to read data corruption under some
conditions
x
18
20000028
In L1 Data cache, full Cache write back functionality has an issue
x
19
20000029
L1 Cache performance degrades under certain conditions
x
20
20000030
Usage of Type 3C instruction in a certain sequence may not work as expected
x
21
20000031
GP Timer Generates First Interrupt/Trigger One Edge Late in EXTCLK Mode
x
22
20000032
Accessing SMMRs from L2 or external memory locations may not work as expected when L1 cache is enabled
x
23
20000033
EMDMA transfer with modifier "1" may fail for certain SHARC L1 boundary locations
x
24
20000034
The save state operation may not work as expected in the IIR Accelerator
x
25
20000035
Spurious stalls are generated during certain instruction sequences involving F0 register
x
26
20000036
Data Cache line fill may not work as expected if it is preceded by a misaligned through data cache access
x
27
20000037
DMC read state machine may not be in correct state after DMC initialization
x
28
20000038
Error Address in the Boot Config Struct is Incorrect
x
29
20000039
OTP API does not report OTP errors
x
30
20000040
DMC is not reset after the PLL frequency changes in boot ROM
x
31
20000041
INDIRECT Mode is not functional in boot ROM
x
32
20000042
CGU0_CLKOUTSEL is not set from the values in OTP
x
33
20000043
Key unwrapping on the SHARC fails when using with ROM API
x
34
20000044
Slave boot modes IGNORE block processing not functional with Page mode enabled in a non-secure boot
situation
x
35
20000045
SHARC+ core executing IDLE instruction fails to acknowledge with SIDIS, when a reset sequence is initiated by
another core
x
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Silicon Anomaly List
ADSP-SC582/583/584/587/589/ADSP-21583/584/587
No.
ID
Description
0.1
36
20000046
TMU FAULT/ALERT Status does not get cleared by writing 1 to the corresponding status bits
x
37
20000047
SPU Range Protection for MMR space gets violated if any write access is done to Reserved memory spaces
aliased to these MMR space
x
38
20000048
CGU0_STAT.LWERR Bit Gets Erroneously Set Under Certain Conditions
x
39
20000049
SPI Transmit Collision Error may occasionally be missed
x
40
20000050
SPORT May Drive Data Pins During Inactive Channels in Multichannel Mode
x
41
20000051
Secure SPI Master Boot Only Supported From Memory-Mapped SPI Devices on SPI2
x
42
20000052
SPI Master Boot in Peripheral DMA mode fails for block size greater than 64KB
x
43
20000053
Reading Certain PKTE Registers May Return Incorrect Data During Packet Processing
x
44
20000054
SPDIF_RX_TDMCLK_O signal cannot be routed using SRU
x
45
20000055
Incorrect parameter passed to callback routines
x
46
20000061
SPI data pins are driven high in open drain mode
x
47
20000062
The software selection of SPI Slave Enable Signal does not drive to the programmed value in the Slave Select
Register
x
48
20000063
Reads of SPU_SECCHK by Non-secure Masters Result in an Erroneous Violation Interrupt
x
49
20000064
Misaligned data cache access may affect the functioning of L1 Parity
x
50
20000065
L1 Cache Range Based Functionality has some issues
x
Key: x = anomaly exists in revision
. = Not applicable
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Silicon Anomaly List
DETAILED LIST OF SILICON ANOMALIES
The following list details all known silicon anomalies for the ADSP-SC582/583/584/587/589/ADSP-21583/584/587 including a description,
workaround, and identification of applicable silicon revisions.
1. 20000002 - Data forwarding from Rn/Sn(n = 0-15) to any DAG register may fail in presence of stalls for
certain sequence of instructions:
DESCRIPTION:
An instruction involving a DAG operation such as address generation or modify following a type5a instruction may fail under following
conditions:
1. The source register of the DAG operation is has been updated in a previous type5a instruction.
2. The source of the register transfer in type5a instruction is same as the destination of the compute operation.
3. These two instructions are separated by five or fewer instructions.
4. The pipeline is stalled due to any reason such as data/control dependence or those arising out of L1 memory bank conflict.
When the above conditions are met, the DAG operation may produce incorrect result due to value forwarding from first instruction to the
DAG operation going wrong. The type5a instruction however, produces the expected result updating the DAG register correctly.
Example:
1.
2.
3.
4.
5.
6.
7.
r2 = r2 - r13, i4 = r2; //type 5a compute destination (r2) same as DAG
//register (i4) update source
if eq jump target1; //Condition set to use dependence;stalls the pipe
nop;
nop;
nop;
nop;
i5=b2w(i4); //DAG operation using same DAG register (i4) as source;
//separated from type5a by 5 instructions
In the above case, i5 in instruction #7 gets updated with incorrect value even though i4 contains the correct value from instruction #1.
WORKAROUND:
1. Split the type5a instruction which conforms to the use case described above.
2. Avoid using the relevant DAG register in a DAG operation within 6 instructions of type5a instruction of above description
APPLIES TO REVISION(S):
0.1
2. 20000003 - Transacations to Certain SPU and SMPU MMR Regions Cause Erroneous Errors:
DESCRIPTION:
Non-secure reads or writes to the upper half of each SPU instance's MMR space will be erroneously blocked and cause a bus error when
the SPU is set as non-secure slave. The same is true for each SMPU instance. The affected MMR address range can be calculated for each
instance of the SPU and SMPU as follows:
Lower bound = Instance Address Offset + 0x800
Upper bound = Instance Address Offset + 0xFFF
WORKAROUND:
None
APPLIES TO REVISION(S):
0.1
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3. 20000005 - Loading I12 register with invalid instruction address may result in unpredictable behavior
when BTB is enabled with software optimization:
DESCRIPTION:
When BTB is enabled with Software return optimization, branch target address is predicted by reading the value of I12 register, instead
of the branch target buffer itself. Hence loading I12 register with an invalid instruction address will result in an unpredictable behavior
of the core.
WORKAROUND:
Use I12 register only for instruction addressing purpose if software return optimization is enabled in BTB.
APPLIES TO REVISION(S):
0.1
4. 20000006 - DM-PM priority may not be honored for the second Type-1 instruction in case of consecutive
Type-1 instructions having DM-write and PM-read from same L2 or external memory address:
DESCRIPTION:
In case of type-1 instructions where parallel(PM and DM) data transfers happen, processor performs DM access first. But this DM-PM priority
may be violated in the sequence which has Consecutive Type-1 instructions where:
1. DM access being write and PM access being read
2. Both Read and Write access happens from/to the same L2 or external memory address
Eg:
dm(addrA) = r0, r1 = pm(addrA);
dm(addrB) = r2, r3 = pm(addrB);
Here addrA and addrB are L2 or external memory addresses. The second type1 instruction may load r3 with old value of addrB instead
of r2.
WORKAROUND:
Avoid codes having DM-PM sequence dependency in case of DM-write and PM-read to the same L2 or external memory address.
APPLIES TO REVISION(S):
0.1
5. 20000007 - Flush instruction may not work as expected under some conditions:
DESCRIPTION:
The Flush instruction will not behave as expected, during L1 cache Range based Write back Invalidation is in process and any of the
following conditions occur:
1. The operation is interrupted.
2. The instructions following the FLUSH instruction is dependent on the cache operation.
WORKAROUND:
1. Interrupt should be disabled from range register setting to the loop end. To avoid long wait by interrupts,it is recommended to split
entire range into smaller ranges.
2. Flush instruction should be padded with 5 unrelated instructions.
3. Use only Range register pair 0 for Write back invalidation.
APPLIES TO REVISION(S):
0.1
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Silicon Anomaly List
6. 20000009 - IDLE instruction in the vicinity of Cacheable data access instruction may lead to unexpected
results:
DESCRIPTION:
When L1 Data Cache is enabled, the IDLE instruction has to be separated from cache-able data accesses for proper operation.
WORKAROUND:
5 NOPs should be placed after cache-able data access till IDLE instruction.
APPLIES TO REVISION(S):
0.1
7. 20000010 - DMA and Data cache access conflict may lead to unexpected results:
DESCRIPTION:
Data Cache(DM and PM) uses L1 Block 1 and block 2 respectively. When L1 data cache is enabled, DMA to L1 block 1 and block 2 may not
work as expected when there is a conflict between the DMA and the Data cache access.
WORKAROUND:
When L1 Cache is enabled, avoid DMA and Cache-able data access conflict by restricting the DMA, not to use L1 Memory Block 1 and
Block 2 addresses.
APPLIES TO REVISION(S):
0.1
8. 20000013 - Instruction cache functioning gets affected by un-cached external data access:
DESCRIPTION:
In a scenario where only the Instruction cache is enabled, external data access(un-cached) may affect the working of the Instruction cache.
WORKAROUND:
1. Avoid un-cached external data accesses with I-cache accesses by enabling the data cache and bringing the data to L1 Memory.
2. If only Instruction cache needs to be enabled, external data access has to be avoided.
APPLIES TO REVISION(S):
0.1
9. 20000016 - Load of ASTATy to use in condition has more than 1 cycle effect latency:
DESCRIPTION:
When SIMD is enabled, loading ASTATy register in order to use it in a condition has more than 1 cycle effect latency.
WORKAROUND:
Separate ASTATy load from use with 5 unrelated instructions if SIMD is ON.
APPLIES TO REVISION(S):
0.1
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10. 20000017 - Parity status remains stuck if immediately after instruction parity error there is change-offlow to non-L1 location:
DESCRIPTION:
When Instruction parity error occurs and there is a change-of-flow to non-L1 location(Eg. Interrupt service routine in external memory),
the parity error will not get cleared even if zero is written into GPERR_STAT register. This results in the parity error interrupt to be
generated continuously.
WORKAROUND:
A dummy or actual branch should be added to L1 Memory from the Parity ISR.
APPLIES TO REVISION(S):
0.1
11. 20000018 - Speculative read accesses launched on pipeline flush may lead to system hang under some
conditions:
DESCRIPTION:
Speculative accesses are the accesses which are launched ahead of their execute stage and hence they could be killed in case of pipe
flush or any other abort like condition false.
SHARC+ core launches all the non MMR reads speculatively based on the current values of index and modifier registers. Hence, in case of
pipeline flush after a branch, loop etc., they could end-up launching extra accesses based on the further Ix = Ix+My or on the stale
value of index registers. If they end up landing on a memory interface which is not functional (neither initialized nor blocked by SMPU)
then such accesses could hang the system.
WORKAROUND:
The following conditions should be met to avoid the issue:
1. If DMC-0 ,DMC-1 or SMC is not used , it should be blocked by the SMPU
2. Both the SHARC Cores should be out of reset
3. If the SPI Flash memory is not used , then the following piece of code should be added in the application
*pREG_SPI2_TXCTL = (BITM_SPI_TXCTL_TEN | BITM_SPI_TXCTL_TTI);
*pREG_SPI2_RXCTL = (BITM_SPI_RXCTL_REN | BITM_SPI_RXCTL_RTI);
*pREG_SPI2_CTL = (BITM_SPI_CTL_EN|BITM_SPI_CTL_MSTR| BITM_SPI_CTL_MMSE);
APPLIES TO REVISION(S):
0.1
12. 20000019 - Certain range in DMC VISA space is not accessible:
DESCRIPTION:
One-third of the address in each of DMC VISA Execution space have not been mapped. Hence the memory range given below is not
accessible.
DMC-0 :
DMC-1 :
0x0900-000 to 0x09ff-fff
0x0d00-000 to 0x0dff-fff
WORKAROUND:
None
APPLIES TO REVISION(S):
0.1
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Silicon Anomaly List
13. 20000020 - When L1 Cache is enabled, usage of Byte modifiers in a certain sequence of instructions may
not work as expected:
DESCRIPTION:
When L1-cache is enabled, Byte modifier may not work as expected in the following instruction sequence:
1. Any DM-external access. //Instruction n
2. PM access with byte-word specifier. //Instruction n+1
Eg:
dm(i0,m0) = r0; //I0 points to the external memory
pm(i8,m8) = r1 (BW);
WORKAROUND:
One unrelated instruction should be used between DM(External)access and the PM access with Byte modifier.
Eg:
dm(i0,m0) = r0; //I0 points to the external memory
NOP;
pm(i8,m8) = r1 (BW);
APPLIES TO REVISION(S):
0.1
14. 20000021 - Fast Interrupt mode in L1 Cache is not functional:
DESCRIPTION:
The Fast interrupt servicing mode in L1 Cache is not functional. Bit 24 FISREN of the Cache Configuration (CACFG) register cannot be
used in the application.
WORKAROUND:
None
APPLIES TO REVISION(S):
0.1
15. 20000022 - Determining the success of an Exclusive Access (load or store) instruction based on the AZ
flag of ASTAT register is not reliable:
DESCRIPTION:
The expected behavior is that the success of the exclusive access (store or load) will set the AZ flag in ASTATx register (in ASTATy also if
SIMD is enabled) while a failure will clear it. But this does not work as expected and hence checking the response of the Exclusive Load
and Store Access based on AZ flag is not reliable.
WORKAROUND:
Do not check for any status following an Exclusive Read access. Ensure that access is targeted to one of the following spaces:
1 L2 memory
2 DMC-0 or DMC-1 memory and the DMC initialization is done
3 SMC
After an exclusive write operation , check for the VALID bit of the SMPU_EXACSTATx register to determine the success of an Exclusive
write operation.Valid bit = 1 indicates and success and valid bit = 0 indicates a failure.
APPLIES TO REVISION(S):
0.1
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16. 20000023 - Short word SIMD data should be short word aligned in L2 and external memories:
DESCRIPTION:
When SIMD is enabled, all the short word data access from L2 and external memory locations should be short word aligned.
Eg: For Load or store of DM/PM(Ix,My)(sw), where Ix points to L2 or external memory address , Ix should be short word aligned.
WORKAROUND:
None
APPLIES TO REVISION(S):
0.1
17. 20000024 - Consecutive instructions having external memory access may lead to read data corruption
under some conditions:
DESCRIPTION:
External memory read data can be corrupted, if there are more than 2 external reads and more than 2 external writes in a window of 4
instructions. The issue is not seen if there are just 2 external reads and 2 external writes in a window of 4 instructions.
Consider the following sequence of instructions where I0,I8,I1 and I9 point to external memory address. Under some circumstances ,
the read data (R0 and R1) may get corrupted.
R0 = dm(I0, M0),
dm(I1, M0) = R0,
R0 = dm(I0, M0),
dm(I1, M0) = R0,
R1 = pm(I8,M8);
pm(I9,M8) = R1;
R1 = pm(I8,M8);
pm(I9,M8) = R1;
WORKAROUND:
Avoid having greater than 2 external reads and greater than 2 external writes in a window of four instructions.
APPLIES TO REVISION(S):
0.1
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Silicon Anomaly List
18. 20000028 - In L1 Data cache, full Cache write back functionality has an issue:
DESCRIPTION:
When full cache Write-back feature is used, last line of way1 is not written-back even though the line is dirty ,when the Write-back bit (
DMCAWB for DM Cache or PMCAWB for PM Cache) is set in the Cache Configuration register (CACFG).
WORKAROUND:
Before performing a full cache write-back, perform 12 dummy read access( 6 with DM and 6 with PM ) to the external memory address
which falls in the last line of the cache
A
A
A
A
A
A
=
=
=
=
=
=
dm(addr1)
dm(addr2)
dm(addr3)
dm(addr4)
dm(addr5)
dm(addr6)
A
A
A
A
A
A
=
=
=
=
=
=
pm(addr1)
pm(addr2)
pm(addr3)
pm(addr4)
pm(addr5)
pm(addr6)
Only 6 different addresses is enough and the dummy reads can happen to the same six addresses for both DM and PM accesses (The Tag
field of the addresses should be different in each case). Also the addresses chosen have to be outside of the Range selected for noncacheability. The following 6 addresses can be chosen for the workaround
0x2008_FFC0
0x2009_FFC0
0x200a_FFC0
0x200b_FFC0
0x2018_FFC0
0x2019_FFC0
APPLIES TO REVISION(S):
0.1
19. 20000029 - L1 Cache performance degrades under certain conditions:
DESCRIPTION:
If the range based non-cacheability feature is selected, in addition to the one specified in the range register pair,certain other addresses
which satisfies the below conditions will be non-cacheable:
1. External memory VISA addresses overlapping with the lower 24 bits of the addresses in the range register pair.
2. External memory Non-VISA addresses(multiplied by 3) overlapping with the lower 25 bits of the addresses in the range register.
Any access to the non-cacheable range when Cache is enabled will take more cycles.
WORKAROUND:
Avoid code execution from external memory addresses where ever:
1. The lower 24 bits of the addresses in the range register pair overlaps with the VISA address.
2. The lower 25 bits of the addresses in the range register pair overlaps with the Non-VISA address multiplied by 3.
APPLIES TO REVISION(S):
0.1
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20. 20000030 - Usage of Type 3C instruction in a certain sequence may not work as expected:
DESCRIPTION:
In VISA mode, Type 3C instructions should not be used for reads when there is a conditional write instruction preceding it.
Eg : if eq, dm(i0,m0) = r5;
R0 = dm(i4,m4);// Type 3C read
Sequences such as above should be avoided.
WORKAROUND:
Any one of the following workarounds can be implemented.
1. Force the Type 3C instruction to uncompressed 48 bit instruction using the assembler directives.
if eq, dm(i0,m0) = r5;
.NOCOMPRESS;
R0 = dm(i4,m4);// Type 3C read
.FORCECOMPRESS;
2. Insert a NOP; instruction between the conditional write and the Type3C instruction.
if eq, dm(i0,m0) = r5;
NOP;
R0 = dm(i4,m4);// Type 3C read
APPLIES TO REVISION(S):
0.1
21. 20000031 - GP Timer Generates First Interrupt/Trigger One Edge Late in EXTCLK Mode:
DESCRIPTION:
When TIMER is configured in External Clock mode, after the TIMER_TMRn_CNT register reaches the value programmed in the
TIMER_TMRn_PER register, the corresponding TIMER_DATA_ILAT bit should be set along with a trigger / interrupt being generated.
However, TIMER_DATA_ILAT bit will be set after the TIMER_TMRn_CNT register rolls over to 1.
Consider TIMER_TMRn_PER register to be configured to a value n. After the TIMER has started, the first interrupt/ trigger will occur after
the TIMER receives n+1 edges externally and the subsequent ones after every n edges
WORKAROUND:
For interrupts/ triggers to occur at every n edges of the external clock the TIMER_TMRn_PER register should be configured to n-1 for
the initial event and to n for subsequent ones.
Pseudo code:
TIMER_TMRn_PER = n-1;
TIMER_RUN_SET = 1;
TIMER_TMRn_PER = n;
// Configure PERIOD register with n-1
// Run the timer
// Configure PERIOD register with n
APPLIES TO REVISION(S):
0.1
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Silicon Anomaly List
22. 20000032 - Accessing SMMRs from L2 or external memory locations may not work as expected when L1
cache is enabled:
DESCRIPTION:
The SMMR accesses from L2 or external memories may not work as expected when L1 Cache is enabled.
WORKAROUND:
All the sMMR accesses has to be done from L1 Memory only when the L1 cache is enabled.
APPLIES TO REVISION(S):
0.1
23. 20000033 - EMDMA transfer with modifier "1" may fail for certain SHARC L1 boundary locations:
DESCRIPTION:
EMDMA transfer with modifier (EMDMA_MOD0/EMDMA_MOD1) equal to "1" may fail if the DMA address range (EMDMA_INDX0/1 to
EMDMA_INDX0/1+EMDMA_CNT0/1) crosses 4 K Byte boundary of the SHARC L1 memory. This anomaly is applicable for L1 memory of
both the SHARC cores. EMDMA transfers with modifier other than "1" are not affected by this anomaly.
For example, suppose an EMDMA is set to transfer 1024 bytes from L2 memory to SHARC core1 L1 such that the EMDMA_INDX0 register
is set to 0x2C1FEC (close to 4 K Byte boundary location 0x2C2000) and the EMDMA_CNT0 register is set to 1024, some of the words
might not get transferred correctly from L2 to L1.
WORKAROUND:
In case it is required to perform an EMDMA transfer to/from SHARC L1 memory with modifier equal to "1", both of the following
conditions should be satisfied to work around this issue:
1. The start address corresponding to the SHARC L1 memory (EMDMA_INDX0/1) should be 32 bytes (i.e. eight 32 bit words) aligned.
AND
2. The count corresponding to the SHARC L1 memory (EMDMA_CNT0/1) should be multiple of 8.
APPLIES TO REVISION(S):
0.1
24. 20000034 - The save state operation may not work as expected in the IIR Accelerator:
DESCRIPTION:
The save state operation (enabled by the IIR_CTL1.SS bit) can be used to write back the biquad state values (DK1, DK2) to the
coefficient buffer. This values can be reloaded back to the IIR Accelerator later for the next processing iteration. Because of this anomaly,
the IIR Accelerator may write back wrong/duplicate DK1, DK2 values to the coefficient buffer.
WORKAROUND:
One way to work around this issue in software is to use the IIR accelerator in debug mode to explicitly read the DK1, DK2 values and write
back these values to the coefficient buffer using core instead of using the automatic save state functionality (IIRCTL1.SS bit). More
details on how to use debug mode to read the biquad state variables, please refer the ADSP-SC58x SHARC Processor Hardware Reference.
APPLIES TO REVISION(S):
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25. 20000035 - Spurious stalls are generated during certain instruction sequences involving F0 register:
DESCRIPTION:
The following sequences results in spurious pipeline stalls:
1. Any compute instruction that updates F0, followed by an instruction that has null compute field.
ex: F0 = F1 * F2;
DM(I0,M0)=R4, R5=PM(I8,M8); //Type-1 instruction with null-compute
2. Any compute instruction that updates F0, followed by an instruction which has immediate field (data or address) in [22:16] bits.
ex : F0 = F1 * F2;
M11 = 0x82404fff;
3. In case of compressed instructions (VISA), any compute instruction that updates F0, followed by a compressed instruction.
ex :
F0 = F2 COPYSIGN F4;
NOP; //16-bit instruction
R1 = DM(I2,M4), R0 = PM(I8,M9);
4. Any floating-point compute instruction with a destination register F0, followed by a no-operand or single operand compute
instruction, with unused source registers are coded as R0.
ex : F0 = PASS F4;
R10 = pass R11; //Y operand is not used, hence flushed to 0 in opcode by assembler
WORKAROUND:
Avoid the usage of F0 register in such sequence of instructions.
APPLIES TO REVISION(S):
0.1
26. 20000036 - Data Cache line fill may not work as expected if it is preceded by a misaligned through data
cache access:
DESCRIPTION:
Misaligned accesses are the accesses straddling to two cache lines (say line L1 and L2). The cache line fill (to either L1 or L2) may not work
as expected in the below sequence:
1. Misaligned data cache through access (cache access is straddling to line L1 and L2, and there is no line fill as it is a through access)
2. Data cache access which results in Cache line fill to the same line (L1 or L2)
Here the cache line fill may not work as expected.
WORKAROUND:
Misaligned accesses issue can be avoided by having the following restrictions on the data alignment:
1. All byte word data should be short word aligned.
2. All short word data should be normal word aligned.
3. All normal word data and long word data should be long word aligned.
APPLIES TO REVISION(S):
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Silicon Anomaly List
27. 20000037 - DMC read state machine may not be in correct state after DMC initialization:
DESCRIPTION:
Read accesses to the DMC require the DMC read state machine to be in the correct state. Because of this anomaly, the DMC read state
machine may not be in a correct state after initializing the DMC and this may result in DMC read failures.
WORKAROUND:
To avoid the above anomaly, the following steps should be followed just after the DMC Initialization is over and before performing any
DMC access:
1. Perform a dummy read to any DMC location.
2. Set bit 12(RESETDAT) of the DMCx_PHY_CTL0 register.
3. Clear bit 12(RESETDAT) of the DMCx_PHY_CTL0 register.
For example, the following C code can be used to perform the above steps for DMC0:
int dummy_read; int* pDMC_Address;
pDMC_Address = (int *)0x80000000;
dummy_read = *pDMC_Address;
*pREG_DMC0_PHY_CTL0 |= 0x1000;
*pREG_DMC0_PHY_CTL0 &= ~0x1000;
APPLIES TO REVISION(S):
0.1
28. 20000038 - Error Address in the Boot Config Struct is Incorrect:
DESCRIPTION:
The 'errorReturn' field of the ADI_ROM_BOOT_CONFIG struct does not point to the location of the error inside boot ROM error handler.
WORKAROUND:
Use the stack to find the trace back to the failing function.
APPLIES TO REVISION(S):
0.1
29. 20000039 - OTP API does not report OTP errors:
DESCRIPTION:
The errors in the OTP controller are masked when using the OTP API.
WORKAROUND:
Applications should check the OTP status register for errors according to the defined bits in the HRM.
APPLIES TO REVISION(S):
0.1
30. 20000040 - DMC is not reset after the PLL frequency changes in boot ROM:
DESCRIPTION:
The DMC initialization using OTP does not work as expected, as the DMC driver in the boot rom does not reset the DLL after a change in
the PLL frequency. As a result, DLL fails to lock to new frequency.
WORKAROUND:
None
APPLIES TO REVISION(S):
0.1
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31. 20000041 - INDIRECT Mode is not functional in boot ROM:
DESCRIPTION:
The INDIRECT mode allows the booting of data via intermediate internal buffers. This is currently not functional and cannot be used.
WORKAROUND:
None
APPLIES TO REVISION(S):
0.1
32. 20000042 - CGU0_CLKOUTSEL is not set from the values in OTP:
DESCRIPTION:
The CGU0_CLKOUTSEL value is not updated by boot rom, though it is configured in the OTP.
WORKAROUND:
None
APPLIES TO REVISION(S):
0.1
33. 20000043 - Key unwrapping on the SHARC fails when using with ROM API:
DESCRIPTION:
ROM API call on SHARC for BLw(Key Unwrapping) Secure boot fails if stack space is mapped to L1 space. Key unwrap operation makes use
of the PKTE DMA engine. This engine is configured to work with only L2 space in the boot ROM.
WORKAROUND:
ROM API application should setup the stack in L2 or L3 space.
APPLIES TO REVISION(S):
0.1
34. 20000044 - Slave boot modes IGNORE block processing not functional with Page mode enabled in a nonsecure boot situation:
DESCRIPTION:
Page mode allows for boot transfer of larger blocks of data via an intermediate buffer. When ignore blocks are processed in slave boot
modes with page mode enabled they should be transferred to the intermediate buffer. Instead the data is discarded resulting in the boot
kernel failing to process data from the intermediate buffer incorrectly. Page mode is not enabled by default and can only be enabled
when using the boot API or through initcodes and thus should not be used for the slave boot modes.
WORKAROUND:
None
APPLIES TO REVISION(S):
0.1
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Silicon Anomaly List
35. 20000045 - SHARC+ core executing IDLE instruction fails to acknowledge with SIDIS, when a reset
sequence is initiated by another core:
DESCRIPTION:
When the SHARC+ core is executing an IDLE instruction and ARM or another SHARC+ core issues a reset sequence as shown below:
1. Clear the previous core Reset status bit on the CRSTAT register
2. Set the SIx bit correspond to the core on the SIDIS register
3. Wait for the acknowledgement from SHARC+ Core by polling for the SIx bit of the SISTAT register
Due to the anomaly, SHARC+ does not send the ACK when it is executing IDLE instruction. The SIx bit in SISTAT register of the
respective core is never set.
WORKAROUND:
None
APPLIES TO REVISION(S):
0.1
36. 20000046 - TMU FAULT/ALERT Status does not get cleared by writing 1 to the corresponding status bits:
DESCRIPTION:
TMU module has two status bits FLTHI and ALRTHI on the TMU_STAT register which are set when the temperature goes beyond certain
value. These bits are Write 1 to clear (W1C) but they do not work as expected. When FLTHI bit is set, writing to FLTHI bit of the TMU_STAT
register does not clear the status. Similarly when ALRTHI bit is set, writing to ALRTHI bit does not clear the status.
WORKAROUND:
When either FLTHI bit or ALRTHI bit or both the bits are set, always write 1 to both the FLTHI and ALRTHI of the TMU_STAT register to clear
the status.
APPLIES TO REVISION(S):
0.1
37. 20000047 - SPU Range Protection for MMR space gets violated if any write access is done to Reserved
memory spaces aliased to these MMR space:
DESCRIPTION:
The ADSP-SC58x processors have many reserved memory spaces in MMR address region. Some of these reserved memory are getting
aliased to the valid MMR spaces. The below list has the MMRs which have aliased memory map:
1.
2.
3.
4.
5.
6.
7.
LP DMA cluster - LP0 DDE and LP1 DDE
WDT0,1
All SCLK0 DMA clusters - SPORT DDEs, UART DDEs, MDMA DDEs, HAE DDEs
SCLK1 DMA cluster - SPI and PPI DDEs
USB0,1
DAI0,1
EMDMA0
When the range protection is enabled from SPU, any write access to the MMR regions will not go through as they are protected. But the
write accesses are not protected using SPU when the accesses are done using the reserved space. Hence the writes using the reserved
address space updates the actual MMR region though the protection is enabled.
WORKAROUND:
None
APPLIES TO REVISION(S):
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38. 20000048 - CGU0_STAT.LWERR Bit Gets Erroneously Set Under Certain Conditions:
DESCRIPTION:
The LWERR bit in the CGU0_STAT register will become erroneously set under the following conditions:
1. SPU_CTL.GLCK is enabled.
2. Any register within the CGU that can be locked has its lock bit set.
3. A write is made to a system MMR of another peripheral that shares that the same 12 LSBs as the locked CGU register.
Although CGU0_STAT.LWERR becomes erroneously set under these conditions, a bus error does not occur as a result. A bus error only
occurs under the conditions specified in the ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference.
WORKAROUND:
There are two possible workarounds:
1. Change any one of the 3 conditions listed in the description.
2. When tracing the source of a bus error, check CGU0_STAT.LWERR after all of other possible sources of the error have been checked.
This will prevent incorrect attribution of bus errors to the CGU.
APPLIES TO REVISION(S):
0.1
39. 20000049 - SPI Transmit Collision Error may occasionally be missed:
DESCRIPTION:
SPI Transmit Collision Error is signalled when loading data to the transmit shift register happens near the first transmitting edge of
SPI_CLK. This error is signalled only in slave mode. But due to incorrect timing of the first drive edge signal, it can occasionally cause a
Transmit Collision Error to be unreported in the SPI_STAT register.
WORKAROUND:
None
APPLIES TO REVISION(S):
0.1
40. 20000050 - SPORT May Drive Data Pins During Inactive Channels in Multichannel Mode:
DESCRIPTION:
When a SPORT is operating in multichannel mode, the transmitter tri-states the data pins during the inactive channels. When SPMUX
functionality is enabled, under specific conditions, one SPORT half may continue to drive on the inactive channels. This happens when all
the below conditions are true.
1.
2.
3.
4.
5.
6.
7.
SPORT half "x" is configured as transmitter (SPORT_CTL_x.SPTRAN = 1).
Imports Frame sync internally from the pairing half SPORT (SPORT_CTL2_x.FSMUXSEL = 1).
Multichannel Frame Delay is zero (SPORT_MCTL_x.MFD = 0).
Window Offset is zero (SPORT_MCTL_x.OFFSET = 0).
Channel-0 of multichannel frame is enabled for transmission (SPORT_CS0_x.CH0 = 1).
Frame sync is active low (SPORT_xCTL.LFS = 1).
Frame Sync edge Detect bit is 0 (SPORT_CTL_x.FSED = 0).
If any of these conditions is false, this anomaly does not occur.
When this exact configuration is used, after completion of all the active channels, the SPORT half transmitter drives the first bit of next
word to be transmitted once the number of channels specified in WSIZE expires. Therefore the SPORT half may drive on inactive channels
which can cause contention when other transmitters configured to drive on these inactive channels.
WORKAROUND:
Avoid any one of the above conditions. For example:
1. Set the Frame Sync edge Detect bit (SPORT_CTL_x.FSED = 1).
2. Use Window Offset other than zero.
3. Use Multichannel Frame Delay other than zero.
APPLIES TO REVISION(S):
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Silicon Anomaly List
41. 20000051 - Secure SPI Master Boot Only Supported From Memory-Mapped SPI Devices on SPI2:
DESCRIPTION:
Secure SPI master boot can only be done in memory-mapped mode from SPI2. SPI0 and SPI1 do not support memory-mapped mode and
therefore cannot support secure SPI master boot. The same restriction applies when calling the ROM API to boot.
WORKAROUND:
If secure SPI boot is needed, always configure dBootCommand to use SPI2 in XIP mode. When calling the ROM API, ensure that the lowest
nibble (boot source device) of the boot command parameter is 0x7. The memory-mapped address where the boot needs to be started
also needs to be passed as a start address parameter. For example, the below ROM API call boots from SPI flash which is mapped to
0x60000000 in XIP mode using SPI2:
adi_rom_Boot(0x60000000,0,0,0,0x207);
APPLIES TO REVISION(S):
0.1
42. 20000052 - SPI Master Boot in Peripheral DMA mode fails for block size greater than 64KB:
DESCRIPTION:
SPI Master Boot in Peripheral DMA mode fails using ROM API if the block size is greater than 64KB.
WORKAROUND:
Block size in the bootstream should be less than 64KB.
APPLIES TO REVISION(S):
0.1
43. 20000053 - Reading Certain PKTE Registers May Return Incorrect Data During Packet Processing:
DESCRIPTION:
Reading out the PKTE_BUF_THRESH, PKTE_INBUF_CNT, or PKTE_OUTBUF_CNT register within one SCLK1 cycle of the Packet Engine
starting to process a packet results in an incorrect value being read. This situation can happen when working in Direct Host Mode and
starting to poll for the amount of data that can be transferred (input or output) shortly after starting packet processing by writing to the
PKTE_SA_RDY register. For Autonomous Ring Mode there is no need to read the affected registers because the data will be automatically
transferred out to specified host memory buffers.
WORKAROUND:
In all modes the anomaly can by avoided by not reading any of the affected registers after starting packet processing using the
PKTE_SA_RDY register.
Additionally, since Direct Host Mode is a manual sequential operation, the Data Output Buffer can be emptied before configuring and
starting a new job to process another packet. It can then be assumed that the Data Input Buffer is empty when starting with a new packet.
By skipping the first poll this anomaly can be avoided. Also, the maximum amount of data to transfer can be assumed to be equal to the
Input Data Buffer size of 256 bytes so there is no need to check the threshold register to gauge this. For the output side it suffices not to
start polling for the availability of data before input data has been transferred.
APPLIES TO REVISION(S):
0.1
44. 20000054 - SPDIF_RX_TDMCLK_O signal cannot be routed using SRU:
DESCRIPTION:
The SPDIF_RX_TDMCLK_O signal is not connected to SRU internally. Hence this signal cannot be routed to other peripheral inputs and/or
to DAI pins using SRU.
WORKAROUND:
None
APPLIES TO REVISION(S):
0.1
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45. 20000055 - Incorrect parameter passed to callback routines:
DESCRIPTION:
The boot kernel incorrectly passes the address of the buffer as the second argument to user callback routines instead of the address of the
ADI_ROM_BOOT_BUFFER item. The ADI_ROM_BOOT_BUFFER item contains both the address and the size of the buffer that has just been
processed.
WORKAROUND:
If user callbacks are required to be enabled and used, the size of the payload currently processed can be retrieved by analyzing contents
of the boot structure for which the pointer is passed as the first parameter to the user callback.
APPLIES TO REVISION(S):
0.1
46. 20000061 - SPI data pins are driven high in open drain mode:
DESCRIPTION:
SPI in open drain mode tri-states the output when data driven is logic high. But due to a race condition, the data pins will drive logic high
for a small duration.
WORKAROUND:
None
APPLIES TO REVISION(S):
0.1
47. 20000062 - The software selection of SPI Slave Enable Signal does not drive to the programmed value in
the Slave Select Register:
DESCRIPTION:
The SPI Slave Enable signal can be selected via software by setting to the required value in the Slave Select Register. However, this value
doesn't get driven on the SPI Slave Enable Signal.
WORKAROUND:
Perform two back to back writes to the Slave Select Register in order to drive the signal to the required level.
APPLIES TO REVISION(S):
0.1
48. 20000063 - Reads of SPU_SECCHK by Non-secure Masters Result in an Erroneous Violation Interrupt:
DESCRIPTION:
Reads of SPU_SECCHK by non-secure masters result in an erroneous SPU violation interrupt. The erroneous interrupt will only be
observed if the SPU violation interrupt is enabled.
WORKAROUND:
There are two possible workarounds:
1. Don't use SPU_SECCHK.
2. Ignore the erroneous SPU interrupt after SPU_SECCHK is read.
APPLIES TO REVISION(S):
0.1
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Silicon Anomaly List
49. 20000064 - Misaligned data cache access may affect the functioning of L1 Parity:
DESCRIPTION:
When both L1 Cache and L1 Parity is enabled, a spurious parity error interrupt may be generated if there is any misaligned data cache
accesses.
WORKAROUND:
This issue can be averted if the Data cache misalignment is avoided by having the following restrictions on the data alignment:
1. All byte word data should be short word aligned
2. All short word data should be normal word aligned
3. All normal word data and long word data should be long word aligned
APPLIES TO REVISION(S):
0.1
50. 20000065 - L1 Cache Range Based Functionality has some issues:
DESCRIPTION:
Due to some issues found with the Range based functionality of L1 Cache, only the following configurations are supported:
1. Write Back Invalidation Range (On Range Register pair 0)
2. Write Through Range (On Range Register pair 4 and 5)
3. Locking Range for Data (DM and PM) Cache (On Range Register pair 1,2 and 3)
4. Non-Cacheable Range for Data (DM and PM) Cache (On Range Register pair 2,3,4 and 5)
WORKAROUND:
None
APPLIES TO REVISION(S):
0.1
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