FEATURES
PIN CONNECTIONS
Very low voltage noise: 1 nV/√Hz maximum at 100 Hz
Excellent current gain match: 0.5%
Low offset voltage (VOS): 200 μV maximum (SOIC)
Outstanding offset voltage drift: 0.03 μV/°C
High gain bandwidth product: 200 MHz
C1 1
8
C2
B1 2
7
B2
E1 3
6
E2
5
NIC
NIC 4
SSM2212
NOTES
1. NIC = NO INTERNAL CONNECTION.
09043-001
Data Sheet
Audio, Dual-Matched
NPN Transistor
SSM2212
13 C1
E1A 1
12 NIC
E1B 2
11 C2
E2B 3
SSM2212
10 NIC
9
NIC
NIC 8
NIC 7
B2 6
NIC 5
E2A 4
NOTES
1. NIC = NO INTERNAL CONNECTION.
09043-020
14 NIC
16 NIC
15 B1
Figure 1. 8-Lead SOIC_N
Figure 2. 16-Lead LFCSP_WQ
GENERAL DESCRIPTION
The SSM2212 is a dual, NPN-matched transistor pair that is
specifically designed to meet the requirements of ultralow noise
audio systems.
With its extremely low input base spreading resistance (rbb' is
typically 28 Ω) and high current gain (hFE typically exceeds 600 at
IC = 1 mA), the SSM2212 can achieve outstanding signal-to-noise
ratios. The high current gain results in superior performance
compared to systems incorporating commercially available
monolithic amplifiers.
Excellent matching of the current gain (ΔhFE) to approximately
0.5% and low VOS of less than 10 μV typical make the SSM2212
ideal for symmetrically balanced designs, which reduce highorder amplifier harmonic distortion.
Stability of the matching parameters is guaranteed by protection
diodes across the base-emitter junction. These diodes prevent
degradation of beta and matching characteristics due to reverse
biasing of the base-emitter junction.
The SSM2212 is also an ideal choice for accurate and reliable
current biasing and mirroring circuits. Furthermore, because
the accuracy of a current mirror degrades exponentially with
mismatches of VBE between transistor pairs, the low VOS of the
SSM2212 does not need offset trimming in most circuit
applications.
The SSM2212 SOIC performance and characteristics are
guaranteed over the extended temperature range of −40°C to
+85°C.
The SSM2212 is available in 8-lead SOIC and 16-lead LFCSP
packages.
Rev. C
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Tel: 781.329.4700 ©2010–2015 Analog Devices, Inc. All rights reserved.
Technical Support
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SSM2212
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Resistance .......................................................................5
Pin Connections ............................................................................... 1
ESD Caution...................................................................................5
General Description ......................................................................... 1
Typical Performance Characteristics ..............................................6
Revision History ............................................................................... 2
Pin Configurations and Function Descriptions ............................9
Specifications..................................................................................... 3
Applications Information .............................................................. 10
Electrical Characteristics—SOIC Package ................................ 3
Fast Logarithmic Amplifier....................................................... 10
Electrical Characteristics—LFCSP Package .............................. 4
Outline Dimensions ....................................................................... 11
Absolute Maximum Rating ............................................................. 5
Ordering Guide .......................................................................... 11
REVISION HISTORY
6/15—Rev. B to Rev. C
Added LFCSP Package ....................................................... Universal
Changes to Features Section and General Description Section....... 1
Changed Pin Configuration Section to Pin Connections Section .. 1
Added Figure 2; Renumbered Sequentially ....................................... 1
Added Electrical Characteristics—LFCSP Package Section and
Table 2; Renumbered Sequentially ...................................................... 4
Changes to Table 4 .................................................................................. 5
Added Pin Configurations and Function Descriptions Section,
Figure 17, Table 5, Figure 18, and Table 6 .......................................... 9
Added Figure 21.................................................................................... 11
Updated Outline Dimensions ............................................................ 11
Changes to Ordering Guide................................................................ 11
7/10—Rev. A to Rev. B
Changes to Figure 1 .......................................................................... 1
6/10—Rev. 0 to Rev. A
Changes to Fast Logarithmic Amplifier Section .......................... 8
6/10—Revision 0: Initial Version
Rev. C | Page 2 of 12
Data Sheet
SSM2212
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—SOIC PACKAGE
VCB = 15 V, IO = 10 µA, TA = 25°C, unless otherwise specified.
Table 1.
Parameter
DC AND AC CHARACTERISTICS
Current Gain1
Current Gain Match2
Noise Voltage Density3
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
IC = 1 mA
−40°C ≤ TA ≤ +85°C
IC = 10 µA
−40°C ≤ TA ≤ +85°C
10 µA ≤ IC ≤ 1 mA
IC = 1 mA, VCB = 0 V
fO = 10 Hz
fO = 100 Hz
fO = 1 kHz
fO = 10 kHz
IC = 1 mA
VCB = 0 V, IC = 1 mA
−40°C ≤ TA ≤ +85°C
0 V ≤ VCB ≤ VMAX4,1 µA ≤ IC ≤ 1 mA5
1 µA ≤ IC ≤ 1 mA5, VCB = 0 V
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +85°C, VOS trimmed to 0 V
300
300
200
200
605
0.5
5
%
1.6
0.9
0.85
0.85
0.4
10
2
1
1
1
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
µV p-p
µV
µV
µV
µV
µV/°C
µV/°C
V
MHz
pA
nA
pA
nA
pA
nA
nA
nA
nA
nA
pA/°C
V
pF
Ω
pF
hFE
ΔhFE
eN
Low Frequency Noise (0.1 Hz to 10 Hz)
Offset Voltage
eN p-p
VOS
Offset Voltage Change vs. VCB
Offset Voltage Change vs. IC
Offset Voltage Drift
ΔVOS/ΔVCB
ΔVOS/ΔIC
ΔVOS/ΔT
Breakdown Voltage
Gain Bandwidth Product
Collector-to-Base Leakage Current
BVCEO
fT
ICBO
Collector-to-Collector Leakage Current
ICC
Collector-to-Emitter Leakage Current
ICES
Input Bias Current
IB
Input Offset Current
IOS
Input Offset Current Drift
Collector Saturation Voltage
Output Capacitance
Bulk Resistance
Collector-to-Collector Capacitance
ΔIOS/ΔT
VCE (SAT)
COB
RBE
CCC
550
10
5
0.08
0.03
200
220
50
70
1
0.3
40
IC = 10 mA, VCE = 10 V
VCB = VMAX
−40°C ≤ TA ≤ +85°C
VCC = VMAX6, 7
−40°C ≤ TA ≤ +85°C
VCE = VMAX, VBE = 0 V6, 7
−40°C ≤ TA ≤ +85°C
IC = 10 µA
−40°C ≤ TA ≤ +85°C
IC = 10 µA
−40°C ≤ TA ≤ +85°C
IC = 10 µA6, −40°C ≤ TA ≤ +85°C
IC = 1 mA, IB = 100 µA
VCB = 15 V, IE = 0 µA
10 µA ≤ IC ≤ 10 mA6
VCC = 0 V
Current gain is guaranteed with collector-to-base voltage (VCB) swept from 0 V to VMAX at the indicated collector currents.
Current gain match (ΔhFE) is defined as follows: ΔhFE = (100(ΔIB)(hFE min)/IC).
3
Noise voltage density is guaranteed, but not 100% tested.
4
This is the maximum change in VOS as VCB is swept from 0 V to 40 V.
5
Measured at IC = 10 µA and guaranteed by design over the specified range of IC.
6
Guaranteed by design.
7
ICC and ICES are verified by measurement of ICBO.
1
2
Rev. C | Page 3 of 12
200
25
3
35
4
35
4
40
0.05
23
0.3
35
500
500
500
50
50
6.2
13
150
0.2
1.6
SSM2212
Data Sheet
ELECTRICAL CHARACTERISTICS—LFCSP PACKAGE
VCB = 15 V, IO = 100 µA, TA = 25°C, unless otherwise specified.
Table 2.
Parameter
DC AND AC CHARACTERISTICS
Current Gain1
Current Gain Match2
Noise Voltage Density3
1
2
3
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
IC = 1 mA, VCB = 15 V
IC = 1 mA, VCB = 0 V
IC = 100 µA, VCB = 15 V
IC = 100 µA, VCB = 0 V
100 µA ≤ IC ≤ 1 mA
IC = 1 mA, VCB = 0 V
fO = 10 Hz
fO = 100 Hz
fO = 1 kHz
fO = 10 kHz
IC = 1 mA
VCB = 0 V, IC = 1 mA
VCB = 0 V, IC = 100 µA
IC = 10 mA, VCE = 10 V
IC = 100 µA
IC = 100 µA
VCB = 15 V, IE = 0 µA
VCC = 0 V
300
200
350
250
1800
1300
2100
1500
0.5
2400
2200
2500
2300
5
%
1.6
0.9
0.85
0.85
0.4
25
10
200
2
1
1
1
hFE
ΔhFE
eN
Low Frequency Noise (0.1 Hz to 10 Hz)
Offset Voltage
eN p-p
VOS
Gain Bandwidth Product
Input Bias Current
Input Offset Current
Output Capacitance
Collector-to-Collector Capacitance
fT
IB
IOS
COB
CCC
Current gain is guaranteed with collector-to-base voltage (VCB) swept from 0 V to VMAX at the indicated collector currents.
Current gain match (ΔhFE) is defined as follows: ΔhFE = (100(ΔIB)(hFE min)/IC).
Noise voltage density is guaranteed, but not 100% tested.
Rev. C | Page 4 of 12
250
250
200
10
23
35
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
µV p-p
µV
µV
MHz
nA
nA
pF
pF
Data Sheet
SSM2212
ABSOLUTE MAXIMUM RATING
Table 3.
Parameter
Breakdown Voltage of
Collector-to-Base Voltage (BVCBO)
Breakdown Voltage of
Collector-to-Emitter Voltage (BVCEO)
Breakdown Voltage of
Collector-to-Collector Voltage (BVCC)
Breakdown Voltage of
Emitter-to-Emitter Voltage (BVEE)
Collector Current (IC)
Emitter Current (IE)
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
THERMAL RESISTANCE
Rating
40 V
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
40 V
Table 4. Thermal Resistance
40 V
Package Type
8-Lead SOIC (R-8)
16-Lead LFCSP (CP-16-22)
40 V
20 mA
20 mA
−65°C to +150°C
−40°C to +85°C
−65°C to +150°C
300°C
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. C | Page 5 of 12
θJA
120
75
θJC
45
4.4
Unit
°C/W
°C/W
SSM2212
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCE = 5 V, unless otherwise specified.
900
CH1 4.92V p-p
800
TA = +125°C
CURRENT GAIN (hFE)
700
1
TA = +25°C
600
500
400
TA = –55°C
300
M4.00s
A CH1
15.8V
100
0.001
0.01
0.1
1
COLLECTOR CURRENT (mA)
Figure 6. Current Gain vs. Collector Current (VCB = 0 V)
Figure 3. Low Frequency Noise (0.1 Hz to 10 Hz), IC = 1 mA, Gain = 10,000,000
900
1k
800
1mA
700
100
CURRENT GAIN (hFE)
NOISE VOLTAGE DENSITY (nV/ Hz)
09043-005
CH1 2.00V
09043-002
200
IC = 1µA TEST
10
IC = 10µA TEST
IC = 1mA TEST
1
600
500
400
300
1µA
200
1
10
100
1k
10k
100k
FREQUENCY (Hz)
0
–100
09043-003
0.1
0.1
–50
0
50
100
150
TEMPERATURE (°C)
Figure 4. Noise Voltage Density vs. Frequency
09043-006
100
Figure 7. Current Gain vs. Temperature (Excludes ICBO)
100
0.70
BASE EMITTER VOLTAGE, VBE (V)
0.65
60
RS = 100kΩ
40
RS = 10kΩ
0.01
0.55
VCE = 5V
0.50
0.45
0.40
0.35
RS = 1kΩ
0
0.001
0.60
0.1
COLLECTOR CURRENT, IC (mA)
1
0.30
0.001
0.01
0.1
1
COLLECTOR CURRENT, IC (mA)
Figure 5. Total Noise vs. Collector Current, f = 1 kHz
Figure 8. Base Emitter Voltage vs. Collector Current
Rev. C | Page 6 of 12
10
09043-008
20
09043-004
TOTAL NOISE (nV/ Hz)
80
SSM2212
100
1000
10
100
CURRENT, ICBO (nA)
1
VCE = 5V
0.1
10
1
0.1
0.01
0.01
0.1
1
0.01
25
09043-009
0.001
0.001
10
COLLECTOR CURRENT, IC (mA)
50
75
100
125
TEMPERATURE (°C)
Figure 9. Small Signal Input Resistance vs. Collector Current
09043-012
INPUT RESISTANCE, hIE (MΩ)
Data Sheet
Figure 12. Collector-to-Base Leakage Current vs. Temperature
1m
40
CAPACITANCE, C CB (pF)
0.01m
VCE = 5V
1µ
30
25
20
15
10
0.1µ
0
0.01
0.1
1
10
100
1000
COLLECTOR CURRENT, IC (mA)
0
09043-010
0.01µ
0.001
10
20
30
40
50
REVERSE BIAS VOLTAGE (V)
09043-013
5
Figure 13. Collector-to-Base Capacitance vs. Reverse Bias Voltage
Figure 10. Small Signal Output Conductance vs. Collector Current
40
100
35
CAPACITANCE, C CC (pF)
TA = –55°C
TA = +125°C
10
TA = +25°C
1
0.1
30
25
20
15
10
0.01
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
SATURATION VOLTAGE, VSAT (V)
0.9
0
0
10
20
30
40
COLLECTOR-TO-SUBSTRATE VOLTAGE (V)
Figure 14. Collector-to-Collector Capacitance vs.
Collector-to-Substrate Voltage
Figure 11. Collector Current vs. Saturation Voltage
Rev. C | Page 7 of 12
50
09043-014
5
09043-017
COLLECTOR CURRENT, IC (mA)
CONDUCTANCE, h OE (mho)
35
0.1m
SSM2212
Data Sheet
1000
4.0
3.5
CAPACITANCE, C CC (pF)
10
1
3.0
2.5
2.0
1.5
1.0
0.1
0.01
25
50
75
100
125
TEMPERATURE (°C)
Figure 15. Collector-to-Collector Leakage Current vs. Temperature
0
0
10
20
30
REVERSE BIAS VOLTAGE (V)
40
50
09043-016
0.5
09043-015
CURRENT, ICC (nA)
100
Figure 16. Collector-to-Collector Capacitance vs. Reverse Bias Voltage
Rev. C | Page 8 of 12
Data Sheet
SSM2212
C1 1
B1 2
SSM2212
TOP VIEW
E1 3 (Not to Scale)
NIC 4
8
C2
7
B2
6
E2
5
NIC
NOTES
1. NIC = NO INTERNAL CONNECTION.
09043-021
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 17. SOIC Pin Configuration
Table 5. SOIC Pin Function Descriptions
13 C1
14 NIC
Description
Collector of Channel 1.
Base of Channel 1.
Emitter of Channel 1.
No Internal Connection.
Emitter of Channel 2.
Base of Channel 2.
Collector of Channel 2.
16 NIC
E1A 1
E1B 2
E2B 3
12 NIC
SSM2212
TOP VIEW
(Not to Scale)
10 NIC
NIC
NIC 8
NIC 7
B2 6
9
NIC 5
E2A 4
11 C2
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO THE LOWEST POTENTIAL.
09043-022
Mnemonic
C1
B1
E1
NIC
E2
B2
C2
15 B1
Pin No.
1
2
3
4, 5
6
7
8
Figure 18. LFCSP Pin Configuration
Table 6. LFCSP Pin Function Descriptions
Pin No.
1
2
3
4
5, 7, 8, 9, 10, 12, 14, 16
6
11
13
15
Mnemonic
E1A
E1B
E2B
E2A
NIC
B2
C2
C1
B1
EPAD
Description
Emitter of Channel 1. Must be connect to E1B.
Emitter of Channel 1. Must be connect to E1A.
Emitter of Channel 2. Must be connect to E2A.
Emitter of Channel 2. Must be connect to E2B.
No Internal Connection.
Base of Channel 2.
Collector of Channel 2.
Collector of Channel 1.
Base of Channel 1.
Exposed Pad. The exposed pad must be connected to the lowest potential.
Rev. C | Page 9 of 12
SSM2212
Data Sheet
APPLICATIONS INFORMATION
FAST LOGARITHMIC AMPLIFIER
To compensate for the temperature dependence of the kT/q term, a
resistor with a positive 0.35%/°C temperature coefficient is chosen
for R2. The output is inverted with respect to the input and is
nominally −1 V/decade using the component values indicated.
The circuit in Figure 19 is a modification of a standard
logarithmic amplifier configuration. Running the SSM2212 at
2.5 mA per side (full scale) allows a fast response with a wide
dynamic range. The circuit has a 7 decade current range and a
5 decade voltage range, and it is capable of 2.5 µs settling time to
1% with a 1 V to 10 V step. The output follows the equation:
R3 + R2 kT V REF
ln
R2
q
V IN
+15V
VIN
(0V TO 10V)
RS
4kΩ
2
8
1/2
AD8512
1
VO
3
4
–15V
330pF
R3
7.5kΩ
330pF
VREF
10V
R1
4kΩ
SSM2212
6
1/2
AD8512
7
4kΩ
R2
500Ω
R2 = TEL LABS QB1E (+0.35%/°C)
09043-018
VO =
5
Figure 19. Fast Logarithmic Amplifier
Rev. C | Page 10 of 12
Data Sheet
SSM2212
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
4.00 (0.1574)
3.80 (0.1497)
1
5
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
0.50 (0.0196)
0.25 (0.0099)
1.75 (0.0688)
1.35 (0.0532)
45°
8°
0°
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
012407-A
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 20. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters (and inches)
0.30
0.23
0.18
0.50
BSC
13
PIN 1
INDICATOR
16
1
12
EXPOSED
PAD
1.75
1.60 SQ
1.45
9
TOP VIEW
0.80
0.75
0.70
SEATING
PLANE
0.50
0.40
0.30
4
8
5
0.25 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
08-16-2010-E
PIN 1
INDICATOR
3.10
3.00 SQ
2.90
Figure 21. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
SSM2212RZ
SSM2212RZ-R7
SSM2212RZ-RL
SSM2212CPZ-R7
SSM2212CPZ-RL
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Z = RoHS Compliant Part.
Rev. C | Page 11 of 12
Package Option
R-8
R-8
R-8
CP-16-22
CP-16-22
Branding
A3F
A3F
SSM2212
Data Sheet
NOTES
©2010–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09043-0-6/15(C)
Rev. C | Page 12 of 12