ADSP-TS201S EZ-KIT Lite®
Evaluation System Manual
Revision 2.0, January 2005
Part Number
82-000770-01
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106
a
Copyright Information
© 2005 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.
Printed in the USA.
Limited Warranty
The EZ-KIT Lite evaluation system is warranted against defects in materials and workmanship for a period of one year from the date of purchase
from Analog Devices or from an authorized dealer.
Disclaimer
Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark Notice
The Analog Devices logo, TigerSHARC, VisualDSP++, the CROSSCORE logo, and EZ-KIT Lite are registered trademarks of Analog
Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.
Regulatory Compliance
The ADSP-TS201S EZ-KIT Lite evaluation system has been certified to
comply with the essential requirements of the European EMC directive
89/336/EEC (inclusive 93/68/EEC) and, therefore, carries the “CE”
mark.
The ADSP-TS201S EZ-KIT Lite evaluation system had been appended to
Analog Devices Development Tools Technical Construction File referenced “DSPTOOLS1” dated December 21, 1997 and was awarded CE
Certification by an appointed European Competent Body and is on file.
The EZ-KIT Lite evaluation system contains ESD
(electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human
body and equipment and can discharge without
detection. Permanent damage may occur on devices
subjected to high-energy discharges. Proper ESD
precautions are recommended to avoid performance
degradation or loss of functionality. Store unused
EZ-KIT Lite boards in the protective shipping
package.
CONTENTS
PREFACE
Purpose of This Manual ................................................................. xii
Intended Audience ......................................................................... xii
Manual Contents ........................................................................... xii
What’s New in This Manual .......................................................... xiii
Technical or Customer Support ...................................................... xiv
Supported Processors ...................................................................... xiv
Product Information ....................................................................... xv
MyAnalog.com .......................................................................... xv
Processor Product Information ................................................... xv
Related Documents .................................................................. xvi
Online Technical Documentation ............................................ xvii
Accessing Documentation From VisualDSP++ .................... xviii
Accessing Documentation From Windows .......................... xviii
Accessing Documentation From Web ................................... xix
Printed Manuals ....................................................................... xix
VisualDSP++ Documentation Set ......................................... xix
Hardware Tools Manuals ...................................................... xix
Processor Manuals ................................................................. xx
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
v
CONTENTS
Data Sheets .......................................................................... xx
Notation Conventions ................................................................... xxi
USING EZ-KIT LITE
Package Contents ......................................................................... 1-2
Default Configuration .................................................................. 1-3
Installation and Session Startup ..................................................... 1-5
Evaluation License Restrictions ..................................................... 1-6
Memory Map ............................................................................... 1-6
SDRAM Interface ......................................................................... 1-7
Flash Memory .............................................................................. 1-8
Programmable FLAG Pins ............................................................ 1-9
Interrupt Pins ............................................................................. 1-10
Audio Interface ........................................................................... 1-11
Processor Link Ports ................................................................... 1-11
Example Programs ...................................................................... 1-12
Flash Programmer Utility ............................................................ 1-13
EZ-KIT LITE HARDWARE REFERENCE
System Architecture ...................................................................... 2-2
External Port ........................................................................... 2-3
Expansion Interface ................................................................. 2-3
JTAG Emulation Port ............................................................. 2-4
Switch Settings ............................................................................. 2-5
Audio Amplification Selection (SW1) ...................................... 2-6
vi
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
CONTENTS
Processor Mode Selections (SW2) ............................................ 2-6
Processor Boot Strap Settings .............................................. 2-7
SYSCON/SDRCON Mode Settings .................................... 2-7
Interrupt Enable Settings .................................................... 2-8
Link Port Width Settings .................................................... 2-8
FLAGs and IRQs Switch Settings (SW10) ................................ 2-9
Configuration Resistors ............................................................... 2-10
Processor ID Settings ............................................................. 2-10
Clock Mode Settings ............................................................. 2-12
Control Impedance Selection ................................................. 2-14
Drive Strength Selection ........................................................ 2-15
LEDs and Push Buttons .............................................................. 2-16
Power LED (LED1) ............................................................... 2-16
Reset LEDs (LED2 and LED8) .............................................. 2-17
FLAG LEDs (LED3–6) ......................................................... 2-17
USB Monitor LED (LED9) ................................................... 2-17
Programmable FLAG Push Buttons (SW6–9) ......................... 2-18
Interrupt Push Buttons (SW4–5) ........................................... 2-18
Reset Push Button (SW3) ...................................................... 2-19
Connectors ................................................................................. 2-19
Audio (P1–2) ........................................................................ 2-20
Power (P3) ............................................................................ 2-20
JTAG (P4) ............................................................................ 2-21
USB (P5) .............................................................................. 2-21
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
vii
CONTENTS
Expansion Interface (J1–3) .................................................... 2-21
Link Ports (J4–7) .................................................................. 2-22
Specifications ............................................................................. 2-22
Power Supply ........................................................................ 2-22
BILL OF MATERIALS
INDEX
viii
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
PREFACE
Thank you for purchasing the ADSP-TS201S EZ-KIT Lite®, Analog
Devices (ADI) evaluation system for TigerSHARC® floating-point
embedded processors.
The TigerSHARC processor is a Static Super Scalar (SSS) architecture targeted at software-defined radio applications. In these wireless
infrastructure applications, the TigerSHARC processor is replacing
field-programmable gate arrays (FPGAs) in the Chip Rate processing
applications for third generation cellular. The performance, flexibility,
multiprocessing and IO capabilities of the TigerSHARC processor makes
it superior to FPGA implementations.
The evaluation board is designed to be used in conjunction with the VisualDSP++® development environment to test the capabilities of the
ADSP-TS201S TigerSHARC processor. The VisualDSP++ development
environment gives you the ability to perform advanced application code
development and debug, such as:
• Create, compile, assemble, and link application programs written
in C++, C, and ADSP-TS201S assembly
• Load, run, step-in, step-out, step-over, halt, and set breakpoints in
application program
• Read and write data and program memory
• Read and write core and peripheral registers
• Plot memory
Access to the ADSP-TS201S processor from a personal computer (PC) is
achieved through a USB port or an optional JTAG emulator. The USB
interface gives unrestricted access to the ADSP-TS201S processor and the
evaluation board peripherals. Analog Devices JTAG emulators offer faster
communication between the host PC and target hardware. Analog Devices
carries a wide range of in-circuit emulation products. To learn more about
Analog Devices emulators and processor development tools, go to
http://www.analog.com/processors/tools/.
The ADSP-TS201S EZ-KIT Lite provides example programs to demonstrate the capabilities of the evaluation board.
ADSP-TS201S EZ-KIT Lite installation is part of the VisuL The
alDSP++ installation. The EZ-KIT Lite is a licensed product that
offers an unrestricted evaluation license for the first 90 days. Once
the initial unrestricted 90-day evaluation license expires:
• VisualDSP++ allows a connection to the ADSP-TS201S EZ-KIT
Lite via the USB Debug Agent interface only. Connections to simulators and emulation products are no longer allowed.
• The linker restricts a users program to 128K words of internal
memory for code space with no restrictions for data space.
Refer to the VisualDSP++ Installation Quick Reference Card for details.
The board features:
• Two Analog Devices ADSP-TS201S processors
D
D
500 MHz Core Clock Speed
Configurable Core Clock Mode
• Analog Devices AD1871 96 kHz Analog-to-Digital Converter
D
x
Line-In 3.5 mm Stereo Jack
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Preface
• Analog Devices AD1854 96 kHz Digital-to-Analog Converter
D
Line-Out 3.5 mm Stereo Jack
• SDRAM Memory
D
32 MB (4 MB x 64)
• Flash Memory
D
512K Main Flash Memory
• USB Debugging Interface
• Interface Connectors
D
D
D
14-Pin Emulator Connector for JTAG Interface
LVDS Link Ports via RJ-45 Connectors
Expansion Interface Connectors (not populated)
• General-Purpose IO
D
D
D
4 Push Button FLAGS (two for each processor)
2 Push Button Interrupts (one for each processor)
4 LED FLAG Outputs (two for each processor)
• Analog Devices ADP3331, ADP3336, and ADP3339 for Voltage
Regulation
The EZ-KIT Lite board contains two external memories: flash memory
and SDRAM. The flash memory can be used to store user-specific boot
code. By configuring the boot mode switch (SW2) and programming the
flash memory, the board can run as a stand-alone unit. The SDRAM is
shared by both processors and can be used to store data external to the
processors. For more information, see “Memory Map” on page 1-6.
The EZ-KIT Lite board contains an audio interface, facilitating creation
of audio signal processing applications.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
xi
Purpose of This Manual
Additionally, the EZ-KIT Lite board provides expansion connectors,
allowing you to connect to the processor’s external port (EP).
Purpose of This Manual
The ADSP-TS201S EZ-KIT Lite Evaluation System Manual provides
instructions for installing the product hardware (board). The text
describes the operation and configuration of the board components and
provides guidelines for running your own code on the ADSP-TS201S
EZ-KIT Lite. Finally, a schematic and a bill of materials are provided as a
reference for future designs.
The product software installation is detailed in the
Intended Audience
The primary audience of this manual is a programmer who is familiar with
Analog Devices processors. This manual assumes that the audience has a
working knowledge of the appropriate processor architecture and instruction set. Programmers who are unfamiliar with Analog Devices processors
can use this manual but should supplement it with other texts (such as the
ADSP-TS201 TigerSHARC Processor Hardware Reference and the
ADSP-TS201 TigerSHARC Processor Programming Reference) that describe
your target architecture.
Programmers who are unfamiliar with VisualDSP++ should refer to the
VisualDSP++ online Help and user’s or getting started guides. For the
locations of these documents, see “Related Documents”.
Manual Contents
The manual consists of:
xii
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Preface
• Chapter 1, “Using EZ-KIT Lite” on page 1-1
Provides information on the EZ-KIT Lite from a programmer’s
perspective and outlines the board’s memory map.
• Chapter 2, “EZ-KIT Lite Hardware Reference” on page 2-1
Provides information on the hardware aspects of the EZ-KIT Lite.
• Appendix A, “Bill Of Materials” on page A-1
Provides a list of components used to manufacture the EZ-KIT
Lite board.
• Appendix B, “Schematics” on page B-1
Provides the resources to allow EZ-KIT Lite board-level debugging
or to use as a reference design.
appendix is not part of the online Help. The online Help
L This
viewers should go to the PDF version of the ADSP-TS201S
EZ-KIT Lite Evaluation System Manual located in the
Docs\EZ-KIT Lite Manuals folder on the installation CD to see the
schematics. Alternatively, the schematics can be found on the Analog Devices Web site, www.analog.com/processors.
What’s New in This Manual
This revision of the ADSP-TS201S EZ-KIT Lite Evaluation System Manual
provides an updated listing of related documents and updated licensing
information.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
xiii
Technical or Customer Support
Technical or Customer Support
You can reach DSP Tools Support in the following ways.
• Visit the Embedded Processing and DSP products Web site at
http://www.analog.com/processors/technicalSupport
• E-mail tools questions to
dsptools.support@analog.com
• E-mail processor questions to
dsp.support@analog.com
• Phone questions to 1-800-ANALOGD
• Contact your Analog Devices, Inc. local sales office or authorized
distributor
• Send questions by mail to:
Analog Devices, Inc.
One Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
USA
Supported Processors
The ADSP-TS201S EZ-KIT Lite evaluation system supports the Analog
Devices ADSP-TS201S TigerSHARC embedded processors.
xiv
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Preface
Product Information
You can obtain product information from the Analog Devices website,
from the product CD-ROM, or from the printed publications (manuals).
Analog Devices is online at www.analog.com. Our website provides information about a broad range of products—analog integrated circuits,
amplifiers, converters, and embedded processors.
MyAnalog.com
MyAnalog.com is a free feature of the Analog Devices Web site that allows
customization of a Web page to display only the latest information on
products you are interested in. You can also choose to receive weekly
e-mail notifications containing updates to the Web pages that meet your
interests. MyAnalog.com provides access to books, application notes, data
sheets, code examples, and more.
Registration:
Visit www.myanalog.com to sign up. Click Register to use MyAnalog.com.
Registration takes about five minutes and serves as means for you to select
the information you want to receive.
If you are already a registered user, just log on. Your user name is your
e-mail address.
Processor Product Information
For information on embedded processors and processors, visit our Web
site at www.analog.com/processors, which provides access to technical
publications, data sheets, application notes, product overviews, and product announcements.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
xv
Product Information
You may also obtain additional information about Analog Devices and its
products in any of the following ways.
• E-mail questions or requests for information to
dsp.support@analog.com
• Fax questions or requests for information to
1-781-461-3010 (North America)
+49 (89) 76 903-557 (Europe)
• Access the FTP Web site at
ftp ftp.analog.com or ftp
137.71.23.21
ftp://ftp.analog.com
Related Documents
For information on product related development software, see the following publications.
Table 1. Related Processor Publications
Title
Description
ADSP-TS201S Embedded Processor Datasheet
General functional description, pinout, and
timing
ADSP-TS201 TigerSHARC Processor Hardware
Reference
Description of internal processor architecture
and all register functions
ADSP-TS201 TigerSHARC Processor Programming Reference
Description of all allowed processor assembly
instructions
Table 2. Related VisualDSP++ Publications
xvi
Title
Description
VisualDSP++ User’s Guide
Description of VisualDSP++ features and usage
VisualDSP++ Assembler and Preprocessor
Manual
Description of the assembler function and commands
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Preface
Table 2. Related VisualDSP++ Publications (Cont’d)
Title
Description
VisualDSP++ C/C++ Complier and
Description of the complier function and comLibrary Manual for TigerSHARC Processors mands for TigerSHARC processors
VisualDSP++ Linker and Utilities Manual
Description of the linker function and commands
VisualDSP++ Loader Manual
Description of the loader/splitter function and commands
All documentation is available online. Most documentation is available in
printed form.
you plan to use the EZ-KIT Lite board in conjunction with a
L IfJTAG
emulator, also refer to the documentation that accompanies
the emulator.
Visit the Technical Library Web site to access all processor and tools manuals and data sheets:
http://www.analog.com/processors/resources/technicalLibrary
Online Technical Documentation
Online documentation comprises the VisualDSP++ Help system, software
tools manuals, hardware tools manuals, processor manuals, the Dinkum
Abridged C++ library, and Flexible License Manager (FlexLM) network
license manager software documentation. You can easily search across the
entire VisualDSP++ documentation set for any topic of interest. For easy
printing, supplementary .PDF files of most manuals are provided in the
Docs folder on the VisualDSP++ installation CD.
Each documentation file type is described as follows.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
xvii
Product Information
File
Description
.CHM
Help system files and manuals in Help format
.HTM or
.HTML
Dinkum Abridged C++ library and FlexLM network license manager software documentation. Viewing and printing the .HTML files requires a browser, such as
Internet Explorer 4.0 (or higher).
.PDF
VisualDSP++ and processor manuals in Portable Documentation Format (PDF).
Viewing and printing the .PDF files requires a PDF reader, such as Adobe Acrobat
Reader (4.0 or higher).
If documentation is not installed on your system as part of the software
installation, you can add it from the VisualDSP++ CD at any time by running the Tools installation. Access the online documentation from the
VisualDSP++ environment, Windows® Explorer, or the Analog Devices
Web site.
Accessing Documentation From VisualDSP++
To view VisualDSP++ Help, click on the Help menu item or go to the
Windows task bar and navigate to the VisualDSP++ documentation via
the Start menu.
To view ADSP-TS201S EZ-KIT Lite Help, which is part of the VisualDSP++ Help system, use the Contents or Search tab of the Help
window.
Accessing Documentation From Windows
In addition to any shortcuts you may have constructed, there are many
ways to open VisualDSP++ online Help or the supplementary documentation from Windows.
Help system files (.CHM) are located in the Help folder, and .PDF files are
located in the Docs folder of your VisualDSP++ installation CD-ROM.
The Docs folder also contains the Dinkum Abridged C++ library and the
FlexLM network license manager software documentation.
xviii
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Preface
Your software installation kit includes online Help as part of the Windows® interface. These help files provide information about VisualDSP++
and the ADSP-TS201S EZ-KIT Lite evaluation system.
Accessing Documentation From Web
Download manuals at the following Web site:
http://www.analog.com/processors/resources/technicalLibrary/manuals.
Select a processor family and book title. Download archive (.ZIP) files, one
for each manual. Use any archive management software, such as WinZip,
to decompress downloaded files.
Printed Manuals
For general questions regarding literature ordering, call the Literature
Center at 1-800-ANALOGD (1-800-262-5643) and follow the prompts.
VisualDSP++ Documentation Set
To purchase VisualDSP++ manuals, call 1-603-883-2430. The manuals
may be purchased only as a kit.
If you do not have an account with Analog Devices, you are referred to
Analog Devices distributors. For information on our distributors, log onto
http://www.analog.com/salesdir/continent.asp.
Hardware Tools Manuals
To purchase EZ-KIT Lite and In-Circuit Emulator (ICE) manuals, call
1-603-883-2430. The manuals may be ordered by title or by product
number located on the back cover of each manual.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
xix
Product Information
Processor Manuals
Hardware reference and instruction set reference manuals may be ordered
through the Literature Center at 1-800-ANALOGD (1-800-262-5643),
or downloaded from the Analog Devices Web site. Manuals may be
ordered by title or by product number located on the back cover of each
manual.
Data Sheets
All data sheets (preliminary and production) may be downloaded from the
Analog Devices Web site. Only production (final) data sheets (Rev. 0, A,
B, C, and so on) can be obtained from the Literature Center at
1-800-ANALOGD (1-800-262-5643); they also can be downloaded from
the Web site.
To have a data sheet faxed to you, call the Analog Devices Faxback System
at 1-800-446-6212. Follow the prompts and a list of data sheet code
numbers will be faxed to you. If the data sheet you want is not listed,
check for it on the Web site.
xx
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Preface
Notation Conventions
Text conventions used in this manual are identified and described as
follows.
Example
Description
Close command
(File menu)
Titles in reference sections indicate the location of an item within the
VisualDSP++ environment’s menu system (for example, the Close
command appears on the File menu).
{this | that}
Alternative required items in syntax descriptions appear within curly
brackets and separated by vertical bars; read the example as this or
that. One or the other is required.
[this | that]
Optional items in syntax descriptions appear within brackets and separated by vertical bars; read the example as an optional this or that.
[this,…]
Optional item lists in syntax descriptions appear within brackets
delimited by commas and terminated with an ellipse; read the example
as an optional comma-separated list of this.
.SECTION
Commands, directives, keywords, and feature names are in text with
letter gothic font.
filename
Non-keyword placeholders appear in text with italic style format.
L
Note: For correct operation, ...
A Note provides supplementary information on a related topic. In the
online version of this book, the word Note appears instead of this
symbol.
a
Caution: Incorrect device operation may result if ...
Caution: Device damage may result if ...
A Caution identifies conditions or inappropriate usage of the product
that could lead to undesirable results or product damage. In the online
version of this book, the word Caution appears instead of this symbol.
[
Warning: Injury to device users may result if ...
A Warning identifies conditions or inappropriate usage of the product
that could lead to conditions that are potentially hazardous for the
devices users. In the online version of this book, the word Warning
appears instead of this symbol.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
xxi
Notation Conventions
conventions, which apply only to specific chapters, may
L Additional
appear throughout this document.
xxii
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
1 USING EZ-KIT LITE
This chapter provides specific information to assist you with development
of programs for the ADSP-TS201S EZ-KIT Lite evaluation system.
The information appears in the following sections.
• “Package Contents” on page 1-2
Lists the items contained in your ADSP-TS201S EZ-KIT Lite
package.
• “Default Configuration” on page 1-3
Shows the default configuration of the ADSP-TS201S EZ-KIT
Lite.
• “Installation and Session Startup” on page 1-5
Instructs how to start a new or open an existing
ADSP-TS201SEZ-KIT Lite session using VisualDSP++.
• “Evaluation License Restrictions” on page 1-6
Describes the restrictions of the VisualDSP++ demo license
shipped with the EZ-KIT Lite.
• “Memory Map” on page 1-6
Describes the ADSP-TS201S EZ-KIT Lite board’s memory map.
• “SDRAM Interface” on page 1-7
Defines the register values needed to configure the external memory for SDRAM access.
• “Flash Memory” on page 1-8
Describes how to program and use the flash memory.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
1-1
Package Contents
• “Programmable FLAG Pins” on page 1-9
Describes the function and use of the programmable FLAG pins on
the EZ-KIT Lite evaluation system.
• “Interrupt Pins” on page 1-10
Describes the function and use of the interrupt pins on the
EZ-KIT Lite evaluation system.
• “Audio Interface” on page 1-11
Describes how to use and configure the audio interface.
• “Processor Link Ports” on page 1-11
Describes how to use and configure the link ports.
• “Example Programs” on page 1-12
Provides information about the example programs included in the
ADSP-TS201S EZ-KIT Lite evaluation system.
• “Flash Programmer Utility” on page 1-13
Provides information on the Flash Programmer utility included
with VisualDSP++.
For detailed information about programming the ADSP-TS201S TigerSHARC processor, see the documents referred to as “Related
Documents”.
Package Contents
Your ADSP-TS201S EZ-KIT Lite package contains the following items.
• ADSP-TS201S EZ-KIT Lite board
• VisualDSP++ Installation Quick Reference Card
• ADSP-TS201S EZ-KIT Lite Evaluation System Manual (this
document)
1-2
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Using EZ-KIT Lite
• CD containing:
D
D
D
D
VisualDSP++ software
ADSP-TS201 EZ-KIT Lite debug software
USB driver files
Example programs
• Universal 7.5V DC power supply
• USB 2.0 cable
• Registration card (please fill out and return)
If any item is missing, contact the vendor where you purchased your
EZ-KIT Lite or contact Analog Devices, Inc.
Default Configuration
The EZ-KIT Lite evaluation system contains ESD
(electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human
body and equipment and can discharge without
detection. Permanent damage may occur on devices
subjected to high-energy discharges. Proper ESD
precautions are recommended to avoid performance
degradation or loss of functionality. Store unused
EZ-KIT Lite boards in the protective shipping
package.
The ADSP-TS201S EZ-KIT Lite board is designed to run outside your
personal computer as a stand-alone unit. You do not have to open your
computer case.
When removing the EZ-KIT Lite board from the package, handle the
board carefully to avoid the discharge of static electricity, which may damage some components. Figure 1-1 shows the default jumper settings, DIP
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
1-3
Default Configuration
switches, connector locations, and LEDs used in installation. Confirm
that your board is set up in the default configuration) before using the
board.
Figure 1-1. EZ-KIT Lite Hardware Setup
1-4
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Using EZ-KIT Lite
Installation and Session Startup
correct operation, install the software and hardware in the
L For
order presented in the VisualDSP++ Installation Quick Reference
Card.
To set up an EZ-KIT Lite session in VisualDSP++:
1. Verify that the yellow USB monitor LED (LED9, located near the
USB connector) is lit. This signifies that the board is communicating properly with the host PC and is ready to run VisualDSP++.
2. From the Start menu, navigate to the VisualDSP++ environment
via the Programs menu.
If you are running VisualDSP++ for the first time, the New Session
dialog box appears on the screen (skip the rest of the procedure and
go to step 3).
If you have run VisualDSP++ previously, the last opened session
appears on the screen.
To switch to another session, via the Session List dialog box, hold
down the Ctrl key while starting VisualDSP++ (go to step 5).
3. In Debug Target, choose TigerSHARC Emulators/EZ-KIT Lites.
In Platform, select ADSP-TS201 EZ-KIT Lite via Debug Agent.
In Session name, type a new name or accept the default.
4. Click OK to return to the Session List.
5. Highlight the session and click Activate.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
1-5
Evaluation License Restrictions
Evaluation License Restrictions
The ADSP-TS201S EZ-KIT Lite installation is part of the VisualDSP++
installation. The EZ-KIT Lite is a licensed product that offers an unrestricted evaluation license for the first 90 days. Once the initial
unrestricted 90-day evaluation license expires:
• VisualDSP++ allows a connection to the ADSP-TS201S EZ-KIT
Lite via the USB Debug Agent interface only. Connections to simulators and emulation products are no longer allowed.
• The linker restricts a users program to 128K words of internal
memory for code space with no restrictions for data space.
Refer to the VisualDSP++ Installation Quick Reference Card for details.
Memory Map
The ADSP-TS201S processor has 24 Mbits of internal memory that can
be used for program storage or data storage. The configuration of internal
memory is detailed in the ADSP-TS201 TigerSHARC Processor Hardware
Reference.
The ADSP-TS201S EZ-KIT Lite board contains 512K x 8-bit of external
flash memory. The memory is divided into eight uniform 64 Kb sections.
This memory connects to the processor’s ~BMS and ~MSO pins. The flash
memory can be accessed in boot memory space as well as the external
memory bank zero space.
The board also contains 4M x 64-bit of external SDRAM memory. This
memory connects to the processor’s SDRAM interface.
1-6
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Using EZ-KIT Lite
Table 1-1. EZ-KIT Lite Evaluation Board Memory Map
Internal
Memory
External
Memory
Start Address
End Address
Content
0x0000 0000
0x 0001 FFFF
Internal Memory 0
0x0004 0000
0x0005 FFFF
Internal Memory 2
0x0008 0000
0x0009 FFFF
Internal Memory 4
0x000C 0000
0x000D FFFF
Internal Memory 6
0x0010 0000
0x0011 FFFF
Internal Memory 8
0x0014 0000
0x0015 FFFF
Internal Memory 10
0x001E 0000
0x001E 03FF
Internal Registers
0x001F 0000
0x001F 03FF
SOC Registers
0x0C00 0000
0x0FFF FFFF
Broadcast
0x1000 0000
0x13FF FFFF
Processor ID 0
0x1400 0000
0x17FF FFFF
Processor ID 1
0x3000 0000
0x37FF FFFF
External Memory Space Bank 0 (MS0);
MS0 includes flash memory which ends at
0x3007 FFFF.
0x3800 0000
0x39FF FFFF
External Memory Space Bank 1
0x4000 0000
0x43FF FFFF
External Memory Space (MSSD0);
MSSD0 includes SDRAM which ends at
0x407F FFFF.
0x8000 0000
0xFFFF FFFF
Host
SDRAM Interface
The SDRAM on the EZ-KIT Lite evaluation board is 32 MB. To access
SDRAM, the SYSCON and SDRCON registers must be configured properly.
The SDRAM default values are:
•
SYSCON
= 0x00189067
•
SDRCON
= 0x00005983
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
1-7
Flash Memory
For the supplied memory, the
follows:
SDRCON
register should be configured as
• SDRAM enable, CAS latency of two cycles
• pipe depth of zero, page boundary of 256 words
• refresh rate of every 3700 cycles, precharge to RAS of two cycles
• RAS to precharge of five cycles
• init sequence is MRS cycle follows refresh
and
registers define bus control configuration.
[ The
They can be written once only after reset and cannot be changed
SYSCON
SDRCON
during system operation.
In emulation space, the
and the
registers can be
L written
to as many times as needed. The USB debug monitor operSYSCON
SDRCON
ates in emulation space and allows “always writable” mode for these
registers.
Flash Memory
The AT49BV040 chip provides a total of 512K x 8-bits of external flash
memory, arranged into eight uniform 64 Kb memory blocks. The block
addresses are shown in Table 1-2.
Table 1-2. Flash Memory Map
1-8
Start Address
End Address
Content
0x3000 0000
0x3000 FFFF
Uniform Block 0
0x3001 0000
0x3001 FFFF
Uniform Block 1
0x3002 0000
0x3002 FFFF
Uniform Block 2
0x3003 0000
0x3003 FFFF
Uniform Block 3
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Using EZ-KIT Lite
Table 1-2. Flash Memory Map (Cont’d)
Start Address
End Address
Content
0x3004 0000
0x3004 FFFF
Uniform Block 4
0x3005 0000
0x3005 FFFF
Uniform Block 5
0x3006 0000
0x3006 FFFF
Uniform Block 6
0x3007 0000
0x3007 FFFF
Uniform Block 7
To program the flash memory with your boot code, you must first create a
loader file from your processor code. You set up the loader in VisualDSP++ depending on how you plan to boot the flash. For information
on creating a loader file, refer to VisualDSP++ online help and the
VisualDSP++ Loader Manual.
Next, the loader file must be programmed into the flash memory. This can
be done using the VisualDSP++ Flash Programmer utility (see “Flash Programmer Utility” on page 1-13).
Programmable FLAG Pins
Each ADSP-TS201S processor has four programmable FLAG pins. Two
FLAG pins from each processor (FLAG0 and FLAG1) allow interaction with
the running program through the use of a switch (SW6–9). The FLAG2 and
FLAG3 pins from each processor are connected to LEDs (LED3–6).
After the processor is reset, the programmable FLAGs are configured as
inputs. The direction of each programmable FLAG is configured in the
FLAGREG register. If the FLAG is configured for an output, the value to be
output is set in the FLAGREG register. If the FLAG is configured for an
input, the value on the FLAG pin is read from the SQSTAT register. Programmable FLAGs are summarized in Table 1-3. For more information
on how to configure the programmable FLAG pins, see the ADSP-TS201S
TigerSHARC Processor Hardware Reference.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
1-9
Interrupt Pins
Table 1-3. Programmable FLAG Pin Summary
FLAG
Connected To
Use
FLAG0_A
SW9
FLAG1_A
SW8
The FLAG0 and FLAG1 pins are connected to the push
buttons to supply feedback for program execution. For
instance, you can write user input to trigger a routine
when the push button is pressed.
FLAG0_B
SW6
FLAG1_B
SW7
FLAG2_A
LED4
FLAG3_A
LED6
FLAG2_B
LED5
FLAG3_B
LED3
The FLAG2 and FLAG3 pins are connected to the LEDs to
supply feedback during program execution.
Interrupt Pins
The ADSP-TS201S processor includes four interrupt pins (IRQ3–0) for
interaction with the running program. One external interrupt from each
processor is directly accessible through push button switches SW4 and SW5
on the EZ-KIT Lite board. Interrupts are summarized in Table 1-4. For
more information on configuring the interrupt pins, see the
ADSP-TS201S TigerSHARC Processor Hardware Reference.
Table 1-4. Interrupt Pin Summary
Interrupt
Connected To
Use
IRQ0_A
SW4
IRQ0_B
SW5
The IRQ0 interrupt is connected to push buttons to supply
feedback for program execution. For instance, you can write
your code to perform a different function when an interrupt is
detected.
1-10
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Using EZ-KIT Lite
Audio Interface
The audio interface of the EZ-KIT Lite board allows you to interface with
the board’s analog-to-digital converter (ADC) and digital-to-analog converter (DAC). The audio interface consists of two main ICs: AD1871 and
AD1854.
The AD1871 is a stereo audio ADC intended for digital audio applications requiring high-performance analog-to-digital conversion. The
AD1871 provides 97 dB THD+N and 107 dB dynamic range.
The AD1854 is a high-performance, single-chip stereo, audio DAC delivering 113 dB dynamic range and 112 dB SNR at a 48 kHz sample rate.
Because the ADSP-TS201S processor does not have any SPORTs, an Xilinx field-programmable gate array (FPGA) generates the audio interface
control signals between the processor and the audio circuit. Setting the
FLAG3 signal of processor A “high” enables the audio interface inside of the
FPGA. Once the audio interface has been enabled, the audio data can be
transferred to and from the processor by generating a DMAR0 cycle. The
audio data interfaces with the processor via the lowest 24 bits of the data
bus (D23–0).
Refer to the audio example program included in the EZ-KIT Lite’s installation directory for more information on how to use the audio interface.
Refer to “Audio (P1–2)” on page 2-20 for information about the audio
connectors.
Processor Link Ports
The link ports on the ADSP-TS201S processor use LVDS signaling to
communicate with each another. Each processor has a TX (transmit) port
and RX (receive) port for each of its link ports. The RJ-45 connectors, J4
and J5, are the TX and RX for processor A. Similarly, J6 and J7 are TX
and RX for processor B. The TX and RX of one processor’s link ports
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
1-11
Example Programs
should be respectively connected to RX and TX of another processor’s link
port. In this manner, the TX of one processor connects to the RX of the
other processor.
The link ports should be connected using a standard CAT 5E networking
cable. The length of the cable may affect the maximum frequency at which
the data can be transferred. Refer to the ADSP-TS201S Embedded Processor Datasheet for more information.
There are four link ports on each of the processors on the EZ-KIT Lite.
Link Port0 of both processors connects to the field-programmable gate
array (FPGA) at U20. Link Port1 of both processors connects to J3 of the
expansion interface. Link Port2 of each of the processors connects to each
other. Finally, Link Port3 connects to the RJ-45 connectors (J4–J7).
The L0CLKIN_P of both processor A and processor B are pulled up internally in the FPGA. Similarly, L0CLKININ_N of both processor A and
processor B are pulled down internally in the FPGA. Finally, R12 and R28
are not populated. All of this is done to avoid noise affecting the EZ-KIT
Lite operation.
To suppress noise from the expansion interface, a similar pull-up or
pull-down scheme has been used on Link Port1. The board’s R240 and
R239 are used to pull up L1CLKIN_P of both processors. Similarly, R242 and
R241 are used to pull down L1CLKIN_N of both processors. Finally, R14 and
R30 are not populated to avoid a short between 2.5V power and GND. The
link ports can be reactivated by removing the pull up and pull downs and
adding a 100 Ohm resistor on R14 and R30.
Example Programs
Example programs are provided with the ADSP-TS201S EZ-KIT Lite to
demonstrate various capabilities of the evaluation board. These programs
are installed with the EZ-KIT Lite software and can be found in the
1-12
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
Using EZ-KIT Lite
subdirectory of the VisualDSP++
installation directory. Please refer to the readme file provided with each
example program for more information.
\…\TS\EZ-KITs\ADSP-TS201\Examples
the examples, do not change these bits:
[ When running
or
(bits 8 or 9) in the
register.
BGEN
NMOD
SQCTL
The change can disable communications with the host.
Flash Programmer Utility
The ADSP-TS201S EZ-KIT Lite evaluation system includes a Flash Programmer utility. The utility allows you to program the flash memory on
the EZ-KIT Lite. The Flash Programmer is installed with VisualDSP++.
Once the utility is installed, it is accessible from the Tools pull-down
menu.
For more information on the Flash Programmer utility, refer to the online
Help.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
1-13
Flash Programmer Utility
1-14
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
2 EZ-KIT LITE HARDWARE
REFERENCE
This chapter describes the hardware design of the ADSP-TS201S EZ-KIT
Lite board. The following topics are covered.
• “System Architecture” on page 2-2
Describes the configuration of the ADSP-TS201S processor and
explains how the board components interface with the EZ-KIT
Lite.
• “Switch Settings” on page 2-5
Shows the location and describes the function of each configuration DIP switch.
• “Configuration Resistors” on page 2-10
Shows the location and describes the function of each configuration resistor.
• “LEDs and Push Buttons” on page 2-16
Shows the location and describes the function of the LEDs and
push buttons.
• “Connectors” on page 2-19
Shows the location of and gives the part number for all of the connectors on the board. In addition, provides the manufacturer and
part number information for the mating parts.
• “Specifications” on page 2-22
Describes the power connector.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
2-1
System Architecture
System Architecture
This section describes the processor’s configuration on the EZ-KIT Lite
board.
Figure 2-1. System Architecture
The EZ-KIT Lite has been designed to demonstrate the capabilities of the
ADSP-TS201S TigerSHARC processor. The processor is powered by
three separate regulators for the core, the internal DRAM, and the IO.
2-2
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
The processor core voltage is set to 1.15V. The internal DRAM is powered by an external 1.5V regulator. Finally, the external interface (IO)
operates at 2.5V but can accept up to 3.3V levels.
A 20 MHz SMT oscillator in conjunction with a clock generator set to 5x
supply the input clock to the processors. The speed at which the core
operates is determined by pull-up and pull-down resistors on both the
clock generator (U1) and the SCLKRAT[2:0] bit of each of the processors.
For more information, see “Clock Mode Settings” on page 2-12. By
default, the processor core runs at 500 MHz (20 MHz x 5 (U1) x 5
(sclkrat) =500 MHz).
External Port
The external port (EP) connects to a 512K x 8-bit flash memory. The
flash memory connects to the boot memory select pin (~BMS) and memory
bank zero pin (~MS0), allowing the memory to be used to boot the processor as well as to store information during normal operation. Refer to
“Flash Memory” on page 1-8 for information about the flash memory
locations.
The EP also connects to a 4M x 64-bit SDRAM. Refer to “SDRAM Interface” on page 1-7 for information on how to configure the SDRAM
registers.
Expansion Interface
The expansion interface consists of three connectors. The following table
shows the interfaces each connector provides. For the exact pinout of these
connectors, refer to Appendix B, “Schematics”.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
2-3
System Architecture
Table 2-1. Expansion Interface Connectors
Connector
Interfaces
J1
5V, GND, Address, Data
J2
2.5V, GND, SDRAM control signals, FLAGs, IRQs, TIMERs, Data
J3
GND, Reset, DMA, Memory Control, CLKOUT, Link Ports signals
When you use the expansion interface, limits to the current and to the
interface speed must be taken into consideration. The maximum current
limit depends on the capabilities of the regulator. Additional circuitry can
also add extra loading to signals, decreasing their maximum effective
speed.
Devices does not support and is not responsible for the
L Analog
effects of additional circuitry.
JTAG Emulation Port
The JTAG emulation port allows an emulator to access the processor’s
internal and external memory, as well as the special function registers
through a 14-pin header. See “JTAG (P4)” on page 2-21 for more information about the JTAG connector. To learn more about available
emulators, contact Analog Devices as described in “Product Information”
on page -xv.
For more information about designing JTAG into a custom board or to
learn more about the JTAG interface, please refer to EE-68 found at Analog Devices website.
2-4
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Switch Settings
This section describes the function of the DIP switches SW1, SW2, and
SW10. The location of the switches and their respective default settings are
shown in Figure 2-2.
Figure 2-2. Switch Locations
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
2-5
Switch Settings
Audio Amplification Selection (SW1)
The SW1 switch determines the amplification of right and left signals connected to the Line-IN connector P1. A non-powered electret microphone
can be used by simply varying the switch setting to the values shown in
Table 2-2. An amplification gain of a factor of 10 can be achieved by setting the switch into electret microphone use.
Table 2-2. Audio Amplification Selection (SW1)
Position 1
Position 2
Position 3
Position 4
Audio Amplification Mode
OFF1
OFF
ON
ON
No amplification
ON
ON
OFF
OFF
For electret microphone use
1
Default settings
Processor Mode Selections (SW2)
The SW2 switch configures several processor strap pins, which set the processor’s operating modes after power up or hard reset:
• “Processor Boot Strap Settings”
• “SYSCON/SDRCON Mode Settings”
• “Interrupt Enable Settings”
• “Link Port Width Settings”
The switch settings should not be changed while power is applied to the
board. Many of the strap pin settings may be re-configured in software
after the processor is powered up. Refer to the ADSP-TS201S Embedded
Processor Datasheet for more information.
2-6
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Processor Boot Strap Settings
Position 1 of the SW2 switch determines how the processor boots.
Table 2-3 shows the available boot mode settings. Refer to the
ADSP-TS201S Embedded Processor Datasheet for more information.
Table 2-3. Processor Boot Strap Settings (SW2 Position 1)
Position 1
Boot Mode
OFF1
EPROM Boot
ON
External Boot or Link Port Boot
1
Default settings
SYSCON/SDRCON Mode Settings
Position 2 of the SW2 switch determines how the processor handles writes
to the SYSCON and SDRCON registers. Table 2-4 shows the setting for the
type of write. Refer to the ADSP-TS201S Embedded Processor Datasheet for
more information.
Table 2-4. SYSCON/SRDCON Mode Settings (SW2 Position 2)
Position 2
SYSCON/SDRCON Mode
OFF1
SYSCON/SDRCON one-time writable
ON
SYSCON/SDRCON always writable
1
Default settings
space, the
and
registers can be written
L toIn asemulation
many times as needed. The USB debug monitor operates in
SYSCON
SDRCON
emulation space and allows “always writable” mode for these
registers.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
2-7
Switch Settings
Interrupt Enable Settings
Positions 3 and 5 of the SW2 switch determine how each of the processor
handles interrupts. Table 2-5 and Table 2-6 show the settings for the
interrupt modes. Refer to the ADSP-TS201S Embedded Processor Datasheet
for more information.
Table 2-5. Interrupt Enable Settings (SW2 Position 3)
Position 3
Interrupt Enable Mode for Processor A (U11)
OFF1
Disable interrupts, level-sensitive mode
ON
Enable interrupts, edge-sensitive mode
1
Default settings
Table 2-6. Interrupt Enable Settings (SW2 Position 5)
Position 5
Interrupt Enable Mode for Processor B (U12)
OFF1
Disable interrupts, level-sensitive mode
ON
Enable interrupts, edge-sensitive mode
1
Default settings
Link Port Width Settings
Positions 4 and 6 of the SW2 switch determine the link port data width.
Table 2-7 and Table 2-8 show the settings for the two types of link ports
data widths. Refer to the ADSP-TS201S Embedded Processor Datasheet for
more information.
Table 2-7. Link Port Width Settings (SW2 Position 4)
Position 4
Link Port Data Width for Processor A (U11)
OFF1
1-Bit link port data width
ON
4-Bit link port data width
1
2-8
Default settings
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Table 2-8. Link Port Width Settings (SW2 Position 6)
Position 6
Link Port Data Width for Processor B (U12)
OFF1
1-Bit link port data width
ON
4-Bit link port data width
1
Default settings
FLAGs and IRQs Switch Settings (SW10)
The SW10 switch determines the source of the FLAG and IRQ signals connected to each of the prospective processors. The source can be modified
so that the nets can be driven by either a push button switch or an external
source via the Expansion Header. Refer to “Programmable FLAG Push
Buttons (SW6–9)” and “Interrupt Push Buttons (SW4–5)” on page 2-18
for information on FLAGs, IRQs, and the associated push buttons.
Table 2-9 shows the setting for the interrupt modes.
Table 2-9. FLAGs and IRQs Switch Settings (SW10)
DSP A
DSP B
DSP A
DSP B
Use With
Position 1 Position 2
(FLAG0) (FLAG1)
Position 3 Position 4 Position 5 Position 6
(FLAG0) (FLAG1) (IRQ0)
(IRQ0)
OFF
OFF
OFF
OFF
OFF
OFF
External source
ON1
ON
ON
ON
ON
ON
On-board push button
switch
1
Default settings
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
2-9
Configuration Resistors
Configuration Resistors
This section describes the function of the two TigerSHARC processors’
configuration resistors. The location of the configuration resistors and
their respective default settings are shown in Figure 2-3.
Figure 2-3. Resistor Locations (Bottom View of Board)
Processor ID Settings
The two ADSP-TS201S processors on the EZ-KIT Lite are factory-configured to set the processor A to an ID value of zero and processor B to an ID
value of one. This means that in the cluster processor A is the master.
2-10
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Although it is not recommended, the ID value of each processor can be
varied by placing 500 Ohm resistors in the appropriate position.
Table 2-10 and Table 2-11 show the available ID settings.
EZ-KIT Lite must have a processor with the processor ID set
L The
must be present in order to allow inito zero ( ) on the board.
0
ID0
tialization of SDRAM external memory. Internal pull-up or
pull-downs on certain pins, such as memory interface and bus arbitration, are enabled only when the ID=(000). Refer to the
ADSP-TS201S TigerSHARC Processor Hardware Reference for more
information.
Table 2-10. Processor A ID Pins Configuration
R115 (Net: ID2_A)
R117 (Net: ID1_A)
R120 (Net: ID0_A)
ID[2:0] Value
Not populated1
Not populated
Not populated
0
Not populated
Not populated
Populated
1
Not populated
Populated
Not populated
2
Not populated
Populated
Populated
3
Populated
Not populated
Not populated
4
Populated
Not populated
Populated
5
Populated
Populated
Not populated
6
Populated
Populated
Populated
7
1
Default settings
Table 2-11. Processor B ID Pins Configuration
R122 (Net: ID2_B)
R123 (Net: ID1_B)
R124 (Net: ID0_B)
ID[2:0] Value
Not populated
Not populated
Not populated
0
Not populated1
Not populated
Populated
1
Not populated
Populated
Not populated
2
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
2-11
Configuration Resistors
Table 2-11. Processor B ID Pins Configuration (Cont’d)
R122 (Net: ID2_B)
R123 (Net: ID1_B)
R124 (Net: ID0_B)
ID[2:0] Value
Not populated
Populated
Populated
3
Populated
Not populated
Not populated
4
Populated
Not populated
Populated
5
Populated
Populated
Not populated
6
Populated
Populated
Populated
7
1
Default settings
Clock Mode Settings
The resistors on the clock generator (U1) and the resistors on the SCLKRAT
pins[2:0] of each of the processors determine the frequency at which the
two processor operate. The frequency supplied to CLKIN of the processor
may also be changed by replacing the 20 MHz oscillator (U18) shipped
with the board with a different oscillator. Ensure that the selected clock
mode and frequency do not exceed the minimum and maximum specifications of the ADSP-TS201S processor as noted in the datasheet.
The final frequency at which the processors operate is determined by the
following equation:
(Freq of U18)*(Mult Factor of U1)*(Mult Factor of SCLKRAT pins) =
Final Oper Freq
The default frequency factory setting is 20
MHz*5*5 = 500 MHz.
Table 2-12 through Table 2-14 show the resistor settings for the clock
generator and the SCLKRAT pins. For more information on the clock
modes, see the ADSP-TS201S Embedded Processor Datasheet.
Processor A and Processor B SCLK ratios must be of the same
L The
value.
2-12
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Table 2-12. Clock Generator (U1) Settings
R215
R224
R3
R223
Multiplication Factor
Not populated
Populated
Not populated
Populated
2
Not populated
Populated
Populated
Populated
3
Not populated
Populated
Populated
Not populated
4
Populated
Populated
Not populated
Populated
4.25
Populated1
Populated
Populated
Populated
5
Populated
Populated
Populated
Not populated
6
Populated
Not populated
Not populated
Populated
6.25
Populated
Not populated
Populated
Populated
8
Populated
Not populated
Populated
Not populated
Reserved (Test mode)
1
Default settings
Table 2-13. SCLK Ratio Settings for Processor A
R128 (SCLKRAT2)
R127 (SCLKRAT1)
R133 (SCLKRAT0)
Multiplication Factor
Not populated
Not populated
Not populated
4
Not populated1
Not populated
Populated
5
Not populated
Populated
Not populated
6
Not populated
Populated
Populated
7
Populated
Not populated
Not populated
8
Populated
Not populated
Populated
10
Populated
Populated
Not populated
12
Populated
Populated
Populated
Reserved
1
Default settings
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
2-13
Configuration Resistors
Table 2-14. SCLK Ratio Settings for Processor B
R126 (SCLKRAT2)
R125 (SCLKRAT1)
R45 (SCLKRAT0)
Multiplication Factor
Not populated
Not populated
Not populated
4
Not populated1
Not populated
Populated
5
Not populated
Populated
Not populated
6
Not populated
Populated
Populated
7
Populated
Not populated
Not populated
8
Populated
Not populated
Populated
10
Populated
Populated
Not populated
12
Populated
Populated
Populated
Reserved
1
Default settings
Control Impedance Selection
The CONTROLIMP1 and CONTROLIMP0 resistors set the impedance and driver
mode of the processors, as described in Table 2-15. The resistors are used
together with the drive strength pins to determine the actual impedance
and drive strength. Refer to the ADSP-TS201S Embedded Processor
Datasheet for more information.
Table 2-15. Control Impedance Selection
R143 (CONTROLIMP1)
R131 (CONTROLIMP0)
Driver Mode
Populated1
Not populated
Normal
Populated
Populated
Pulse mode
Not populated
Not populated
A/D mode
Not populated
Populated
Pulse mode, A/D mode
1
2-14
Default settings
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Drive Strength Selection
The DS[2:0] pins of each processor determine the digital drive strength, as
described in Table 2-16 and Table 2-17. Refer to the ADSP-TS201S
Embedded Processor Datasheet for more information.
Table 2-16. Drive Strength Setting for Processor A
R136 (DS2)
R132 (DS1)
R135 (DS0)
Drive Strength
Output
Impedance
Populated
Not populated
Populated
11.1%
26Ω
Populated
Not populated
Not populated
23.8%
32Ω
Populated
Populated
Populated
36.5%
40Ω
Populated
Populated
Not populated
49.2%
50Ω
Not populated
Not populated
Populated
61.9%
62Ω
Not populated
Not populated
74.6%
70Ω
Not populated
Populated
Populated
87.3%
96Ω
Not populated
Populated
Not populated
100%
120Ω
Not
1
populated1
Default settings
Table 2-17. Drive Strength Setting for Processor B
R138 (DS2)
R139 (DS1)
R137 (DS0)
Drive Strength
Output
Impedance
Populated
Not populated
Populated
11.1%
26Ω
Populated
Not populated
Not populated
23.8%
32Ω
Populated
Populated
Populated
36.5%
40Ω
Populated
Populated
Not populated
49.2%
52Ω
Not populated
Not populated
Populated
61.9%
62Ω
Not populated1
Not populated
Not populated
74.6%
70Ω
Not populated
Populated
Populated
87.3%
96Ω
Not populated
Populated
Not populated
100%
120Ω
1
Default settings
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
2-15
LEDs and Push Buttons
LEDs and Push Buttons
This section describes the function of the LEDs and push buttons.
Figure 2-4 shows the locations of the LEDs and push buttons.
Figure 2-4. LED and Push Button Locations
Power LED (LED1)
The green LED, LED1, indicates that power is being properly supplied to
the board.
2-16
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Reset LEDs (LED2 and LED8)
When LED2 is lit, the USB interface is being reset. This interface is only
reset when it is not configured. Once it has been configured, you must
remove power to reset the USB interface.
When LED8 is lit, it indicates that the master reset of all the major ICs is
active.
FLAG LEDs (LED3–6)
The FLAG LEDs connect to the processor’s FLAG pins (FLAG2 and
FLAG3). These LEDs are active “high” and are lit by an output of “1” from
the processor. Refer to “Programmable FLAG Pins” on page 1-9 for information on how to utilize the FLAGs when programming the processor.
Table 2-18 shows the FLAG signals and the corresponding LEDs.
Table 2-18. FLAG LEDs
FLAG Pin
LED Reference Designator
FLAG Pin
LED Reference Designator
FLAG2_A
LED4
FLAG2_B
LED5
FLAG3_A
LED6
FLAG3_B
LED3
USB Monitor LED (LED9)
The USB monitor LED indicates that USB communication has been initialized successfully, allowing you to connect to the processor using
VisualDSP++. If LED9 is not lit, try resetting the board and/or reinstalling
the USB driver (see “Installing EZ-KIT Lite USB Driver” on page 1-7).
VisualDSP++ is actively communicating with the EZ-KIT
L When
Lite target board, the LED can flicker, indicating communications
handshake.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
2-17
LEDs and Push Buttons
Programmable FLAG Push Buttons (SW6–9)
Four push buttons are provided for general-purpose user input. The SW6,
SW7, SW8, and SW9 push buttons connect to the processor’s programmable
FLAG pins. The push buttons are active “high” and when pressed, send a
high (1) to the processor. Refer to “Programmable FLAG Pins” on
page 1-9 for more information on how to use the FLAGs. Table 2-19
shows the FLAG signals and the corresponding switches.
Table 2-19. FLAG Push Buttons
FLAG Pin
Push Button Reference Designator
FLAG0_A
SW9
FLAG1_A
SW8
FLAG0_B
SW6
FLAG1_B
SW7
Interrupt Push Buttons (SW4–5)
Two push buttons, SW4 and SW5, are provided for user interrupts. The
push buttons connect to the processor’s interrupt pins. The push buttons
are active “low” and, when pressed, send a low (0) to the processor. Refer
to “Interrupt Pins” on page 1-10 for more information on how to use the
interrupts. Table 2-20 shows the interrupt signals and the corresponding
switches.
Table 2-20. Interrupt Push Buttons
Interrupt Pin
Push Button Reference Designator
IRQ0_A
SW4
IRQ0_B
SW5
2-18
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Reset Push Button (SW3)
The RESET push button, SW3, resets all the ICs on the board, except the
USB interface after it has been configured.
Connectors
This section describes the connector functionality and provides information about mating connectors. The locations of the connectors are shown
in Figure 2-5.
Figure 2-5. Connector Locations
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
2-19
Connectors
Audio (P1–2)
There are two 3.5 mm stereo audio jacks.
Part Description
Manufacturer
Part Number
3.5 mm stereo jack
Shogyo
SJ-0359AM-5
Mating Connector
3.5 mm stereo plug to 3.5 mm ste- Radio Shack
reo cable
L12-2397A
Power (P3)
The power connector provides all the power necessary to operate the
EZ-KIT Lite board.
Part Description
Manufacturer
Part Number
2.5 mm Power Jack (P3)
SWITCHCRAFT
RAPC712
Digi-Key
SC1152-ND
Mating Power Supply (shipped with the EZ-KIT Lite)
7.5V Power Supply
2-20
GlobTek
TR9CC2000LCP-Y
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
JTAG (P4)
The JTAG header is the connecting point for a JTAG in-circuit emulator
pod. For more information about designing JTAG into a custom board or
to learn more about the JTAG interface, please refer to EE-68 found at
Analog Devices website.
3 is missing to provide keying. Pin 3 in the mating connector
L Pin
should have a plug. When an emulator is connected to the JTAG
header, the USB debug interface is disabled.
using an emulator with the EZ-KIT Lite board, follow the
[ When
connection instructions provided with the emulator.
USB (P5)
The USB connector is a standard Type B USB receptacle.
Part Description
Manufacturer
Part Number
Type B USB receptacle
Mill-Max
897-30-004-90-000
Digi-Key
ED90003-ND
Mating Connector
USB cable (provided with the kit)
Assman
AK672/2-3
Digi-Key
AE1302-ND
Expansion Interface (J1–3)
Three board-to-board connectors provide signals for most of the processor’s peripheral interfaces. The connectors are located at the bottom of the
board. For more information about the expansion interface, see “Expansion Interface” on page 2-3.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
2-21
Specifications
Part Description
Manufacturer
Part Number
90 Position 0.05" Spacing
Samtec
SFC-145-T2-F-D-A
Mating Connector
90 Position 0.05” Spacing
(Through Hole)
Samtec
TFM-145-x1 Series
90 Position 0.05” Spacing
(Surface Mount)
Samtec
TFM-145-x2 Series
90 Position 0.05” Spacing
(Low Cost)
Samtec
TFC-145 Series
Link Ports (J4–7)
There are four RJ-45 connectors on the EZ-KIT Lite. Two connectors are
used for Link Port 3 of Processor A and two are used for Link Port 3 of
Processor B.
Part Description
Manufacturer
Part Number
8-Pin RJ-45 Connector
TYCO
1-1609214-1
Mating Cables
BLK CAT 5E Cable (1 Foot)
E-FILLIATE
119-5136
Gray CAT 5E Cable (1 Meter)
Digi-Key
AE1233-ND
Specifications
This section provides the requirements for powering the board.
Power Supply
The power connector supplies DC power to the EZ-KIT Lite board.
Table 2-21 shows the power connector pinout.
2-22
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Table 2-21. Power Connectors
Terminal
Connection
Center pin
+7.5 VDC@2amps
Outer Ring
GND
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
2-23
Specifications
2-24
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
A BILL OF MATERIALS
The bill of materials corresponds to the board schematics on page B-1.
Please check the latest schematics on the Analog Devices website,
http://www.analog.com/Processors/Processors/DevelopmentTools/tec
hnicalLibrary/manuals/DevToolsIndex.html#Evaluation%20Kit%20Manuals.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
A-1
A-2
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
1
2
1
1
3
1
2
1
1
1
2
1
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
#
1
Ref.
U28
Reference Designator
512K-X-8-BIT-FLASH-3.3V
3.3V 1:5 CLK DRIVER
3.3V CLK GENERATOR
4MX32-SDRAM-166MHZ
N-CHANNEL-MOSFET
ADJ-7A-SWITCH-REG-CNTRLR
P-CHANNEL-MOSFET
ADJUSTABLE-3A-SWITCH-REG
12.288MHz SMT OSCILLATOR
SINGLE-2-INPUT-NAND
ADJ 200MA REGULATOR
3.3V-OCTAL-BUFFER
U10
U37
U1
U24–25
U36
VR5
U35
VR1–2
U2
U15, U31, U38
VR4
U13
HEX-INVER-SCHMITT-TRIGGER U14, U30
3.3V-OCTAL-BUFFER
Description
LT1765ES8
SG-8002CA-PCC-ND
SN74AHC1G00DBVR
ADP3331ART
IDT74FCT3244APY
74LVC14AD
SN74LVT244BDW
Part Number
ATMEL
IDT
IDT
MICRON
VISHAY
LINEAR TECH
AT49BV040-90JC
IDT49FCT3805AQ
IDT5V928PGI
MT48LC4M32B2TG–7
SI9804DY
LTC1773EMS
FAIRCHILD SEMI FDS6375
LINEAR TECH
DIGIKEY
TI
ANALOG
DEVICES
IDT
TI
TI
Manufacturer
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
1
1
1
4
1
1
1
2
4
17
18
19
20
21
22
23
24
25
1
4
16
26
2
#
15
Ref.
VR6
U9
U3
U6–8, U26
VR3
U5
C5
C22, C24,
C56–57
C47–48
Reference Designator
PWR 2.5MM_JACK
RUBBER FEET BLACK
P3
MH1–2, MH4–5
TigerSHARC ADSP-TS201S Proces- U11–12
sor
ADJ 500MA REGULATOR
STERO-DAC
STERO-DAC
DUAL AUDIO OP AMP
3.3V 1.5A REGULATOR
VOLTAGE-SUPERVISOR
0.1uF 50V 20%
2200pF 50V 5%
1000pF 50V 5%
Description
SWITCH-CRAFT
MOUSER
ANALOG
DEVICES
ANALOG
DEVICES
ANALOG
DEVICES
ANALOG
DEVICES
NATIONAL
ANALOG
DEVICES
ANALOG
DEVICES
AVX
AVX
AVX
Manufacturer
SC1152-ND12
517-SJ-5018BK
ADSP-TS201SABP-ENG
ADP3336ARM-REEL
AD1871YRS
AD1854JRS
LMV722M
ADP3339AKC-3.3-RL
ADM708SAR
12065E104MAT2A
12065A222JAT050
12065A102JAT2A
Part Number
Bill Of Materials
A-3
A-4
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
2
4
1
12 0.00 1/8W 5%
4
2
4
15 0.1uF 50V 10% CERM
4
2
29
30
31
32
33
34
35
36
37
38
10uF 16V 10% TANT
0.001uF 50V 5% NPO
0.01uF 100V 10% CERM
330pF 50V 5% NPO
AMBER-SMT
4 PIN SMT SWITCH
RJ45 8PIN RIGHT ANGLE
DIP6
0.05 45X2 SMT
3
28
SPST-MOMENTARY 6MM
Description
7
#
27
Ref.
DIGIKEY
TYCO
DIGIKEY
SAMTEC
PANASONIC
Manufacturer
AVX
AVX
PANASONIC
CT22–23
C10–11, C13–14
SPRAGUE
AVX
AVX
C4, C51, C63, C66,
C142–143, C145–149,
C247–249
C1–2, C7–8
C25, C30
LED3–6,
R76, R91, R104, R107, YAGEO
R109–110, R113,
R118, R178–179,
R189, R202
SW1
J4–7
SW2, SW10
J1–3
SW3–9
Reference Designator
293D106X9016C2T
08055A102JAT2A
08055C104KAT
08051C103KAT2A
08055A331JAT
LN1461C-TR
0.0ECT-ND
CKN1363-ND
1-1609214-1
CKN1364-ND
SFC-145-T2-F-D-A
EVQ-PAD04M
Part Number
1
1
6
2
12 100pF 100V 5% NPO
3
1
41
42
43
44
45
46
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
47
3A SCHOT_RECT
10uF 16V 10% TANT
49.9K 1/8W 1%
2.00K 1/8W 1%
10.5K 1/8W 1%
10.7K 1/8W 1%
4.7K 100MW 5%
4
40
Description
39 10K 100MW 5%
#
39
Ref.
Manufacturer
AVX
DALE
BECKMAN
DALE
AVX
D2
CT1–3
MICRO-SEMI
AVX
C3, C6, C9, C12, C15, AVX
C20–21, C23, C27,
C31, C52–53
R60, R63
R37–38,R88, R121,
R156–157
R227
R217
R5, R93, R186, R188
R3, R26,
AVX
R39–42, R77,
R86–87, R89,
R92, R94, R100,
R102, R108, R112,
R116, R153, R158–
160,
R182–183, R187,
R194, R195, R203,
R213–215, R223–224,
R235–236, R238–242
Reference Designator
HSM350J
TAJB106K016R
12061A101JAT2A
CR32-4992F-T
CR32-2001F-T
BCR1/81052FT
CRCW1206-1072FRT1
CR21-4701F-T
CR21-103J-T
Part Number
Bill Of Materials
A-5
A-6
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
4
2
8
2
4
4
1
1
1
2
52
53
54
55
56
57
58
60
61
62
1
50
5
3
49
51
6
#
48
Ref.
680PF 50V 1% NPO
698K 1/8W 1%
340K 1/8W 1%
47PF 100V 10%
1UF 16V 10% X7R
120PF 50V 5% NPO
11.0K 1/8W 1%
5.76K 1/8W 1%
750K 1/8W 1%
237 1/8W 1%
600 100MHZ 500MA FERRITE
BEAD
2A SILICON RECTIFIER
220pf 50V 10% NPO
100 100MW 5%
Description
C26, C29
R201
R192
C64
C54, C70–72
C16–19
R61–62
R44,R53–57, R150,
R152
R47, R49
R46, R48, R50, R52
FER1–3, FER6–7
D1
C28, C32, C62
R78, R85, R95, R99,
R101, R103
Reference Designator
AVX
DALE
DALE
KEMET
MURATA
PHILLIPS
DALE
PHYCOMP
DALE-VISHAY
AVX
DIGIKEY
GENERALSEMI
AVX
AVX
Manufacturer
08055A681FAT2A
CRCW0805-6983FT
CRCW0805-3403FT
C1206C470K1GACTU
GRM40X7R105K016AL
1206CG121J9B200
CRCW12061102FRT1
9C12063A5761FKHFT
CRCW12067503FRT1
CR32-2370F-T
240-1019-1-ND
S2A
12061A221JAT2A
CR21-101J-T
Part Number
2
2
2
2
2
1
18 0.00 100MW 5%
1
1
2
65
66
67
68
69
70
71
72
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
73
74
10UH X 10%
35.7K 1/10W 1%
190 100MHZ 5A FERRITE BEAD
332K 1/10W 1%
2A SL22 SCHOTTKY
68UF 25V 20% ELEC
10UF 16V 20% ELEC
1.65K 1/8W 1%
3.32K 1/8W 1%
5.49K 1/8W 1%
4
64
2.74K 1/8W 1%
Description
2
#
63
Ref.
PHILIPS
GENERAL
SEMI
PANASONIC
DIG01
PANASONIC
DALE
PANASONIC
DALE
Manufacturer
L1–2
R220
FER5
PANASONIC
YAGEO
MURATA
R1–2, R7–10, R130,
VISHAY
R155, R161, R181,
R184–185, R208–212,
R226
R234
D4, D5
CT6–7
CT4–5
R67, R72
R66, R71
R64–65, R69–70
R68, R73
Reference Designator
ELJ-FC100KF
9C08052A3572FKHFT
DLW5BSN191SQ2
CRCW0805 0.0 RT1
9C08052A3323FKRT/R
SL22
EEV-FC1E680P
PCE3062TR-ND
ERJ-8ENF1651V
CRCW12063321FRT1
ERJ-8ENF5491V
CRCW12062741FRT1
Part Number
Bill Of Materials
A-7
A-8
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
6
3
53 0.1UF 10V 10%
78
79
80
4.7UF 6.3V 10%
1000PF 10V 20%
4
77
1UF 10V 10%
0.47UF 16V 10%
2
76
Description
11 22 1/10W 5%
#
75
Ref.
AVX
YAGEO
AVX
AVX
VISHAY/DALE
Manufacturer
C69, C75,C79–84,
AVX
C155–162,
C108,C110–115,C118,
C120–122, C141,
C144,C165–166,
C182,C184–185,
C187,C197–201,
C221–225,
C228–231,
C237–239, C241
C61, C65, C76
C38–40,
C42–43, C45
C37, C41, C44, C46
C73–74
R4, R6, R11, R24,
R32,
R34–35,R129,
R205–207
Reference Designator
0402ZD104KAT2A
08056D475KAT2A
1206CG229C9B200
0805ZC105KAT2A
0805YC474KAT2A
CRCW0805220JRT1
Part Number
16 499 1/10W 1%
1
2
1
1
1
1
2
1
83
84
85
86
87
88
89
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
90
91
3A MBRS340T3
SUPERMINI SCHOTTKY
80.6K 1/10W 1%
30K 1/10W 5%
2.55K 1/10W 1%
0.01 1.5W 5%
1.5UH 45MOHM 20%
1UH 5.9MOHMS 30%
4.7K 31MW 5%
2
82
Description
46 0.01UF 16V 10%
#
81
Ref.
Manufacturer
CTS
D3
D6–7
R221
R218
R105
R219
L4–5
L6
ON SEMI
CENTRAL
SEMI
VISHAY
VISHAY
VISHAY
IRC
TYCO
DIGIKEY
R23, R25,R45,
VISHAY
R51,R111, R114,R124,
R133,R140–146,R154
RN3–4
C68,C85–90,C92–99, AVX
C103–104, 107, C109,
C129–140,C167,
C181,C183,C202–205,
C216,C218–220,C227,
C232,C240, C242
Reference Designator
MBRS340T3
CMDSH-3
CRCW08058062FRT1
CRCW0805303JRT1
CRCW08052251FRT1
LR2512-01-R010-F
DS6630-1R5M
919AS-1RON=P3-ND
CRCW08054990FRT1
746X101472J
0402YC103KAT2A
Part Number
Bill Of Materials
A-9
A-10
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
2
1
2
44 1000PF 50V 5% CERM
1
2
1
22 100 1/10W 1%
3
94
95
96
97
98
99
100
101
102
100K 1/8W 5%
210K 1/4W 1%
57.6K 1/4W 1%
64.9K 1/10W 1%
2.2uF 10V 10% CERM
150uF 10V 10% TANT-LOW-ESR
100uF 10V 10% TANT-LOW-ESR
0.18uF 25V 10% CERM
2
93
680uF 6.3V 10% TANT-LOW-ESR
Description
1
#
92
Ref.
R58–59, R228
R13, R15–22, R27,
R29, R31, R33, R36,
R43, R83, R96,R98,
R230–233
R190
R147–148
R191
C67, C168–180,
C186,C188–196,
C206–215, C217,
C226,C233–236,
C243–246
C59–60
CT14
CT16–17
C55, C58
CT15
Reference Designator
AVX
VISHAY
VISHAY
VISHAY
VISHAY
AVX
AVX
KEMET
AVX
AVX
AVX
Manufacturer
CR1206-1003FRT1
CRCW08051000FRT1
CRCW08052103FRT1
CRCW12065762FRT1
CRCW08056492FRT1
04025C102JAT2A
0805ZD225KAT2A
T494D157K010AS
TPSC107K010R0075
08053C184KAT2A
TPSE687K006R0045
Part Number
7
1
2
1
2
1
2
6
2
1
1
2
5
104
105
106
107
108
109
110
111
112
113
114
115
#
103
Ref.
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
10uF 6.3V 10% TANT
3.5MM STEREO_JACK
2.5A RESETABLE
IDC 7X2
QUICKSWITCH-257
1uF 25V 20% TANT
604 1/8W 1%
GREEN-SMT GULL-WING
RED-SMT GULL-WING
13.0K 1/8W 1%
10.0K 1/8W 1%
20MHZ 1/2
270 1/8W 5%
Description
C91, C100, C154,
C163, C164
P1–2
F1
P4
U22–23
CT8–13
R74–75
LED1
LED2,LED8
R225
R216, R222
U18
R79–82, R84, R90,
R151
Reference Designator
AVX
A/D ELEC.
RAYCHEM
BERG
ANALOG
DEVICES
PANASONIC
DALE
PANASONIC
PANASONIC
PANASONIC
DALE
ECLIPTEK
AVX
Manufacturer
08056D106KAT2A
ST-323-5
SMD250-2
54102-T08-07
ADG774ABRQ
ECS-T1EY105R
CRCW12066040FRT1
LN1361C
LN1261C
ERJ-8ENF1302V
CRCW1206-1002FRT1
EC1100HS-20.000M
CR32-271J-T
Part Number
Bill Of Materials
A-11
A-12
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
A
B
C
D
1
1
2
2
ADSP-TS201S EZ-KIT Lite
3
3
ANALOG
DEVICES
4
Approvals
Date
Title
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-TS201S EZ-KIT LITE - TITLE
Drawn
Checked
Engineering
A
B
C
Size
Board No.
C
Date
Rev
A0178-2002
1.1C
Sheet
3-1-2004_10:59
D
1
of
15
A
B
C
DSP A
U11
A[0:31]
1
A0
H24
A1
H23
A2
H22
A3
H21
A4
G24
A5
G23
A6
G22
A7
G21
A8
F24
A9
F23
A10
E24
A11
E23
A12
F22
A13
F21
A14
E22
A15
E21
A16
D24
A17
D23
A18
B24
A19
D22
A20
C21
A21
2
ADDR1
DATA1
ADDR2
DATA2
ADDR3
DATA3
ADDR4
DATA4
ADDR5
DATA5
ADDR6
DATA6
ADDR7
DATA7
ADDR8
DATA8
ADDR9
DATA9
ADDR10
DATA10
ADDR11
DATA11
ADDR12
DATA12
A21
A23
B21
A24
C20
A25
D20
A26
C19
A27
D19
A28
A20
A29
B20
A30
A19
DATA13
ADDR14
DATA14
ADDR15
DATA15
ADDR16
DATA16
ADDR18
DATA17
DATA18
ADDR19
DATA19
ADDR20
DATA20
ADDR21
DATA21
A23
A22
A31
DATA0
ADDR17
ADDR22
ADDR23
DATA22
DATA23
ADDR24
DATA24
ADDR25
DATA25
ADDR26
DATA26
ADDR27
DATA27
ADDR28
DATA28
ADDR29
DATA29
ADDR30
DATA30
ADDR31
DATA31
B19
DATA32
DATA33
AA15
NC1
AB4
NC2
R21
NC3
DATA34
DATA35
DATA36
DATA37
DATA38
DATA39
DATA40
DATA41
Y1
EMU
TCK_DSP_A
3
TCK
W3
TDI
TDI
W4
TDO_A
TDO
AC4
TMS
PLACE CLOSE TO DSP PINS
EMU
Y2
AD4
TRST
TMS
TRST
DATA42
DATA43
DATA44
DATA45
DATA46
DATA47
DATA48
SCLK_DSP_A
DATA49
R2
0.00
805
DATA50
R7
0.00
805
DATA51
DATA52
P1
R2
C33
10PF
805
DNP
SCLK1
DATA53
SCLK2
DATA54
DATA55
C34
10PF
805
DNP
DATA56
DATA57
DATA58
T1
DSP_RESET
RST_IN
DATA59
DATA60
U2
R1
0.00
805
DATA61
DATA62
V3
4
RST_OUT
POR_IN
LABEL "DSP A" near this DSP
D[0:63]
ADDR0
ADDR13
D
DATA63
D17
D0
A17
D1
B17
D2
C16
D3
D16
D4
A16
D5
B16
D6
C15
D7
D15
D8
A15
D9
B15
D10
A14
D11
KEEP THESE NETS THE SAME LENGTH
1
PLACE CLOSE TO IDT5v929 PINS
R4
22
805
SCLK_DSP_A
U11
3.3V
B14
D12
C14
D13
RD
D14
D14
WRL
A13
D15
WRH
B13
D16
ACK
C12
D17
BRST
D12
D18
C18
RD
A18
WRL
B18
WRH
C17
ACK
D18
BRST
AC7
CPA
CPA
SCLK_DSP_B
AD7
DPA
DPA
AA7
DMAR0
AB7
DMAR1
A12
D19
B12
D20
MS1
D21
MSH
D11
D22
BMS
A11
D23
C11
B11
D24
A10
D25
B10
D26
C10
D27
D10
D28
A9
D29
B9
D30
C9
BR[0:7]
D32
A8
D33
BR1
L3
BR2
L4
BR3
M1
D35
D8
D36
A7
D37
B7
D38
C7
D39
M4
R4
BR4
AD8
AA8
AB8
HBG
D41
CAS
B6
D42
A5
D43
J1
J2
K3
LDQM
K4
HDQM
D44
D45
D6
D46
SDA10
C5
D47
SDCKE
D5
D48
SDWE
A4
D49
B4
D50
K1
K2
L1
MSSD0
MSSD[0:3]
MSSD1
D51
MSSD2
D3
D54
D1
D55
D2
D56
E3
D57
E4
D58
F3
D59
F4
D60
E1
D61
E2
D62
F1
D63
ID2
R224
10K
805
N1
R223
10K
805
2
X1_I
3
X2_O
ID0_A
Q2
Q3
Q4
Q6
Q7
6
SDRAM_CLK0
7
10
R32
22
805
11
14
SDRAM_CLK1
15
R34
22
805
18
19
CLKOUT_EXP
R35
22
805
AD2
GND1
R26
10K
805
ID1_A
U3
ID2_A
SCLKRAT0
SCLKRAT1
H4
1
OE
SCLKRAT0_A
M2
SCLKRAT1_A
T2
24
S0
23
S1
R11
22
805
U18
GND3
GND4
5
OUT
1
REF
20MHZ
OSC001
SCLKRAT2_A
GND2
GND5
TP1
8
2
TP6
9
16
17
21
IDT5V928PGI
TSSOP24
BM
BOFF
BUSLOCK
W1
CONTROLIMP0
V4
CONTROLIMP1
HBR
CONTROLIMP0
CONTROLIMP1
HBG
T4
DS0
U4
DS1
V2
DS2
MSSD3
DS0_A
DS1_A
PLACE CLOSE TO EACH OTHER
DS2_A
RAS
CAS
LDQM
W2
ENEDREG
TMR0E
ENEDREG_A
Y3
TMR0E_A
3
HDQM
FLAG0
C6
D53
BR7
Q1
Q5
3.3V
BR5
BR6
Q0
22
OE
ID1
BR7
HBR
D40
B1
IOEN
R24
22
805
PLACE TEST POINTS NEXT TO EACH OTHER
A6
D52
AA6
IOEN
BR3
BR6
BUSLOCK
D7
C4
IORD
ID0
T3
BOFF
IOWR
AD5
IORD
BR2
M3
P4
AC5
R3
10K
805
BR1
BR5
AC8
DMAR3_A
BR0
BR4
BM_A
RAS
A2
DMAR3
SCLKRAT2
D34
C8
B5
L2
D31
D9
B8
BR0
R215
10K
805
DMAR2_A
AD6
IOWR
4
VDD
5
VDDQ1
12
VDDQ2
13
VDDQ3
20
VDDQ4
DMAR1_A
AC6
MS0
U1
DMAR0
DMAR2
G3
MS0
F2
MS1
H2
MSH
G4
BMS
R6
22
805
SDA10
FLAG1
SDCKE
FLAG2
SDWE
FLAG3
U1
MSSD0
G1
MSSD1
V1
MSSD2
H3
MSSD3
IRQ0
IRQ1
IRQ2
IRQ3
AC1
FLAG0_A
AA2
FLAG1_A
AA1
FLAG2_A
Y4
FLAG3_A
AA5
IRQ0_A
AB6
IRQ1_A
AB5
IRQ2_A
AA3
IRQ3_A
FLAG[3:0]_A
3.3V
3.3V
IRQ[3:0]_A
C108
0.1UF
402
C107
0.01UF
402
C103
0.01UF
402
C104
0.01UF
402
C141
0.1UF
402
ADSP-TS201S
BP576
IDT5V928PGI
ANALOG
DEVICES
ADSP-TS201S
BP576
Approvals
Date
Title
20MHz
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-TS201S EZ-KIT LITE - DSP A
Drawn
Checked
Engineering
A
B
C
Size
Board No.
C
Date
Rev
A0178-2002
1.1C
Sheet
3-1-2004_10:59
D
2
of
15
A
B
C
D
DSP B
U12
A[0:31]
A0
A1
A2
1
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
2
A23
A24
A25
A26
A27
A28
A29
A30
A31
H24
ADDR0
H23
ADDR1
H22
ADDR2
H21
ADDR3
G24
ADDR4
G23
ADDR5
G22
ADDR6
G21
ADDR7
F24
ADDR8
F23
ADDR9
E24
ADDR10
E23
ADDR11
F22
ADDR12
F21
ADDR13
E22
ADDR14
E21
ADDR15
D24
ADDR16
D23
ADDR17
B24
ADDR18
D22
ADDR19
C21
ADDR20
A23
ADDR21
A21
ADDR22
B21
ADDR23
C20
ADDR24
D20
ADDR25
C19
ADDR26
D19
ADDR27
A20
ADDR28
B20
ADDR29
A19
ADDR30
B19
ADDR31
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DATA16
DATA17
DATA18
DATA19
DATA20
DATA21
DATA22
DATA23
DATA24
DATA25
DATA26
DATA27
DATA28
DATA29
DATA30
DATA31
DATA32
DATA33
AA15
NC1
AB4
NC2
R21
NC3
DATA34
DATA35
DATA36
DATA37
DATA38
DATA39
DATA40
DATA41
Y1
EMU
3
TCK_DSP_B
TCK
W3
TDI_B
TDI
W4
TDO_B
TDO
AC4
TMS
AD4
TRST
TMS
PLACE CLOSE TO DSP PINS
EMU
Y2
TRST
DATA42
DATA43
DATA44
DATA45
DATA46
DATA47
DATA48
SCLK_DSP_B
DATA49
R8
0.00
805
DATA50
R9
0.00
805
DATA51
DATA52
P1
SCLK1
R2
SCLK2
C36
10PF
805
DNP
DATA53
DATA54
DATA55
C35
10PF
805
DNP
DATA56
DATA57
DATA58
T1
DSP_RESET
RST_IN
DATA59
DATA60
R10
0.00
805
U2
RST_OUT
DATA61
DATA62
V3
POR_IN
LABEL "DSP B" near this DSP
D[0:63]
DATA63
D17
D0
A17
D1
B17
D2
C16
D3
D16
D4
A16
D5
B16
D6
C15
D7
D15
D8
A15
D9
B15
D10
A14
D11
B14
D12
C14
D13
RD
D14
D14
WRL
1
2.5V
R5
4.7K
805
BR0
R93
4.7K
805
HBR
U12
D15
WRH
D16
ACK
C12
D17
BRST
D12
D18
A12
D19
MS0
B12
D20
MS1
C11
D21
MSH
D11
D22
BMS
A11
D23
A13
B13
C18
RD
A18
WRL
AC7
CPA
AD7
DPA
DPA
B18
WRH
C17
D18
RN4
AA7
ACK
DMAR0
BRST
DMAR1
DMAR0
BR3
AB7
DMAR1_B
BR2
D24
A10
D25
DMAR2
G3
MS0
F2
MS1
H2
MSH
G4
BMS
BR0
BR[0:7]
BR1
BR2
B10
D26
BR3
C10
D27
BR4
D10
D28
A9
D29
B9
D30
BR5
BR6
BR7
C9
D9
D31
L2
BR0
L3
BR1
L4
BR2
M1
BR3
T3
BR4
M3
BR5
M4
BR6
R4
BR7
BM_B
B8
D34
BOFF
C8
D35
BUSLOCK
D8
D36
A7
D37
HBR
B7
D38
HBG
C7
D39
D7
D40
RAS
A6
D41
CAS
B6
D42
A5
D43
LDQM
B5
D44
HDQM
C6
D45
D6
D46
C5
D47
SDCKE
D48
A4
D49
B4
D50
A2
D51
C4
D52
AA8
HBR
AB8
HBG
J1
RAS
J2
CAS
K3
LDQM
K4
HDQM
K1
SDA10
K2
SDCKE
L1
SDWE
SDWE
MSSD[0:3]
MSSD0
U1
MSSD0
MSSD1
G1
MSSD2
MSSD3
B1
D53
D3
D54
D1
D55
D2
D56
E3
D57
E4
D58
F3
D59
F4
D60
E1
D61
E2
D62
F1
D63
MSSD1
V1
MSSD2
H3
MSSD3
BR1
AD6
DMAR3_B
SDCKE
DMAR2_A
AC5
IOWR
IOWR
DMAR3_A
AD5
IORD
IORD
AA6
IOEN
IOEN
BOFF
DMAR1_B
1
R1
2
R2
3
R3
4
R4
6
R5
7
R6
8
R7
9
R8
COM1
COM2
5
10
2
4.7K
RNET8
ID0
ID1
ID2
N1
ID0_B
AD2
RN3
ID1_B
U3
ID2_B
DMAR0
DMAR1_A
SCLKRAT0
SCLKRAT1
H4
M2
T2
SCLKRAT0_B
DMAR3_B
SCLKRAT1_B
DMAR2_B
SCLKRAT2_B
BR5
BR6
W1
CONTROLIMP0
V4
CONTROLIMP1
T4
DS0
U4
DS1
V2
DS2
TMR0E
CONTROLIMP0
BR7
CONTROLIMP1
BR4
1
R1
2
R2
3
R3
4
R4
6
R5
7
R6
8
R7
9
R8
COM1
COM2
5
10
4.7K
RNET8
DS0_B
DS1_B
DS2_B
W2
ENEDREG
ENEDREG_B
Y3
TMR0E_B
3
FLAG0
SDA10
D5
P4
BM
AC8
BOFF
AD8
BUSLOCK
DMAR2_B
DMAR3
SCLKRAT2
D32
D33
A8
2.5V
CPA
AC6
B11
2.5V
FLAG1
FLAG2
FLAG3
IRQ0
IRQ1
IRQ2
IRQ3
AC1
FLAG0_B
AA2
FLAG1_B
AA1
FLAG2_B
Y4
FLAG3_B
AA5
IRQ0_B
AB6
IRQ1_B
AB5
IRQ2_B
AA3
IRQ3_B
FLAG[3:0]_B
IRQ[3:0]_B
ADSP-TS201S
BP576
ANALOG
DEVICES
4
ADSP-TS201S
BP576
Approvals
Date
Title
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-TS201S EZ-KIT LITE - DSP B
Drawn
Checked
Engineering
A
B
C
Size
Board No.
C
Date
Rev
A0178-2002
1.1C
Sheet
3-1-2004_10:59
D
3
of
15
A
B
C
Link Port 0
Link Port 1
Link Port 2
Link Port 3
ALL NETS ON THIS PAGE EXCEPT L?ACK?_? and L?BCMP?_? ARE DIFFERETIAL PAIRS
THESE SIGNAL SHOULD BE ROUTING ACCORDING THE GUIDELINES SET IN EE-179
DSP A
FPGA
EXP INT
DSP B
RJ45
D
DSP B
FPGA
EXP INT
DSP A
RJ45
2_5V_DSP_A
2_5V_DSP_B
DSP A
1
DSP B
U11
PLACE CLOSE TO DSP A PINS (CRITICAL)
L0DATI0_P_A
R27
100
805
L0DATI0_N_A
L0DATI0_P_A
L0DATI0_N_A
R12
100
805
DNP
L0CLKIN_P_A
L0CLKIN_N_A
L0CLKIN_P_A
L0CLKIN_N_A
L0ACKO_A
L0BCMPI_A
L1DATI0_P_A
2_5V_DSP_A
2
L1DATI0_N_A
R13
100
805
P24
L0DATO0_P
P23
L0DATO0_N
P22
L0DATO1_P
P21
L0DATO1_N
N22
L0DATO2_P
N21
L0DATO2_N
M24
L0DATO3_P
M23
L0DATO3_N
N24
L0CLKO_P
N23
L0CLKO_N
R24
L0ACKI
R23
L0BCMPO
T22
AA24
L1DATO0_P
AA23
L1DATO0_N
Y22
L1DATO1_P
Y21
L1DATO1_N
Y24
L1DATO2_P
Y23
L1DATO2_N
W24
L1DATO3_P
W23
L1DATO3_N
W22
L1CLKO_P
W21
L1CLKO_N
AC24
L1ACKI
AA22
L1BCMPO
U24
L1DATI0_P_A
U23
L1DATI0_N_A
V24
V23
R240
10K
805
V22
V21
R14
100
805
DNP
U22
L1CLKIN_P_A
U21
L1CLKIN_N_A
L1CLKIN_P_A
L1CLKIN_N_A
T23
L1ACKO_A
T24
L1BCMPI_A
R15
100
805
AD21
L2DATI0_P_A
L2DATI0_P_A
L2DATI0_N_A
R16
100
805
R242
10K
805
AC21
L2DATI0_N_A
AB20
L2DATI1_P_A
AA20
L2DATI1_N_A
L2DATI1_P_A
L2DATI1_N_A
AD20
L2DATI2_P_A
AC20
L2DATI2_N_A
R17
100
805
AD19
L2DATI3_P_A
L2DATI2_P_A
L2DATI2_N_A
AC19
L2DATI3_N_A
AB19
L2CLKIN_P_A
R18
100
805
AA19
L2CLKIN_N_A
L2DATI3_P_A
L2DATI3_N_A
3
AB21
L2ACKO_A
AD23
L2BCMPI_A
R19
100
805
L2CLKIN_P_A
L2CLKIN_N_A
AD14
L3DATI0_P_A
AC14
L3DATI0_N_A
AB14
AA14
AB13
AA13
R20
100
805
AD12
AC12
L3DATI0_P_A
L3DATI0_N_A
AD13
L3CLKIN_P_A
AC13
L3CLKIN_N_A
R21
100
805
AC15
L3ACKO_A
L3CLKIN_P_A
L3CLKIN_N_A
AD15
L3BCMPI_A
2_5V_DSP_A
4
R108
10K
805
R116
10K
805
R119
10K
805
DNP
U12
J24
L0DATI0_P
J23
L0DATI0_N
K22
L0DATI1_P
K21
L0DATI1_N
L24
L0DATI2_P
L23
L0DATI2_N
L22
L0DATI3_P
L21
L0DATI3_N
K24
L0CLKIN_P
K23
L0CLKIN_N
J21
L0ACKO
J22
L0BCMPI
T21
L1DATI0_P
L1DATI0_N
L1DATI1_P
L1DATI1_N
L1DATI2_P
L1DATI2_N
L1DATI3_P
L1DATI3_N
L1CLKIN_P
L1CLKIN_N
L1ACKO
L1BCMPI
L2DATI0_P
L2DATI0_N
L2DATI1_P
L2DATI1_N
L2DATI2_P
L2DATI2_N
L2DATI3_P
L2DATI3_N
L2CLKIN_P
L2CLKIN_N
L2ACKO
L2BCMPI
L3DATI0_P
L3DATI0_N
L3DATI1_P
L3DATI1_N
L3DATI2_P
L3DATI2_N
L3DATI3_P
L3DATI3_N
L3CLKIN_P
L3CLKIN_N
L3ACKO
L3BCMPI
PLACE CLOSE TO DSP B PINS (CRITICAL)
L0DATO0_P_A
L0DATO0_N_A
J24
L0DATI0_P_B
L0DATI0_N_B
L0DATI0_P_B
L0DATI0_N
K22
L0DATI1_P
K21
L0DATI1_N
L24
L0DATI2_P
L23
L0DATI2_N
L22
L0DATI3_P
L21
L0DATI3_N
K24
L0CLKIN_P
K23
L0CLKIN_N
J21
L0ACKO
J22
L0BCMPI
L0DATI0_N_B
R28
100
805
DNP
L0CLKIN_P_B
L0CLKIN_N_B
L0CLKOUT_P_A
L0CLKIN_P_B
L0CLKOUT_N_A
L0CLKIN_N_B
L0ACKI_A
L0ACKO_B
L0BCMPO_A
AB16
L2DATO0_P
AA16
L2DATO0_N
AD17
L2DATO1_P
AC17
L2DATO1_N
AD18
L2DATO2_P
AC18
L2DATO2_N
AB18
L2DATO3_P
AA18
L2DATO3_N
AB17
L2CLKO_P
AA17
L2CLKO_N
AD16
L2ACKI
AC16
L2BCMPO
AD9
L3DATO0_P
AC9
L3DATO0_N
AB10
L3DATO1_P
AA10
L3DATO1_N
AD11
L3DATO2_P
AC11
L3DATO2_N
AB11
L3DATO3_P
AA11
L3DATO3_N
AD10
L3CLKO_P
AC10
L3CLKO_N
AB9
L3ACKI
AA9
L3BCMPO
L1DATO0_P_A
L0BCMPI_B
T22
L1DATI0_P_B
2_5V_DSP_B
L1DATO0_N_A
T21
L1DATI0_N_B
R29
100
805
U24
R239
10K
805
R30
100
805
DNP
L1ACKI_A
L1CLKIN_P_B
L1CLKIN_N_B
L1CLKIN_P_B
L1CLKIN_N_B
L1BCMPO_A
L1ACKO_B
L1BCMPI_B
R36
100
805
L2DATO0_P_A
L2DATO0_N_A
L2DATO0_N_A
R43
100
805
L2DATO1_N_A
L2DATO2_P_A
L2DATO1_N_A
L2DATO3_N_A
L2DATO2_N_A
L2ACKI_A
L2CLKOUT_N_A
L2DATO3_P_A
L2DATO3_N_A
L2BCMPO_A
L2ACKI_A
L2BCMPO_A
R98
100
805
L3DATO0_P_A
L2DATO3_N_A
L2CLKOUT_P_A
R96
100
805
L2CLKOUT_N_A
L2DATO2_P_A
L2DATO3_P_A
L2DATO2_P_A
L2CLKOUT_P_A
L2CLKOUT_P_A
L2CLKOUT_N_A
L3DATO0_N_A
AD14
L3DATI0_P_B
L3DATI0_N
AB14
L3DATI1_P
AA14
L3DATI1_N
AB13
L3DATI2_P
AA13
L3DATI2_N
AD12
L3DATI3_P
AC12
L3DATI3_N
AD13
L3CLKIN_P
AC13
L3CLKIN_N
AC15
L3ACKO
AD15
L3BCMPI
R31
100
805
L3DATI0_N_B
R33
100
805
L3CLKOUT_P_A
L3CLKIN_P_B
L3CLKIN_P_B
L3CLKIN_N_B
L3CLKOUT_N_A
L3CLKIN_N_B
L3ACKI_A
L3ACKO_B
L3BCMPO_A
L3BCMPI_B
ADSP-TS201S
BP576
2_5V_DSP_B
R235
10K
805
R153
10K
805
R236
10K
805
R237
10K
805
DNP
L1BCMPI_A
ANALOG
DEVICES
R238
10K
805
Approvals
L3BCMPI_B
Checked
L3BCMPI_A
Engineering
B
L0DATO0_P_B
L0DATO0_N_B
L0CLKOUT_P_B
L0CLKOUT_N_B
L0ACKI_B
L0BCMPO_B
AA24
L1DATO0_P
AA23
L1DATO0_N
Y22
L1DATO1_P
Y21
L1DATO1_N
Y24
L1DATO2_P
Y23
L1DATO2_N
W24
L1DATO3_P
W23
L1DATO3_N
W22
L1CLKO_P
W21
L1CLKO_N
AC24
L1ACKI
AA22
L1BCMPO
L1DATO0_P_B
L1DATO0_N_B
2
L1CLKOUT_P_B
L1CLKOUT_N_B
L1ACKI_B
L1BCMPO_B
AB16
L2DATO0_P
AA16
L2DATO0_N
AD17
L2DATO1_P
AC17
L2DATO1_N
AD18
L2DATO2_P
AC18
L2DATO2_N
AB18
L2DATO3_P
AA18
L2DATO3_N
AB17
L2CLKO_P
AA17
L2CLKO_N
AD16
L2ACKI
AC16
L2BCMPO
L2DATI0_P_A
L2DATI0_N_A
L2DATI1_P_A
L2DATI1_N_A
L2DATI2_P_A
L2DATI2_N_A
L2DATI3_P_A
L2DATI3_N_A
L2CLKIN_P_A
L2CLKIN_N_A
L2ACKO_A
3
L2BCMPI_A
AD9
L3DATO0_P
AC9
L3DATO0_N
AB10
L3DATO1_P
AA10
L3DATO1_N
AD11
L3DATO2_P
AC11
L3DATO2_N
AB11
L3DATO3_P
AA11
L3DATO3_N
AD10
L3CLKO_P
AC10
L3CLKO_N
AB9
L3ACKI
AA9
L3BCMPO
L3DATO0_P_B
L3DATO0_N_B
L3CLKOUT_P_B
L3CLKOUT_N_B
L3ACKI_B
L3BCMPO_B
Date
Title
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-TS201S EZ-KIT LITE - DSP LINK PORTS
Drawn
L2BCMPO_A
L2BCMPI_A
P24
L0DATO0_P
P23
L0DATO0_N
P22
L0DATO1_P
P21
L0DATO1_N
N22
L0DATO2_P
N21
L0DATO2_N
M24
L0DATO3_P
M23
L0DATO3_N
N24
L0CLKO_P
N23
L0CLKO_N
R24
L0ACKI
R23
L0BCMPO
ADSP-TS201S
BP576
L0BCMPI_A
L1BCMPI_B
L3DATI0_P
AC14
L3DATI0_N_B
L3DATI0_P_B
L2DATI0_P
L2DATI0_N
AB20
L2DATI1_P
AA20
L2DATI1_N
AD20
L2DATI2_P
AC20
L2DATI2_N
AD19
L2DATI3_P
AC19
L2DATI3_N
AB19
L2CLKIN_P
AA19
L2CLKIN_N
AB21
L2ACKO
AD23
L2BCMPI
L2DATO2_N_A
R83
100
805
L2DATO3_P_A
L1DATI1_P
AC21
R241 L2DATO0_N_A
10K
L2DATO1_P_A
805
L2DATO1_N_A
L2DATO1_P_A
L2DATO2_N_A
AD21
L2DATO0_P_A
L2DATO0_P_A
L2DATO1_P_A
L1DATI0_N
L1DATI1_N
V24
L1DATI2_P
V23
L1DATI2_N
V22
L1DATI3_P
V21
L1DATI3_N
U22
L1CLKIN_P
U21
L1CLKIN_N
T23
L1ACKO
T24
L1BCMPI
L1DATI0_N_B
L1CLKOUT_N_A
L1DATI0_P
U23
L1DATI0_P_B
L1CLKOUT_P_A
L0DATI0_P
J23
R22
100
805
L0BCMPI_B
A
1
C
Size
Board No.
C
Date
Rev
A0178-2002
1.1C
Sheet
3-1-2004_10:59
D
4
of
15
A
B
3.3V
C
D
2.5V
1V_DSP_A
R121
2.00K
1206
R38
2.00K
1206
1V_DSP_B
L1
10UH
1008
DSP_SCLK_VREF
L2
10UH
1008
DSP_VREF
A1V_DSP_A
A1V_DSP_B
1
R37
2.00K
1206
R88
2.00K
1206
C41
1UF
805
1
C37
1UF
805
C44
1UF
805
C46
1UF
805
PLACE CLOSE TOGETHER
USE at least 3 vias per connection
PLACE CLOSE TOGETHER
USE at least 3 vias per connection
1.0V
DSP A
1V_DSP_A
R76
0.00
1206
1V_DSP_B
1_5V_DSP_B
1.5V
R110
0.00
1206
U12
U11
2
P8
2
IDC2X1
2X1
DNP
3
A1V_DSP_A
DSP_SCLK_VREF
F10
F13VDD1
F14VDD2
F17VDD3
F18VDD4
F19VDD5
F6VDD6
F7VDD7
F8VDD8
F9VDD9
G10VDD10
G13VDD11
G14VDD12
G17VDD13
G18VDD14
G19VDD15
G6VDD16
G7VDD17
G8VDD18
G9VDD19
H18VDD20
H19VDD21
H6VDD22
H7VDD23
J18VDD24
J19VDD25
J6VDD26
J7VDD27
K6VDD28
K7VDD29
L6VDD30
L7VDD31
M18VDD32
M19VDD33
M6VDD34
M7VDD35
N18VDD36
N19VDD37
N6VDD38
N7VDD39
P6VDD40
P7VDD41
R6VDD42
R7VDD43
T18VDD44
T19VDD45
T6VDD46
T7VDD47
U10VDD48
U18VDD49
U19VDD50
U6VDD51
U7VDD52
V10VDD53
V13VDD54
V14VDD55
V17VDD56
V18VDD57
V19VDD58
V6VDD59
V7VDD60
V8VDD61
V9VDD62
W10VDD63
W13VDD64
W14VDD65
W17VDD66
W18VDD67
W19VDD68
W6VDD69
W7VDD70
W8VDD71
W9VDD72
VDD73
N3
N4VDD_A1
VDD_A2
P2
R3SCLK_VREF1
SCLK_VREF2
F11
VDD_DRAM1F12
VDD_DRAM2F15
VDD_DRAM3F16
VDD_DRAM4G11
VDD_DRAM5G12
VDD_DRAM6G15
VDD_DRAM7G16
VDD_DRAM8K18
VDD_DRAM9K19
VDD_DRAM10L18
VDD_DRAM11L19
VDD_DRAM12P18
VDD_DRAM13P19
VDD_DRAM14R18
VDD_DRAM15R19
VDD_DRAM16U11
VDD_DRAM17V11
VDD_DRAM18V12
VDD_DRAM19V15
VDD_DRAM20V16
VDD_DRAM21W11
VDD_DRAM22W12
VDD_DRAM23W15
VDD_DRAM24W16
VDD_DRAM25
R104
0.00
1206
P10
1
2
IDC2X1
2X1
DNP
2_5V_DSP_A
AB23
VDD_IO1AB24
VDD_IO2AC22
VDD_IO3AC3
VDD_IO4AD22
VDD_IO5AD3
VDD_IO6C23
VDD_IO7C24
VDD_IO8E10
VDD_IO9E11
VDD_IO10E12
VDD_IO11E13
VDD_IO12E14
VDD_IO13E15
VDD_IO14E17
VDD_IO15E19
VDD_IO16E6
VDD_IO17E8
VDD_IO18F20
VDD_IO19F5
VDD_IO20G20
VDD_IO21H20
VDD_IO22H5
VDD_IO23K20
VDD_IO24K5
VDD_IO25L20
VDD_IO26L5
VDD_IO27M20
VDD_IO28M5
VDD_IO29N20
VDD_IO30N5
VDD_IO31P20
VDD_IO32P5
VDD_IO33R20
VDD_IO34R5
VDD_IO35U20
VDD_IO36U5
VDD_IO37V20
VDD_IO38W20
VDD_IO39W5
VDD_IO40Y10
VDD_IO41Y11
VDD_IO42Y12
VDD_IO43Y13
VDD_IO44Y14
VDD_IO45Y15
VDD_IO46Y17
VDD_IO47Y19
VDD_IO48Y6
VDD_IO49Y8
VDD_IO50
J4
VREF
2.5V
R107
0.00
1206
P11
1
2
IDC2X1
2X1
DNP
DSP_VREF
A1
A22VSS1
A24VSS2
A3VSS3
AA12VSS4
AA21VSS5
AA4VSS6
AB1VSS7
AB12VSS8
AB15VSS9
AB2VSS10
AB22VSS11
AB3VSS12
AC2VSS13
AC23VSS14
AD1VSS15
AD24VSS16
B2VSS17
B22VSS18
B23VSS19
B3VSS20
C1VSS21
C13VSS22
C2VSS23
C22VSS24
C3VSS25
D13VSS26
D21VSS27
D4VSS28
E16VSS29
E18VSS30
E20VSS31
E5VSS32
E7VSS33
E9VSS34
G2VSS35
G5VSS36
H1VSS37
H10VSS38
H11VSS39
H12VSS40
H13VSS41
H14VSS42
H15VSS43
H16VSS44
H17VSS45
H8VSS46
H9VSS47
J10VSS48
J11VSS49
J12VSS50
J13VSS51
J14VSS52
J15VSS53
J16VSS54
J17VSS55
J20VSS56
J3VSS57
J5VSS58
J8VSS59
J9VSS60
K10VSS61
K11VSS62
K12VSS63
K13VSS64
K14VSS65
K15VSS66
K16VSS67
K17VSS68
K8VSS69
K9VSS70
L10VSS71
L11VSS72
L12VSS73
L13VSS74
L14VSS75
L15VSS76
VSS77
L16
VSS78L17
VSS79L8
VSS80L9
VSS81M10
VSS82M11
VSS83M12
VSS84M13
VSS85M14
VSS86M15
VSS87M16
VSS88M17
VSS89M21
VSS90M22
VSS91M8
VSS92M9
VSS93N10
VSS94N11
VSS95N12
VSS96N13
VSS97N14
VSS98N15
VSS99N16
VSS100N17
VSS101N2
VSS102N8
VSS103N9
VSS104P10
VSS105P11
VSS106P12
VSS107P13
VSS108P14
VSS109P15
VSS110P16
VSS111P17
VSS112P3
VSS113P8
VSS114P9
VSS115R1
VSS116R10
VSS117R11
VSS118R12
VSS119R13
VSS120R14
VSS121R15
VSS122R16
VSS123R17
VSS124R22
VSS125R8
VSS126R9
VSS127T10
VSS128T11
VSS129T12
VSS130T13
VSS131T14
VSS132T15
VSS133T16
VSS134T17
VSS135T20
VSS136T5
VSS137T8
VSS138T9
VSS139U12
VSS140U13
VSS141U14
VSS142U15
VSS143U16
VSS144U17
VSS145U8
VSS146U9
VSS147V5
VSS148Y16
VSS149Y18
VSS150Y20
VSS151Y5
VSS152Y7
VSS153Y9
VSS154
C42
1000PF
805
2
IDC2X1
2X1
DNP
A1V_DSP_B
DSP_SCLK_VREF
F10
F13VDD1
F14VDD2
F17VDD3
F18VDD4
F19VDD5
F6VDD6
F7VDD7
F8VDD8
F9VDD9
G10VDD10
G13VDD11
G14VDD12
G17VDD13
G18VDD14
G19VDD15
G6VDD16
G7VDD17
G8VDD18
G9VDD19
H18VDD20
H19VDD21
H6VDD22
H7VDD23
J18VDD24
J19VDD25
J6VDD26
J7VDD27
K6VDD28
K7VDD29
L6VDD30
L7VDD31
M18VDD32
M19VDD33
M6VDD34
M7VDD35
N18VDD36
N19VDD37
N6VDD38
N7VDD39
P6VDD40
P7VDD41
R6VDD42
R7VDD43
T18VDD44
T19VDD45
T6VDD46
T7VDD47
U10VDD48
U18VDD49
U19VDD50
U6VDD51
U7VDD52
V10VDD53
V13VDD54
V14VDD55
V17VDD56
V18VDD57
V19VDD58
V6VDD59
V7VDD60
V8VDD61
V9VDD62
W10VDD63
W13VDD64
W14VDD65
W17VDD66
W18VDD67
W19VDD68
W6VDD69
W7VDD70
W8VDD71
W9VDD72
VDD73
N3
N4VDD_A1
VDD_A2
P2
R3SCLK_VREF1
SCLK_VREF2
F11
VDD_DRAM1F12
VDD_DRAM2F15
VDD_DRAM3F16
VDD_DRAM4G11
VDD_DRAM5G12
VDD_DRAM6G15
VDD_DRAM7G16
VDD_DRAM8K18
VDD_DRAM9K19
VDD_DRAM10L18
VDD_DRAM11L19
VDD_DRAM12P18
VDD_DRAM13P19
VDD_DRAM14R18
VDD_DRAM15R19
VDD_DRAM16U11
VDD_DRAM17V11
VDD_DRAM18V12
VDD_DRAM19V15
VDD_DRAM20V16
VDD_DRAM21W11
VDD_DRAM22W12
VDD_DRAM23W15
VDD_DRAM24W16
VDD_DRAM25
R113
0.00
1206
P12
1
2
IDC2X1
2X1
DNP
2_5V_DSP_B
AB23
VDD_IO1AB24
VDD_IO2AC22
VDD_IO3AC3
VDD_IO4AD22
VDD_IO5AD3
VDD_IO6C23
VDD_IO7C24
VDD_IO8E10
VDD_IO9E11
VDD_IO10E12
VDD_IO11E13
VDD_IO12E14
VDD_IO13E15
VDD_IO14E17
VDD_IO15E19
VDD_IO16E6
VDD_IO17E8
VDD_IO18F20
VDD_IO19F5
VDD_IO20G20
VDD_IO21H20
VDD_IO22H5
VDD_IO23K20
VDD_IO24K5
VDD_IO25L20
VDD_IO26L5
VDD_IO27M20
VDD_IO28M5
VDD_IO29N20
VDD_IO30N5
VDD_IO31P20
VDD_IO32P5
VDD_IO33R20
VDD_IO34R5
VDD_IO35U20
VDD_IO36U5
VDD_IO37V20
VDD_IO38W20
VDD_IO39W5
VDD_IO40Y10
VDD_IO41Y11
VDD_IO42Y12
VDD_IO43Y13
VDD_IO44Y14
VDD_IO45Y15
VDD_IO46Y17
VDD_IO47Y19
VDD_IO48Y6
VDD_IO49Y8
VDD_IO50
J4
VREF
2.5V
R118
0.00
1206
P13
1
2
IDC2X1
2X1
DNP
C45
1000PF
805
C39
1000PF
805
A1
A22VSS1
A24VSS2
A3VSS3
AA12VSS4
AA21VSS5
AA4VSS6
AB1VSS7
AB12VSS8
AB15VSS9
AB2VSS10
AB22VSS11
AB3VSS12
AC2VSS13
AC23VSS14
AD1VSS15
AD24VSS16
B2VSS17
B22VSS18
B23VSS19
B3VSS20
C1VSS21
C13VSS22
C2VSS23
C22VSS24
C3VSS25
D13VSS26
D21VSS27
D4VSS28
E16VSS29
E18VSS30
E20VSS31
E5VSS32
E7VSS33
E9VSS34
G2VSS35
G5VSS36
H1VSS37
H10VSS38
H11VSS39
H12VSS40
H13VSS41
H14VSS42
H15VSS43
H16VSS44
H17VSS45
H8VSS46
H9VSS47
J10VSS48
J11VSS49
J12VSS50
J13VSS51
J14VSS52
J15VSS53
J16VSS54
J17VSS55
J20VSS56
J3VSS57
J5VSS58
J8VSS59
J9VSS60
K10VSS61
K11VSS62
K12VSS63
K13VSS64
K14VSS65
K15VSS66
K16VSS67
K17VSS68
K8VSS69
K9VSS70
L10VSS71
L11VSS72
L12VSS73
L13VSS74
L14VSS75
L15VSS76
VSS77
L16
VSS78L17
VSS79L8
VSS80L9
VSS81M10
VSS82M11
VSS83M12
VSS84M13
VSS85M14
VSS86M15
VSS87M16
VSS88M17
VSS89M21
VSS90M22
VSS91M8
VSS92M9
VSS93N10
VSS94N11
VSS95N12
VSS96N13
VSS97N14
VSS98N15
VSS99N16
VSS100N17
VSS101N2
VSS102N8
VSS103N9
VSS104P10
VSS105P11
VSS106P12
VSS107P13
VSS108P14
VSS109P15
VSS110P16
VSS111P17
VSS112P3
VSS113P8
VSS114P9
VSS115R1
VSS116R10
VSS117R11
VSS118R12
VSS119R13
VSS120R14
VSS121R15
VSS122R16
VSS123R17
VSS124R22
VSS125R8
VSS126R9
VSS127T10
VSS128T11
VSS129T12
VSS130T13
VSS131T14
VSS132T15
VSS133T16
VSS134T17
VSS135T20
VSS136T5
VSS137T8
VSS138T9
VSS139U12
VSS140U13
VSS141U14
VSS142U15
VSS143U16
VSS144U17
VSS145U8
VSS146U9
VSS147V5
VSS148Y16
VSS149Y18
VSS150Y20
VSS151Y5
VSS152Y7
VSS153Y9
VSS154
2
3
DSP_VREF
ADSP-TS201S
BP576
ADSP-TS201S
BP576
ADSP-TS201S
BP576
ADSP-TS201S
BP576
C40
1000PF
805
R109
0.00
1206
P9
1
1.5V
U12
U11
R91
0.00
1206
1
1_5V_DSP_A
1.0V
DSP B
C43
1000PF
805
C38
1000PF
805
ANALOG
DEVICES
PLACE CLOSE TO DSP B PINS
PLACE CLOSE TO DSP A PINS
4
Approvals
Date
Title
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-TS201S EZ-KIT LITE - DSP POWER
Drawn
Checked
Engineering
A
B
C
Size
Board No.
C
Date
Rev
A0178-2002
1.1C
Sheet
3-1-2004_10:59
D
5
of
15
A
B
2.5V
C
D
2.5V
ID[2-0] have internal 5Kohm pull-down resistors
R115
499
805
DNP
1
R117
499
805
DNP
R120
499
805
DNP
R122
499
805
DNP
ID2_A
ID2_B
ID1_A
ID1_B
ID0_A
ID0_B
DSP A
Default ID = 0
R123
499
805
DNP
DSP B
Default ID = 1
R124
499
805
Proc ID
0
1
2
3
4
5
6
7
2.5V
PLACE A LABEL "HIGH" NEAR SW2.12
PLACE A LABEL FOR THE SIGNAL NAME NEXT TO SW2 PINS 1-6
1
R140
499
805
THESE RESISTORS DO NOT NEED TO BE VERY CLOSE TO THE DSP
IF POSSIBLE I WOULD LIKE THEM ALL ON THE BOTTOM OF THE BOARD
ORGANIZED IN GROUPS SIMILAR TO SHOW HERE
DEPENDING ON HOW MUCH ROOM YOU CAN LEAVE NEAR THEM
I WOULD LIKE TO LABEL SOME OF THEM
BMS
BM_A
SCLKRAT2_A
SCLKRAT2_B
SCLKRAT1_A
SCLKRAT1_B
SCLKRAT0_A
SCLKRAT0_B
2
DSP A
Default PLL Ratio = 5X
CCLK = 500MHz
R125
499
805
DNP
R45
499
805
SCLKRAT(2-0)
000
001
010
011
100
101
110
111
4
9
5
8
6
7
6
SCLKRAT[2-0] have internal 5Kohm pull-down resistors
R126
499
805
DNP
10
5
TMR0E_B
R133
499
805
11
3
4
BM_B
R127
499
805
DNP
2
3
2.5V
ON 12
2
BUSLOCK
TMR0E_A
R128
499
805
DNP
R141
499
805
R142
499
805
R144
499
805
R145
499
805
R146
499
805
SW2
1
1
2.5V
ID(2-0)
000
001
010
011
100
101
110
111
SWT017
DIP6
All strap pins have internal 5Kohm pull-down resistors during DSP reset
Switch OFF (Signal Pulled Low)
Switch ON (Signal Pulled High)
BMS
* EPROM Boot
External or link port boot
BM
* Disable interupts, level sensitive
Enable interupts, edge sensitive
TMR0E
* 1-bit Link Port Data Width
4-bit Link Port Data Width
BUSLOCK * SYSCON/SDRCON one-time writable
SYSCON/SDRCON always writable
* indicates DEFAULT
PLL Ratio
4
5
6
7
8
10
12
RESERVED
2
DSP B
Default PLL Ratio = 5X
CCLK = 500MHz
KEEP STUB TO THE SIGNAL AS SMALL AS POSSIBLE
2.5V
L1BCMPO_A
L1BCMPO_B
REALLY (L1BCMP0_B)
L2BCMPO_A
R131
499
805
DNP
CONTROLIMP0
CONTROLIMP1
DEFAULT = NORMAL
CONTROLIMP0 has an internal 5Kohm pull-down resistor
CONTROLIMP1 has an internal 5Kohm pull-up resistor
CONTROLIMP(1:0)
00
01
10
11
L3BCMPO_A
L2BCMPI_A
L3BCMPO_B
Driver Mode
Normal
Pulse Mode
A/D Mode
Pulse Mode, A/D Mode
R134
499
805
DNP
R23
499
805
R51
499
805
R106
499
805
DNP
R111
499
805
R114
499
805
R143
499
805
3
3
ENEDREG_A
2.5V
ENEDREG_B
2.5V
R25
499
805
R132
499
805
DNP
R139
499
805
DNP
DS2_A
DS2_B
DS1_A
DS1_B
DS0_A
DS0_B
R135
499
805
DNP
R154
499
805
R136
499
805
DNP
DS1 has internal 5Kohm pull-down resistor
DS2 and DS0 have internal 5Kohm pull-up resistors
R137
499
805
DNP
DS(2-0)
000
001
010
011
100
101
110
111
R138
499
805
DNP
Drive Strength
11.1%
23.8%
36.5%
49.2%
61.9%
74.6%
87.3%
100%
OUTPUT IMP
26
32
40
50
62
70
96
120
DEFAULT
ANALOG
DEVICES
4
Approvals
Date
Title
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-TS201S EZ-KIT LITE - CONFIG
Drawn
Checked
Engineering
A
B
C
Size
Board No.
C
Date
Rev
A0178-2002
1.1C
Sheet
3-4-2004_10:58
D
6
of
15
A
B
C
D
SDRAM 256Mb
(32MB - 4M x 64bits)
FLASH (512Kbx8)
LABEL "SDRAM(LOW)"
1
LABEL "SDRAM(HIGH)"
D[0:63]
1
A[0:18]
U24
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
SDA10
A12
U25
25
A0
26
A1
27
A2
60
A3
61
A4
62
A5
63
A6
64
A7
65
A8
66
A9
24
A10
21
A11
2
D0
A1
25
4
D1
A2
26
DQ0
DQ1
5
D2
A3
27
7
D3
A4
60
8
D4
A5
61
DQ2
DQ3
DQ4
10
D5
A6
62
11
D6
A7
63
DQ5
DQ6
13
D7
A8
64
74
D8
A9
65
DQ7
DQ8
76
DQ9
77
DQ10
79
DQ11
80
DQ12
A13
A14
22
BA0
23
BA1
82
DQ13
83
DQ14
85
DQ15
2
20
CS
67
CKE
68
CLK
SDRAM_CS
SDCKE
SDRAM_CLK0
31
DQ16
33
DQ17
17
WE
18
CAS
19
RAS
CAS
RAS
A13
D14
A14
22
23
D16
20
SDRAM_CS
D17
67
SDCKE
68
SDRAM_CLK1
39
D21
40
D22
42
D23
45
D24
47
D25
71
48
D26
28
50
D27
59
51
D28
53
D29
14
54
D30
30
56
D31
57
DQ24
DQ25
DQ26
DQ27
DQ29
DQ30
DQ31
17
SDWE
18
CAS
19
RAS
16
HDQM
69
3.3V
70
73
44
VSS1
58
VSS2
72
VSS3
86
VSS4
3
VDDQ1
9
VDDQ2
35
VDDQ3
41
VDDQ4
49
VDDQ5
55
VDDQ6
75
VDDQ7
81
VDDQ8
DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
DQ9
1
15
29
43
6
3
12
9
32
35
38
41
46
49
52
55
78
75
84
81
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
MT48LC4M32B2
TSOP86
A11
BA0
BA1
CS
CKE
CLK
WE
CAS
RAS
DQM0
DQM1
DQM2
DQM3
NC1
NC2
NC3
C129
0.01UF
402
C130
0.01UF
402
C132
0.01UF
402
D32
4
D33
5
D34
7
D35
8
D36
10
D37
11
D38
13
D39
74
D40
76
12
A1
11
A2
10
A3
9
A4
8
A5
7
A6
6
A7
5
A8
27
A9
26
A10
23
A11
25
A12
4
A13
28
A14
29
A15
3
A16
2
A17
30
A18
1
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
MS0
D52
BMS
1
U31
1
U38
4
4
2
SN74AHC1G00
SOT23-5
D53
22
2
SN74AHC1G00
SOT23-5
24
RD
31
WRL
A0
D0
A1
D1
A2
D2
A3
D3
A4
D4
A5
D5
A6
D6
A7
D7
13
D0
14
D1
15
D2
17
D3
18
D4
19
D5
20
D6
21
D7
A8
A9
A10
A11
A12
A13
A14
A15
A16
2
A17
A18
CE
OE
WE
D54
AT49BV040
PLCC32RS
D55
D56
D57
D58
D59
D60
D61
D62
D63
NC4
NC5
NC6
44
VSS1
58
VSS2
72
VSS3
86
VSS4
VDD1
VDD2
VDD3
VDD4
3.3V
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
3.3V
3.3V
3
R155
0.00
805
6
VSSQ1
12
VSSQ2
32
VSSQ3
38
VSSQ4
46
VSSQ5
52
VSSQ6
78
VSSQ7
84
VSSQ8
VDDQ1
MSSD[0:1]
MSSD0
SDRAM_CS
C113
0.1UF
402
C112
0.1UF
402
C109
0.01UF
402
R149
0.00
805
MSSD1
DNP
PLACE CLOSE TO DSP (not so critical)
SN74AHC1G00
SN74AHC1G00
AT49BV040
MT48LC4M32B2
TSOP86
3.3V
4
2
77
DQ10
79
DQ11
80
DQ12
82
DQ13
83
DQ14
85
DQ15
31
DQ16
33
DQ17
34
DQ18
36
DQ19
37
DQ20
39
DQ21
40
DQ22
42
DQ23
45
DQ24
47
DQ25
48
DQ26
50
DQ27
51
DQ28
53
DQ29
54
DQ30
56
DQ31
A10
D15
D20
DQ22
1
VDD1
15
VDD2
29
VDD3
43
VDD4
3
21
37
DQ28
3.3V
D13
D19
DQ21
14
NC1
30
NC2
57
NC3
69
NC4
70
NC5
73
NC6
A12
A0
D12
D18
DQ20
16
DQM0
71
DQM1
28
DQM2
59
DQM3
66
24
SDA10
D11
36
DQ23
LDQM
A10
D10
34
DQ18
DQ19
SDWE
D9
U10
A0
3.3V
C131
0.01UF
402
C136
0.01UF
402
C135
0.01UF
402
C133
0.01UF
402
C134
0.01UF
402
C140
0.01UF
402
C139
0.01UF
402
C137
0.01UF
402
ANALOG
DEVICES
C138
0.01UF
402
Approvals
Date
Title
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-TS201S EZ-KIT LITE - MEMORY
Drawn
SDRAM
SDRAM
Checked
Engineering
A
B
C
Size
Board No.
C
Date
Rev
A0178-2002
1.1C
Sheet
3-4-2004_11:06
D
7
of
15
A
B
C
D
KEEP ALL OF THESE COMPONENTS OVER THE AGND PLANE
PLACE NEAR CONNECTOR
CT5
10UF
CAP002
FER2
600
1206
1
R44
5.76K
1206
R148
57.6K
1206
1
TRY TO KEEP ALL TRACES AS SHORT AS POSSIBLE
INL-_AMPIN
R58
100K
1206
C16
120PF
1206
C20
100PF
1206
3.3V
R52
237
1206
U6
2
1
INL-_AMPOUT
INL-
AGND
3
LMV722M
SOIC8
LABEL "LINE IN"
R55
5.76K
1206
VREF_AUDIO
C14
0.001UF
805
R54
5.76K
1206
P1
C12
100PF
1206
ADC
ADC LEFT
R42
10K
805
C17
120PF
1206
1
5
AGND
AUDIO_IN_LEFT
4
R49
750K
1206
LOOPBACK_LEFT
3
2
U9
13
R50
237
1206
U6
6
LOOPBACK_RIGHT
AUDIO_IN_RIGHT
C11
0.001UF
805
12
7
CON001
STEREO_JACK
INL+
11
5
10
LMV722M
SOIC8
2
18
AGND
19
AGND
16
CT4
10UF
CAP002
FER1
600
1206
R53
5.76K
1206
R147
57.6K
1206
17
CAPLN
CASC
CAPLP
VINLP
VINLN
VINRP
CAPRN
CAPRP
LRCLK
BCLK
DOUT
C18
120PF
1206
C15
100PF
1206
24
RESET
SLAVE MODE
MCLK IS 256 x Fs
48 kHZ SAMPLE RATE
I S I/F MODE
8
2
VINRN
1
MCLK
MCLK
21
XCTRL
2
CCLK/{256~/512}
3
COUT/{DF0}
4
CIN/{DF1}
5
CLATCH/{M~/S}
INR-_AMPIN
R59
100K
1206
R39
10K
805
RESET
DIN
28
LRCLK
27
BCLK
26
DR
25
14
VREF
VREF_AUDIO
AD1871YRS
SSOP28
2
C4
0.1UF
805
R48
237
1206
U7
1
INR-_AMPOUT
CT2
10UF
B
INR-
AGND
3
LMV722M
SOIC8
PLACE NEAR CONNECTOR
R57
5.76K
1206
C13
0.001UF
805
C3
100PF
1206
R56
5.76K
1206
C9
100PF
1206
AGND
C8
0.01UF
805
ADC RIGHT
C19
120PF
1206
AGND
R47
750K
1206
3
C2
0.01UF
805
C1
0.01UF
805
C10
0.001UF
805
3
KEEP THESE CLOSE TO AD1871
7
U26
2
C7
0.01UF
805
R46
237
1206
U7
6
C6
100PF
1206
INR+
AGND
5
1
LMV722M
SOIC8
3
LMV722M
SOIC8
AGND
THE GND AND AGND PLANES SHOULD GO FROM PIN 8 to PIN 21 of U9
AGND
A5V
6
7
VREF_AUDIO
LMV722M
SOIC8
A5V
3.3V
R179
0.00
1206
5V
C146
0.1UF
805
C145
0.1UF
805
C148
0.1UF
805
C249
0.1UF
805
C149
0.1UF
805
PLACE RESISTOR BETWEEN AD1871 and AD1854
R156
2.00K
1206
3
6
4
5
4
R152
5.76K
1206
ON
7
3
INR-_AMPIN
8
2
2
R150
5.76K
1206
1
SW1
1
4
C147
0.1UF
805
WHEN USING AN ELECTRET MICROPHONE
PLACE SW1.1 AND SW1.2 IN ON POSITION
PLACE SW1.3 AND SW1.4 IN OFF POSITION
5
A5V
AGND
R157
2.00K
1206
U26
A5V
ANALOG
DEVICES
AUDIO_IN_RIGHT
AUDIO_IN_LEFT
INR-_AMPOUT
AGND
AGND
AGND
AGND
NEAR U6
NEAR U7
NEAR U26
AD1871
AD1871
SWT018
DIP4
4
PH: 1-800-ANALOGD
Date
Title
ADSP-TS201S EZ-KIT LITE - AUDIO IN
Drawn
Checked
INL-_AMPIN
Engineering
A
Nashua, NH 03063
AD1871
Approvals
INL-_AMPOUT
20 Cotton Road
B
C
Size
Board No.
C
Date
Rev
A0178-2002
1.1C
Sheet
3-4-2004_10:58
D
8
of
15
A
B
C
D
1
1
KEEP ALL OF THESE COMPONENTS OVER THE AGND PLANE
R65
5.49K
1206
R62
11.0K
1206
C27
100PF
1206
R66
3.32K
1206
THE GND AND AGND PLANES SHOULD GO FROM PIN 10 to PIN 20 of U3
DAC LEFT
C25
330PF
805
MCLK
BCLK
LRCLK
DT
3.3V
R74
604
1206
1
3
U3
2
CT7
68UF
CAP003
U8
C23
100PF
1206
DAC
10
96/48~
6
384/256~
7
X2MCLK
2
MCLK
26
BCLK
25
LRCLK
27
SDATA
2
16
OUTL17
OUTL+
OUTL-
13
OUTR12
OUTR+
OUTR-
R64
5.49K
1206
C26
680PF
805
LMV722M
SOIC8
R67
1.65K
1206
C24
2200PF
1206
R63
49.9K
1206
OUTL+
2
R68
2.74K
1206
OUTR+
C28
220PF
1206
LABEL "LINE OUT"
14
FILTR
19
FILTB
AGND
P2
1
VREF_AUDIO
4
CCLK
3
CLATCH
5
CDATA
22
ZEROL
8
ZEROR
CT3
10UF
B
C5
0.1UF
1206
5
CT1
10UF
B
AGND
LOOPBACK_LEFT
LOOPBACK_RIGHT
RESET
R40
10K
805
4
3
2
24
RESET
CON001
STEREO_JACK
R70
5.49K
1206
9
DEEMP
23
MUTE
R61
11.0K
1206
AGND
21
IDPM0
20
IDPM1
AD1854JRS
SSOP28
C31
100PF
1206
R71
3.32K
1206
C30
330PF
805
DAC RIGHT
6
CT6
68UF
CAP003
U8
C21
100PF
1206
R75
604
1206
7
5
3
R69
5.49K
1206
SLAVE MODE
MCLK IS 256 x Fs
48 kHZ SAMPLE RATE
I S I/F MODE
5V
A5V
C29
680PF
805
LMV722M
SOIC8
R72
1.65K
1206
3
C22
2200PF
1206
R60
49.9K
1206
A5V
R73
2.74K
1206
C32
220PF
1206
AGND
C142
0.1UF
805
C143
0.1UF
805
C153
0.1UF
805
AGND
AD1854
AGND
AGND
AD1854
NEAR U8
ANALOG
DEVICES
4
Approvals
Date
Title
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-TS201S EZ-KIT LITE - AUDIO OUT
Drawn
Checked
Engineering
A
B
C
Size
Board No.
C
Date
Rev
A0178-2002
1.1C
Sheet
3-1-2004_10:59
D
9
of
15
A
B
C
D
3.3V
3.3V
R89
10K
805
LABEL "IRQ_A"
LABEL "FLAG0_A"
3.3V
R94
10K
805
1
R99
100
805
U14
U30
1
R95
100
805
SW4
SWT013
SPST-MOMENTARY
U14
11
SW9
SWT013
SPST-MOMENTARY
10
2
1
74LVC14A
SOIC14
1
2
IRQ0_A_S
74LVC14A
SOIC14
CT9
1UF
A
74LVC14A
SOIC14
R92
10K
805
3.3V
CT8
1UF
A
USB_CONFIGURED
R86
10K
805
LABEL "RESET"
3.3V
U5
1
U15
4
3.3V
1
MR
4
PFI
SW3
SWT013
SPST-MOMENTARY
LABEL "FLAG1_A"
13
2
SW8
SWT013
SPST-MOMENTARY
12
U14
SW5
SWT013
SPST-MOMENTARY
74LVC14A
SOIC14
SN74AHC1G00
SOT23-5
7
RESET
R130
0.00
805
DSP_RESET
3
U14
U30
4
SOFT_RESET
3
74LVC14A
SOIC14
4
IRQ0_B_S
74LVC14A
SOIC14
2
CT10
1UF
A
CT13
1UF
A
USB_RESET
2
ADM708SAR
SOIC8
R85
100
805
R78
100
805
RESET
8
5
PFO
R100
10K
805
LABEL "IRQ_B"
R77
10K
805
RESET
3.3V
3.3V
LABEL "USB RESET"
USB RESET
LED2
RED-SMT
LED001
RESET
LED8
RED-SMT
LED001
LABEL "RESET"
3.3V
R112
10K
805
R160
10K
805
R158
10K
805
R84
270
1206
R159
10K
805
R87
10K
805
LABEL "FLAG0_B"
U13
U30
R103
100
805
5
USB_RESET
6
U14
5
SW6
SWT013
SPST-MOMENTARY
RESET
74LVC14A
SOIC14
6
74LVC14A
SOIC14
U30
9
CT12
1UF
A
3
FLAG2_A
74LVC14A
SOIC14
11
FLAG2_B
FLAG3_A
10
FLAG3_B
74LVC14A
SOIC14
13
1
ON 12
2
11
3
10
4
9
1
2
R101
100
805
8
IRQ0_A_S
6
6
IRQ0_B_S
5
5
74LVC14A
SOIC14
4
9
3
U14
SWT017
DIP6
8
7
3.3V
15
17
2A1
2A2
2A3
2A4
9
2Y1
7
2Y2
5
2Y3
3
2Y4
3
FLAG3_B
LED3
AMBER-SMT
LED001
OE2
12
FLAG3_A/AUDIO
LED6
AMBER-SMT
LED001
FLAG2_B
LED5
AMBER-SMT
LED001
FLAG2_A
LED4
AMBER-SMT
LED001
POWER
LED1
GREEN-SMT
LED001
IDT74FCT3244APY
SSOP20
R79
270
1206
R80
270
1206
R81
270
1206
R82
270
1206
R151
270
1206
FLAG0_A
FLAG1_A
FLAG0_B
FLAG1_B
3.3V
3.3V
3.3V
3.3V
LABEL "POWER"
LABEL "FLAG3_B"
LABEL "FLAG2_B"
LABEL "FLAG3_A/AUDIO"
LABEL "FLAG2_A"
3.3V
IRQ0_A
IRQ0_B
Switch ON = Pushbutton will drive DSP net.
Switch OFF = DSP net can come from an external source
DEFAULT = All Switches ON
4
13
SW10
R102
10K
805
CT11
1UF
A
18
1Y1
16
1Y2
14
1Y3
12
1Y4
1
OE1
74LVC14A
SOIC14
SW7
SWT013
SPST-MOMENTARY
11
19
U30
3.3V
2
1A1
4
1A2
6
1A3
8
1A4
8
U30
LABEL "FLAG1_B"
R90
270
1206
C114
0.1UF
402
C118
0.1UF
402
C111
0.1UF
402
C120
0.1UF
402
ANALOG
DEVICES
C144
0.1UF
402
Approvals
Date
Title
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-TS201S EZ-KIT LITE - RESET/PB/LED
Drawn
SN74AHC1G00 74LVC14
74LVC14 IDT74FCT3244APY ADM708
Checked
Engineering
A
B
C
Size
Board No.
C
Date
Rev
A0178-2002
1.1C
Sheet
3-1-2004_10:59
D
10
of
15
A
B
C
D
Expansion Interface (TYPE A)
PLACE LABEL "EXPANSION INTERFACE (TYPE A)" NEAR MIDDLE CONNECTOR
5V
1
2.5V
2.5V
5V
WARNING: WHEN CONNECTING TO ANOTHER BOARD
MAKE SURE TX CONNECTOR GOES TO A RX CONNECTOR
DO NOT USE CROSSOVER CABLE
3.3V
1
D[0:63]
A[0:31]
J4
J3
1
L3CLKOUT_P_A
4
3
L3CLKOUT_N_A
6
5
L3DATO0_P_A
8
7
2
J1
2
J2
1
2
1
4
3
4
3
6
5
6
5
1
LABEL "DSP A TX"
2
3
4
A1
2
3
A0
A3
8
7
A2
A5
10
9
A4
A7
12
11
A6
A9
14
13
A11
16
A13
A15
CLKOUT_EXP
8
7
10
9
12
11
A8
14
13
15
A10
16
15
18
17
A12
D49
18
17
20
19
A14
D51
20
19
A17
22
21
A16
D53
22
A19
24
23
A18
D55
24
A21
26
25
A20
D57
A23
28
27
A22
A25
30
29
A24
A27
32
31
A26
A29
34
33
A28
A31
36
35
A30
9
12
11
14
13
16
15
18
17
D48
20
19
D50
22
21
21
D52
24
23
23
D54
26
25
26
25
D56
28
27
D59
28
27
D58
30
29
D61
30
29
D60
32
31
D63
32
31
D62
34
33
34
33
36
35
36
35
38
37
38
37
40
39
40
39
42
41
SDCKE
HDQM
FLAG3_A
DPA
10
CAS
FLAG1_A
SDWE
SDA10
RAS
LDQM
MSSD0
DMAR3_B
IOWR
MSSD1
MSSD3
RESET
L1DATO0_N_A
L1CLKOUT_N_A
FLAG0_A
L1BCMPO_A
FLAG2_A
L1DATI0_N_A
FLAG0_B
L1CLKIN_N_A
38
37
D1
40
39
D0
D3
42
41
D2
42
41
44
43
D5
44
43
D4
44
43
46
45
D7
46
45
D6
46
45
48
47
50
49
52
51
54
53
56
55
FLAG1_B
FLAG3_B
FLAG2_B
L1BCMPI_A
L1DATO0_N_B
L1CLKOUT_N_B
D9
48
47
D8
48
47
D11
50
49
D10
50
49
D13
52
51
D12
52
51
D15
54
53
D14
54
53
D17
56
55
D16
56
55
58
57
D19
58
57
D18
58
57
60
59
D21
60
59
D20
60
59
62
61
D23
62
61
D22
62
61
64
63
D25
64
63
D24
64
63
66
65
D27
66
65
D26
66
65
68
67
D29
68
67
D28
68
67
70
69
D31
70
69
D30
70
69
72
71
D33
72
71
D32
72
71
74
73
D35
74
73
D34
74
73
76
75
D37
76
75
D36
76
75
78
77
D39
78
77
D38
78
77
80
79
D41
80
79
D40
80
79
82
81
D43
82
81
D42
82
81
84
83
D45
84
83
D44
84
83
86
85
IRQ1_A
IRQ3_A
IRQ1_B
IRQ3_B
L1BCMPO_B
L1DATI0_N_B
L1CLKIN_N_B
L1BCMPI_B
IOEN
TMR0E_A
BUSLOCK
HBG
IRQ0_A
BMS
IRQ2_A
MS0
IRQ0_B
MS1
IRQ2_B
ACK
DMAR0
L3ACKI_A
DMAR1_A
L3DATO0_N_A
DMAR2_B
L3BCMPO_A
MSH
DSP A TX
5
6
7
8
IORD
CON_RJ45
MSSD2
BM_B
J5
L3CLKIN_P_A
L1DATO0_P_A
L3CLKIN_N_A
L1CLKOUT_P_A
L3DATI0_P_A
1
2
LABEL "DSP A RX"
3
4
L1ACKI_A
L1DATI0_P_A
L3ACKO_A
L1CLKIN_P_A
L3DATI0_N_A
L1ACKO_A
L3BCMPI_A
DSP A RX
2
5
6
7
8
L1DATO0_P_B
CON_RJ45
L1CLKOUT_P_B
L1ACKI_B
L1DATI0_P_B
L1CLKIN_P_B
J6
L1ACKO_B
BOFF
L3CLKOUT_P_B
L3CLKOUT_N_B
L3DATO0_P_B
1
2
3
LABEL "DSP B TX"
4
L3ACKI_B
HBR
L3DATO0_N_B
L3BCMPO_B
DSP B TX
5
6
7
8
CPA
RD
CON_RJ45
3
WRL
WRH
J7
D47
86
85
88
87
90
45X2
CON019
89
D46
BM_A
BRST
86
85
88
87
L3CLKIN_P_B
88
87
90
89
L3CLKIN_N_B
90
89
L3DATI0_P_B
45X2
CON019
1
2
LABEL "DSP B RX"
3
DSP B RX
4
45X2
CON019
L3ACKO_B
L3DATI0_N_B
L3BCMPI_B
5
6
7
8
CON_RJ45
ANALOG
DEVICES
4
Approvals
Date
Title
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-TS201S EZ-KIT LITE - EXPANSION INT
Drawn
Checked
Engineering
A
B
C
Size
Board No.
C
Date
Rev
A0178-2002
1.1C
Sheet
3-1-2004_10:59
D
11
of
15
A
B
C
D
3.3V
PLACE CLOSE TO OSC
All USB interface circuitry is considered proprietary and has
been omitted from this schematic.
R41
10K
805
U2
1
OE
OUT
3.3V
When designing your JTAG interface please refer to the
Engineer to Engineer Note EE-68 which can be found at
http://www.analog.com
R129
22
805
3
AUDIOCLK
12.288MHZ
OSC003
1
1
R182
10K
805
R213
10K
805
R214
10K
805
R186
4.7K
805
PLACE CLOSE TO FPGA
R205
22
805
3.3V
MCLK
U22
2
MCLK_S
3
USB_TMS
R206
22
805
5
BCLK
BCLK_S
LRCLK
R203
10K
805
LRCLK_S
R181
0.00
805
4
I1A
TMS
I0B
YB
7
U28
2
I1B
11
I0C
10
I1C
14
I0D
13
I1D
USB_TRST
R187
10K
805
YA
6
USB_TCK
R207
22
805
I0A
USB_TDI
YC
9
4
6
YD
12
8
1
S
15
E
D[0:23]
M15
AUDIO_RD
M16
AUDIO_WRL
D6
AUDIO_EN
E14
ADUIO_DMAR
N11
AUDIO_SELECT
RD
WRL
FLAG3_A
DMAR0
2
MS1
L15
AUDIO_DOUT
L14
AUDIO_DIN
T5
AUDIO_BCLK
C1
AUDIO_LRCLK
DT
DR
BCLK_S
LRCLK_S
N14
AUDIO_MCLK
MCLK_S
T9
AUDIOCLK
AUDIO_CLK
R97
0.00
805
PLACE CLOSE TO FPGA PINS (CRITICAL)
H2
DSP_RESET
DSP_RESET
P6
AUDIO_D0
F2
AUDIO_D1
C6
AUDIO_D2
D8
AUDIO_D3
E16
AUDIO_D4
F15
AUDIO_D5
G12
AUDIO_D6
G13
AUDIO_D7
K13
AUDIO_D8
K14
AUDIO_D9
R4
AUDIO_D10
F1
AUDIO_D11
A3
AUDIO_D12
A6
AUDIO_D13
A7
AUDIO_D14
B3
AUDIO_D15
B5
AUDIO_D16
B7
AUDIO_D17
C4
AUDIO_D18
C5
AUDIO_D19
C15
AUDIO_D20
C16
AUDIO_D21
D2
AUDIO_D22
D7
AUDIO_D23
D0
R188
4.7K
805
13
EMU
15
17
D1
ADG774A
QSOP16
D2
P4
1
1A2
1A3
1A4
1
2
D3
19
R230
100
805
L0DATO0_P_A
L0DATO0_N_A
L0DATO0_P_A
L0DATO0_N_A
L0CLKOUT_P_A
R231
100
805
L0CLKOUT_N_A
L0ACKI_A
L0CLKOUT_P_A
L0CLKOUT_N_A
L0BCMPO_A
R233
100
805
L0DATO0_P_B
L0DATO0_N_B
L0DATO0_P_B
L0DATO0_N_B
L0CLKOUT_P_B
R232
100
805
L0CLKOUT_N_B
L0ACKI_B
L0CLKOUT_P_B
L0CLKOUT_N_B
L0BCMPO_B
2A2
2A3
2A4
R211
0.00
805
R212
0.00
805
OE1
3
4
OE2
5
6
SN74LVT244DW
SOIC20
7
8
9
10
11
12
13
14
2
D4
D5
U23
D6
2
D7
D8
3
USB_EMU
5
D9
IDC7X2
7X2
D10
YA
4
I1A
I0B
YB
I1B
11
I0C
10
I1C
14
I0D
13
I1D
D11
D12
D13
D14
DSP JTAG HEADER
D15
I0A
7
6
USB_TDO
U37
YC
10
YD
R184
0.00
805
9
2
OUT_A1
3
OUT_A2
4
OUT_A3
6
OUT_A4
7
OUT_A5
IN_A
12
3.3V
1
S
15
E
D16
9
OE_A
TCK_DSP_A
R185
0.00
805
TCK_DSP_B
D17
R183
10K
805
ADG774A
QSOP16
D18
11
19
OUT_B1
18
OUT_B2
17
OUT_B3
15
OUT_B4
14
OUT_B5
IN_B
D19
D20
D21
12
D22
OE_B
D23
13
MON
3
L4
LA_DATI0_P
L5
LA_DATI0_N
M1
LA_CLKIN_P
N1
LA_CLKIN_N
L3
LA_ACKO
M2
LA_BCOMPI
J2
LB_DATI0_P
J3
LB_DATI0_N
K2
LB_CLKIN_P
K3
LB_CLKIN_N
H1
LB_ACKO
J4
LB_BCOMPI
M3
LA_DATO0_P
M4
LA_DATO0_N
P1
LA_CLKO_P
P2
LA_CLKO_N
N2
LA_ACKI
N3
LA_BCOMPO
L0DATI0_P_A
IDT49FCT3805
QSOP20
L0DATI0_N_A
L0CLKIN_P_A
3.3V
3.3V
3.3V
3.3V
L0CLKIN_N_A
L0ACKO_A
L0BCMPI_A
K4
LB_DATO0_P
K5
LB_DATO0_N
L1
LB_CLKO_P
L2
LB_CLKO_N
J1
LB_ACKI
K1
LB_BCOMPO
L0DATI0_P_B
L0DATI0_N_B
R208
0.00
805
C115
0.1UF
402
C110
0.1UF
402
C121
0.1UF
402
C122
0.1UF
402
TDO_A
TDI_B
L0CLKIN_P_B
R180
0.00
805
DNP
L0CLKIN_N_B
L0ACKO_B
L0BCMPI_B
R209
0.00
805
TDO
12.288MHz
IDT74FCT3244
QS3257
TDO_B
QS3257
ANALOG
DEVICES
4
Approvals
XC2S150E
FT256
Date
Title
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-TS201S EZ-KIT LITE - JTAG/FPGA
Drawn
Checked
Engineering
A
9
2Y1
7
2Y2
5
2Y3
3
2Y4
2A1
DNP
3
TRST
R161
0.00
805
TDI
11
TDO
U20
R210
0.00
805
18
1Y1
16
1Y2
14
1Y3
12
1Y4
1A1
B
C
Size
Board No.
C
Date
Rev
A0178-2002
1.1C
Sheet
3-4-2004_11:17
D
12
of
15
A
B
F1
2.5A
FUS001
3
1
2
D
D2
SCHOT_RECT
3A
DO214AB
FER5
CHOKE_COIL
4
C
UNREG_IN
P3
1
C48
1000PF
1206
2
D1
S2A_RECT
2A
DO-214AA
3
7_5V_POWER
CON005
2.5MM_JACK
FER7
600
1206
MH1
TP2
TP3
TP4
MH2
MH3
MH4
TP5
1
1
FER6
600
1206
C47
1000PF
1206
SHGND
SHGND
SHGND
1.8V
5V
A5V
UNREG_IN
3.3V
R234
332K
805
VR6
7
IN1
8
IN2
6
SD
2
R178
0.00
1206
1
OUT1
2
OUT2
3
OUT3
5
FB
GND
4 ADP3336ARM
MSOP8
FER3
600
1206
VR4
2
INPUT
6
SD
R190
210K
805
C70
1UF
805
3.3V
C54
1UF
805
C72
1UF
805
C73
0.47UF
805
VR3
3
ERR
1
OUTPUT
5
FB
GND
4 ADP3331ART
SOT23-6
R202
0.00
1206
UNREG_IN
C74
0.47UF
805
C71
1UF
805
R228
100K
1206
R192
340K
805
3
CT22
10UF
C
INPUT
2
OUTPUT
GND
1
ADP3339AKC-33
SOT-223
C247
0.1UF
805
CT23
10UF
C
C248
0.1UF
805
2
R201
698K
805
R191
64.9K
805
AGND
2.5V
U35
UNREG_IN
UNREG_IN
D6
CMDSH-3
100MA
SOD-323
R227
10.5K
1206
R219
0.01
2512
VR2
2
VIN
3
C66
0.1UF
805
1.5V
R225
13.0K
1206
C60
2.2UF
805
BOOST
C58
0.18UF
805
1
5
SHDN
SW
8
SYNC
FB
4
GND
7
VC
L5
1.5UH
IND003
R105
2.55K
805
6
C57
2200PF
1206
LT1765
SO-8
D4
SL22
2A
DO-214AA
CT16
100UF
C
R222
10.0K
1206
C61
4.7UF
805
C51
0.1UF
805
CT14
150UF
D
R218
30K
805
C63
0.1UF
805
3
SYNC/FCB
10
SW
TG
3
7
4
8
1.0V
L6
1UH
IND004
3
2
RUN/SS
6
BG
1
5
2
6
3
7
4
8
7
4
VFB
SI9804DY
SOIC8
LTC1773
MSOP10
C53
100PF
1206
D7
CMDSH-3
100MA
SOD-323
6
U36
9
SENSE
1
ITH
5
GND
UNREG_IN
2
VR5
8
VIN
C62
220PF
1206
5
FDS6375
SOIC8
C64
47PF
1206
3
1
R221
80.6K
805
R220
35.7K
805
D3
MBRS340T3
3A
DIO002
CT15
680UF
E
C65
4.7UF
805
C52
100PF
1206
2.5V
VR1
2
VIN
R226
0.00
805
4
C59
2.2UF
805
5
SHDN
3
SW
8
SYNC
6
FB
4
GND
7
VC
LT1765
SO-8
C55
0.18UF
805
1
BOOST
L4
1.5UH
IND003
R189
0.00
1206
R217
10.7K
1206
C56
2200PF
1206
D5
SL22
2A
DO-214AA
R216
10.0K
1206
ANALOG
DEVICES
CT17
100UF
C
C76
4.7UF
805
Approvals
Date
Title
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-TS201S EZ-KIT LITE - POWER
Drawn
Checked
Engineering
A
B
C
Size
Board No.
C
Date
Rev
A0178-2002
1.1C
Sheet
3-1-2004_10:59
D
13
of
15
A
B
C
D
1V_DSP_A
VDD (1.0V) Bypass Caps (per DSP)
(8) 1nF
(4) 0.01uF
(5) 0.1uF
(1) 100uF
C173
1000PF
402
C174
1000PF
402
C175
1000PF
402
C176
1000PF
402
C177
1000PF
402
C178
1000PF
402
C179
1000PF
402
C180
1000PF
402
C219
0.01UF
402
C218
0.01UF
402
C216
0.01UF
402
C220
0.01UF
402
C221
0.1UF
402
C222
0.1UF
402
C223
0.1UF
402
C224
0.1UF
402
C225
0.1UF
402
1
1
1V_DSP_B
ALL BYPASS CAPS SHOULD BE PLACED AS CLOSE AS POSSIBLE TO THE CORISPONDING IC
TRACES FROM COMPONENT TO CAPACITOR AND FROM THE CAPACITOR TO GND SHOULD BE AS SHORT AS POSSIBLE
THE PRIORITY FOR THE PLACEMENT:
1V_DSP_X
1_5V_DSP_X
2_5V_DSP_X
C206
1000PF
402
C196
1000PF
402
C207
1000PF
402
C208
1000PF
402
C209
1000PF
402
C210
1000PF
402
C195
1000PF
402
C211
1000PF
402
C203
0.01UF
402
C204
0.01UF
402
C205
0.01UF
402
C202
0.01UF
402
C201
0.1UF
402
C200
0.1UF
402
C199
0.1UF
402
C198
0.1UF
402
C197
0.1UF
402
2
2
1_5V_DSP_A
1_5V_DSP_B
VDD_DRAM (1.5V) Bypass Caps (per DSP)
(6) 1nF
(2) 0.01uF
(4) 0.1uF
(1) 100uF
C67
1000PF
402
C168
1000PF
402
C169
1000PF
402
C170
1000PF
402
C171
1000PF
402
C172
1000PF
402
C68
0.01UF
402
C167
0.01UF
402
C165
0.1UF
402
C166
0.1UF
402
C75
0.1UF
402
C69
0.1UF
402
C212
1000PF
402
C226
1000PF
402
C217
1000PF
402
C215
1000PF
402
C214
1000PF
402
C213
1000PF
402
2_5V_DSP_A
C232
0.01UF
402
C227
0.01UF
402
C229
0.1UF
402
C228
0.1UF
402
C230
0.1UF
402
C231
0.1UF
402
2_5V_DSP_B
3
3
VDD_IO (2.5V) Bypass Caps (per DSP)
(8) 1nF
(2) 0.01uF
(4) 0.1uF
(1) 100uF
C194
1000PF
402
C193
1000PF
402
C192
1000PF
402
C191
1000PF
402
C190
1000PF
402
C189
1000PF
402
C188
1000PF
402
C186
1000PF
402
C181
0.01UF
402
C183
0.01UF
402
C182
0.1UF
402
C187
0.1UF
402
C185
0.1UF
402
C184
0.1UF
402
C234
1000PF
402
C246
1000PF
402
C236
1000PF
402
C245
1000PF
402
C233
1000PF
402
C244
1000PF
402
C243
1000PF
402
C235
1000PF
402
C242
0.01UF
402
C240
0.01UF
402
ANALOG
DEVICES
4
Approvals
Date
Title
C241
0.1UF
402
C237
0.1UF
402
C238
0.1UF
402
C239
0.1UF
402
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-TS201S EZ-KIT LITE - DSP BYPASS
Drawn
Checked
Engineering
A
B
C
Size
Board No.
C
Date
Rev
A0178-2002
1.1C
Sheet
3-1-2004_10:59
D
14
of
15
A
B
C
D
1
1
3.3V
3.3V
U20
R16
C155
0.1UF
402
C156
0.1UF
402
C157
0.1UF
402
C162
0.1UF
402
C158
0.1UF
402
C159
0.1UF
402
C160
0.1UF
402
C161
0.1UF
402
C154
10UF
805
C99
0.01UF
402
C92
0.01UF
402
C93
0.01UF
402
C94
0.01UF
402
C95
0.01UF
402
C91
10UF
805
R194
10K
805
C100
10UF
805
PROGRAM
A15
PROGRAM_CCLK
A14
PROGRAM_CS
A13
PROGRAM_WR
R195
10K
805
PROGRAM_D0
PROGRAM_D1
PROGRAM_D2
PROGRAM_D3
PROGRAM_D4
T2
FPGA_M0
R1
FPGA_M1
R3
FPGA_M2
SPARTANIIe FPGA
2
2.5V
1.8V
2.5V
C97
0.01UF
402
C98
0.01UF
402
C85
0.01UF
402
C86
0.01UF
402
C87
0.01UF
402
C88
0.01UF
402
C89
0.01UF
402
C90
0.01UF
402
C164
10UF
805
C79
0.1UF
402
C80
0.1UF
402
C81
0.1UF
402
C82
0.1UF
402
C83
0.1UF
402
C84
0.1UF
402
C163
10UF
805
1.8V
SPARTANIIe FPGA
PROGRAM_D6
PROGRAM_D7
E8
3.3V
C96
0.01UF
402
PROGRAM_D5
VCCO1_B0
F7
VCCO2_B0
F8
VCCO3_B0
E9
VCCO4_B1
F9
VCCO5_B1
F10
VCCO6_B1
G11
VCCO7_B2
H11
VCCO8_B2
H12
VCCO9_B2
J11
VCCO10_B3
J12
VCCO11_B3
K11
VCCO12_B3
L9
VCCO13_B4
L10
VCCO14_B4
M9
VCCO15_B4
L7
VCCO16_B5
L8
VCCO17_B5
M8
VCCO18_B5
J5
VCCO19_B6
J6
VCCO20_B6
K6
VCCO21_B6
G6
VCCO22_B7
H5
VCCO23_B7
H6
VCCO24_B7
PROGRAM_INIT
PROGRAM_DONE
D4
D13
3
F14
G15
J14
L13
L16
P16
P15
T15
2
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
C14
E15
A2
FPGA_TCK
C13
FPGA_TDI
B14
FPGA_TDO
B1
FPGA_TMS
SPARTANIIe FPGA
C3
B16
VCCINT1
GND17
VCCINT2
GND18
VCCINT3
GND19
VCCINT4
GND20
E5
VCCINT5
E12
VCCINT6
M5
VCCINT7
M12
VCCINT8
N4
VCCINT9
N13
VCCINT10
P3
VCCINT11
P14
VCCINT12
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
A1
A16
B15
B2
F11
F6
G10
G7
G8
G9
H10
H7
H8
H9
J10
J7
J8
J9
K10
K7
3
K8
K9
L11
L6
R15
R2
T1
T16
XC2S150E
FT256
ANALOG
DEVICES
4
Approvals
Date
Title
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-TS201S EZ-KIT LITE - CONTROLLER
Drawn
Checked
Engineering
A
B
C
Size
Board No.
C
Date
Rev
A0178-2002
1.1C
Sheet
3-1-2004_10:59
D
15
of
15
I
INDEX
A
AD1854 digital-to-analog converter, -xi, 1-11
AD1871 analog-to-digital converter, -x, 1-11
ADSP-TS201S processor
clock frequency, 2-12
core speed, 2-3
core voltage, 2-3
driver modes, 2-14
drive strength, 2-15
external Flash memory, 1-6
impedance selection, 2-14
input clock, 2-3
internal memory, 1-6
memory map, 1-6
SDRAM interface, 1-6
amplification, 2-6
audio
amplification, 2-6
connectors (P1, P2), 2-20
data transfer, 1-11
interface, -xi, 1-11
see also AD1854 and AD1871
B
bill of materials, A-1
~BMS, boot memory select pin, 1-6, 2-3
board peripherals, -x
boot
code, 1-9
memory select pin (~MS0), 2-3
memory space, 1-6
strap settings, 2-7
broadcast, 1-7
bus control configuration, 1-8
C
clock
frequency, 2-12
generator (U1), 2-3, 2-12
modes, 2-12
ratios, 2-12
configuration resistors, 2-10
connectors
diagram of, 1-4, 2-19
J1-J3 (expansion interface), 2-4, 2-21
J4-J7 (link ports), 2-22
P1 (audio), 2-6, 2-20
P2 (audio), 2-20
P4 (JTAG), 2-4, 2-21
P5 (USB), 2-21
contents, EZ-KIT Lite package, 1-2
control impedance, 2-14
CONTROLIMP resistors, 2-14
converters (ADC/DAC), 1-11
core power regulator, 2-2
current limit, 2-4
customer support, -xiv
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
I-1
INDEX
D
F
data
bus (D23-0), 1-11
memory, 1-6
transfer, 1-12
DIP switches, see SW
DMAR0 cycle, 1-11
DRAM, 2-3
drive strength, 2-15
DSP A
drive strength setting, 2-15
processor ID setting, 2-10
processor link ports, 1-11
DSP B
drive strength setting, 2-15
processor ID setting, 2-10
processor link ports, 1-11
features, EZ-KIT Lite board, -x
field-programmable gate arrays (FPGAs), -ix,
1-11, 1-12
FLAG
LEDs (LED3-6), 2-17
pins, 1-9, 2-17, 2-18
push buttons (SW6-9), 2-18
source switch (SW10), 2-9
FLAG0 signal, 1-9, 1-10, 2-18
FLAG1 signal, 1-9, 1-10, 2-18
FLAG2 signal, 1-9, 1-10, 2-17
FLAG3 signal, 1-9, 1-10, 1-11, 2-17
FLAGREG register, 1-9
flash memory
boot memory select pin, 2-3
flash chip described, 1-8
specifications listed, -xi
E
electrostatic discharge, 1-3
emulation
port, 2-4
space, 2-7
SYSCON and SDRCON registers, 1-8
EPROM boot, 2-7
example programs, 1-12
expansion
header, 2-9
interface, 2-3, 2-21
external
interface regulator, 2-3
interrupts, 1-10
memory, -xi, 1-6, 2-4
ports, -xii, 2-3
regulator, 2-3
EZ-KIT Lite board
architecture, 2-2
features, -x
I-2
G
general-purpose IO, -xi
H
Help, online, -xix, 1-13
host, external memory addresses, 1-7
I
interface connectors, -xi
internal
DRAM power regulator, 2-2
memory, 1-6, 1-7, 2-4
interrupt
enable settings, 2-8
modes, 2-8
mode switch (SW10), 2-9
pins, 1-10, 2-18
push buttons (SW4, SW5), 2-18
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
INDEX
IO
general purpose specifications, -xi
power regulator, 2-2
push buttons, 2-18
IRQ0_A (SW4) interrupt pin, 1-10, 2-18
IRQ0_B (SW5) interrupt pin, 1-10, 2-18
J
JTAG
emulation port, 2-4
emulator, -x
header, 2-21
jumper settings, 1-3
L
L0CLKIN pins, 1-12
LEDs
diagram of, 1-4
LED1 (power), 2-16
LED2 (USB reset), 2-17
LED3 (FLAG3_B), 1-9, 1-10, 2-17
LED4 (FLAG2_A), 1-9, 1-10, 2-17
LED5 (FLAG2_B), 1-9, 1-10, 2-17
LED6 (FLAG3_A), 1-9, 1-10, 2-17
LED8 (processor reset), 2-17
LED9 (USB monitor), 1-5, 2-17
license restrictions, 1-6
link ports, 1-11, 2-8
loader file, 1-9
LVDS signaling, 1-11
~MS0, memory bank zero pin, 1-6, 2-3
N
networking cable, 1-12
noise, 1-12
notation conventions, -xxi
O
oscillator (U18), 2-3, 2-12
P
package contents, 1-2
peripheral interfaces, 2-21
power
connector (P3), 2-20
LED (LED1), 2-16
supply, 2-22
processor ID, 1-7, 2-10
programmable FLAG pins
see FLAG pins
program memory, 1-6
push buttons
SW3 (reset), 2-19
SW4-5 (interrupt), 1-10, 2-18
SW6 (FLAG0_B), 1-10, 2-18
SW7 (FLAG1_B), 1-10, 2-18
SW8 (FLAG1_A), 1-10, 2-18
SW9 (FLAG0_A), 1-10, 2-18
R
M
master processor, 2-10
memory
map, see ADSP-TS201S processor
memory blocks, see flash memory, flash chip
described
microphone, 2-6
registering this product, 1-3
registers
SDRAM, 2-3
SDRCON, 1-7, 2-7
SOC, 1-7
SQSTAT, 1-9
SYSCON, 1-7, 2-7
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
I-3
INDEX
reset
LEDs (LED2, LED8), 2-17
push button (SW3), 2-19
resistors
clock mode settings, 2-12
control impedance, 2-14
diagram of, 2-10
locations of, 2-10
RJ-45 connectors
interface connectors, -xi
part numbers and manufacturers, 2-22
TX and RX for DSP A, 1-11
S
SCLKRAT bit, 2-3, 2-12
SDRAM
default values, 1-7
memory, 1-6
registers, 2-3
specification listed, -xi
uses for, -xi
SDRCON registers, 1-7, 2-7
SOC registers, 1-7
specifications, power connector, 2-22
SQSTAT register, 1-9
I-4
switches
location and default settings, 2-5
SW1, 2-6
SW10, 2-9
SW2, -xi, 2-7, 2-8
SW6-9, 1-9, 1-10
SYSCON registers, 1-7, 2-7
system architecture, EZ-KIT Lite board, 2-2
U
USB
cable, 1-3
connector (P7), 2-21
debug monitor, 1-8, 2-7
interface, 2-17
monitor LED (LED9), 2-17
port, -x
V
VisualDSP++
documentation, -xix
Flash Programmer utility, 1-9
online Help, -xix
voltage regulators, -xi
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
INDEX
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
I-5