AN-616
APPLICATION NOTE
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AD9430 Evaluation Board Modifications for XTAL Oscillator Clocking
by Gary Hendrickson and Chad Shelton
INTRODUCTION
The AD9430-170/210-CMOS evaluation board is designed
to accommodate clocking from an external signal source
or an on-board XTAL oscillator. The board, as shipped,
interfaces with a single-ended 1 V p-p sine wave source
applied to SMA J5 on the board. This signal is converted
to differential LVPECL levels by an on-board differential
receiver, an LVEL16.
Figure 1. Place two 50  (R22, R24) terminations to ground
at the outputs of the XTAL. The Enable pin on the XTAL
should be connected by placing a 100  resistor to ground
(R15). Figure 4 shows the final configuration of the board.
Power for the crystal is supplied using the VCLK_VXTAL pin
on the power terminal block. Place a 0.1 µF capacitor for C14.
R38, R21, and R23 are not needed for this XTAL.
The board can be modified as follows:
5
6
4
VCC OUTPUT OUTPUT
The differential receiver must be removed and solder
bridges must be placed at the far end of the XTAL oscillator output traces as shown in Figure 1.
VECTRON JN00158
E/D
1
Figure 1. Place Required Solder Bridges at End of Traces
(Under the LVEL16 Part)
GND
1
E/D
2
NC
3
GND
GND
VCC 6
5
OUTPUT
4
OUTPUT
U8
GND
3
Figure 3. Vectron XTAL Pinout
SOLDER HERE
R15
100
NC
2
R21
R22
R24
R23
VCLK
C14
P1
R22
50
GND
6
5
4
1
2
3
P2
OPTIONAL XTAL
R24
50
GND
Figure 2. Schematic Using the Vectron JN00158 XTAL
The Vectron XTAL schematic is shown in Figure 2. To use
the Vectron oscillator, remove the LVEL16, R19, and R20
from the board and connect the solder bridges as shown in
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Figure 4. Board Layout of the Vectron XTAL
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VCLK
VCC 6
5
4
OUTPUT
U8
GND
VCLK
P1
OPTIONAL XTAL
1
VO–
VF561
R22
100 VCLK
GND
R38 FOR
VF561 CRYSTAL
2
GND
R21
100
VO+
3
R23
100
P2
VCC
4
E03271–0–12/02(0)
R38
100
1
OUTPUT
2
3
GND
Figure 6. Valpey-Fisher VF561 Pinout
R24
100
GND
Figure 5. Schematic Using the Valpey-Fisher VF561
XTAL USING THE VALPEY-FISHER XTAL
The Valpey-Fisher schematic is shown in Figure 5. To use
the Valpey-Fisher oscillator, remove the LVEL16, R19, and
R20 from the board and connect the solder bridges as
shown in Figure 1. R21, R22, R23, and R24 values can be
adjusted to maintain a 50  Thevenin equivalent termination to VCLK-2V if desired. (The outputs are ac-coupled at
the ADC clock inputs.)
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Place a 0  or short across R38 for VO–. Figure 7 shows
the final configuration of the board. Power for the crystal
is supplied using the VCLK_VXTAL pin on the power terminal block. Place a 0.1 µF capacitor for C14. R15 is not
needed for this XTAL.
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The VF561 is available in a wide range of frequencies
(15 MHz to 300 MHz) allowing for a variety of sample
rates to be used and characterized. The low jitter
(1 ps rms max) is sufficient to meet the AD9430 clocking
requirements in most applications.
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PRINTED IN U.S.A.
Figure 7. Board Layout of the Valpey-Fisher VF561
© 2002 Analog Devices, Inc. All rights reserved. Trademarks and registered
trademarks are the property of their respective companies.
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