10-Bit, 170/200 MSPS
3.3 V A/D Converter
AD9411
Data Sheet
FEATURES
B
SO
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
SENSE VREF AGND DRGND DRVDD AVDD
SCALABLE
REFERENCE
TE
AD9411
VIN+
VIN–
TRACK
AND
HOLD
ADC
10
10-BIT
PIPELINE /
CORE
CLK+
CLK–
CLOCK
MANAGEMENT
LVDS
OUTPUTS
LVDS TIMING
DATA,
OVERRANGE
IN LVDS
DCO+
DCO–
S1
S5
04530-0-001
APPLICATIONS
FUNCTIONAL BLOCK DIAGRAM
LE
SNR = 60 dB @ fIN up to 70 MHz @ 200 MSPS
ENOB of 9.8 @ fIN up to 70 MHz @ 200 MSPS (–0.5 dBFS)
SFDR = 80 dBc @ fIN up to 70 MHz @ 200 MSPS (–0.5 dBFS)
Excellent linearity:
DNL = ±0.15 LSB (typical)
INL = ±0.25 LSB (typical)
LVDS output levels
700 MHz full-power analog bandwidth
On-chip reference and track-and-hold
Power dissipation = 1.25 W typical @ 200 MSPS
1.5 V input voltage range
3.3 V supply operation
Output data format option
Clock duty cycle stabilizer
Pin compatible to LVDS mode AD9430
Figure 1.
PRODUCT HIGHLIGHTS
The AD9411 is a 10-bit monolithic sampling analog-to-digital
converter optimized for high performance, low power, and ease
of use. The product operates up to a 200 MSPS conversion rate
and is optimized for outstanding dynamic performance in
wideband carrier and broadband systems. All necessary
functions, including track-and-hold (T/H) and reference, are
included on the chip to provide a complete conversion solution.
1.
High performance.
Maintains 60 dB SNR @ 200 MSPS with a 70 MHz input.
2.
Low power.
Consumes only 1.25 W @ 200 MSPS.
3.
Ease of use.
LVDS output data and output clock signal allow interface
to current FPGA technology. The on-chip reference and
sample-and-hold function provide flexibility in system
design. Use of a single 3.3 V supply simplifies system
power supply design.
4.
Out-of-range (OR).
The OR output bit indicates when the input signal is
beyond the selected input range.
O
GENERAL DESCRIPTION
The ADC requires a 3.3 V power supply and a differential
sample clock for full performance operation. The digital outputs
are LVDS compatible and support both twos complement and
offset binary format. A data clock output is available to ease
data capture.
Fabricated on an advanced BiCMOS process, the AD9411 is
available in a 100-lead surface-mount plastic package (e-PAD
TQFP-100) specified over the industrial temperature range
(–40°C to +85°C).
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.
AD9411
Data Sheet
TABLE OF CONTENTS
Clock Outputs (DCO+, DCO–) ............................................... 19 AC Specifications .............................................................................. 4 Voltage Reference ....................................................................... 19 Digital Specifications........................................................................ 5 Noise Power Ratio Testing (NPR) ............................................ 19 Switching Specifications .................................................................. 6 Evaluation Board ............................................................................ 21 Explanation of Test Levels ........................................................... 6 Power Connector........................................................................ 21 Absolute Maximum Ratings............................................................ 7 Analog Inputs ............................................................................. 21 ESD Caution .................................................................................. 7 Gain .............................................................................................. 21 Pin Configuration and Function Descriptions ............................. 8 Clock ............................................................................................ 21 Terminology .................................................................................... 10 Voltage Reference ....................................................................... 21 Equivalent Circuits ......................................................................... 12 Data Format Select ..................................................................... 21 Typical Performance Characteristics ........................................... 13 Data Outputs ............................................................................... 21 LE
TE
DC Specifications ............................................................................. 3 Application Notes ........................................................................... 18 CLOCK XTAL ............................................................................ 21 Clock Input .................................................................................. 18 Outline Dimensions ....................................................................... 27 Analog Input ............................................................................... 18 Ordering Guide .......................................................................... 27 B
SO
LVDS Outputs ............................................................................. 19 REVISION HISTORY
1/12—Data Sheet Changed from Rev. A to Rev. B
Added Exposed Pad Notation to Figure 3 ..................................... 8
Added Pin 55 to Table 6 ................................................................... 9
Changes to Ordering Guide .......................................................... 27
O
7/04—Data Sheet Changed from Rev. 0 to Rev. A
Added 200 MSPS Grade .................................................... Universal
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 27
1/04—Revision 0: Initial Version
Rev. B | Page 2 of 28
Data Sheet
AD9411
DC SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V, unless
otherwise noted.
Table 1.
AD9411-170
TEMPERATURE DRIFT
Offset Error
Gain Error
Reference Out (VREF)
Full
25°C
25°C
25°C
Full
25°C
Full
VI
I
I
I
VI
I
VI
Guaranteed
–3
–5
–0.5
± 0.15
–0.6
± 0.25
–0.8
± 0.5
–1
± 0.5
Full
Full
Full
V
V
V
58
0.02
+0.12/
–0.24
25°C
25°C
25°C
25°C
I
IV
I
I
1.15
O
B
SO
REFERENCE
Reference Out (VREF)
Output Current1
IVREF Input Current2
ISENSE Input Current2
ANALOG INPUTS (VIN+, VIN–)3
Differential Input Voltage Range
(S5 = GND)
Differential Input Voltage Range
(S5 = AVDD)
Input Common-Mode Voltage
Input Resistance
Input Capacitance
POWER SUPPLY (LVDS Mode)
AVDD
DRVDD
Supply Currents
IANALOG (AVDD = 3.3 V)4
IDIGITAL (DRVDD = 3.3 V)4
Power Dissipation4
Power Supply Rejection
Min
Typ
12
Max
Min
Typ
12
+3
+5
+0.5
+0.6
+0.8
+1
Guaranteed
–3
–5
–0.5
± 0.15
–0.6
± 0.25
–0.8
± 0.5
–1
± 0.5
TE
Integral Nonlinearity (INL)
Temp
AD9411-200
LE
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Test
Level
1.235
1.6
1.3
3.0
20
5.0
Max
Unit
Bits
+3
+5
+0.5
+0.6
+0.8
+1
mV
% FS
LSB
LSB
LSB
LSB
58
0.02
+0.12/
–0.24
1.15
1.235
1.6
μV/°C
%/°C
mV/°C
1.3
3.0
20
5.0
V
mA
mA
mA
Full
V
1.536
1.536
V
Full
V
0.766
0.766
V
Full
Full
25°C
VI
VI
V
2.65
2.2
2.8
3
5
2.9
3.8
2.65
2.2
2.8
3
5
2.9
3.8
V
kΩ
pF
Full
Full
IV
IV
3.1
3.0
3.3
3.3
3.6
3.6
3.2
3.0
3.3
3.3
3.6
3.6
V
V
Full
Full
Full
25°C
VI
VI
VI
V
335
49
1.27
–7.5
372
57
1.42
385
49
1.43
–7.5
425
57
1.59
mA
mA
W
mV/V
1
Internal reference mode; SENSE = floats.
External reference mode; SENSE = DRVDD; VREF driven by external 1.23 V reference.
3
S5 (Pin 1) = GND. See the Analog Input section. S5 = GND in all dc, ac tests, unless otherwise specified
4
IAVDD and IDRVDD are measured with an analog input of 10.3 MHz, –0.5 dBFS, sine wave, rated clock rate, and in LVDS output mode. See the Typical Performance
Characteristics and Application Notes sections for IDRVDD. Power consumption is measured with a dc input at rated clock rate in LVDS output mode.
2
Rev. B | Page 3 of 28
AD9411
Data Sheet
AC SPECIFICATIONS1
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V, unless
otherwise noted.
Table 2.
AD9411-170
Temp
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Typ
I
I
V
V
59
59
I
I
V
V
58.5
58.5
2
O
1
AD9411-200
Max
Min
Typ
60.2
60.1
60
59.1
59
59
60.2
60.1
60
59.1
dB
dB
dB
dB
60
60
59.5
57.5
58.5
58.5
60
60
59.5
57.5
dB
dB
dB
dB
9.5
9.5
9.8
9.8
9.7
9.3
Bits
Bits
Bits
Bits
LE
25°C
25°C
25°C
25°C
I
I
V
V
Max
TE
Min
9.5
9.5
B
SO
Parameter
SNR
Analog Input @ –0.5 dBFS
10 MHz
70 MHz
100 MHz
240 MHz
SINAD
Analog Input @ –0.5 dBFS
10 MHz
70 MHz
100 MHz
240 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
10 MHz
70 MHz
100 MHz
240 MHz
WORST HARMONIC (Second or Third)
Analog Input @ –0.5 dBFS 10 MHz
10 MHz
70 MHz
100 MHz
240 MHz
WORST HARMONIC (Fourth or Higher)
Analog Input @ –0.5 dBFS 10 MHz
10 MHz
70 MHz
100 MHz
240 MHz
TWO-TONE IMD2
F1, F2 @ –7 dBFS
ANALOG INPUT BANDWIDTH
Test
Level
9.8
9.8
9.7
9.3
Unit
25°C
25°C
25°C
25°C
I
I
V
V
–80
–80
−74
−69
–73
–73
–80
–80
−74
−69
–70
–70
dBc
dBc
dBc
dBc
25°C
25°C
25°C
25°C
I
I
V
V
–82
–82
−76
−70
–75
–75
–82
–82
−76
−70
–75
–75
dBc
dBc
dBc
dBc
25°C
25°C
V
V
70
700
All ac specifications tested by driving CLK+ and CLK– differentially.
F1 = 30.5 MHz, F2 = 31 MHz.
Rev. B | Page 4 of 28
70
700
dBc
MHz
Data Sheet
AD9411
DIGITAL SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 3.
1
Test Level
Min
Full
Full
Full
25°C
IV
VI
VI
V
0.2
1.375
3.2
Full
Full
Full
Full
25°C
25°C
IV
IV
VI
VI
V
V
2.0
Full
Full
VI
VI
AD9411-170
Typ
Max
1.5
5.5
4
0.2
1.375
3.2
AD9411-200
Typ
1.5
5.5
4
Max
Unit
1.575
6.5
V
V
kΩ
pF
2.0
0.8
190
10
30
4
247
454
1.125
1.375
Twos Complement or Binary
See the Equivalent Circuits section.
All ac specifications tested by driving CLK+ and CLK– differentially, |(CLK+) – (CLK–)| > 200 mV.
3
Clock inputs’ common mode can be externally set, such that 0.9 V < CLK< 2.6 V.
4
LVDS RTERM = 100 Ω, LVDS output current set resistor (RSET) = 3.74 kΩ(1% tolerance).
O
B
SO
2
1.575
6.5
Min
TE
Temp
Rev. B | Page 5 of 28
0.8
190
10
30
4
LE
Parameter
CLOCK INPUTS
(CLK+, CLK–)1
Differential Input Voltage2
Common-Mode Voltage3
Input Resistance
Input Capacitance
LOGIC INPUTS (S1, S2, S4, S5)
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Input Current
Logic 0 Input Current
Input Resistance
Input Capacitance
LVDS LOGIC OUTPUTS4
VOD Differential Output Voltage
VOS Output Offset Voltage
Output Coding
247
454
1.125
1.375
Twos Complement or Binary
V
V
μA
μA
kΩ
pF
mV
V
AD9411
Data Sheet
SWITCHING SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 4.
Maximum Conversion Rate1
Minimum Conversion Rate1
CLK+ Pulse Width High (tEH)1
CLK+ Pulse Width Low (tEL)1
OUTPUT (LVDS Mode)
Valid Time (tV)
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
DCO Propagation Delay (tCPD)
Data to DCO Skew (tPD–tCPD)
Latency
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Full
Full
Full
Full
Test
Level
VI
V
IV
IV
Full
Full
25°C
25°C
Full
Full
Full
25°C
25°C
VI
VI
V
V
VI
IV
IV
V
V
Out-of-Range Recovery Time
25°C
V
All ac specifications tested by driving CLK+ and CLK– differentially.
AD9411-170
Typ
Max
170
Min
AD9411-200
Typ
Max
Unit
200
40
12.5
12.5
2
2
2.0
MSPS
MSPS
ns
ns
40
12.5
12.5
2
2
2.0
3.2
0.5
0.5
2.7
0.5
14
1.2
0.25
1.8
0.2
4.3
3.8
0.8
1
1.8
0.2
3.2
0.5
0.5
2.7
0.5
14
1.2
0.25
ns
ns
ns
ns
ns
ns
Cycles
ns
ps
rms
Cycles
4.3
3.8
0.8
1
B
SO
1
Min
TE
Temp
LE
Parameter (Conditions)
EXPLANATION OF TEST LEVELS
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100%
production tested at temperature extremes for military devices.
N–1
O
N
N+1
AIN
tEL
tEH
1/fS
CLK+
CLK–
tPD
N–14
DATA OUT
N–13
N
N+1
14 CYCLES
DCO+
04530-0-002
DCO–
tCPD
Figure 2. LVDS Timing Diagram
Rev. B | Page 6 of 28
Data Sheet
AD9411
ABSOLUTE MAXIMUM RATINGS
Table 5.
1
Rating
4V
–0.5 V to AVDD +0.5 V
–0.5 V to DRVDD +0.5 V
–0.5 V to AVDD +0.5 V
20 mA
–55ºC to +125°C
–65ºC to +150°C
150°C
150°C
25°C/W, 32°C/W
Typical θJA = 32°C/W (heat slug not soldered); typical θJA = 25°C/W (heat slug
soldered) for multilayer board in still air with solid ground plane.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions outside of those indicated in the operation
section of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect
device reliability.
TE
Parameter
AVDD, DRVDD
Analog Inputs
Digital Inputs
REFIN Inputs
Digital Output Current
Operating Temperature
Storage Temperature
Maximum Junction Temperature
Maximum Case Temperature
θJA1
O
B
SO
LE
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 7 of 28
AD9411
Data Sheet
AVDD
AVDD
AGND
AGND
AVDD
AVDD
AGND
AGND
AGND
AVDD
AVDD
AVDD
AGND
AGND
OR+
OR–
DVRDD
DRGND
D9+
D9–
D8+
D8–
D7+
D7–
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
1
75
DRVDD
2
74
3
73
DRGND
D6+
AGND
4
72
D6–
AVDD
5
71
D5+
S1
6
70
D5–
LVDSBIAS
7
69
D4+
AVDD
8
68
D4–
AGND
9
67
DRGND
66
D3+
65
D3–
64
DCO+
63
DCO–
62
61
DRVDD
DRGND
60
D2+
59
D2–
58
57
D1+
D1–
56
D0+
55
D0–
54
DRVDD
53
DRGND
52
DNC
51
DNC
TE
S5
DNC
AGND
SENSE 10
VREF 11
AGND 12
AD9411
AGND 13
TOP VIEW
(Not to Scale)
LE
AVDD 14
AVDD 15
AGND 16
AGND 17
AVDD 18
AVDD 19
AGND 20
VIN+ 21
VIN– 22
AGND 23
B
SO
AVDD 24
DNC 50
DNC 49
DRGND 48
47
DRVDD
DNC 46
DNC 45
DNC 44
DNC 43
DNC 42
AGND 41
AVDD 40
AVDD 39
AGND 38
CLK– 37
CLK+ 36
AGND 35
AVDD 34
AVDD 33
AGND 32
AGND 31
AGND 30
AVDD 29
AVDD 28
AVDD 27
AGND 26
AGND 25
NOTES
1. THE AD9411 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE
DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
O
Figure 3. TQFP_EP Pinout
Rev. B | Page 8 of 28
04530-0-003
100 AGND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
AD9411
Table 6. Pin Function Descriptions
Mnemonic
S5
2, 42–46,49–52
3, 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31,
32, 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100
5, 8, 14, 15, 18, 19, 24, 27, 28, 29, 33, 34,
39, 40, 88, 89, 90, 94, 95, 98, 99
6
7
DNC
AGND
10
11
21
22
36
37
47, 54, 62, 75, 83
48, 53, 61, 67, 74, 82
SENSE
VREF
VIN+
VIN–
CLK+
CLK–
DRVDD
DRGND
55
56
57
58
59
60
63
64
65
66
68
69
70
71
72
73
76
77
78
79
80
81
84
85
D0–
D0+
D1–
D1+
D2–
D2+
DCO–
DCO+
D3–
D3+
D4–
D4+
D5–
D5+
D6–
D6+
D7–
D7+
D8–
D8+
D9–
D9+
OR–
OR+
AVDD
Data Format Select. GND = binary; AVDD = twos complement.
Set Pin for LVDS Output Current. Place a 3.74 kΩ resistor terminated to
ground.
Reference Mode Select Pin. Float for internal reference operation.
1.235 V Reference Input/Output. Function depends on SENSE.
Analog Input. True.
Analog Input. Complement.
Clock Input. True (LVPECL levels).
Clock Input. Complement (LVPECL levels).
3.3 V Digital Output Supply (3.0 V to 3.6 V).
Digital Output Ground. AGND and DRGND should be tied together to a
common ground plane.
D0 Complement Output Bit.
D0 True Output Bit.
D1 Complement Output Bit.
D1 True Output Bit.
D2 Complement Output Bit.
D2 True Output Bit.
Data Clock Output. Complement.
Data Clock Output. True.
D3 Complement Output Bit.
D3 True Output Bit.
D4 Complement Output Bit.
D4 True Output Bit.
D5 Complement Output Bit.
D5 True Output Bit.
D6 Complement Output Bit.
D6 True Output Bit.
D7 Complement Output Bit.
D7 True Output Bit.
D8 Complement Output Bit.
D8 True Output Bit.
D9 Complement Output Bit.
D9 True Output Bit.
Overrange Complement Output Bit.
Overrange True Output Bit.
O
B
SO
LE
S1
LVDSBIAS
Function
Full-Scale Adjust Pin. AVDD sets FS = 0.768 V p-p differential;
GND sets FS = 1.536 V p-p differential.
Do Not Connect.
Analog Ground. AGND and DRGND should be tied together to a common
ground plane.
3.3 V Analog Supply.
TE
Pin No.
1
Rev. B | Page 9 of 28
AD9411
Data Sheet
TERMINOLOGY
Clock Pulse Width/Duty Cycle
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
The delay between the 50% point of the rising edge of the clock
command and the instant at which the analog input is sampled.
Pulse width high is the minimum amount of time the clock
pulse should be left in the Logic 1 state to achieve rated
performance; pulse width low is the minimum time the clock
pulse should be left in the low state. Refer to the timing
implications of changing tENCH in the Application Notes, Clock
Input section. At a given clock rate, these specifications define
an acceptable CLOCK duty cycle.
Aperture Uncertainty (Jitter)
Full-Scale Input Power
The sample-to-sample variation in aperture delay.
Expressed in dBm. Computed using the following equation:
Aperture Delay
TE
Analog Bandwidth
Crosstalk
Coupling onto one channel being driven by a low level (–40 dBFS)
signal when the adjacent interfering channel is driven by a fullscale signal.






LE
PowerFULLSCALE

V 2
FULLSCALE RMS
 10 log
Z INPUT


0.001

Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
Gain Error
The difference between the measured and ideal full-scale input
voltage range of the ADC.
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Harmonic Distortion, Second
B
SO
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180°
out of phase. Peak-to-peak differential is computed by rotating
the input’s phase 180° and again taking the peak measurement.
The difference is then computed between both peak
measurements.
O
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB)
Calculated from the measured SNR based on the equation
SNRMEASURED  1.76 dB
ENOB 
6.02
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Minimum Conversion Rate
The CLOCK rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Maximum Conversion Rate
The CLOCK rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of CLK+ and CLK–
and the time when all output data bits are within valid logic
levels.
Rev. B | Page 10 of 28
Data Sheet
AD9411
Noise (for Any Range within the ADC)
Two-Tone Intermodulation Distortion Rejection
Calculated as follows:
The ratio of the rms value of either input tone to the rms value of
the worst third-order intermodulation product, reported in dBc.
 SNRdBc  Signal dBFS 
 FS
V NOISE  Z  0.001  10 dBM

10


Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered) or in dBFS (always
related back to converter full scale).
Power Supply Rejection Ratio (PSRR)
Worst Other Spur
TE
where Z is the input impedance, FS is the full scale of the device
for the frequency in question, SNR is the value of the particular
input level, and Signal is the signal level within the ADC reported
in dB below full scale. This value includes both thermal and
quantization noise.
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonics) reported in dBc.
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
Transient Response Time
Signal-to-Noise Ratio (without Harmonics)
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above negative full scale to 10%
below positive full scale.
LE
The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics but excluding dc.
Out-of-Range Recovery Time
B
SO
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above positive full scale to 10% above
negative full scale, or from 10% below negative full scale to 10%
below positive full scale.
O
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered) or dBFS (always related
back to converter full scale).
Rev. B | Page 11 of 28
AD9411
Data Sheet
EQUIVALENT CIRCUITS
AVDD
FULL
SCALE
K
12k
12k
0.1F
CLK+
VREF
CLK–
150
150
A1
1V
10k
200
DISABLE
A1
VDD
TE
Figure 4. Clock Inputs
AVDD
Figure 7. VREF, SENSE I/O
3.5k
3.5k
SENSE
1k
VIN–
LE
VIN+
20k
04530-0-005
20k
Figure 5. Analog Inputs
30k
04530-0-006
S1,S5
B
SO
VDD
O
Figure 6. S1 to S5 Inputs
Rev. B | Page 12 of 28
V+
V–
DX–
DX+
V–
V+
Figure 8. Data Outputs
04530-0-008
DRVDD
04530-0-007
04530-0-004
10k
Data Sheet
AD9411
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
–10
–10
SNR = 60.1dB
SINAD = 59.9dB
H2 = –91.3dBc
H3 = –75.2dBc
SFDR = 75.3dBc
–30
–30
–40
–50
–60
–60
dB
–50
–70
–70
–80
–80
–90
–100
–100
–110
–110
–120
0
10
20
30
40
50
60
70
80
MHz
–120
0
20
30
40
50
MHz
60
70
0
0
–10
LE
–10
SNR = 59.8dB
SINAD = 59.8dB
H2 = –91.9dBc
H3 = –80.6dBc
SFDR = 73.2dBc
–20
–30
–40
–20
–30
80
90
100
SNR = 59.5dB
SINAD = 59.4dB
H2 = –82.5dBc
H3 = –72.8dBc
SFDR = 72.7dBc
–40
–50
–50
dB
–60
–60
–70
–110
–120
0
10
20
30
40
50
60
70
80
MHz
–90
–100
–110
–120
0
0
O
–30
–40
dB
–70
–70
–80
–80
–90
–100
–100
–110
–110
–120
50
60
70
80
MHz
04530-0-011
–90
40
70
80
90
100
SNR = 50.6dB
SINAD = 43.8dB
H2 = –44.8dBc
H3 = –67.4dBc
SFDR = 43.6dBc
–40
–60
30
60
–30
–60
20
50
MHz
–20
–50
10
40
0
–50
0
30
–10
SNR = 59.2dB
SINAD = 59.1dB
H2 = –70.1dBc
H3 = –87.0dBc
SFDR = 69.8dBc
–20
20
Figure 13. FFT: fS = 200 MSPS, AIN = 65 MHz @ −0.5 dBFS
Figure 10. FFT: fS = 170 MSPS, AIN = 65 MHz @ –0.5 dBFS
–10
10
04530-A-002
–100
–80
–120
0
10
20
30
40
50
MHz
60
70
80
90
100
Figure 14. FFT: fS = 200 MSPS, AIN = 70 MHz @ −0.5 dBFS,
Single-Ended Drive, 1.5 V Input Range
Figure 11. FFT: fS = 170 MSPS, AIN = 10.3, MHz @ –0.5 dBFS,
Single-Ended Input, 0.76 V Input Range
Rev. B | Page 13 of 28
04530-A-003
–90
04530-0-010
–80
B
SO
–70
dB
10
Figure 12. FFT: fS = 200 MSPS, AIN = 10.3 MHz @ −0.5 dBFS
Figure 9. FFT: fS = 170 MSPS, AIN = 10.3 MHz @ −0.5 dBFS
dB
TE
–90
04530-0-009
dB
–40
–20
04530-A-001
–20
SNR = 59.7dB
SINAD = 59.5dB
H2 = –83.6dBc
H3 = –72.6dBc
SFDR = 72.5dBc
AD9411
Data Sheet
100
0
–10
SFDR = 71.5dBc
90
–20
–30
80
–40
THIRD
–50
SECOND
dB
dB
SFDR
70
–60
–70
60
–80
50
–100
–90
–110
100
150
200
250
300
350
400
AIN (MHz)
–120
0
20
30
40
50
60
70
80
MHz
Figure 15. Harmonic Distortion (Second and Third) and SFDR vs. AIN
Frequency @ 170 MSPS
Figure 18. Two-Tone Intermodulation Distortion
(30.5 MHz and 31.0 MHz; fS = 170 MSPS)
100
0
–20
SECOND
–40
70
THIRD
SFDR
–60
SFDR = 78.8dBc
–80
50
100
150
200
(MHz)
250
300
350
400
0
57
10
20
30
40
50
(MHz)
60
70
80
90
Figure 19. Two-Tone Intermodulation Distortion
(69.3 MHz and 70.3 MHz; fS = 200 MSPS)
80
SNR_170
59
250
–120
Figure 16. Harmonic Distortion (Second and Third) and SFDR vs. AIN
Frequency @ 200 MSPS
61
100
04530-A-004
0
04530-A-008
40
–100
04530-A-006
50
B
SO
60
(dB)
80
LE
90
(dB)
10
04530-0-019
50
TE
0
04530-0-015
40
SFDR_170
75
70
SNR_200
51
SINAD_170
(dB)
53
60
50
47
45
45
100
150
200
250
(MHz)
300
350
400
450
04530-A-007
49
50
SINAD_200
55
SINAD_200
0
SFDR_200
65
SINAD_170
O
(dB)
55
40
0
50
100
150
200
(MSPS)
Figure 20. SINAD and SFDR vs. Clock Rate
(AIN = 10.3 MHz @ –0.5 dBFS) 170/200 grade
Figure 17. SNR and SINAD vs. AIN Frequency; fS = 170/200 MSPS,
AIN @ –0.5 dBFS Full Scale = 1.536 V
Rev. B | Page 14 of 28
Data Sheet
AD9411
90
300
60
250
50
40
OUTPUT SUPPLY
CURRENT
150
30
100
20
50
0
100
10
120
140
160
180
200
220
0
240
ENCODE (MSPS)
400
80
350
70
60
ANALOG SUPPLY CURRENT
250
50
200
40
OUTPUT SUPPLY CURRENT
30
150
20
100
0
100
50
20
10
120
140
160
180
200
SAMPLE RATE (MSPS)
73
71
69
1.2
RO = 13 TYP
1.0
220
0
240
0.8
0.6
0.4
0.2
0
0
2
63
61
4
5
6
7
8
Figure 25. VREFOUT vs. ILOAD (Both Speed Grades)
80
SFDR
75
70
(dB)
65
3
ILOAD (mA)
65
SNR
60
SINAD
55
SINAD
59
55
20
30
40
50
60
70
80
ENCODE POSITIVE DUTY CYCLE (%)
90
Figure 23. SINAD and SFDR vs. Clock Pulse Width High
(AIN = 10.3 MHz @ –0.5 dBFS, 170 MSPS)
50
0.5
0.7
0.9
1.1
1.3
1.5
VREF (V)
Figure 26. Sinad, SFDR vs. VREF in External Reference Mode
(AIN = 70 MHz @ –0.5 dBFS, 200 MSPS)
Rev. B | Page 15 of 28
04530-A-011
57
04530-0-025
dB
1
SFDR
O
67
80
1.4
Figure 22. IAVDD and IDRVDD vs. Clock Rate, 200 MSPS Grade, CLOAD = 5 pF
(AIN = 10.3 MHz @ –0.5 dBFS)
75
30
40
50
60
70
SAMPLE CLOCK POSITIVE DUTY CYCLE
Figure 24. SINAD and SFDR vs. Clock Pulse Width High
(AIN = 10.3 MHz @ –0.5 dBFS, 200 MSPS)
04530-A-009
50
SINAD
55
VREF (V)
300
SNR
LE
90
IDRVDD OUTPUT SUPPLY CURRENT (mA)
450
65
60
B
SO
IAVDD ANALOG SUPPLY CURRENT (mA)
Figure 21. IAVDD and IDRVDD vs. Clock Rate, 170 MSPS Grade, CLOAD = 5 pF
(AIN = 10.3 MHz @ –0.5 dBFS)
SFDR
70
04530-A-016
200
75
04530-A-010
70
TE
350
(dB)
80
ANALOG SUPPLY
CURRENT
IDRVDD OUTPUT SUPPLY CURRENT (mA)
400
80
04530-2-023
IAVDD ANALOG SUPPLY CURRENT (mA)
450
Data Sheet
2.0
90
1.5
85
1.0
80
0.5
75
% GAIN ERROR
USING EXT REF
0
SFDR
dB
GAIN ERROR (%)
AD9411
70
–0.5
65
–1.0
60
–1.5
55
SNR
–10
10
30
50
70
90
TEMPERATURE (°C)
50
–50
–10
10
30
50
70
90
TEMPERATURE (°C)
Figure 27. Full-Scale Gain Error vs. Temperature
(AIN = 10.3 MHz @ –0.5 dBFS, 170/200 MSPS)
60
–30
TE
–30
04530-0-028
–2.0
–50
04530-0-030
SINAD
Figure 30. SNR, SINAD, and SFDR vs. Temperature
(AIN = 10.3 MHz @ –0.5 dBFS, 170 MSPS)
1.00
AVDD = 3.6V
0.75
59
LE
0.50
AVDD = 3.3V
(dB)
0.25
LSB
AVDD = 3.15V
58
0
57
–0.25
AVDD = 3.0V
–0.50
0
20
40
TEMPERATURE (°C)
60
80
–0.75
–1.00
0
O
400
500
600
700
800
900
1000
Figure 31. Typical INL Plot
(AIN = 10.3 MHz @ –0.5 dBFS, 170/200 MSPS)
1.0
0.8
0.6
0.4
LSB
0
–0.2
1.235
–0.4
–0.6
1.230
2.7
2.9
3.1
3.3
3.5
3.7
3.9
–0.8
–1.0
0
200
300
400
500
CODE
AVDD (V)
Figure 29. VREF Output Voltage vs. AVDD (Both Speed Grades)
100
600
700
800
900
1000
04530-0-033
1.225
2.5
300
0.2
1.240
04530-0-029
VREFOUT (V)
1.245
200
CODE
Figure 28. SINAD vs. Temperature and AVDD
(AIN = 10.3 MHz @ –0.5 dBFS, 200 MSPS)
1.250
100
04530-0-032
–20
04530-A-012
55
–40
B
SO
56
Figure 32. Typical DNL Plot (AIN = 10.3 MHz @ –0.5 dBFS) 170/200 MSPS
Rev. B | Page 16 of 28
Data Sheet
AD9411
0
110
NPR = 51 dB
CLK = 200MSPS
NOTCH AT 18.5MHz
100
–20
90
SFDR –dBFS
80
–40
60
dB
dB
70
50
40
80dB
REFERENCE LINE
30
–60
–80
SFDR –dBc
20
–100
–70
–60
–50
–40
–30
–20
–10
0
ANALOG INPUT LEVEL (dBFS)
Figure 33. SFDR vs. AIN Input Level 10.3 MHz, AIN @ 170 MSPS
–120
0
15
20
MHz
25
30
35
40
4.5
LE
80
70
4.0
SFDR –dBFS
SFDR –dBc
ns
50
40
30
70dB REFERENCE LINE
0
–70
–60
–50
–40
–30
–20
ANALOG INPUT LEVEL (dBFS)
–10
TCPD
04530-A-013
10
0
2.5
–40
–40
O
0
20
40
60
80
100
Figure 37. Propagation Delay vs. Temperature (Both Speed Grades)
900
NPR = 51.2dB
ENCODE = 170MSPS
NOTCH @ 18.15MHz
–20
–20
TEMPERATURE (°C)
Figure 34. SFDR vs. AIN Input Level 70 MHz, AIN @ 200 MSPS
0
TPD
3.0
B
SO
20
3.5
04530-0-036
60
1.4
800
1.3
VOS
700
1.2
600
1.1
500
1.0
–80
–100
–140
0
10
20
30
40
MHz
04530-0-035
–120
400
0.9
VOD
300
0.8
200
0.7
100
0.6
0
0.5
0
2
4
6
8
10
12
14
RSET (k
Figure 35. Noise Power Ratio Plot (170 MSPS Grade)
Figure 38. LVDS Output Swing, Common-Mode Voltage vs. RSET,
Placed at LVDSBIAS (Both Speed Grades)
Rev. B | Page 17 of 28
VOS (V)
VDIF (mV)
–60
04530-0-037
dB
10
Figure 36. Noise Power Ratio Plot (200 MSPS Grade)
90
NOISE LEVEL (dB)
5
04530-A-005
–80
TE
0
–90
04530-0-034
10
AD9411
Data Sheet
APPLICATION NOTES
CLOCK INPUT
Any high speed A/D converter is extremely sensitive to the
quality of the sampling clock provided by the user. A track-andhold circuit is essentially a mixer, and any noise, distortion, or
timing jitter on the clock is combined with the desired signal at
the A/D output. For this reason, considerable care has been
taken in the design of the clock inputs of the AD9411, and the
user is advised to give careful thought to the clock source.
S1 (Data Format
Select)
1
0
X
X
S5 (Full-Scale
Select)2
X
X
1
0
Mode
Twos Complement
Offset Binary
Full Scale = 0.768 V
Full Scale = 1.536 V
1
X = Don’t Care.
2
S5 full-scale adjust (refer to the Analog Input section).
ANALOG INPUT
The analog input to the AD9411 is a differential buffer. For best
dynamic performance, impedances at VIN+ and VIN– should
match. The analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven
differentially. SNR and SINAD performance degrades significantly if the analog input is driven with a single-ended signal.
LE
The AD9411 has an internal clock duty cycle stabilization
circuit that locks to the rising edge of CLK+ and optimizes
timing internally. This allows a wide range of input duty cycles
at the input without degrading performance. Jitter in the rising
edge of the input is still of paramount concern and is not
reduced by the internal stabilization circuit. The duty cycle
control loop does not function for clock rates less than 30 MHz
nominally. The time constant associated with the loop should
be considered in applications where the clock rate changes
dynamically, requiring a wait time of 1.5 μs to 5 μs after a
dynamic clock frequency increase before valid data is available.
This circuit is always on and cannot be disabled by the user.
Table 7. Output Select Coding1
TE
The AD9411 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated high bandwidth
track-and-hold circuit that samples the signal prior to quantization by the 10-bit core. For ease of use, the part includes an onboard reference and input logic that accepts TTL, CMOS, or
LVPECL levels. The digital output’s logic levels are LVDS
(ANSI-644) compatible.
B
SO
A wideband transformer, such as Mini-Circuits’ ADT1-1WT,
can provide the differential analog inputs for applications that
require a single-ended-to-differential conversion. Both analog
inputs are self-biased by an on-chip resistor divider to a
nominal 2.8 V (refer to the Equivalent Circuits section). Note
that the input common-mode can be overdriven by
approximately +/−150 mV around the self-bias point, as shown
in Figure 42.
The clock inputs are internally biased to 1.5 V (nominal) and
support either differential or single-ended signals. For best
dynamic performance, a differential signal is recommended. An
MC100LVEL16 performs well in the circuit to drive the clock
inputs, as illustrated in Figure 39. Note that for this low voltage
PECL device, the ac coupling is optional.
O
0.1F
Special care was taken in the design of the analog input section
of the AD9411 to prevent damage and corruption of data when
the input is overdriven. The nominal differential input range is
approximately 1.5 V p-p ~ (768 mV × 2). Note that the best
performance is achieved with S5 = 0 (full-scale = 1.5). See
Figure 40 and Figure 41.
AD9411
S5 = GND
CLK+
PECL
GATE
CLK–
VIN+
510
510
04530-A-017
0.1F
768mV 2.8V
Figure 39. Driving Clock Inputs with LVEL16
2.8V
VIN–
DIGITALOUT = ALL 0s
04530-0-041
DIGITALOUT = ALL 1s
Figure 40. Differential Analog Input Range
Rev. B | Page 18 of 28
Data Sheet
AD9411
providing a low skew clocking solution (see Figure 2). The onchip clock buffers should not drive more than 5 pF of capacitance
to limit switching transient effects on performance. The output
clocks are LVDS signals requiring 100 Ω differential termination
at receiver.
S5 = AVDD
VIN+
768mV 2.8V
2.8V
04530-0-042
VIN– = 2.8V
61
SINAD
60
dB
K
S5 = 0
S5 = 1
58
K = 1.24
K = 0.62
0.1F
VREF
A1
1V
04530-A-014
B
SO
2.2
2.4
2.6
2.8
3.0
ANALOG INPUT COMMON MODE (V)
3.2
EXTERNAL 1.23V
REFERENCE
200
1k
Figure 42. SINAD Sensitivity to Analog Input Common-Mode Voltage,
(Ain = −.5 dBfs Differential Drive, S5 = 0)
DISABLE
A1
SENSE
VDD
3.3V
04530-0-043
57
56
2.0
FULL
SCALE
LE
59
A stable and accurate 1.23 V voltage reference is built into the
AD9411 (VREF). The analog input full-scale range is linearly
proportional to the voltage at VREF. Note that an external
reference can be used by connecting the SENSE pin to VDD
(disabling internal reference) and driving VREF with the
external reference source. No appreciable degradation in
performance occurs when VREF is adjusted ±5%. A 0.1 μF
capacitor to ground is recommended at the VREF pin in
internal and external reference applications. Float the SENSE
pin for internal reference operation.
TE
Figure 41. Single-Ended Analog Input Range
VOLTAGE REFERENCE
LVDS OUTPUTS
O
The off-chip drivers provide LVDS compatible output levels. A
3.74 kΩ RSET resistor placed at Pin 7 (LVDSBIAS) to ground
sets the LVDS output current. The RSET resistor current is
ratioed on-chip, setting the output current at each output equal
to a nominal 3.5 mA (11 × IRSET). A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a
nominal 350 mV swing at the receiver. LVDS mode facilitates
interfacing with LVDS receivers in custom ASICs and FPGAs
that have LVDS capability for superior switching performance
in noisy environments. Single point-to-point network topologies
are recommended with a 100 Ω termination resistor as close to
the receiver as possible. It is recommended to keep the trace
lengths < 4 inches and to keep differential output trace lengths
as equal as possible.
Figure 43. Using an External Reference
NOISE POWER RATIO TESTING (NPR)
NPR is a test that is commonly used to characterize the return
path of cable systems where the signals are typically QAM signals with a “noise-like” frequency spectrum. NPR performance
of the AD9411 was characterized in the lab yielding an effective
NPR = 51.2 dB at an analog input of 18 MHz. This agrees with a
theoretical maximum NPR of 51.6 dB for a 10-bit ADC at 13 dB
backoff. The rms noise power of the signal inside the notch is
compared with the rms noise level outside the notch using an
FFT. This test requires sufficiently long record lengths to
guarantee a large number of samples inside the notch. A highorder band-stop filter that provides the required notch depth
for testing is also needed.
CLOCK OUTPUTS (DCO+, DCO–)
The input clock is buffered on-chip and available off-chip at
DCO+ and DCO–. These clocks can facilitate latching off-chip,
Rev. B | Page 19 of 28
AD9411
Data Sheet
SIGNAL
GENERATOR
REFIN
3.3V
3.3V
+
+
AVDD GND DRVDD GND
BAND-PASS
FILTER
VDL GND
ANALOG
J4
10MHz
REFOUT
SIGNAL
GENERATOR
CLOCK
J5
DATA
CAPTURE
AND
PROCESSING
TE
AD9411 EVALUATION BOARD
O
B
SO
LE
Figure 44. Evaluation Board Connections
Rev. B | Page 20 of 28
04530-0-044
3.3V
+
Data Sheet
AD9411
EVALUATION BOARD

Offset binary

Internal voltage reference

Full-scale adjust = low
POWER CONNECTOR
2
Analog Supply for ADC (350 mA)
Output Supply for ADC (50 mA)
Supply for Support Logic
Supply for Clock Buffer/Optional XTAL
Optional External Reference Input
AVDD, DRVDD, and VDL are the minimum required power connections.
LVEL16 clock buffer can be powered from AVDD or VCLK at E47 jumper.
B
SO
1
CLOCK
The clock input is terminated to ground through 50 Ω resistor
at SMB connector J5. The input is ac-coupled to a high speed
differential receiver (LVEL16) that provides the required low
jitter, fast edge rates needed for optimum performance. J5 input
should be > 0.5 V p-p. Power to the LVEL16 is set at Jumper
E47. E47–E45 powers the buffer from AVDD; E47–E46 powers
the buffer from VCLK/V_XTAL.
The AD9411 has an internal 1.23 V voltage reference. The ADC
uses the internal reference as the default when Jumpers E24–E27
and E25–E26 are left open. The full scale can be increased by
placing an optional resistor (R3). The required value varies with
the process and needs to be tuned for the specific application.
Full scale can similarly be reduced by placing R4; tuning is
required here as well. An external reference can be used by
shorting the SENSE pin to 3.3 V (place Jumper E26–E25).
Jumper E27–E24 connects the ADC VREF pin to the
EXT_VREF pin at the power connector.
LE
AVDD1 3.3 V
DRVDD1 3.3 V
VDL1 3.3 V
VCLK/V_XTAL
EXT_VREF2
Full scale is set at E17–E19, E17–E18 sets S5 low, full scale =
1.5 V differential; E17–E19 sets S5 high, full scale = 0.75 V
differential. Best performance is obtained at 1.5 V full scale.
VOLTAGE REFERENCE
Power is supplied to the board via a detachable 12-lead power
strip (three 4-pin blocks).
Table 8. Power Connector, LVDS Mode
GAIN
TE
The AD9411 evaluation board offers an easy way to test the
AD9411 in LVDS mode. It requires a clock source, an analog
input signal, and a 3.3 V power supply. The clock source is
buffered on the board to provide the clocks for the ADC,
latches, and a data-ready signal. The digital outputs and output
clocks are available at a 40-pin connector, P23. The board has
several different modes of operation and is shipped in the
following configurations:
DATA FORMAT SELECT
The evaluation board accepts a 1.3 V p-p analog input signal
centered at ground at SMB connector J4. This signal is
terminated to ground through 50 Ω by R16. The input can be
alternatively terminated at the T1 transformer secondary by
R13 and R14. T1 is a wideband RF transformer that provides a
single-ended-to-differential conversion, allowing the ADC to be
driven differentially, which minimizes even-order harmonics.
An optional second transformer, T2, can be placed following T1
if desired. This provides some performance advantage (~1 dB to
2 dB) for high analog input frequencies (>100 MHz). If T2 is
placed, cut the two shorting traces at the pads. The analog
signal can be low-pass filtered by R41, C12 and R42, C13 at the
ADC input. The footprint for transformer T2 can be modified
to accept a wideband differential amplifier (AD8351) for low
frequency applications where gain is required. See the PCB
schematic for more information.
Data format select (DFS) sets the output data format of the
ADC. Setting DFS (E1–E2) low sets the output format to be
offset binary; setting DFS high (E1–E3) sets the output to twos
complement.
O
ANALOG INPUTS
DATA OUTPUTS
The ADC LVDS digital outputs are routed directly to the
connector at the card edge. Resistor pads placed at the output
connector allow for termination if the connector receiving logic
lack the differential termination for the data bits and DCO.
Each output trace pair should be terminated differentially at
the far end of the line with a single 100 ohm resistor.
CLOCK XTAL
An optional XTAL oscillator can be placed on the board to
serve as a clock source for the PCB. Power to the XTAL is
through the VCLK/VXTAL pin at the power connector. If an
oscillator is used, ensure proper termination for best results.
The board was tested with a Valpey Fisher VF561 and a Vectron
JN00158-163.84.
Rev. B | Page 21 of 28
AD9411
Data Sheet
Table 9. Evaluation Board Bill of Material—AD9411 PCB
No.
1
Quantity
33
Reference Designator
C1, C3*, C4–C11, C15–C17, C18*,
C19–C32, C35, C36, C39*, C40*, C58-C62
Device
Capacitor
Package
0603
Value
0.1 μF
2
4
C33*, C34*, C37*, C38*
Capacitor
0402
0.1 μF
3
4
C63–C66
Capacitor
TAJD
4
1
C2*
Capacitor
0603
10 pF
5
2
C12*, C13*
Capacitor
0603
20 pF
6
7
2
2
J4, J5
P21, P22
Jacks
Power Connectors—Top
8
2
P21, P22
Power Connectors—Posts
9
1
P23
40-Pin Right Angle Connector
SMB
25.602.5453.0
Wieland
Z5.531.3425.0
Wieland
Digi-Key
S2131-20-ND
10
16
R1, R6–R12*, R15*, R31–R37*
Resistor
11
1
R2
Resistor
12
3
R5, R16, R27
13
2
R17, R18
14
2
R19, R20
15
2
R29, R30
16
2
R41, R42
17
2
18
2
19
6
20
5
21
2
22
1
23
2
TE
0603
3.7 kΩ
Resistor
0603
50
Resistor
0603
510
Resistor
0603
150
Resistor
0603
1 kΩ
Resistor
0603
25
R3, R4
Resistor
0603
3.8 kΩ
R13, R14
Resistor
0603
25
R22*, R23*, R24*, R25*, R26*, R28*
Resistor
0603
100
R38*, R39*, R40*, R45*, R47*
Resistor
0402
25
R43*, R44*
Resistor
0402
10 kΩ
R46*
Resistor
0402
1.2 kΩ
R48*, R49*
Resistor
0402
0
1 kΩ
B
SO
LE
100
2
R50*, R51*
Resistor
0402
1
T1, T2*
RF Transformer
Mini Circuits
ADT1-1WT
1
U2
RF Amp
AD8351
27
1
U9
Optional XTAL
JN00158 or VF561
28
1
U1
AD9411
TQFP-100
29
1
U3
MC100LVEL16
SO8NB
25
26
10 μF
0402
O
24
CAPL
* C2, C3, C12, C13, C18, C33, C34, C37, C38, C39, C40, R1, R6–R12, R15, R22–R26, R28, R31–R40, R43–R51 and T2 not placed.
Rev. B | Page 22 of 28
04530-A-015
GND
4
P4
R27
50
R17
510
C5
0.1F
C30
0.1F
AMPIN
E19
AIN
15
16
17
18
19
20
21
VCC
GND
GND
VCC
VCC
GND
R18
510
VDL
25
24
2
3
4
U3
GND
C8
0.1F
GND
GND
R5
50
R19
510
ELOUTB
ELOUT
R20
510
6
7
GND
C36
0.1F
AGND
AVDD
AGND
AINB
AVDD
AGND
AGND
AVDD
AVDD
VCC
D
Q
QN
DN
VBB
VEE
5
8
E45
E46
GND
10EL16
E47
C13
20pF
GND
VCC
23
22
GND
14
VCC
GND
AVDD
13
GND
AGND
12
GND
AGND
VREF
SENSE
11
AGND
9
10
AVDD
LVDSBIAS
S1
S2
AGND
S4
GND
7
6
5
4
3
DNC
S5
8
R30
1k
2
1
VCC
VCC
R42 GND
25
C2
10pF
C3
0.1F
GND
C1
0.1F
E24
E26
R29 GND
1k
VCC
E17
GND
E18
U1
AD9411
C9
0.1F
C10
0.1F
C4
0.1F
D9B
D9
GND
DR
R37
100
DRB
D6
R10
100
D6B
P3 3
P1 1
P9 9
2 P2
P11 11
10 P10
P5 5
P13 13
12 P12
4 P4
P15 15
14 P14
P7 7
P17 17
16 P16
6 P6
P19 19
18 P18
8 P8
P21 21
P27 27
28 P28
20 P20
P29 29
30 P30
P23 23
P31 31
32 P32
22 P22
P33 33
34 P34
P25 25
P35 35
36 P36
24 P24
P37 37
26 P26
P39 39
GND
GND
DR
GND
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D1F
D2F
DOR
D4B
D4
D8B
D8
38 P38
R33
100
R12
100
40 P40
D3
R32
100
D3B
D5
R9
100
D5B
D7
R11
100
D7B
D2
R31
100 GND
DRVDD
DRVDD 54
DRB
D2B
GND
DRGND 53
GND
DNC 52
D1
D11B
R15
DNC 51
100
D10B
D1B
D9B
D8B
D7B
D6B
D0
D5B
R36
D4B
100
D3B
D0B
D1F
D2B
R35
D1B
100
D1FB
D0B
D2F
D1FB
R34
100
D2FB
D2FB
DORB
GND
CONNECTOR
GND
D0– 55
D0+ 56
D1+ 58
D1– 57
D2– 59
D2+ 60
DRVDD
DRVDD 62
GND
GND
DRVDD
DRGND 61
DC0– 63
DC0+ 64
D3– 65
D3+ 66
DRGND 67
D4– 68
D4+ 69
D5– 70
D5+ 71
D6– 72
DRGND 74
D6+ 73
DRVDD 75
R8
100
D10B
D10
TE
LE
B
SO
AMPINB
C15
R41
0.1F
25
R14
25
GND
GND
J5
R13
25
6 C11
0.1F
4
2
PRI SEC
1
5
NC
3
ENCODE
4
GND
2
6 C7
0.1F
PRI SEC
1
5
NC
3
E27
VREF
VCC
E25
C12
20pF
GND
GND
R4
3.8k
ADT1-1WT
T2 OPTIONAL
VCC
E3
E2
GND
E1
R3
GND 3.8k
GND
VCC
VCC
GND
ADT1-1WT
P21
T2
PTM1CRO4
P22
T1
C6
0.1F
AMP
GND
ANALOG R16
J4 50
3
P3
R2
3.8k
2
P2
MTHOLE6
H1
R7
100
AGND
26
GND
PTM1CRO4
D11
R6
100
D11B
AVDD
27
VCC
GND
GND
AVDD
28
VCC
GND
DRVDD
VCC
AGND 100
AVDD
29
VCC
1
VCC
AVDD 99
AGND
30
GND
P1
MTHOLE6
GND
AVDD 98
AGND
31
GND
H2
GND
AGND 97
AGND
32
VDL
VCC
AGND 96
AVDD
33
4
VCC
AVDD 95
AVDD 94
AVDD
34
VCC
P4
MTHOLE6
GND
AGND 93
AGND
35
GND
H3
GND
AGND 92
CLK+
36
~ENC
O
GND
AGND 91
CLK–
37
GND
VCC
AVDD 90
AGND
38
GND
VREF
VCC
AVDD 89
AVDD
39
VCC
3
VCC
AVDD 88
AVDD
40
2
GND
AGND 87
AGND
41
GND
P3
OR+ 85
DNC
42
P2
GND
AGND 86
DNC
43
VCC
MTHOLE6
OR– 84
DNC
44
H4
DRVDD
DVRDD 83
DNC
45
GND
GND
DRGND 82
DNC
46
1
D9– 80
DRVDD
47
P1
D9+ 81
DRGND
48
GND
DRVDD
GND
D8– 78
DNC
P16
DORB
D8+ 79
DNC
Rev. B | Page 23 of 28
49
Figure 45. Evaluation Board Schematic
50
GROUND PAD UNDER PART
D7– 76
DOR
D7+ 77
R1
100
Data Sheet
AD9411
AD9411
VCC
Data Sheet
+
C64
10F
C16
0.1F
C17
0.1F
C19
0.1F
C21
0.1F
C23
0.1F
C20
0.1F
C22
0.1F
C25
0.1F
C24
0.1F
C27
0.1F
C26
0.1F
C29
0.1F
C28
0.1F
C31
0.1F
C32
0.1F
C35
0.1F
GND
DRVDD
VDL
+
C65
10F
C61
0.1F
C62
0.1F
C60
0.1F
C59
0.1F
C58
0.1F
+
C66
10F
VREF
C18
0.1F
GND
GND
+
C63
10F
GND
TO USE VF561 CRYSTAL
GND
VDL
R28
100
GND
1
E/D
VCC
6
2
NC
OUTPUTB
5
3
GND
OUTPUT
4
R23
100
VDL
TE
R22
100
JN00158
P4
R25
100
U9
GND
VDL
LE
R24
100
P5
04530-0-046
R26
100
GND
B
SO
Figure 46. Evaluation Board Schematic (continued)
R51
1k
R50
1k
VDL
POWER DOWN
USE R43 OR R44
GND
AMP IN
AMP
C33
0.1F
C34
0.1F
R45
25k
R47
25k
PWUP
VOCM 10
RGP1
INHI
3
INLO
VPOS 9
OPHI 8
2
OPLO
4
R40
25k
GND
U2
AD8351
1
R39
25k
C37
0.1F
GND
R44
10k
O
R38
25k
C38
0.1F
GND
R43
10k
VDL
5
RPG2
R49
0
C39
0.1F
AMPINB
7
COMM 6
GND
R48
0
C40
0.1F
AMPIN
R46
1.2k
Figure 47. Evaluation Board Schematic (continued)
Rev. B | Page 24 of 28
04530-0-053
VDL
GND
AD9411
04530-0-049
Figure 50. PCB Ground Layer
04530-0-048
04530-0-050
O
B
SO
Figure 48. PCB Top Side Silkscreen
LE
TE
Data Sheet
Figure 51. PCB Split Power Plane
Figure 49. PCB Top Side Copper Routing
Rev. B | Page 25 of 28
Data Sheet
Figure 53. PCB Bottom Side Silkscreen
O
B
SO
Figure 52. PCB Bottom Side Copper Routing
Rev. B | Page 26 of 28
04530-0-052
04530-0-051
LE
TE
AD9411
Data Sheet
AD9411
OUTLINE DIMENSIONS
0.75
0.60
0.45
16.00 BSC SQ
1.20
MAX
14.00 BSC SQ
100
1
SEATING
PLANE
76
76
75
100
1
75
PIN 1
BOTTOM VIEW
(PINS UP)
TOP VIEW
(PINS DOWN)
51
50
1.05
1.00
0.95
7°
3.5°
0°
0.27
0.22
0.17
0.15
0.05
26
6.50
NOM
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
LE
0.50 BSC
25
50
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
021809-A
51
25
26
0.20
0.09
TE
CONDUCTIVE
HEAT SINK
B
SO
Figure 54. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-100)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD9411BSVZ-170
AD9411BSVZ-200
Package Description
100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
Z = RoHS Compliant Part.
O
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
Rev. B | Page 27 of 28
Package Option
SV-100
SV-100
AD9411
Data Sheet
O
B
SO
LE
TE
NOTES
©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04530-0-1/12(B)
Rev. B | Page 28 of 28