Filterless, High Efficiency,
Mono 3 W Class-D Audio Amplifier
SSM2375
Data Sheet
FEATURES
Spread-spectrum pulse density modulation (PDM) is used to
provide lower EMI-radiated emissions compared with other
Class-D architectures. The inherent randomized nature of
spread-spectrum PDM eliminates the clock intermodulation
(beating effect) of several amplifiers in close proximity.
Filterless Class-D amplifier with spread-spectrum
Σ-Δ modulation
3 W into 3 Ω load and 1.4 W into 8 Ω load at 5.0 V supply
with <1% total harmonic distortion (THD + N)
93% efficiency at 5.0 V, 1.4 W into 8 Ω speaker
>100 dB signal-to-noise ratio (SNR)
High PSSR at 217 Hz: 80 dB
Flexible gain adjustment pin: 0 dB to 12 dB in 3 dB steps
Fixed input impedance: 80 kΩ
User-selectable ultralow EMI emissions mode
Single-supply operation from 2.5 V to 5.5 V
20 nA shutdown current
Short-circuit and thermal protection with autorecovery
Available in 9-ball, 1.5 mm × 1.5 mm WLCSP
Pop-and-click suppression
The SSM2375 includes an optional modulation select pin
(ultralow EMI emissions mode) that significantly reduces the
radiated emissions at the Class-D outputs, particularly above
100 MHz. In ultralow EMI emissions mode, the SSM2375
can pass FCC Class B radiated emission testing with 50 cm,
unshielded speaker cable without any external filtering.
The device also includes a highly flexible gain select pin that
allows the user to select a gain of 0 dB, 3 dB, 6 dB, 9 dB, or
12 dB. The gain selection feature improves gain matching
between multiple SSM2375 devices within a single application
as compared to using external resistors to set the gain.
APPLICATIONS
The SSM2375 has a micropower shutdown mode with a typical
shutdown current of 20 nA. Shutdown is enabled by applying
a logic low to the SD pin.
Mobile phones
MP3 players
Portable electronics
The device also includes pop-and-click suppression circuitry.
This suppression circuitry minimizes voltage glitches at the
output during turn-on and turn-off, reducing audible noise
on activation and deactivation.
GENERAL DESCRIPTION
The SSM2375 is a fully integrated, high efficiency, Class-D audio
amplifier. It is designed to maximize performance for mobile
phone applications. The application circuit requires a minimum
of external components and operates from a single 2.5 V to 5.5 V
supply. It is capable of delivering 3 W of continuous output power
with <1% THD + N driving a 3 Ω load from a 5.0 V supply.
Other features that simplify system-level integration of the
SSM2375 include input low-pass filtering to suppress out-of-band
DAC noise interference to the PDM modulator and fixed-input
impedance to simplify component selection across multiple
platform production builds.
The SSM2375 features a high efficiency, low noise modulation
scheme that requires no external LC output filters. The modulation
continues to provide high efficiency even at low output power.
The SSM2375 operates with 93% efficiency at 1.4 W into 8 Ω
or with 85% efficiency at 3 W into 3 Ω from a 5.0 V supply and
has an SNR of >100 dB.
The SSM2375 is specified over the industrial temperature range
of −40°C to +85°C. It has built-in thermal shutdown and output
short-circuit protection. It is available in a halide-free, 9-ball,
1.5 mm × 1.5 mm wafer level chip scale package (WLCSP).
FUNCTIONAL BLOCK DIAGRAM
POWER SUPPLY
2.5V TO 5.5V
10µF
0.1µF
SSM2375
VDD
22nF
OUT+
GAIN
CONTROL
IN+
IN–
22nF
SHUTDOWN
MODULATOR
(Σ-Δ)
IN–
INTERNAL
OSCILLATOR
BIAS
SD
FET
DRIVER
EDGE
CONTROL
OUT–
EDGE
EMISSION
CONTROL
GND
GAIN
RGAIN
GAIN SELECT
GAIN = 0dB, 3dB, 6dB, 9dB, OR 12dB
09011-001
IN+
Figure 1.
Rev. A
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SSM2375
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 13
Applications ....................................................................................... 1
Overview ..................................................................................... 13
General Description ......................................................................... 1
Gain Selection ............................................................................. 13
Functional Block Diagram .............................................................. 1
Pop-and-Click Suppression ...................................................... 13
Revision History ............................................................................... 2
EMI Noise.................................................................................... 13
Specifications..................................................................................... 3
Output Modulation Description .............................................. 13
Absolute Maximum Ratings ............................................................ 5
Layout .......................................................................................... 14
Thermal Resistance ...................................................................... 5
Input Capacitor Selection .......................................................... 14
ESD Caution .................................................................................. 5
Power Supply Decoupling ......................................................... 14
Pin Configuration and Function Descriptions ............................. 6
Outline Dimensions ....................................................................... 15
Typical Performance Characteristics ............................................. 7
Ordering Guide .......................................................................... 15
Typical Application Circuits.......................................................... 12
REVISION HISTORY
4/13—Rev. 0 to Rev. A
Changes to Figure 33 and Figure 34............................................. 12
Changes to Gain Selection Section and Table 5 ......................... 13
Updated Outline Dimensions ....................................................... 15
9/10—Revision 0: Initial Version
Rev. A | Page 2 of 16
Data Sheet
SSM2375
SPECIFICATIONS
VDD = 5.0 V, TA = 25°C, RL = 8 Ω +33 µH, EDGE = GND, unless otherwise noted.
Table 1.
Parameter
DEVICE CHARACTERISTICS
Output Power
Efficiency
Total Harmonic Distortion + Noise
Input Common-Mode Voltage
Range
Common-Mode Rejection Ratio
Average Switching Frequency
Differential Output Offset Voltage
POWER SUPPLY
Supply Voltage Range
Power Supply Rejection Ratio
Symbol
Test Conditions/Comments
PO
f = 1 kHz, 20 kHz BW
RL = 8 Ω, THD = 1%, VDD = 5.0 V
RL = 8 Ω, THD = 1%, VDD = 3.6 V
RL = 8 Ω, THD = 1%, VDD = 2.5 V
RL = 8 Ω, THD = 10%, VDD = 5.0 V
RL = 8 Ω, THD = 10%, VDD = 3.6 V
RL = 8 Ω, THD = 10%, VDD = 2.5 V
RL = 4 Ω, THD = 1%, VDD = 5.0 V
RL = 4 Ω, THD = 1%, VDD = 3.6 V
RL = 4 Ω, THD = 1%, VDD = 2.5 V
RL = 4 Ω, THD = 10%, VDD = 5.0 V
RL = 4 Ω, THD = 10%, VDD = 3.6 V
RL = 4 Ω, THD = 10%, VDD = 2.5 V
RL = 3 Ω, THD = 1%, VDD = 5.0 V
RL = 3 Ω, THD = 1%, VDD = 3.6 V
RL = 3 Ω, THD = 1%, VDD = 2.5 V
RL = 3 Ω, THD = 10%, VDD = 5.0 V
RL = 3 Ω, THD = 10%, VDD = 3.6 V
RL = 3 Ω, THD = 10%, VDD = 2.5 V
PO = 1.4 W into 8 Ω, VDD = 5.0 V
PO = 1 W into 8 Ω, f = 1 kHz, VDD = 5.0 V
PO = 0.5 W into 8 Ω, f = 1 kHz, VDD = 3.6 V
η
THD + N
VCM
VCM = 2.5 V ± 100 mV, f = 217 Hz, output referred
VDD
PSRR
ISD
GAIN CONTROL
Closed-Loop Gain
Input Impedance
Gain
ZIN
SD = VDD, fixed input impedance (0 dB to 12 dB)
SHUTDOWN CONTROL
Input Voltage High
Input Voltage Low
Turn-On Time
Turn-Off Time
Output Impedance
VIH
VIL
tWU
tSD
ZOUT
Shutdown Current
Max
Unit
VDD − 1
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
%
%
%
V
2.0
dB
kHz
mV
5.5
V
1.42
0.72
0.33
1.77
0.91
0.42
2.52
1.28
0.56
3.17 1
1.6
0.72
3.21
1.52
0.68
3.71
1.9
0.85
93
0.01
0.01
55
250
0.1
Gain = 6 dB
Guaranteed from PSRR test
Inputs are ac-grounded, CIN = 0.1 µF
VRIPPLE = 100 mV at 217 Hz
VRIPPLE = 100 mV at 1 kHz
VIN = 0 V, no load, VDD = 5.0 V
VIN = 0 V, no load, VDD = 3.6 V
VIN = 0 V, no load, VDD = 2.5 V
VIN = 0 V, RL = 8 Ω + 33 µH, VDD = 5.0 V
VIN = 0 V, RL = 8 Ω + 33 µH, VDD = 3.6 V
VIN = 0 V, RL = 8 Ω + 33 µH, VDD = 2.5 V
SD = GND
ISY
Typ
1.0
CMRRGSM
fSW
VOOS
Supply Current
Min
2.5
80
80
3.0
2.7
2.5
3.1
2.8
2.6
20
0
dB
dB
mA
mA
mA
mA
mA
mA
nA
12
80
1.35
0.35
SD rising edge from GND to VDD
SD falling edge from VDD to GND
SD = GND
Rev. A | Page 3 of 16
12.5
5
>100
dB
kΩ
V
V
ms
µs
kΩ
SSM2375
Parameter
NOISE PERFORMANCE
Output Voltage Noise
Signal-to-Noise Ratio
1
Data Sheet
Symbol
Test Conditions/Comments
en
VDD = 5.0 V, f = 20 Hz to 20 kHz, inputs are
ac-grounded, gain = 6 dB, A-weighted
PO = 1.4 W, RL = 8 Ω
SNR
Min
Typ
Max
Unit
30
µV rms
100
dB
Although the SSM2375 has good audio quality above 3 W, continuous output power beyond 3 W without a heat sink must be avoided due to device packaging limitations.
Rev. A | Page 4 of 16
Data Sheet
SSM2375
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 2.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Supply Voltage
Input Voltage
Common-Mode Input Voltage
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
ESD Susceptibility
Rating
6V
VDD
VDD
−65°C to +150°C
−40°C to +85°C
−65°C to +165°C
300°C
4 kV
Table 3. Thermal Resistance
Package Type
9-Ball, 1.5 mm × 1.5 mm WLCSP
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 5 of 16
PCB
1S0P
2S0P
θJA
162
76
θJB
39
21
Unit
°C/W
°C/W
SSM2375
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BALL A1
CORNER
1
2
3
IN–
SD
GAIN
A
IN+
EDGE
OUT–
VDD
OUT+
B
GND
09011-002
C
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1A
1B
1C
2A
2B
2C
3A
3B
3C
Mnemonic
IN−
IN+
GND
SD
EDGE
VDD
GAIN
OUT−
OUT+
Description
Inverting Input.
Noninverting Input.
Ground.
Shutdown Input. Active low digital input.
Edge Rate Control. Active high.
Power Supply.
Gain Control Pin.
Inverting Output.
Noninverting Output.
Rev. A | Page 6 of 16
Data Sheet
SSM2375
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
RL = 8Ω + 33µH
GAIN = 6dB
RL = 8Ω + 33µH
GAIN = 12dB
10
10
VDD = 3.6V
1
THD + N (%)
0.1
1
0.1
VDD = 2.5V
VDD = 2.5V
0.01
0.01
VDD = 5V
0.001
0.01
0.1
1
10
OUTPUT POWER (W)
0.001
0.0001
09011-003
0.001
0.0001
VDD = 5V
0.1
0.01
0.001
Figure 3. THD + N vs. Output Power into 8 Ω, Gain = 6 dB
10
Figure 6. THD + N vs. Output Power into 8 Ω, Gain = 12 dB
100
100
RL = 4Ω + 15µH
GAIN = 12dB
RL = 4Ω + 15µH
GAIN = 6dB
10
10
VDD = 3.6V
THD + N (%)
VDD = 3.6V
THD + N (%)
1
OUTPUT POWER (W)
09011-004
THD + N (%)
VDD = 3.6V
1
0.1
1
VDD = 2.5V
0.1
VDD = 2.5V
0.01
0.01
VDD = 5V
0.1
0.01
1
10
OUTPUT POWER (W)
10
100
VDD = 5V
GAIN = 6dB
RL = 8Ω + 33µH
THD + N (%)
10
1
0.1
VDD = 5V
GAIN = 12dB
RL = 8Ω + 33µH
1
0.1
1W
1W
0.25W
0.25W
0.01
0.01
100
1k
10k
100k
FREQUENCY (Hz)
Figure 5. THD + N vs. Frequency, VDD = 5 V, RL = 8 Ω, Gain = 6 dB
0.001
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 8. THD + N vs. Frequency, VDD = 5 V, RL = 8 Ω, Gain = 12 dB
Rev. A | Page 7 of 16
09011-013
0.5W
0.5W
09011-012
0.001
10
1
0.1
Figure 7. THD + N vs. Output Power into 4 Ω, Gain = 12 dB
100
THD + N (%)
0.01
OUTPUT POWER (W)
Figure 4. THD + N vs. Output Power into 4 Ω, Gain = 6 dB
10
0.001
09011-011
0.001
VDD = 5V
0.001
0.0001
09011-010
0.001
0.0001
SSM2375
Data Sheet
100
10
2W
THD + N (%)
2W
1
0.1
1
0.1
0.5W
0.5W
0.01
0.01
1k
10k
100k
FREQUENCY (Hz)
09011-014
100
0.001
10
Figure 12. THD + N vs. Frequency, VDD = 5 V, RL = 4 Ω, Gain = 12 dB
100
10
THD + N (%)
THD + N (%)
100
VDD = 3.6V
GAIN = 6dB
RL = 8Ω + 33µH
1
0.5W
0.1
VDD = 3.6V
GAIN = 12dB
RL = 8Ω + 33µH
1
0.5W
0.1
0.25W
0.25W
0.01
0.01
0.125W
100
1k
0.125W
10k
100k
FREQUENCY (Hz)
0.001
10
09011-016
0.001
10
10
THD + N (%)
1W
0.1
1
100k
VDD = 3.6V
GAIN = 12dB
RL = 4Ω + 15µH
1W
0.1
0.25W
0.25W
0.01
0.01
0.5W
0.5W
0.001
10
10k
100
VDD = 3.6V
GAIN = 6dB
RL = 4Ω + 15µH
100
1k
10k
100k
FREQUENCY (Hz)
09011-018
THD + N (%)
1k
Figure 13. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 Ω, Gain = 12 dB
100
1
100
FREQUENCY (Hz)
Figure 10. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 Ω, Gain = 6 dB
10
100k
FREQUENCY (Hz)
Figure 9. THD + N vs. Frequency, VDD = 5 V, RL = 4 Ω, Gain = 6 dB
10
10k
1k
100
09011-015
1W
1W
0.001
10
09011-017
THD + N (%)
VDD = 5V
GAIN = 12dB
RL = 4Ω + 15µH
Figure 11. THD + N vs. Frequency, VDD = 3.6 V, RL = 4 Ω, Gain = 6 dB
0.001
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 14. THD + N vs. Frequency, VDD = 3.6 V, RL = 4 Ω, Gain = 12 dB
Rev. A | Page 8 of 16
09011-019
10
100
VDD = 5V
GAIN = 6dB
RL = 4Ω + 15µH
Data Sheet
SSM2375
100
10
THD + N (%)
1
0.1
0.25W
VDD = 2.5V
GAIN = 12dB
RL = 8Ω + 33µH
1
0.1
0.25W
0.0625W
0.0625W
0.01
0.01
0.125W
100k
FREQUENCY (Hz)
100
VDD = 2.5V
GAIN = 6dB
RL = 4Ω + 15µH
10
VDD = 2.5V
GAIN = 12dB
RL = 4Ω + 15µH
0.25W
0.25W
1
THD + N (%)
0.1
1
0.1
0.0625W
0.0625W
0.01
0.01
0.125W
0.125W
1k
100
10k
100k
FREQUENCY (Hz)
0.001
10
09011-022
0.001
10
10k
100k
FREQUENCY (Hz)
Figure 16. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 Ω, Gain = 6 dB
Figure 19. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 Ω, Gain = 12 dB
3.8
3.8
GAIN = 12dB
GAIN = 0dB
3.6
QUIESCENT CURRENT (mA)
3.6
3.4
3.2
4Ω + 15µH
8Ω + 33µH
3.0
2.8
NO LOAD
2.6
3.4
3.2
4Ω + 15µH
3.0
8Ω + 33µH
2.8
NO LOAD
2.6
2.4
3.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
09011-024
2.4
2.2
2.5
1k
100
09011-023
THD + N (%)
100k
Figure 18. THD + N vs. Frequency, VDD = 2.5 V, RL = 8 Ω, Gain = 12 dB
100
QUIESCENT CURRENT (mA)
10k
FREQUENCY (Hz)
Figure 15. THD + N vs. Frequency, VDD = 2.5 V, RL = 8 Ω, Gain = 6 dB
10
1k
100
09011-021
10k
1k
100
0.125W
0.001
10
09011-020
0.001
10
Figure 17. Quiescent Current vs. Supply Voltage, Gain = 0 dB
2.2
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
Figure 20. Quiescent Current vs. Supply Voltage, Gain = 12 dB
Rev. A | Page 9 of 16
09011-025
THD + N (%)
10
100
VDD = 2.5V
GAIN = 6dB
RL = 8Ω + 33µH
SSM2375
Data Sheet
2.0
f = 1kHz
GAIN = 0dB
RL = 8Ω + 33µH
1.8
1.6
OUTPUT POWER (W)
1.4
1.2
1.0
THD + N = 10%
0.8
THD + N = 1%
0.6
1.2
1.0
THD + N = 10%
0.8
0.4
0.2
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
Figure 21. Maximum Output Power vs. Supply Voltage, RL = 8 Ω, Gain = 0 dB
THD + N = 1%
0.6
0.2
0
2.5
0
2.5
3.5
4.0
4.5
5.0
Figure 24. Maximum Output Power vs. Supply Voltage, RL = 8 Ω, Gain = 12 dB
3.5
f = 1kHz
GAIN = 0dB
RL = 4Ω + 15µH
3.0
f = 1kHz
GAIN = 12dB
RL = 4Ω + 15µH
3.0
OUTPUT POWER (W)
2.5
2.0
THD + N = 10%
1.5
THD + N = 1%
1.0
2.5
2.0
THD + N = 10%
1.5
THD + N = 1%
1.0
0.5
3.0
3.5
4.5
4.0
5.0
SUPPLY VOLTAGE (V)
0
2.5
09011-028
0
2.5
Figure 22. Maximum Output Power vs. Supply Voltage, RL = 4 Ω, Gain = 0 dB
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
09011-029
0.5
Figure 25. Maximum Output Power vs. Supply Voltage, RL = 4 Ω, Gain = 12 dB
100
100
VDD = 2.5V
90
VDD = 2.5V
90
80
80
VDD = 5V
VDD = 3.6V
VDD = 3.6V
70
EFFICIENCY (%)
70
60
50
40
30
VDD = 5V
60
50
40
30
20
20
10
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
RL = 4Ω + 15µH
GAIN = 6dB
10
1.8
OUTPUT POWER (W)
Figure 23. Efficiency vs. Output Power into 8 Ω, Gain = 6 dB
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
OUTPUT POWER (W)
Figure 26. Efficiency vs. Output Power into 4 Ω, Gain = 6 dB
Rev. A | Page 10 of 16
09011-031
RL = 8Ω + 33µH
GAIN = 6dB
09011-030
EFFICIENCY (%)
3.0
SUPPLY VOLTAGE (V)
3.5
OUTPUT POWER (W)
1.4
0.4
09011-026
OUTPUT POWER (W)
1.6
f = 1kHz
GAIN = 12dB
RL = 8Ω + 33µH
1.8
09011-027
2.0
Data Sheet
SSM2375
400
800
RL = 8Ω + 33µH
GAIN = 6dB
300
VDD = 3.6V
250
VDD = 2.5V
200
150
100
600
VDD = 3.6V
500
400
VDD = 2.5V
300
200
100
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
OUTPUT POWER (W)
0
0
0
–10
–20
–20
–30
–30
–40
–40
PSRR (dB)
0
–50
–60
–70
–80
–90
–100
10
09011-036
–90
–100
10
100k
3.0
3.5
100
10k
1k
100k
FREQUENCY (Hz)
Figure 28. Common-Mode Rejection Ratio (CMRR) vs. Frequency
Figure 31. Power Supply Rejection Ratio (PSRR) vs. Frequency
7
7
SD INPUT
6
6
5
SD INPUT
OUTPUT
5
VOLTAGE (V)
4
3
2
OUTPUT
4
3
2
1
1
–4
0
4
8
12
16
20
24
TIME (ms)
28
32
36
09011-038
0
–1
–8
2.5
–60
–80
10k
2.0
–50
–70
1k
1.5
Figure 30. Supply Current vs. Output Power into 4 Ω, Gain = 6 dB
–10
FREQUENCY (Hz)
1.0
OUTPUT POWER (W)
Figure 27. Supply Current vs. Output Power into 8 Ω, Gain = 6 dB
100
0.5
09011-037
0.2
Figure 29. Turn-On Response
0
–50
–30
–10
10
30
TIME (µs)
Figure 32. Turn-Off Response
Rev. A | Page 11 of 16
50
70
09011-039
0
09011-032
0
CMRR (dB)
VDD = 5V
09011-033
50
VOLTAGE (V)
RL = 4Ω + 15µH
GAIN = 6dB
700
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
350
VDD = 5V
SSM2375
Data Sheet
TYPICAL APPLICATION CIRCUITS
POWER SUPPLY
2.5V TO 5.5V
10µF
0.1µF
SSM2375
VDD
22nF
IN+
IN+
IN–
22nF
SHUTDOWN
GAIN
CONTROL
IN–
OUT+
MODULATOR
(Σ-∆)
BIAS
SD
INTERNAL
OSCILLATOR
FET
DRIVER
EDGE
CONTROL
OUT–
EDGE
GND
GAIN
RGAIN (9dB/12dB ONLY)
GAIN SELECT
09011-005
GAIN = 0dB (GND), 3dB (OPEN)*, 6dB (VDD), 9dB (GND), OR 12dB (VDD)
*SEE THE GAIN SELECTION SECTION FOR MORE INFORMATION
ON AVOIDING EXCESSIVE INDUCED NOISE.
Figure 33. Monaural Differential Input Configuration
POWER SUPPLY
2.5V TO 5.5V
10µF
0.1µF
SSM2375
VDD
22nF
IN+
IN+
22nF
SHUTDOWN
GAIN
CONTROL
IN–
OUT+
MODULATOR
(Σ-∆)
BIAS
SD
INTERNAL
OSCILLATOR
FET
DRIVER
EDGE
CONTROL
GAIN
EDGE
GND
RGAIN (9dB/12dB ONLY)
GAIN = 0dB (GND), 3dB (OPEN)*, 6dB (VDD), 9dB (GND), OR 12dB (VDD)
*SEE THE GAIN SELECTION SECTION FOR MORE INFORMATION
ON AVOIDING EXCESSIVE INDUCED NOISE.
Figure 34. Monaural Single-Ended Input Configuration
Rev. A | Page 12 of 16
09011-006
GAIN SELECT
OUT–
Data Sheet
SSM2375
THEORY OF OPERATION
OVERVIEW
POP-AND-CLICK SUPPRESSION
The SSM2375 mono Class-D audio amplifier features a filterless
modulation scheme that greatly reduces the external component
count, conserving board space and, thus, reducing systems cost.
The SSM2375 does not require an output filter but, instead, relies
on the inherent inductance of the speaker coil and the natural
filtering of the speaker and human ear to fully recover the audio
component of the switching output.
Voltage transients at the output of audio amplifiers can occur
when shutdown is activated or deactivated. Voltage transients as
low as 10 mV can be heard as an audio pop in a low sensitivity
handset speaker. Clicks and pops can also be classified as undesirable audible transients generated by the amplifier system and,
therefore, as not coming from the system input signal.
Most Class-D amplifiers use some variation of pulse-width
modulation (PWM), but the SSM2375 uses Σ-Δ modulation to
determine the switching pattern of the output devices, resulting
in a number of important benefits.
•
•
Σ-Δ modulators do not produce a sharp peak with many
harmonics in the AM frequency band, as pulse-width
modulators often do.
Σ-Δ modulation provides the benefits of reducing the
amplitude of spectral components at high frequencies,
that is, reducing EMI emissions that might otherwise be
radiated by speakers and long cable traces.
Due to the inherent spread-spectrum nature of Σ-Δ modulation, the need for oscillator synchronization is eliminated
for designs that incorporate multiple SSM2375 amplifiers.
The SSM2375 has a pop-and-click suppression architecture that
reduces these output transients, resulting in noiseless activation
and deactivation from the SD control pin while operating in a
typical audio configuration.
EMI NOISE
The SSM2375 uses a proprietary modulation and spread-spectrum
technology to minimize EMI emissions from the device. For
applications that have difficulty passing FCC Class B emission
tests, the SSM2375 includes a modulation select pin (ultralow
EMI emissions mode) that significantly reduces the radiated
emissions at the Class-D outputs, particularly above 100 MHz.
The SSM2375 also integrates overcurrent and overtemperature
protection.
EMI emission tests on the SSM2375 were performed in a certified
FCC Class B laboratory in low emissions mode (EDGE = VDD).
With a pink noise source, an 8 Ω speaker load, and a 5 V supply,
the SSM2375 was able to pass FCC Class B limits with 50 cm,
unshielded twisted pair speaker cable. Note that reducing the
power supply voltage greatly reduces radiated emissions.
GAIN SELECTION
OUTPUT MODULATION DESCRIPTION
The preset gain of the SSM2375 can be set from 0 dB to 12 dB
in 3 dB steps with one external resistor (optional). The external
resistor is used to select the 9 dB or 12 dB gain setting, as shown
in Table 5.
The SSM2375 uses three-level, Σ-Δ output modulation. Each
output can swing from GND to VDD and vice versa. Ideally, when
no input signal is present, the output differential voltage is 0 V
because there is no need to generate a pulse. In a real-world
situation, there are always noise sources present.
•
To avoid excessive induced noise at high output power, observe
caution under the following conditions: GAIN pin is configured
to the 3 dB gain setting (open) and using both low impedance
(less than 3 Ω + 10 μH) loading and configured for low emissions
mode (EDGE = VDD). To safeguard against the potential induced
noise at high power levels in this configuration, connect a capacitor
from GAIN to GND with a value ranging from 2.2 μF to 4.7 μF.
Alternatively, apply a fixed voltage of VDD/2 to the GAIN pin
to stabilize the gain setting operation under the low impedance/
high power condition stated above.
Table 5. Gain Function Descriptions
Gain Setting (dB)
12
9
6
31
0
1
GAIN Pin Configuration
Tie to VDD through 47 kΩ resistor
Tie to GND through 47 kΩ resistor
Tie to VDD
Open
Tie to GND
Due to this constant presence of noise, a differential pulse is
generated, when required, in response to this stimulus. A small
amount of current flows into the inductive load when the differential pulse is generated.
Most of the time, however, the output differential voltage is 0 V,
due to the Analog Devices, Inc., three-level, Σ-Δ output modulation. This feature ensures that the current flowing through the
inductive load is small.
When the user wants to send an input signal, an output pulse
is generated to follow the input voltage. The differential pulse
density is increased by raising the input signal level. Figure 35
depicts three-level, Σ-Δ output modulation with and without
input stimulus.
See the Gain Selection section for more information on avoiding excessive
induced noise.
Rev. A | Page 13 of 16
SSM2375
Data Sheet
In addition, good PCB layout isolates critical analog paths from
sources of high interference. High frequency circuits (analog
and digital) should be separated from low frequency circuits.
OUTPUT = 0V
+5V
OUT+
0V
+5V
OUT–
0V
+5V
VOUT
Properly designed multilayer PCBs can reduce EMI emissions
and increase immunity to the RF field by a factor of 10 or more,
compared with double-sided boards. A multilayer board allows
a complete layer to be used for the ground plane, whereas the
ground plane side of a double-sided board is often disrupted by
signal crossover.
0V
–5V
OUTPUT > 0V
+5V
OUT+
0V
+5V
OUT–
0V
+5V
INPUT CAPACITOR SELECTION
VOUT
0V
OUTPUT < 0V
+5V
OUT+
0V
+5V
OUT–
VOUT
–5V
09011-009
0V
0V
Figure 35. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus
LAYOUT
As output power increases, care must be taken to lay out PCB
traces and wires properly among the amplifier, load, and power
supply. A good practice is to use short, wide PCB tracks to
decrease voltage drops and minimize inductance. The PCB
layout engineer must avoid ground loops where possible to
minimize common-mode current associated with separate paths
to ground. Ensure that track widths are at least 200 mil for every
inch of track length for lowest DCR, and use 1 oz or 2 oz copper
PCB traces to further reduce IR drops and inductance. A poor
layout increases voltage drops, consequently affecting efficiency.
Use large traces for the power supply inputs and amplifier outputs
to minimize losses due to parasitic trace resistance.
Proper grounding guidelines help to improve audio performance,
minimize crosstalk between channels, and prevent switching
noise from coupling into the audio signal. To maintain high
output swing and high peak output power, the PCB traces that
connect the output pins to the load, as well as the PCB traces to
the supply pins, should be as wide as possible to maintain the
minimum trace resistances. It is also recommended that a large
ground plane be used for minimum impedances.
The SSM2375 does not require input coupling capacitors if the
input signal is biased from 1.0 V to VDD − 1.0 V. Input capacitors
are required if the input signal is not biased within this recommended input dc common-mode voltage range, if high-pass
filtering is needed, or if a single-ended source is used. If highpass filtering is needed at the input, the input capacitor and the
input resistor of the SSM2375 form a high-pass filter whose
corner frequency is determined by the following equation:
fC = 1/(2π × RIN × CIN)
The input capacitor can significantly affect the performance of
the circuit. Not using input capacitors degrades both the output
offset of the amplifier and the dc PSRR performance.
POWER SUPPLY DECOUPLING
To ensure high efficiency, low total harmonic distortion (THD),
and high PSRR, proper power supply decoupling is necessary.
Noise transients on the power supply lines are short-duration
voltage spikes. These spikes can contain frequency components
that extend into the hundreds of megahertz. The power supply
input must be decoupled with a good quality, low ESL, low ESR
capacitor, with a minimum value of 4.7 µF. This capacitor
bypasses low frequency noises to the ground plane. For high
frequency transient noises, use a 0.1 µF capacitor as close as
possible to the VDD pin of the device. Placing the decoupling
capacitors as close as possible to the SSM2375 helps to maintain
efficient performance.
Rev. A | Page 14 of 16
Data Sheet
SSM2375
OUTLINE DIMENSIONS
1.490
1.460 SQ
1.430
3
2
1
A
BALL A1
IDENTIFIER
1.00
REF
B
C
0.50
BSC
TOP VIEW
BOTTOM VIEW
(BALL SIDE UP)
(BALL SIDE DOWN)
0.385
0.360
0.335
COPLANARITY
0.05
END VIEW
SEATING
PLANE
0.350
0.320
0.290
0.270
0.240
0.210
09-04-2012-C
0.655
0.600
0.545
Figure 36. 9-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-9-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
SSM2375CBZ-REEL
SSM2375CBZ-REEL7
EVAL-SSM2375Z
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
9-Ball Wafer Level Chip Scale Package [WLCSP]
9-Ball Wafer Level Chip Scale Package [WLCSP]
Evaluation Board
Z = RoHS Compliant Part.
This package option is halide free.
Rev. A | Page 15 of 16
Package Option 2
CB-9-2
CB-9-2
SSM2375
Data Sheet
NOTES
©2010–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09011-0-4/13(A)
Rev. A | Page 16 of 16