Evaluation Board User Guide
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One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Evaluating the ADAU1442, ADAU1445, and ADAU1446 SigmaDSP Products
FEATURES
GENERAL DESCRIPTION
8-channel analog input and 16-channel analog output
Optical and electrical S/PDIF connections directly to the
S/PDIF I/O pins on the DSP
Full access to all digital I/O via digital connectors
Built-in USB communications interface
Built-in power regulator with wall supply
Interface to external GPIO board
Self-boot capability
Includes full version of SigmaStudio programming tools
Compatible with industry-standard communications and
audio interfaces
This document explains the design and setup of the evaluation
boards for the ADAU1442, ADAU1445, and ADAU1446
SigmaDSP® products. Two evaluation boards are available: the
EVAL-ADAU144xEBZ for evaluation of the ADAU1442 and
ADAU1445, and the EVAL-ADAU1446EBZ for evaluation of
the ADAU1446. Together, the boards are referred to as the EVALADAU144xEBZ.
The EVAL-ADAU144xEBZ provides a full range of analog
and digital inputs and outputs to and from the ADAU144x.
The SigmaDSP can connect to analog I/O signals through
AD1938 codecs. Digital I/O connections are available in both
S/PDIF and 3-wire serial data formats.
PACKAGE CONTENTS
EVAL-ADAU144xEBZ
Universal power supply
USB cable
GPIO daughter board
EVAL-ADUSB2EBZ
QuickStart Guide
EVALUATION BOARD FUNCTIONAL BLOCK DIAGRAM
ANALOG
INPUTS
ANALOG
OUTPUTS
AD1938
CODECS
POWER SUPPLY
REGULATION
DIGITAL
CONNECTORS
COMMUNICATIONS
HEADERS
®
USB CONTROL
INTERFACE
S/PDIF
RECEIVER AND
TRANSMITTER
SPI/I2C
ADAU144x
MULTIPURPOSE PIN INTERFACE
Figure 1.
See the last page for an important warning and disclaimers.
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SELF-BOOT
EEPROM
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Evaluation Board User Guide
TABLE OF CONTENTS
Features .............................................................................................. 1
Transistors ................................................................................... 17
Package Contents .............................................................................. 1
Links ............................................................................................. 18
General Description ......................................................................... 1
Switches ....................................................................................... 20
Evaluation Board Functional Block Diagram ............................... 1
Connectors and Jacks................................................................. 22
Revision History ............................................................................... 2
Circuit Schematics .......................................................................... 24
Using the EVAL-ADAU144xEBZ with SigmaStudio ....................... 3
ADAU144x SigmaDSP .............................................................. 24
SigmaStudio Software Installation ............................................. 3
S/PDIF Transmitter and Receiver ............................................ 25
Installing the Drivers ................................................................... 3
Self-Boot EEPROM .................................................................... 25
Connecting the Evaluation Board .............................................. 4
AD1938 Audio Codecs .............................................................. 26
Adding the EVAL-ADAU144xEBZ to a SigmaStudio Project 4
Analog Audio Inputs .................................................................. 27
Adding an ADAU144x IC............................................................ 5
Analog Audio Outputs ............................................................... 30
Adding a Self-Boot EEPROM ..................................................... 5
External Connectors .................................................................. 34
Programming the Signal Flow .................................................... 5
USB Control Interface ............................................................... 37
Monitoring the USB Communications ................................... 12
Reset Generator .......................................................................... 38
Programming the Self-Boot EEPROM .................................... 12
Power Supply............................................................................... 38
Hardware Description .................................................................... 13
Bill of Materials ........................................................................... 39
Integrated Circuits (ICs) ............................................................ 13
ESD Caution................................................................................ 43
Crystal Resonators...................................................................... 16
REVISION HISTORY
4/10—Revision 0: Initial Version
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USING THE EVAL-ADAU144xEBZ WITH SigmaStudio
SigmaStudio SOFTWARE INSTALLATION
5.
SigmaStudio™ must be installed to use the EVAL-ADAU144xEBZ.
To install the Sigma Studio software, obtain the password from
the QuickStart™ Guide and follow these steps:
Click Search for the best driver in these locations and
select Include this location in the search.
6.
Click Browse and select the USB drivers subfolder, located
in the SigmaStudio install directory.
1.
7.
Click Next.
2.
3.
4.
If Microsoft® .NET Framework Version 2.0 is not already
installed on the PC, install it by downloading the redistributable package from the Microsoft website.
Download the SigmaStudio software
from http://www.analog.com/sigmastudiodownload.
Open the .zip file and extract the files to your PC.
Install SigmaStudio by double-clicking setup.exe and
following the prompts. A computer restart is not required.
INSTALLING THE DRIVERS
After SigmaStudio is installed, follow these steps to install the
drivers:
Figure 4. Windows Found New Hardware Wizard Search and Install Options
8.
When the warning about Windows logo testing appears,
click Continue Anyway.
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2.
Plug the USBi into the USB port of the PC using the
included mini USB cable.
If this is the first time the USBi has been connected to the
PC, the Windows Found New Hardware notification
should appear in the taskbar.
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1.
Figure 2. Windows Found New Hardware Notification
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4.
When the Found New Hardware Wizard opens, click Install
from a list or specific location (Advanced).
Click Next.
Figure 5. Windows Logo Test Warning
Next, Windows proceeds with the installation of the drivers, as
shown in Figure 6.
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3.
Figure 3. Windows Found New Hardware Wizard
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ADDING THE EVAL-ADAU144xEBZ TO A
SigmaStudio PROJECT
To use the EVAL-ADAU144xEBZ with SigmaStudio, follow
these steps:
1.
2.
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3.
Figure 6. Windows Installation of the USBi Drivers
When the installation of the drivers is complete, the
window shown in Figure 7 appears. Click Finish.
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9.
Start the SigmaStudio software.
Begin a new project by opening the File menu and
selecting New Project. (The keyboard shortcut for this
operation is Ctrl + N.)
The default view in SigmaStudio is the Hardware
Configuration tab.
a. On the left side of the screen is the Tree Toolbox tab.
b. Within the Tree Toolbox there is a subsection called
Communication Channels. From the list of Communication Channels, click and hold USBi dragging it to the
right into the empty white project space. See Figure 9
and Figure 10 for details.
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Figure 9. Adding the USBi Communication Channel to the Evaluation Board
for the ADAU144x
Figure 7. Driver Installation Complete
Figure 10. Adding a USBi to the Project
If SigmaStudio cannot detect the USBi on the USB port of the
computer, the background of the USB label turns red, as shown
in Figure 11. This happens if the USBi is not connected or when
the drivers are not installed correctly.
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A notification of successful installation should appear in the
taskbar, as shown in Figure 8.
Figure 8. Successful Driver Installation Notification
1.
2.
Plug the included dc power supply into the J24 power jack on
the board.
Connect the USBi 10-pin communication cable to the J18
communications port on the evaluation board.
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CONNECTING THE EVALUATION BOARD
Figure 11. EVAL-ADAU144xEBZ Not Detected by SigmaStudio
If SigmaStudio detects the USBi on the USB port, the background of the USB label changes to orange, as shown in Figure 12.
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ADDING A SELF-BOOT EEPROM
To evaluate the EVAL-ADAU144xEBZ self-boot functionality,
an E2Prom IC must be added to the project. This corresponds
to the EEPROM U2 device on the evaluation board.
Click and drag an E2Prom IC into the project space.
Drag a wire from the second blue pin on the USBi to the
green pin on the E2Prom IC, as shown in Figure 16.
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1.
2.
Figure 12. USBi Detected by SigmaStudio
ADDING AN ADAU144x IC
Figure 15. Adding an E2Prom IC
To communicate with the targeted ADAU144x IC on the
evaluation board, add ADAU144x to the processor list in
SigmaStudio.
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When the second pin on the USBi communication channel
is connected to the EEPROM, I2C Address 0xA0 is assigned
automatically.
Figure 13. Adding an ADAU144x IC
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To use the USBi to communicate with the target ADAU144x IC,
click the top blue pin of the USB and drag a wire to the green
pin of the ADAU144x IC 1, as shown in Figure 14. The I2C
Address 0x70 is assigned automatically.
Figure 16. Connecting the EVAL-ADAU144xEBZ to the E2Prom IC
An E2Prom IC does not have to be added unless the self-boot
functionality of the board is required.
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PROGRAMMING THE SIGNAL FLOW
To program the signal processing flow, use the Schematic tab,
located at the top of the window as shown in Figure 17.
1.
Click the Schematic tab.
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Figure 14. Connecting the EVAL-ADAU144xEBZ to an ADAU144x IC
Figure 17. Schematic Tab
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3.
Click and drag the Input cell into the project space, as
shown in Figure 20.
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The left side of the schematic box shows the Tree ToolBox. It
contains a list of all signal processing algorithms for use in the
ADAU144x, as shown in Figure 18.
Figure 20. Input Cell
4.
Open the IO folder.
a. Open the Output subfolder.
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b. Locate an Output cell, as shown in Figure 21.
Figure 18. Tree ToolBox
Open the IO folder.
a. Open the Input subfolder.
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b. Locate an Input cell, as shown in Figure 19.
Figure 21. Locating an Output Cell
5.
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2.
Figure 19.Locating an Input Cell
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Click and drag the Output cell into the project space, as
shown in Figure 22.
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To control the volume of the output, a volume control is
required.
7.
Open the Volume Controls folder.
a. Open the Adjustable Gain subfolder.
b. Open the Shared Slider subfolder.
c. Open the Clickless SW Slew subfolder.
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d. Locate the Single SW slew vol cell.
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Figure 24. Locating the Single Slew Volume Cell
8.
Figure 22. Input Cell and Output Cell
Click and drag the Single SW slew vol cell into the project
space, as shown in Figure 25.
To have stereo inputs and outputs, one additional Output cell is
required.
Select the Output1 cell.
a. Press Ctrl + C to copy the cell.
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b. Then press Ctrl + V to paste the copy of the cell. There
should now be two output cells, as shown in Figure 23.
Figure 25. Stereo Input and Output with Slew Volume
To make the volume control stereo, follow these steps as
illustrated in Figure 26.
9.
Right click SW_vol_1, the volume control cell.
10. Select Grow Algorithm, 1. Volume (SW slew).
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6.
11. Select 1.
Figure 23. Stereo Input and Output
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13. Click and drag the Medium Size Eq cell into the project space,
as shown in Figure 29.
Figure 26. Growing the Volume Control
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The resulting volume control cell has two inputs and two outputs
marked with the green and blue points in Figure 27.
Figure 29. Stereo Audio Flow with Volume Control and Single-Band Equalizer
To add more bands to the equalizer, follow Step 14 through
Step 16 (illustrated in Figure 30) and adjust the filter parameters
following Step 17 and Step 18.
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14. Right-click Grow Algorithm.
15. Select 1. 2 Channel – Single Precision.
Figure 27. Stereo Volume Control
16. Select 2.
To add an equalizer, a filter is required. To add a filter, follow
these steps (illustrated in Figure 28):
12. Open the Filters folder.
a. Open Second Order subfolder.
b. Open the Single Precision subfolder.
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c. Open the 2 Ch subfolder.
d. Locate the Medium Size Eq cell.
Figure 30. Growing the Equalizer
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17. Click the blue equalizer icon to alter filter parameters
(see Figure 31).
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Figure 31. Filter Parameters Icon
Figure 28. Locating the Medium Size Equalizer Cell
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18. Configure the filter parameters for each band, as desired
(see Figure 32).
Figure 32. Filter Parameters
Figure 33. Completed Audio Path
20. Set the switches and jumpers to correspond to the default
settings in Figure 35. A black rectangle corresponds to the
position of a switch or jumper.
21. Connect an audio source to the audio input jack, J12, and a
pair of headphones or powered speakers to the audio
output jack, J4.
22. Click the Link Compile Download button to download
the program to the ADAU144x IC.
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19. For each cell, click the blue pin and drag a wire to the green
pin to create an audio path from the input to the output for
each channel, as shown in Figure 33.
Figure 34. Link Compile Download
The device should now process audio in real time.
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Figure 35. Default Switch and Jumper Settings
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Default Switch and Jumper Setting Descriptions
The default setup represents the state of the board when it
leaves the factory. With this configuration, the analog audio is
routed from the input connectors to the codecs, in and out of
the DSP, back through the codecs, and to the output connectors.
Descriptions with direction references are based on the orientation of the board shown in Figure 35.
Table 1. Default Switch and Jumper Setting Descriptions
Board Element
Crystal Oscillator Circuit
Regulator DVDD, IOVDD, AVDD
PVDD
Op Amps
USB Communications
PLLx
CLKMODEx
SELFBOOT
ADRR0
CDATA Line
S/PDIF Receiver
Codec 1 and Codec 2
Serial Ports on Codec 1 and Codec 2
Connection Between the Codecs
and the ADAU144x
Op Amp Reference
Microphone Input
Self-Boot EEPROM
GPIO Interface Board Supply
External Communications Interface
Description
Used as a master clock source. LK1 connected.
Active. LK5, LK11, and LK13 connected.
Active.
Use a 5 V supply. LK19 connected.
Active and in I2C mode. LK27 is in the up position. Note that the SPI functionality of the USB
communications interface has not yet been implemented, and users wishing to test SPI functionality
should connect the EVAL-ADUSB2 (USBi) to the Aardvark header, J18.
Set to 010, 256 × fS mode. The S2 Switch 1, S2 Switch 2, and S2 Switch 3 are in the right, left, and right,
positions, respectively.
In Mode 01, with buffered oscillator output. The S2 Switch 4 and S2 Switch 5 are in the right and left
positions, respectively.
Inactive. The S2 Switch 6 is in the right position.
Set to 0. The S2 Switch 7 is in the right position.
Active. The S2 Switch 8 is in the right position.
Set to RCA/coaxial connector. The S1 switch is in the right position.
Set as slaves to the ADAU144x. LK7 and LK9 are in the right position.
Set as slaves to the ADAU144x. LK6 and LK8 are in the right position.
Enabled. The S6 and S7 switches are in the up position.
Set to FILTR. LK18 is connected, and LK17 is disconnected.
Disabled. LK14 is in the up position.
Connected to the ADAU144x IC. LK15 and LK16 are connected.
Set to 3.3 V. LK10 is set to 3.3 V.
Set to I2C mode. The S4 switch is set to I2C.
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MONITORING THE USB COMMUNICATIONS
Click the expand/collapse button in the leftmost column to view
the full data write. Otherwise, for block writes where more than
one memory location is written, only the first location is shown.
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Use the Capture Window to view all communication transfers
between the PC and the target IC (see Figure 38). For each write,
the write mode, time of write, cell name (if applicable), parameter
name, address, data (in decimal and hexadecimal), and length
are shown.
Figure 36. Writing to the Self-Boot EEPROM
PROGRAMMING THE SELF-BOOT EEPROM
2.
3.
4.
Connect an E2Prom IC to the EVAL-ADAU144xEBZ in
the Hardware Configuration window.
Verify that the EEPROM write protect pin is disabled on
the target board.
Link-compile-download the project by clicking the Link
Compile Download button.
Right-click the ADAU144x IC, and select Write Latest
Compilation to E2PROM, as shown in Figure 36.
Figure 37. Self-Boot EEPROM Download Progress Bar
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1.
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After compiling a project, the registers and RAM contents of the
ADAU144x can be written to a target EEPROM for self-boot. To
use this functionality
Figure 38. Output Capture Window
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HARDWARE DESCRIPTION
INTEGRATED CIRCUITS (ICs)
U19
U20
U17
U1
U16
U18
U2
LK29
U6
U3
U4
U21
U5
U7
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U22
Figure 39. IC Layout
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Table 2. IC Descriptions
Reference
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
LK29
Functional Name
ADAU144x SigmaDSP
24AA256-I/ST 256 kb serial EEPROM
AD1938 audio codec
AD1938 audio codec
TOTX141P 15 Mbps optical transmitter
TORX147L 15 Mbps optical receiver
SC937-02 110 Ω AES/EBU transformer
AD8608ARZ low noise op amp
AD8608ARZ low noise op amp
AD8608ARZ low noise op amp
AD8608ARZ low noise op amp
AD8608ARZ low noise op amp
AD8608ARZ low noise op amp
AD8608ARZ low noise op amp
AD8608ARZ low noise op amp
FT245BL USB to parallel FIFO interface
PIC16LF877-04/PT microcontroller
AT93C46-10SU-2.7 1 kb serial EEPROM
ADP3336ARMZ low dropout voltage regulator
ADP3339AKCZ low dropout voltage regulator
ADM811RARTZ logic low reset output
AD8608ARZ low noise op amp
ASEP3JL-ND programmable oscillator
Description
Digital audio signal processor
Self-boot memory
ADC for Input 0 to Input 3; DAC for Output 0 to Output 7
ADC for Input 4 to Input 7; DAC for Output 8 to Output 15
S/PDIF output jack
S/PDIF input jack
Transformer for electrical S/PDIF output
Filter op amp for Output 0 to Output 3
Filter op amp for Output 4 to Output 7
Filter op amp for Output 8 to Output 11
Filter op amp for Output 12 to Output 15
Filter op amp for Input 0 to Input 1
Filter op amp for Input 2 to Input 3
Filter op amp for Input 4 to Input 5
Filter op amp for Input 6 to Input 7
USB to parallel communications interface
Parallel to SPI/I2C communications interface
USB vendor ID and product ID memory
Analog supply voltage regulator
Digital supply voltage regulator
Master reset generator
Microphone balanced-to-unbalanced converter
Active 12.288 MHz oscillator
Detailed IC Descriptions
U4—AD1938 Audio Codec
U1—ADAU144x SigmaDSP
A four-ADC, eight-DAC audio codec that allows connection of
analog audio signals to the board. The U4 handles Input 4 to
Input 7 and Output 8 to Output 15. It is capable of running synchronously to the ADAU144x or using its own crystal oscillator
circuit. Its serial ports can also act as either master or slave.
Main audio signal processor and connectivity hub in the system.
It includes nine serial input ports and nine serial output ports,
with a total I/O capability of 24 serial audio channels. In addition, two pins are designated as S/PDIF input/output ports.
Inside the DSP are eight asynchronous sample rate converters,
each capable of using any available clock domain as an output
sample rate. The SigmaDSP core runs at 172 MHz and can be
programmed via USB by the SigmaStudio programming tool.
U2—24AA256-I/ST 256 kb Serial EEPROM
Self-boot memory. Has enough memory to store an entire program, including program RAM, parameter RAM, and register
settings. The ADAU144x can optionally boot from this memory
on power-up, reducing the need for a system microcontroller.
U3—AD1938 Audio Codec
A four-ADC, eight-DAC audio codec that allows connection
of analog audio signals to the board. The U3 handles Input 0
to Input 3 and Output 0 to Output 7. It is capable of running
synchronously to the ADAU144x or using its own crystal oscillator circuit. Its serial ports can also act as either master or slave.
U5—TOTX141P 15 Mbps Optical Transmitter
Optical transmitter for S/PDIF signals coming from the SPDIFO
pin of the ADAU144x. It is always active.
U6—TORX147L 15 Mbps Optical Receiver
Optical receiver for S/PDIF signals, which are then routed to
the SPDIFI pin of the ADAU144x. It is selected by putting the
S3 switch into the left position (opposite the RCA label on the
silkscreen).
U7—SC937-02 110 Ω AES/EBU Transformer
Transformer that conditions the S/PDIF output signal from the
SPDIFO pin on the ADAU144x and prepares it for output on
Connector J2, the electrical S/PDIF output jack.
U8—AD8608ARZ Low Noise Op Amp
Operational amplifier used to actively filter the analog outputs
of the AD1938 codecs. The U8 handles Output 0 to Output 3.
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U9—AD8608ARZ Low Noise Op Amp
U17—PIC16LF877-04/PT Microcontroller
Operational amplifier used to actively filter the analog outputs
of the AD1938 codecs. The U9 handles Output 4 to Output 7.
U17 is a microcontroller that serves as a parallel FIFO to the
SPI or I2C bidirectional communications interface. It enables
communication between the ADAU144x and the SigmaStudio
programming tool via the FT245BL.
U10—AD8608ARZ Low Noise Op Amp
Operational amplifier used to actively filter the analog outputs of
the AD1938 codecs. The U10 handles Output 8 to Output 11.
U11—AD8608ARZ Low Noise Op Amp
Operational amplifier used to actively filter the analog outputs
of the AD1938 codecs. The U11 handles Output 12 to Output 15.
U12—AD8608ARZ Low Noise Op Amp
Operational amplifier used to actively filter the analog inputs of
the AD1938 codecs. The U12 handles Input 0 to Input 1.
U13—AD8608ARZ Low Noise Op Amp
Operational amplifier used to actively filter the analog inputs of
the AD1938 codecs. The U13 handles Input 2 to Input 3.
U14—AD8608ARZ Low Noise Op Amp
Operational amplifier used to actively filter the analog inputs to
the AD1938 codecs. The U14 handles Input 4 to Input 5.
U15—AD8608ARZ Low Noise Op Amp
Operational amplifier used to actively filter the analog inputs of
the AD1938 codecs. The U15 handles Input 6 to Input 7.
U16—FT245BL USB to Parallel FIFO Interface
Note that in the current revision of the board, this device is
disabled. The evaluation kit includes the EVAL-ADUSB2EBZ to
be used as a communication interface.
U18—AT93C46-10SU-2.7 1 kb Serial EEPROM
USB device identification memory that contains the USB vendor
ID and product ID numbers, allowing the correct driver to be
chosen and enabling communications to the USB port of the PC.
U19—ADP3336ARMZ Low Dropout Voltage Regulator
U19 is the analog supply voltage regulator; it regulates the dc
power supply to a 3.3 V analog supply.
U20—ADP3339AKCZ Low Dropout Voltage Regulator
Digital supply voltage regulator; it regulates the dc power supply
to a 3.3 V digital supply.
U21—ADM811RARTZ Logic Low Reset Output
Debounced reset signal generator that acts as a master reset for
the board.
U22—AD8608ARZ Low Noise Op Amp
Operational amplifier used to take a balanced analog microphone
input signal and convert it to an unbalanced signal.
Single-chip USB used to parallel the FIFO bidirectional data
transfer interface. It enables communication between the
ADAU144x and the SigmaStudio programming tool via the
PIC16LF877 microcontroller.
LK29—ASEP3JL-ND Programmable Oscillator
Note that in the current revision of the board, this device is
disabled. The evaluation kit includes the EVAL-ADUSB2EBZ to
be used as a communication interface.
An active oscillator that generates a clock signal at 12.288 MHz; it
is useful for simulating an external master clock source in the
system.
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CRYSTAL RESONATORS
Y5
Y1
Y4
Y3
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Y2
Figure 40. Crystal Resonator Layout
Table 3. Crystal Resonator Descriptions
Reference
Y1
Y2
Y3
Y4
Y5
Name
DSP crystal
Codec 1 crystal
Codec 2 crystal
Microcontroller crystal
USB interface crystal
Description
12.288 MHz crystal for the ADAU144x
12.288 MHz crystal for the AD1938 Codec 1
12.288 MHz crystal for the AD1938 Codec 2
6.000 MHz crystal for the PIC16LF877 microcontroller
10.000 MHz crystal for the FT245BL USB interface
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TRANSISTORS
Q1
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Q2
Figure 41. Transistor Layout
Table 4. Transistor Descriptions
Reference
Q1
Q2
Name
Voltage regulator transistor
Microcontroller JTAG reset transistor
Description
Darlington PNP transistor. Acts as a pass transistor for the DVDD supply.
Reset transistor. Required component of the JTAG microcontroller programming circuit.
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19
20
21
22
LINKS
25
26
10
5
13
11
23
27
12
15
16
1
2
3
4
28
24
9
7
6
18 17
8
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14
Figure 42. Link Layout
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Table 5. Link Descriptions
Reference
LK1
Functional Name
Clock select, crystal oscillator circuit
LK2
Clock select, BNC
LK3
Clock select, external clock input
LK4
Clock select, FPGA board
LK5
DVDD regulator circuit enable
LK6
Codec 1 master/slave
LK7
Codec 1 clock select
LK8
Codec 2 master/slave
LK9
Codec 2 clock select
LK10
Multipurpose board supply select
LK11
LK12
LK13
LK14
AVDD enable
PVDD enable
IOVDD enable
Microphone input select
LK15
EEPROM SCL connect
LK16
EEPROM SDA connect
LK17
Op amp reference select, VREF
LK18
Op amp reference select, FILT
LK19
Op amp supply select, 5 V
LK20
Op amp supply select, DVDD
LK21
Op amp supply select, AVDD
LK22
Op amp supply select, GND
LK23
LK24
LK25
Futures
Communication active signal output
Codec 1 external SPI latch connect
LK26
Codec 2 external SPI latch connect
Description
LK1, LK2, LK3, LK4, and LK28 select the master clock input to the ADAU144x. LK1
connects the ADAU144x to its crystal oscillator circuit.
LK1, LK2, LK3, LK4, and LK28 select the master clock input to the ADAU144x. LK2
connects the ADAU144x to a master clock signal input on the SMA input header, J3.
LK1, LK2, LK3, LK4, and LK28 select the master clock input to the ADAU144x. LK3
connects the ADAU144x to an external MCLK signal from the multipurpose pin
interface, J20.
LK1, LK2, LK3, LK4, and LK28 select the master clock input to the ADAU144x. LK4
connects the ADAU144x to an external MCLK signal coming from header, J23.
Connects a regulated DVDD supply from the collector of the pass transistor, Q1, to the
ADAU144x.
Places the Codec 1 serial ports in either master or slave mode, which are marked by M
or S on the silkscreen, respectively.
Connects or disconnects Codec 1 from its crystal oscillator circuit. When disconnected, the codec receives a master clock signal from the ADAU144x.
Places the Codec 2 serial ports in either master or slave mode, which are marked by M
or S on the silkscreen, respectively.
Connects or disconnects Codec 2 from its crystal oscillator circuit. When disconnected, the codec receives a master clock signal from the ADAU144x.
Selects either a 3.3 V (DVDD) or 5 V supply for the optional external multipurpose
board, which attaches to the J20 header.
Connects the AVDD supply to the ADAU144x.
Connects the PVDD supply to the ADAU144x.
Connects the IOVDD supply to the ADAU144x.
Allows the microphone to be input to Codec 2. By default, the jumper should be set
on LINE, which enables both channels on the J15 input jack. However, when set to
MIC, the left channel of J15 is replaced by the microphone signal on J25.
Connects the SCL line of the self-boot EEPROM U2 to the ADAU144x. The jumper must
be connected to program and read from the EEPROM.
Connects the SDA line of the self-boot EEPROM U2 to the ADAU144x. The jumper
must be connected to program and read from the EEPROM.
LK17 and LK18 select the reference level for the active filters. Connecting LK17 selects
a OPVDD/2 reference from a voltage divider on the OPVDD supply.
LK17 and LK18 select the reference level for the active filters. Connecting LK18 selects
a reference output directly from the AD1938 codec.
LK19 to LK22 select the supply for the filter operational amplifiers. LK19 connects a 5 V
supply.
LK19 to LK22 select the supply for the filter operational amplifiers. LK20 connects the
op amps to the DVDD supply.
LK19 to LK22 select the supply for the filter operational amplifiers. LK21 connects the
op amps to the AVDD supply.
LK19 to LK22 select the supply for the filter operational amplifiers. LK22 disables the
op amps by connecting their supplies to ground.
Connects a pin on the microcontroller, which is not yet implemented.
Connects the communications active signal to the multipurpose pin interface header, J20.
Connects the latch signal for Codec 1 to the J18 and J19 external communications
headers, allowing the codec to be programmed independently. When using the
Aardvark or Beagle communications interface in I2C mode, the jumper must be
disconnected.
Connects the latch signal for Codec 1 to the external communications headers (J18
and J19) allowing the codec to be programmed independently. When using the
Aardvark or Beagle communications interface in I2C mode, the jumper must be
disconnected.
Rev. 0 | Page 19 of 44
UG-032
Evaluation Board User Guide
Reference
LK27
Functional Name
Microcontroller communication mode select
LK28
Clock select, active oscillator
Description
Selects either I2C or SPI communication mode for the microcontroller; however, only
I2C is supported by the firmware on the EVAL-ADAU144xEB. To communicate with the
ADAU144x in I2C mode, connect an external I2C programmer to J19.
LK1, LK2, LK3, LK4, and LK28 select the master clock input to the ADAU144x. LK28
selects the ASEP3JL-ND programmable oscillator as the MCLK source.
SWITCHES
S4
S2
S3
S6
S1
08363-043
S7
Figure 43. Switch Layout
Rev. 0 | Page 20 of 44
Evaluation Board User Guide
UG-032
Table 6. Switch Descriptions
Reference
S1
Functional Name
S/PDIF input format select
S2
ADAU144x mode switch
S3
Master reset
S4
Aardvark communication format select
S6
Codec Enable 1
S7
Codec Enable 2
Description
Selects between the optical or electrical S/PDIF receiver input. Note that both
transmitters are active at all times. When the switch is to the left, the optical receiver
is enabled. When to the right, the electrical receiver is enabled.
Sets multiple mode pins on the ADAU144x, including PLL mode, CLK mode, selfboot, and address. For more information on these particular modes, refer to the
ADAU1442/ADAU1445/ADAU1446 datasheet. For each switch, the right position
(the on position) corresponds to a Logic 0. The left position corresponds to a Logic 1.
Triggers a single reset pulse from reset generator U21, and resets all major ICs on
the board.
Selects between I2C and SPI mode for the Aardvark communication interface. When
the switch is in the left position, I2C communications are enabled. When to the right, SPI
communications are enabled.
Enables communication between the ADAU144x and the AD1938 Codec 1. When
the switches are in the on position (up), communications are enabled, and signals
travel freely between the two ICs. When in the off position (down), the signals are
blocked. To use the J21, J22, and J23 headers to input audio data to the ADAU144x
directly, make sure these switches are in the off position.
Enables communication between the ADAU144x and the AD1938 Codec 2. When
the switches are in the on position (up), communications are enabled, and signals
travel freely between the two ICs. When the switches are in the off position (down),
the signals are blocked. To use the J21, J22, and J23 headers to input audio data to
the ADAU144x directly, make sure these switches are in the off position.
Rev. 0 | Page 21 of 44
UG-032
Evaluation Board User Guide
CONNECTORS AND JACKS
J19
J24
J18
J17
J12
J16
J13
J14
J15
J3
J4
J20
J5
J6
J7
J1
J8
J21
J9
J22
J10
J23
J11
J2
08363-044
J25
Figure 44. Connectors and Jacks Layout
Rev. 0 | Page 22 of 44
Evaluation Board User Guide
UG-032
Table 7. Connector and Jack Descriptions
Reference
J1
Functional Name
S/PDIF electrical coax input jack
J2
S/PDIF electrical coax output jack
J3
Master clock input SMA receptacle
J4
J17
J18
Analog Audio Output 0/
Analog Audio Output1
Analog Audio Output 2/
Analog Audio Output 3
Analog Audio Output 4/
Analog Audio Output 5
Analog Audio Output 6/
Analog Audio Output 7
Analog Audio Output 8/
Analog Audio Output 9
Analog Audio Output 10/
Analog Audio Output 11
Analog Audio Output 12/
Analog Audio Output 13
Analog Audio Output 14/
Analog Audio Output 15
Analog Audio Input 0/
Analog Audio Input 1
Analog Audio Input 2/
Analog Audio Input 3
Analog Audio Input 4/
Analog Audio Input 5
Analog Audio Input 6/
Analog Audio Input 7
Microcontroller programming
header
USB connector
Aardvark programming header
J19
J20
Beagle header
Multipurpose pin interface
J21
ADAU144x Interface Connector 1
J22
ADAU144x Interface Connector 2
J23
ADAU144x Interface Connector 3
J24
Coaxial 5 V power jack
J25
Microphone input jack
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
Description
Electrical input jack for the S/PDIF signals. To be active, it must first be selected with
Switch S1. The signal input on this jack is accessible at the SPDIFI pin on the ADAU144x.
Electrical output jack for S/PDIF signals. This jack always needs to be active; it outputs the
signal directly from the SPDIFO jack of the ADAU144x.
Input jack for external master clock signals to the ADAU144x. It is selected by connecting
the jumper on LK2.
Stereo audio output from the AD1938 Codec 1, Channel 0 and Channel 1.
Stereo audio output from AD1938 Codec 1, Channel 2 and Channel 3.
Stereo audio output from AD1938 Codec 1, Channel 4 and Channel 5.
Stereo audio output from AD1938 Codec 1, Channel 6 and Channel 7.
Stereo audio output from AD1938 Codec 2, Channel 8 and Channel 9.
Stereo audio output from AD1938 Codec 2, Channel 10 and Channel 11.
Stereo audio output from AD1938 Codec 2, Channel 12 and Channel 13.
Stereo audio output from AD1938 Codec 2, Channel 14 and Channel 15.
Stereo audio input to AD1938 Codec 1, Channel 0 and Channel 1.
Stereo audio input to AD1938 Codec 1, Channel 2 and Channel 3.
Stereo audio input to AD1938 Codec 2, Channel 4 and Channel 5.
Stereo audio input to AD1938 Codec 2, Channel 6 and Channel 7.
Connects directly to the programming port on the PIC16LF877 microcontroller.
Connects the EVAL-ADAU144xEBZ board to the USB port of a PC.
Allows communication via an Aardvark communication interface instead of the USB
connector. An EVAL-ADUSB2EBZ (also known as USBi) can be connected here, as well.
When J18 is used, the USB connector of the board, J17, should be disconnected from the
USB port of the PC.
Allows communication monitoring via a Beagle sniffer communication interface.
Connects to the included external GPIO daughter board, which allows control of the
ADAU144x via its MP pins. The GPIO board has several forms of interface circuitry,
including potentiometers, pushbuttons, and LEDs.
Header that allows direct access to many of the ADAU144x pins. For more information,
see Figure 58.
Header that allows direct access to many of the ADAU144x pins. For more information,
see the schematic in Figure 58.
Header that allows direct access to many of the ADAU144x pins. For more information,
see the schematic in Figure 58.
Connector for a standard power supply. The supply should be between 5 V and 6 V,
sourcing at least 1.5 A, and have a tip positive polarity.
Mono differential microphone input.
Rev. 0 | Page 23 of 44
UG-032
Evaluation Board User Guide
CIRCUIT SCHEMATICS
ADAU144x SigmaDSP
DVDD
C14
LK13
0.10µF
C13
0.10µF
C12
0.10µF
C11
C6
0.10µF
C10
0.10µF
C5
0.10µF
C9
0.10µF
C4
0.10µF
C8
0.10µF
C3
0.10µF
C7
0.10µF
C2
0.10µF
C16
0.10µF
+
C1
10uF
TP1
0.10µF
TP2
C15
AVDD PVDD TP4
+
NJT4030PT3G
Q1
C206
+
10uF
LRCLK0
BCLK0
15
LRCLK0
12
BCLK0
[5]
[5]
LRCLK1
BCLK1
10
LRCLK1
9
BCLK1
[5]
[5]
LRCLK2
BCLK2
7
LRCLK2
6
BCLK2
[2,5]
[2,5]
LRCLK3
BCLK3
4
LRCLK3
3
BCLK3
[2,5]
[2,5]
LRCLK4
BCLK4
97
LRCLK4
96
BCLK4
[5]
[5]
LRCLK5
BCLK5
93
LRCLK5
92
BCLK5
[5]
[5]
LRCLK6
BCLK6
86
LRCLK6
85
BCLK6
[5]
[5]
LRCLK7
BCLK7
82
LRCLK7
81
BCLK7
[5]
[5]
LRCLK8
BCLK8
78
LRCLK8
74
BCLK8
[2,5]
[2,5]
LRCLK9
BCLK9
71
LRCLK9
70
BCLK9
[5]
[5]
LRCLK10
BCLK10
68
LRCLK10
67
BCLK10
[5]
[5]
LRCLK11
BCLK11
65
LRCLK11
64
BCLK11
44
PVDD
48
AVDD
2
14
27
39
52
63
77
89
25
37
50
75
87
100
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
C217
100nF
C216
100nF
[2,5]
[2,5]
[2,5]
[2,5]
[2,5]
[2,5]
[2,5]
[2,5]
[5]
SDATA_OUT0
SDATA_OUT1
SDATA_OUT2
SDATA_OUT3
SDATA_OUT4
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7
SDATA_OUT8
58
57
56
55
36
35
34
33
19
18
17
16
DVDD
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
MP0
MP1
MP2
MP3
MP4
MP5
MP6
MP7
MP8
MP9
MP10
MP11
R154
10k0
DVDD
R10
10k0
PLL0
PLL1
PLL2
CLKMODE0
CLKMODE1
31
RSVD [5]
10k0
1
2
3
4
5
6
7
8
[1,5,6]
SELFBOOT
[1,5]
ADDR0
[1,2,5,6] CDATA/ADDR1
S2
SW8DIP
[5]
[5]
[5]
[5]
[5]
16
15
14
13
12
11
10
9
DVDD
SPDIFI
54
FPGA_CLK [5]
[2,5,6]
RESET
53
CLKOUT
[2,5]
TP5
R7
OPEN
LK3
MCLK_EXT [5]
J3
LK2
SPDIFO
42
XTALI
41
XTALO
TP7
TP6
R9
OPEN
22pF
PLL_FILT
R8
100k
43
Y1
12.288 MHz
TP8
C23
33nF
C24
1n8F
R5
C21
100r
22pF
C17
OPEN
R6
1k50
DVDD
LK28
L3
PVDD_CONNECT [1]
R191
10k0
R192
49R9
VDD
LK29
OE
OUTPUT
GND
12.288MHz programmable
08363-045
ADDR0
ADDR1/CDATA
CLATCH
SCL/CCLK
SDA/COUT
SELFBOOT
C20
LK1
100nF
20
24
21
22
23
28
+
LK4
CLKOUT
47
98
94
90
83
79
72
69
66
61
R162
PGND
[1,5]
ADDR0
[1,2,5,6] CDATA/ADDR1
[5,6] CLATCH_1442
[2,5,6]
CCLK/SCL
[2,5,6]
COUT/SDA
[1,5,6]
SELFBOOT
RSVD
RESET
46
C233
10uF
100nF
30
CLKMODE0
29
CLKMODE1
45
[5] SPDIFO
SDATA_IN0
SDATA_IN1
SDATA_IN2
SDATA_IN3
SDATA_IN4
SDATA_IN5
SDATA_IN6
SDATA_IN7
SDATA_IN8
AGND
SPDIFI
C208
60
PLL0
59
PLL1
32
PLL2
49
[5]
MP0/ADC0
MP1/ADC1
MP2/ADC2
MP3/ADC3
MP4
MP5
MP6
MP7
MP8
MP9
MP10
MP11
U1
ADAU1442
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
SDATA_IN0
SDATA_IN1
SDATA_IN2
SDATA_IN3
SDATA_IN4
SDATA_IN5
SDATA_IN6
SDATA_IN7
SDATA_IN8
PVDD
L15
10uF
SDATA_OUT0
SDATA_OUT1
SDATA_OUT2
SDATA_OUT3
SDATA_OUT4
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7
SDATA_OUT8
1
13
26
38
51
62
76
88
[2,5]
[2,5]
[2,5]
[2,5]
[5]
[5]
[5]
[5]
[5]
11
8
5
99
95
91
84
80
73
+
IODVDD
IODVDD
IODVDD
IODVDD
IODVDD
IODVDD
IODVDD
IODVDD
[2,5]
[2,5]
VDRIVE
40
C209
DVDD
100nF
C234
E
C
C207
B
R11
1k00
PVDD_CONNECT [1]
TP3
LK5
8
7
6
5
4
3
2
1
LK11
DVDD
LK12
10uF
Figure 45. ADAU144x Circuit Schematic
Rev. 0 | Page 24 of 44
Evaluation Board User Guide
UG-032
S/PDIF TRANSMITTER AND RECEIVER
DVDD
L1
DVDD
100nF
L2
C22
100nF
5
4
2
SHLD1
SHLD2
R1
2
DVDD
10k0
4
3
DVDD
OUT
DGND1
CASE1
5
U6
TORX147L
C19
CASE2
1
U5
TOTX141P
INPUT
DGND
[5] SPDIFO
3
47
SPDIFO
1
SW-SPDT-C
S1
3
1
J1
2
C18
R3
[5] SPDIFI
10nF
46
243r
SPDIFI
U7
J2
HI
R2
75r
LO
2
5
1
8
6
4
10nF
C215
R4
107r
08363-046
TRAFFO-SC937-02
Figure 46. S/PDIF Transmitter and Receiver Circuit Schematics
SELF-BOOT EEPROM
22
SCL/CCLK
23
SDA/COUT
DVDD
C232
100nF
4
VCC
A1
WP
A2
SCL
GND
SDA
8
7
6
5
E2PROM
08363-047
3
A0
LK16
2
LK15
U2
1
Figure 47. Self-Boot EEPROM Circuit Schematic
Rev. 0 | Page 25 of 44
UG-032
Evaluation Board User Guide
AD1938 AUDIO CODECS
DVDD
AVDD
TP9
+
10uF
C212
100nF
C25
100nF
C26
C27
100nF
C28
10uF
C29
100nF
+
C213
R18
10k0
37
AVDD2 48
OR3
OL4
19
ASDATA2
20
ASDATA1
22 ALRCLK
21
ABCLK
OR4
R19
10k0
R20
10k0
R21
10k0
OUT3 [4]
6
OUT4 [4]
7
OUT5 [4]
8
OUT6 [4]
9
OUT7 [4]
AVDD
R12
562r
5n6F
C34
390pF
C35
47
LF
23 CDATA
24
COUT
26
CCLK
27
CLATCH
10
PD/RST
OUT2 [4]
31
35
FILTR
CM 38
TP10
C32
10uF
100nF
C33
+
B A
LK7
10uF
C36
[1,2,5] CLKOUT
+
FILTR_1
[3]
2
MCLKI/XI
3
MCLKO/XO
C30
OPEN
OL3
DSDATA1
DSDATA2
DSDATA3
DSDATA4
DLRCLK
DBCLK
OUT1 [4]
30
AGND
R17
AD1938
OUT0 [4]
29
C31
16
15
14
11
18
17
28
100nF
S6
SW10DIP
20
19
18
17
16
15
14
13
12
11
32 AGND
OPEN
33
OR2
AGND
OPEN
R16
AVDD2
45
ADC2RP
46
ADC2RN
OPEN
R15
AVDD1
[3] IN3+
[3] IN3-
1
CLATCH_1938-1
OL2
AGND
[5,6]
43
ADC2LP
44
ADC2LN
4 AGND
CCLK/SCL
[3] IN2+
[3] IN2-
OL1
34
COUT/SDA
[1,2,5,6]
OR1
DGND
[1,2,5,6]
R14
41
ADC1RP
42
ADC1RN
25
[1,2,5,6] CDATA/ADDR1
39
ADC1LP
40
ADC1LN
[3] IN1+
[3] IN1-
36
SDATA_OUT0
SDATA_OUT1
SDATA_OUT2
SDATA_OUT3
LRCLK9
BCLK9
SDATA_IN1
SDATA_IN0
LRCLK0
BCLK0
[3] IN0+
[3] IN0-
12 DGND
[1,5]
[1,5]
[1,5]
[1,5]
[1,5]
[1,5]
[1,5]
[1,5]
[1,5]
[1,5]
1
2
3
4
5
6
7
8
9
10
AVDD1 5
DVDD
U3
13
100nF
22pF
R13
100r
Y2
12.288 MHz
C37
DVDD
A B
LK6
22pF
[1,2,5,6] RESET
DVDD
AVDD
TP11
10uF
+
100nF
C210
C38
100nF
C39
C40
100nF
C41
10uF
C42
100nF
+
C211
48
AVDD2
37
OR3
19
ASDATA2
20
ASDATA1
22 ALRCLK
21
ABCLK
OR4
OL4
R30
10k0
R31
10k0
OUT9 [4]
30
OUT10 [4]
31
OUT11 [4]
6
OUT12 [4]
7
OUT13 [4]
8
OUT14 [4]
9
OUT15 [4]
AVDD
R22
562r
5n6F
C47
390pF
C48
LF 47
23 CDATA
24
COUT
26
CCLK
27
CLATCH
10
PD/RST
R29
10k0
OUT8 [4]
29
35
FILTR
CM 38
R23
100r
DVDD
A
LK9
10uF
C45
100nF
C46
+
B
C43
C44
[1,2,5] CLKOUT
10uF
AGND
C49
TP12
+
FILTR_2
2
MCLKI/XI
3
MCLKO/XO
22pF
Y3
12.288 MHz
C50
A B
LK8
[1,2,5,6]
22pF
RESET
Figure 48. AD1938 Codecs Circuit Schematics
Rev. 0 | Page 26 of 44
08363-048
R28
10k0
OL3
DSDATA1
DSDATA2
DSDATA3
DSDATA4
DLRCLK
DBCLK
AGND
OPEN
AD1938
28
100nF
16
15
14
11
18
17
32
R27
AVDD2
OR2
1 AGND
OPEN
5
45 ADC2RP
46 ADC2RN
AGND
OPEN
R26
33
[3] IN7+
[3] IN7-
OPEN
R25
AVDD1
OL2
AGND
CLATCH_1938-2
43 ADC2LP
44 ADC2LN
4
CCLK/SCL
[3] IN6+
[3] IN6-
OL1
34
[6]
COUT/SDA
OR1
DGND
[1,2,5,6]
41 ADC1RP
42 ADC1RN
DGND
[1,2,5,6]
R24
[3] IN5+
[3] IN5-
25
[1,2,5,6] CDATA/ADDR1
39 ADC1LP
40 ADC1LN
36
SDATA_OUT4
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7
LRCLK4
BCLK4
SDATA_IN3
SDATA_IN2
LRCLK3
BCLK3
S7
SW10DIP
20
19
18
17
16
15
14
13
12
11
[3] IN4+
[3] IN4-
12
[1,5]
[1,5]
[1,5]
[1,5]
[1,5]
[1,5]
[1,5]
[1,5]
[1,5]
[1,5]
1
2
3
4
5
6
7
8
9
10
AVDD1
U4
DVDD 13
100nF
STJACK3.5SMALL
J14
TP20
5
1
4
6
TP19
Rev. 0 | Page 27 of 44
R137
49k9
L8
600Z
R136
49k9
L7
600Z
C157
C161
100pF
10uF
C160
+
C156
100pF
10uF
5k76
R124
Figure 49. Audio Input 0 to Audio Input 3 Circuit Schematics
VREF
[3]
VREF
[3]
5k76
R135
VREF
[3]
VREF
[3]
+
C153
100nF
13
12
9
10
C168
100nF
2
3
-
+
-
+
6
5
-
+
C158
14
AD8608
U14-D
5k76
R132
5k76
R133
8
AD8608
U14-C
5k76
R134
120pF
7
AD8608
U14-B
C159
-
+
5k76
R127
5k76
R126
1
AD8608
U14-A
5k76
R125
120pF
+
+
+
+
10uF
C151
10uF
C152
10uF
C154
10uF
C155
C162
1n0F
NP0
237r
R130
237r
R131
C167
1n0F
NP0
237r
R129
237r
R128
C163
1n0F
NP0
C164
100pF
C166
1n0F
NP0
C165
100pF
[2]
TP45
IN5+
IN5-
[2]
[2]
IN4+ [2]
IN4-
MIC_IN
STJACK3.5SMALL
J15
[3]
5
1
4
6
LK14
A B
TP22
TP21
R151
49k9
L12
600Z
R150
49k9
L11
600Z
C175
C179
100pF
10uF
C178
+
C174
100pF
10uF
5k76
R138
VREF
[3]
VREF
[3]
5k76
R149
VREF
[3]
VREF
[3]
+
C171
100nF
13
12
9
10
C186
100nF
2
3
-
+
-
+
6
5
-
+
C176
14
AD8608
U15-D
5k76
R146
5k76
R147
8
AD8608
U15-C
5k76
R148
120pF
C177
-
+
7
AD8608
U15-B
5k76
R141
5k76
R140
1
AD8608
U15-A
5k76
R139
120pF
+
+
+
+
10uF
C169
10uF
C170
10uF
C172
10uF
C173
C180
1n0F
NP0
237r
R144
237r
R145
C185
1n0F
NP0
237r
R143
237r
R142
C181
1n0F
NP0
C182
100pF
C184
1n0F
NP0
C183
100pF
[2]
TP46
IN7+
IN7-
[2]
[2]
IN6+ [2]
IN6-
Evaluation Board User Guide
UG-032
ANALOG AUDIO INPUTS
08363-049
STJACK3.5SMALL
J14
TP20
5
1
4
6
TP19
Rev. 0 | Page 28 of 44
R137
49k9
L8
600Z
R136
49k9
L7
600Z
C161
100pF
10uF
C160
+
C156
100pF
10uF
C157
5k76
R124
VREF
[3]
VREF
[3]
5k76
R135
VREF
[3]
VREF
[3]
+
Figure 50. Audio Input 4 to Audio Input 7 Circuit Schematics
C153
100nF
13
12
9
10
C168
100nF
2
3
-
+
-
+
6
5
-
+
C158
14
AD8608
U14-D
5k76
R132
5k76
R133
8
AD8608
U14-C
5k76
R134
120pF
C159
-
+
7
AD8608
U14-B
5k76
R127
5k76
R126
1
AD8608
U14-A
5k76
R125
120pF
+
+
+
+
10uF
C151
10uF
C152
10uF
C154
10uF
C155
C162
1n0F
NP0
237r
R130
237r
R131
C167
1n0F
NP0
237r
R129
237r
R128
C163
1n0F
NP0
C164
100pF
C166
1n0F
NP0
C165
100pF
[2]
TP45
IN5+
IN5-
[2]
[2]
IN4+ [2]
IN4-
MIC_IN
STJACK3.5SMALL
J15
[3]
5
1
4
6
LK14
A B
TP22
TP21
R151
49k9
L12
600Z
R150
49k9
L11
600Z
C175
C179
100pF
10uF
C178
+
C174
100pF
10uF
5k76
R138
VREF
[3]
VREF
[3]
5k76
R149
VREF
[3]
VREF
[3]
+
C171
100nF
13
12
9
10
C186
100nF
2
3
-
+
-
+
6
5
-
+
C176
14
AD8608
U15-D
5k76
R146
5k76
R147
8
AD8608
U15-C
5k76
R148
120pF
C177
-
+
7
AD8608
U15-B
5k76
R141
5k76
R140
1
AD8608
U15-A
5k76
R139
120pF
+
+
+
+
10uF
C169
10uF
C170
10uF
C172
10uF
C173
C180
1n0F
NP0
237r
R144
237r
R145
C185
1n0F
NP0
237r
R143
237r
R142
C181
1n0F
NP0
C182
100pF
C184
1n0F
NP0
C183
100pF
[2]
TP46
IN7+
IN7-
[2]
[2]
IN6+ [2]
IN6-
UG-032
Evaluation Board User Guide
08363-050
Evaluation Board User Guide
UG-032
Opam p VREF select
Opamp Supply select
Opam p supply bypassing
OPVDD [3,4]
+5VA
OPVDD [3,4]
TP14
LK19
OPVDD [3,4]
R187
49k9
DVDD
LK20
TP13
LK17
VREF
[3]
+
R188
49k9
LK18
C220
10uF
+
C221
100nF
C222
100nF
LK21
C223
100nF
C224
100nF
C225
100nF
LK22
[2]
FILTR_1
08363-051
C219
10uF
AVDD
Figure 51. Audio I/O Filter Supply Circuit Schematics
OPVDD
[3,4]
6
R166
10k0
R190
237r
4
C214
1
100nF
5
STJACK3.5SMALL
R167
10k0
R189
237r
2
3
[3] VREF
U22-A
+
1
MIC_IN [3]
AD8606
C197
100nF
OPVDD
[3,4]
6
5
U22-C
AD8606
U22-B
+
7
AD8606
V+
V-
8
4
08363-052
J25
Figure 52. Microphone Input Circuit Schematic
Rev. 0 | Page 29 of 44
[2]
[2]
OUT1
OUT0
4k75
R36
4k75
R32
C52
Rev. 0 | Page 30 of 44
C56
150pF
4k75
R37
150pF
4k75
R33
6
5
2
3
-
1
C55
AD8608
U8-B
7
AD8608
U8-A
470pF
-
+
+
C51
470pF
604r
R38
604r
R34
+
+
47uF
16V
C57
47uF
16V
C53
3n3F
C58
3n3F
C54
R39
49k9 TP40
TP24
R35
49k9
TP23
5
1
4
6
STJACK3.5SMALL
4
[2]
[2]
OUT3
OUT2
4k75
R45
4k75
R42
C62
C63
150pF
4k75
R44
150pF
4k75
R43
13
12
9
10
-
8
C66
AD8608
U8-D
14
AD8608
U8-C
470pF
-
+
+
C59
470pF
604r
R46
604r
R41
+
+
47uF
16V
C65
47uF
16V
C60
3n3F
C64
3n3F
C61
R47
49k9
TP26
R40
49k9
TP25
5
1
4
6
STJACK3.5SMALL
J5
UG-032
Evaluation Board User Guide
ANALOG AUDIO OUTPUTS
Figure 53. Audio Output 0 to Audio Output 3 Circuit Schematics
08363-053
[2]
[2]
OUT5
OUT4
4k75
R53
4k75
R50
C70
Rev. 0 | Page 31 of 44
C71
150pF
4k75
R52
150pF
4k75
R51
6
5
2
3
-
1
C74
AD8608
U9-B
7
AD8608
U9-A
470pF
-
+
+
C67
470pF
604r
R54
604r
R49
+
+
47uF
16V
C73
47uF
16V
C68
3n3F
C72
3n3F
C69
R55
49k9
TP28
R48
49k9
TP39
TP27
5
1
4
6
STJACK3.5SMALL
J6
[2]
[2]
OUT7
OUT6
4k75
R61
4k75
R58
C78
C79
150pF
4k75
R60
150pF
4k75
R59
13
12
9
10
-
8
C82
AD8608
U9-D
14
AD8608
U9-C
470pF
-
+
+
C75
470pF
604r
R62
604r
R57
+
+
47uF
16V
C81
47uF
16V
C76
3n3F
C80
3n3F
C77
R63
49k9
TP30
R56
49k9
TP29
5
1
4
6
STJACK3.5SMALL
J7
Evaluation Board User Guide
UG-032
Figure 54. Audio Output 4 to Audio Output 7 Circuit Schematics
08363-054
[2]
[2]
OUT9
OUT8
4k75
R69
4k75
R66
C86
Rev. 0 | Page 32 of 44
C87
150pF
4k75
R68
150pF
4k75
R67
6
5
2
3
-
1
C90
AD8608
U10-B
7
AD8608
U10-A
470pF
-
+
+
C83
470pF
604r
R70
604r
R65
+
+
47uF
16V
C89
47uF
16V
C84
3n3F
C88
3n3F
C85
R71
49k9
TP41
TP32
R64
49k9
TP31
5
1
4
6
STJACK3.5SMALL
J8
[2] OUT11
[2] OUT10
4k75
R77
4k75
R74
C94
C95
150pF
4k75
R76
150pF
4k75
R75
13
12
9
10
-
8
C98
AD8608
U10-D
14
AD8608
U10-C
470pF
-
+
+
C91
470pF
604r
R78
604r
R73
+
+
47uF
16V
C97
47uF
16V
C92
3n3F
C96
3n3F
C93
R79
49k9
TP34
R72
49k9
TP33
5
1
4
6
STJACK3.5SMALL
J9
UG-032
Evaluation Board User Guide
Figure 55. Audio Output 8 to Audio Output 11 Circuit Schematics
08363-055
[2] OUT13
[2] OUT12
R82
4k75
R85
4k75
R83
C102
C103
150pF
4k75
R84
150pF
4k75
6
5
2
3
-
1
C106
AD8608
U11-B
7
AD8608
U11-A
470pF
-
+
+
C99
470pF
604r
R86
604r
R81
C100
47uF
16V
+
C105
47uF
16V
+
3n3F
C104
3n3F
C101
R87
49k9
TP42
TP36
R80
49k9
TP35
5
1
4
6
[2] OUT15
Rev. 0 | Page 33 of 44
C226
100nF
[3]
C227
100nF
OPVDD
C228
100nF
Opam p su pp ly bypassin g
STJACK3.5SMALL
J10
[2] OUT14
C229
100nF
4k75
R93
4k75
R90
C110
C111
150pF
4k75
R92
150pF
4k75
R91
13
12
9
10
8
C114
AD8608
U11-D
14
AD8608
U11-C
470pF
-
+
+
-
C107
470pF
604r
R94
604r
R89
C113
47uF
16V
+
47uF
16V
+
C108
3n3F
C112
3n3F
C109
R95
49k9
TP38
R88
49k9
TP37
5
1
4
6
STJACK3.5SMALL
J11
Evaluation Board User Guide
UG-032
Figure 56. Audio Output 12 to Audio Output 15 Circuit Schematics
08363-056
UG-032
Evaluation Board User Guide
EXTERNAL CONNECTORS
+5V
DVDD
LK10
A B
DVDD
DVDD
J20-2
1M00
8
7
6
5
4
3
2
1
2
3
4
5
6
1M00 R184
1
R183
J20-1
R171
J20-3
MP0
[1,5]
MP1
[1,5]
MP2
[1,5]
MP3
[1,5]
MP4
[1,5]
MP5
[1,5]
MP6
[1,5]
MP7
[1,5]
MP8
[1,5]
MP9
[1,5]
MP10
[1,5]
MP11
[1,5]
100r
J20-4
R172
J20-5
100r
J20-6
R173
J20-7
100r
J20-8
R174
J20-9
100r
J20-10
R175
J20-11
100r
J20-12
R176
J20-13
100r
J20-14
R177
J20-15
100r
J20-16
R178
J20-17
100r
R179
J20-18
J20-19
100r
J20-20
R180
J20-21
100r
J20-22
R181
J20-23
100r
J20-24
R182
J20-25
100r
J20-26
[1,2,5]
CLKOUT
J20-27
J20-28
[1]
MCLK_EXT
J20-29
J20-30
J20-31
[1,2,5,6]
RESET
J20-32
CCLK/SCL [1,2,5,6]
J20-33
J20-34
CDATA/ADDR1 [1,2,5,6]
J20-35
J20-36
CLATCH_1442 [1,5,6]
J20-37
J20-38
J20-39
[1,2,5,6]
COUT/SDA
J20-40
J20-41
CLATCH_1938-1
[2,6]
J20-42
J20-43
SELFBOOT
[1,5,6]
J20-44
J20-45
J20-46
[6]
SPI/I2C
LK23
J20-47
J20-48
FUTURE0
[6]
LK24
J20-49
COMMS_ACTIVE
[6]
J20-50
TP136
R170
200r
LED
YELLOW
Comms Active
08363-057
D4
Figure 57. Multipurpose Pin Interface Schematic
Rev. 0 | Page 34 of 44
Evaluation Board User Guide
UG-032
TP80
TP59
J21-1
J21-2
LRCLK0
[1,2]
BCLK0
[1,2]
SDATA_IN0
[1,2]
LRCLK1
[1]
BCLK1
J21-11
[1]
[1,2]
LRCLK2
[1]
[1]
J22-9
[1,2]
LRCLK3
[1,2]
[1,2]
SDATA_IN3
[1,2]
[1,2]
LRCLK4
[1,2]
BCLK4
[1,2]
SDATA_IN4
[1,2]
[1]
LRCLK5
[1]
[1]
J23-20
SDATA_IN8
[1]
TP91
BCLK5
[1]
J22-23
SDATA_OUT5
[1,2]
SDATA_IN5
[1]
LRCLK9
[1,2]
[1,2]
[1,5]
MP8
[1,5]
MP9
[1,5]
MP10
[1,5]
MP11
[1,5]
J22-27
BCLK9
J23-25
[1,2]
J23-27
J23-28
J22-29
SDATA_OUT6
[1,2]
[1]
BCLK10
[1]
TP97
J23-31
[1,2]
LRCLK11
[1]
[1]
CLKMODE0
[1]
CLKMODE1
[1]
SELFBOOT
[1,5,6]
TP119
ADDR0
J23-37
[1]
TP120
TP99
J23-38
BCLK11
[1]
J23-39
J23-40
J22-41
PLL2
TP118
J23-35
J23-36
J22-39
[1]
TP117
J23-33
J23-34
SDATA_OUT7
J22-37
PLL1
TP115
J23-29
J23-32
J22-35
[1]
J23-30
LRCLK10
J22-33
PLL0
TP116
TP95
J22-31
TP113
J23-26
J22-40
SDATA_OUT2
MP7
TP114
TP93
TP100
TP79
[1,5]
TP112
J23-23
J23-24
J22-25
J22-38
MP6
TP111
J23-21
J23-22
J22-36
TP78
[1,5]
TP110
J23-19
TP98
TP77
MP5
TP109
J23-17
J23-18
BCLK8
J22-21
J22-34
[1,5]
TP108
J23-15
TP96
SDATA_OUT1
J21-41
LRCLK8
TP89
J22-32
TP76
J21-39
J21-40
[1]
TP75
J21-37
[1,2]
J23-16
J22-19
J22-30
J21-35
SDATA_OUT4
J22-17
TP74
J21-33
J23-13
J23-14
J22-28
J21-30
J21-31
[1]
TP94
TP73
J21-29
SDATA_IN7
J22-15
J22-26
MP4
TP106
J23-11
TP92
SDATA_OUT0
[1,5]
TP107
J22-24
TP72
MP3
J23-12
J22-13
J22-22
TP71
J21-27
J21-38
[1]
TP90
BCLK3
J21-25
J21-36
BCLK7
J22-20
TP70
J21-23
J23-9
J23-10
J22-11
J22-18
TP69
J21-21
J21-34
[1]
TP88
SDATA_IN2
J21-19
J21-32
LRCLK7
J22-16
TP68
[1,5]
TP105
TP87
BCLK2
MP2
J23-8
J22-14
TP67
[1,5]
TP104
J23-7
TP86
TP66
J21-17
J21-28
[1,2]
J22-12
J21-15
J21-26
SDATA_OUT3
TP85
SDATA_IN1
J21-13
J21-24
J23-5
J23-6
J22-7
TP65
J21-22
[1]
J22-10
J21-12
J21-20
SDATA_IN6
TP84
TP64
MP1
TP103
J22-8
J21-9
[1,5]
J23-4
J22-5
TP63
MP0
TP102
J23-3
J22-6
J21-8
J21-18
[1]
TP83
TP62
J21-7
J21-16
BCLK6
TP82
J22-4
J21-5
J21-14
J23-1
J23-2
J22-3
TP61
J21-10
[1]
J22-2
J21-4
J21-6
TP101
LRCLK6
TP81
TP60
J21-3
J22-1
SDATA_OUT8
[1]
CDATA/ADDR1
[1,2,5,6]
CLATCH_1442
[1,5,6]
TP121
J23-41
TP122
J21-42
J22-42
J23-42
J21-43
J22-43
J23-43
J21-44
J22-44
J23-44
J21-45
J22-45
J23-45
J21-46
J22-46
J23-46
CCLK/SCL
[1,2,5,6]
COUT/SDA
[1,2,5,6]
FPGA_CLK
[1]
SPDIFI
[1]
SPDIFO
[1]
TP123
TP124
J21-47
TP130
J22-47
TP132
J23-47
TP125
J22-48
J21-49
J21-50
TP131
J22-49
J23-48
TP133
J22-50
J23-49
J23-50
TP126
J23-51
TP127
J23-52
J23-53
J23-54
CLKOUT
[1,2,5]
TP128
RESET
J23-55
[1,2,5,6]
TP129
J23-56
RSVD
J23-57
[1]
TP134
J23-58
J23-59
TP135
J23-60
Figure 58. ADAU144x Interface Connector Schematic
Rev. 0 | Page 35 of 44
08363-058
J21-48
UG-032
Evaluation Board User Guide
Beagle Header
LK25
J19
1
3
5
7
9
[2,5,6] CLATCH_1938-1
LK26
CLATCH_1938-2
HEADER10
J18
4
6
2
4
6
8
10
CDATA/ADDR1 [1,2,5,6]
HEADER10
Aardvark Header
Figure 59. Aardvark and Beagle I2C and SPI Communications Headers Circuit Schematics
Rev. 0 | Page 36 of 44
08363-059
CCLK/SCL
COUT/SDA
SW-DPDT-SLIDE
[1,2,5,6]
[1,2,5,6]
5
S4
3
CLATCH_1442
1
[1,5,6]
1
3
5
7
9
2
[2,6]
2
4
6
8
10
Figure 60. USB Control Interface Circuit Schematic
Rev. 0 | Page 37 of 44
USB
SH
SH
GND
D+
D-
VC C
J17
6
5
4
3
2
1
100nF
C 192
+ 5V
22pF
C198
8
VC C
6
NC
7
NC
Y4
6MHz
22pF
C199
600Z
L13
+ 5V
C201
28r
R 156
U18
10k0
R 158
1
CS
2
CLK
3
DI
4
DO
93C46
28r
R155
10uF
10k0
R157
R159
2k00
3V3OUT
XTOUT
XTIN
TP54
32
EECS
1
EESK
2
EEDATA
31
TEST
28
27
5
R STOUT
4
R ESET
8
USBDM
7
USBDP
6
U16
R 161
475r
+ 5V
AGN D
29
FT245BL
25
24
23
22
21
20
19
18
100nF
100nF
100nF
100nF
[5] SPI/I2C
NOTES
1. ALL COMPONENTS IN THIS SCHEMATIC,
EXCEPT THE TEST POINTS (TPx), ARE NOT
POPULATED.
10k0
R160
11
SI/WU
10
PWREN
16
RD
15
WR
14
TXE
12
R XF
D0
D1
D2
D3
D4
D5
D6
D7
C188
C189
C190
C191
B
A
LK27
DVDD
J16-5
J16-4
J16-3
J16-2
J16-1
22pF
C194
Y5
10MHz
22pF
C193
[1,5] SELFBOOT
R163 2k00
DVDD
Q2
D0
D1
D2
D3
D4
D5
D6
D7
U17
PIC16F877
MC LR
E
C
R169
2k00
B
R ESET
30
OSC1/CLK IN
31
OSC2/CLK OUT
18
8
R B0/INT
9
R B1
10
R B2
11
R B3
14
R B4/CLATCH3
15
R B5/CLATCH4
16
R B6
17
R B7
38
39
40
41
2
3
4
5
12
NC
13
NC
33
NC
34
NC
DVDD
RA1/AN1
RA0/AN0
DVDD
[1,2,5,6]
10k0
R168
TP53
R E0/AN5
RA5/AN4/SS+
R A4/TOCKI
RA3/AN3/VREF+
R A2/AN2/VREF-
25
24
23
22
21
20
19
32
35
36
37
42
43
44
1
26
R E1/AN6
27
R E2/AN7
100nF
C 196
C195
10uF
C200
100nF
+
RC 0/CLATCH1
RC 1/CLATCH2
RC 2/CLATCH0
RC3/SC K/SCL
R C4/SDI/SDA
R C5/SDO
RC 6/TX
R C7/RX
7
VDD
28
VDD
6
GND
29
GN D
+
GND
5
30
AVCC
3
VCC
26
VCC
13
VCCIO
GND
9
GND
17
L14
R164
2k00
DVDD
R165
2k00
TP47 TP48 TP49 TP50 TP51 TP52
C LATCH_1938-2 [2,6]
CLATC H_1938-1 [2,5,6]
CLATC H_1442 [1,5,6]
CC LK/SC L [1,2,5,6]
COUT/SDA [1,2,5,6]
CDATA/ADDR1 [1,2,5,6]
FUTURE0 [5]
[5]
C OMMS_AC TIVE
Evaluation Board User Guide
UG-032
USB CONTROL INTERFACE
08363-060
UG-032
Evaluation Board User Guide
RESET GENERATOR
DVDD
C187
4
S3
RESET/ 2
RESET
VCC
RESET
[1,2,5,6]
100nF
3
MR
1
GND
100k
R152
U21
08363-061
ADM811RARTZ-REEL7
Figure 61. Reset Generator Circuit Schematic
POWER SUPPLY
3.3 V Regulated Supplies
TP57
ADP3336ARMZ-REEL7
7
1
IN1
OUT1
8
2
IN2
OUT2
6
3
SD
OUT3
5
FB
GND
4
U19
AVDD
+
C218
10nF
R185
78k7
R186
140k
C230
10uF
C231
100nF
AVDD = 3.3 V
DVDD = 3.3 V
+5VA
TP56
TP55
D1
2
MBR0530T1G
+
1
C202
10uF
C203
100nF
TP58
C204
100nF
C205
10uF
R153
200r
D3
BLUE
AVDD
08363-062
D2
RAPC722X
+
1
GND
3
1SMB15AT3G
15V
J24
DVDD
U20
ADP3339AKCZ-3.3-R7
2
3
OUT
IN
4
OUT
Figure 62. Voltage Regulator Circuit Schematic
Rev. 0 | Page 38 of 44
Evaluation Board User Guide
UG-032
ORDERING INFORMATION
BILL OF MATERIALS
Table 8. Bill of Materials (BOM)
Qty.
Reference
66
C1 to C14, C19, 0.10 μF
C22,
C25 to C29,
C31, C33,
C38 to C42,
C44, C46,
C118, C127,
C135, C150,
C153, C168,
C171,
C186 to C192,
C195 to C197,
C203, C204,
C206, C208,
C214, C216,
C217,
C221 to C229,
C231, C232,
C234
Value
Description
Manufacturer
Part No.
Vendor
Vendor No.
Multilayer ceramic,
50 V, X7R (0603)
Panasonic EC
ECJ-1VB1H104K
Digi-Key
PCC2398CT-ND
16
C121, C122,
C130, C131,
C144, C145,
C148, C149,
C162, C163,
C166, C167,
C180, C181,
C184, C185
1.0 nF
Multilayer ceramic,
50 V, NP0 (0603)
Panasonic EC
ECJ-1VC1H102J
Digi-Key
PCC2151CT-ND
1
C24
1.8 nF
Multilayer ceramic,
50 V, NP0 (0603)
TDK Corporation
C1608C0G1H182J
Digi-Key
445-1296-1-ND
2
R8, R152
100 kΩ
Chip resistor, 1%, 125 mW thick Panasonic EC
film (0603)
ERJ-3EKF1003V
Digi-Key
P100KHCT-ND
16
C11, C123,
C124, C132,
C138, C143,
C146, C147,
C156, C161,
C164, C165,
C174, C179,
C182, C183
100 pF
Multilayer ceramic,
50 V, NP0 (0603)
Panasonic EC
ECJ-1VC1H101J
Digi-Key
PCC101ACVCT-ND
15
R5, R13, R23,
R171 to R182
100 Ω
Chip resistor, 1%,
100 mW thick film
(0603)
Panasonic EC
ERJ-3EKF1000V
Digi-Key
P100HCT-ND
1
R4
107 Ω
Chip resistor, 1%,
100 mW thick film
(0603)
Panasonic EC
ERJ-3EKF1070V
Digi-Key
P107HCT-ND
18
R1,
R18 to R21,
R28 to R31,
R154, R157,
R158, R160,
R162,
R166 to R168,
R191
10.0 kΩ
Chip resistor, 1%, 125 mW thick Panasonic EC
film (0603)
ERJ-3EKF1002V
Digi-Key
P10.0KHCT-ND
3
C18, C215,
C218
10 nF
Multilayer ceramic,
50 V, X7R (0603)
ECJ-1VB1H103K
Digi-Key
PCC1784CT-ND
Panasonic EC
Rev. 0 | Page 39 of 44
UG-032
Evaluation Board User Guide
Qty.
Reference
Value
Description
Manufacturer
Part No.
Vendor
Vendor No.
43
C15, C16, C30,
C32, C43, C45,
C116, C119,
C120, C125,
C128, C129,
C133, C134,
C136, C137,
C139, C142,
C151, C152,
C154, C155,
C157, C160,
C169, C170,
C172, C173,
C175, C178,
C200, C202,
C205, C207,
C209 to C213,
C219, C220,
C230, C233
10 μF
Alum electrolytic capacitor FC,
105°C, SMD_B
Panasonic EC
EEE-FC1C100R
Digi-Key
PCE3995CT-ND
8
C117, C126,
C140, C141,
C158, C159,
C176, C177
120 pF
Multilayer ceramic, 50 V,
NP0 (0603)
Panasonic EC
ECJ-1VC1H121J
Digi-Key
PCC121ACVCT-ND
1
R186
140 kΩ
Chip resistor, 1%,100 mW thick
film (0603)
Panasonic EC
ERJ-3EKF1403V
Digi-Key
P140KHCT-ND
16
C52, C56, C62,
C63, C70, C71,
C78, C79, C86,
C87, C94, C95,
C102, C103,
C110, C111
150 pF
Multilayer ceramic, 50 V,
NP0 (0603)
Panasonic EC
ECJ-1VC1H151J
Digi-Key
PCC151ACVCT-ND
1
R11
1.00 kΩ
Chip resistor, 1%, 125 mW thick Panasonic EC
film (0603)
ERJ-3EKF1001V
Digi-Key
P1.00KHCT-ND
1
R6
1.50 kΩ
Chip resistor, 1%,100 mW thick
film (0603)
Panasonic EC
ERJ-3EKF1501V
Digi-Key
P1.50KHCT-ND
1
D2
15 V
TVS Zener 15 V, 600 W, SMB
ON Semiconductor
1SMB15AT3G
Digi-Key
1SMB15AT3GOSCT-ND
2
R170, R153
200 Ω
Chip resistor, 1%,100 mW thick
film (08603)
Panasonic EC
ERJ-3EKF2000V
Digi-Key
P200HCT-ND
10
C20, C21, C36,
C37, C49, C50,
C193, C194,
C198, C199
22 pF
Multilayer ceramic, 50 V,
NP0 (0603)
Panasonic EC
ECJ-1VC1H220J
Digi-Key
PCC220ACVCT-ND
18
R101, R102,
R108, R109,
R114 to R117,
R128 to R131,
R142 to R145,
R189, R190
237 Ω
Chip resistor, 1%, 125 mW thick Panasonic EC
film (0603)
ERJ-3EKF2370V
Digi-Key
P237HCT-ND
1
R3
243 Ω
Chip resistor, 1%,100 mW thick
film (0603)
ERJ-3EKF2430V
Digi-Key
P243HCT-ND
1
U2
2
R155, R156
5
R159, R163 to
R165, R169
Panasonic EC
256 kb I2C CMOS serial EEPROM Microchip
24AA256-I/ST
Digi-Key
24AA256-I/ST-ND
28.0 Ω
Chip resistor, 1%, 125 mW thick Panasonic EC
film (0603)
ERJ-3EKF28R0V
Digi-Key
P28.0HCT-ND
2.00 kΩ
Chip resistor, 1%,100 mW thick
film (0603)
ERJ-3EKF2001V
Digi-Key
P2.00KHCT-ND
Panasonic EC
Rev. 0 | Page 40 of 44
Evaluation Board User Guide
UG-032
Qty.
Reference
Value
Description
Manufacturer
Part No.
Vendor
Vendor No.
16
C54, C58, C61,
C64, C69, C72,
C77, C80, C85,
C88, C93, C96,
C101, C104,
C109, C112
3.3 nF
Multilayer ceramic, 50 V,
X7R (0603)
Panasonic EC
ECJ-1VB1H332K
Digi-Key
PCC1778CT-ND
1
C23
33 nF
Multilayer ceramic, 50 V,
X7R (0603)
Panasonic EC
ECJ-1VB1H333K
Digi-Key
PCC2284CT-ND
2
C35, C48
390 pF
Multilayer ceramic, 50 V,
NP0 (0603)
Panasonic EC
ECJ-1VC1H391J
Digi-Key
PCC391ACVCT-ND
16
C51, C55, C59,
C66, C67, C74,
C75, C82, C83,
C90, C91, C98,
C99, C106,
C107, C114
470 pF
Multilayer ceramic, 50 V,
NP0 (0603)
Panasonic EC
ECJ-1VC1H471J
Digi-Key
PCC2147CT-ND
1
R161
475 Ω
Chip resistor, 1%, 125 mW thick Panasonic EC
film (0603)
ERJ-3EKF4750V
Digi-Key
P475HCT-ND
16
C53, C57, C60,
C65, C68, C73,
C76, C81, C84,
C89, C92, C97,
C100, C105,
C108, C113
47 μF
Alum electrolytic capacitor,
FC, 105°C, SMD_D
EEE-FC1C470P
Digi-Key
PCE4000CT-ND
22
R35, R39, R40,
R47, R48, R55,
R56, R63, R64,
R71, R72, R79,
R80, R87, R88,
R95, R136,
R137, R150,
R151, R187,
R188
49.9 kΩ
Chip resistor, 1%, 100 mW thick Panasonic EC
film (0603)
ERJ-3EKF4992V
Digi-Key
P49.9KHCT-ND
32
R32, R33, R36,
R37, R42 to
R45, R50 to
R53, R58 to
R61, R66 to
R69, R74 to
R77, R82 to
R85, R90 to
R93
4.75 kΩ
Chip resistor, 1%, 100 mW thick Panasonic EC
film (0603)
ERJ-3EKF4751V
Digi-Key
P4.75KHCT-ND
2
C34, C47
5.6 nF
Multilayer ceramic, 50 V,
X7R (0603)
Panasonic EC
ECJ-1VB1H562K
Digi-Key
PCC1781CT-ND
2
R12, R22
562 Ω
Chip resistor, 1%, 125 mW thick Panasonic EC
film (0603)
ERJ-3EKF5620V
Digi-Key
P562HCT-ND
16
R124 to R127,
R132 to R135,
R138 to R141,
R146 to R149
5.76 kΩ
Chip resistor, 1%, 125 mW thick Panasonic EC
film (0603)
ERJ-3EKF5761V
Digi-Key
P5.76KHCT-ND
16
R34, R38, R41,
R46, R49, R54,
R57, R62, R65,
R70, R73, R78,
R81, R86, R89,
R94
604 Ω
Chip resistor, 1%, 100 mW thick Panasonic EC
film (0603)
ERJ-3EKF6040V
Digi-Key
P604HCT-ND
1
R2
75.0 Ω
Chip resistor, 1%, 100 mW thick Panasonic EC
film (0603)
ERJ-3EKF75R0V
Digi-Key
P75.0HCT-ND
1
R185
78.7 kΩ
Chip resistor, 1%, 100 mW thick Panasonic EC
film (0603)
ERJ-3EKF7872V
Digi-Key
P78.7KHCT-ND
2
U3, U4
AD1938YSTZ
Four-ADC, eight-DAC with PLL,
192 kHz, 24-bit CODEC
Analog
Devices
AD1938YSTZ
Panasonic EC
Analog Devices, Inc. AD1938YSTZ
Rev. 0 | Page 41 of 44
UG-032
Evaluation Board User Guide
Qty.
Reference
Description
Manufacturer
Part No.
Vendor
Vendor No.
1
U22
Value
Low noise rail-to-rail
CMOS op amp
Analog Devices
AD8606ARZ
Analog
Devices
AD8606ARZ
8
U8 to U15
Low noise rail-to-rail
CMOS op amp
Analog Devices
AD8608ARZ
Analog
Devices
AD8608ARZ
1
U1
SigmaDSP
Analog Devices
ADAU144x
Analog
Devices
ADAU144x
1
U21
Microprocessor voltage
supervisor, logic low reset
output
Analog Devices
ADM811RARTZ-REEL7
Analog
Devices
ADM811RARTZ-REEL7
1
U19
Adjustable low dropout
voltage regulator
Analog Devices
ADP3336ARMZ-REEL7
Analog
Devices
ADP3336ARMZ-REEL7
1
U20
High accuracy, low dropout,
3.3 V dc voltage regulator
Analog Devices
ADP3339AKCZ-3.3-R7
Analog
Devices
ADP3339AKCZ-3.3-R7
1
U18
1 kb
(128 × 8 bits or
64 × 16 bits)
Serial EEPROM, 1 kB, 2.7 V
Atmel
AT93C46-10SU-2.7
Digi-Key
AT93C46-10SU-2.7-ND
1
C17
Open
Do not stuff
N/A1
N/A1
N/A1
N/A1
1
J3
SMA receptacle straight
PCB mount
Amp-RF Division
901-144-8RFX
Digi-Key
ARFX1231-ND
1
S4
DPDT slide switch vertical
E-Switch
EG2207
Digi-Key
EG1940-ND
3
L1 to L3
Chip ferrite bead, 600 Ω
@ 100 MHz
Steward
HZ0805E601R-10
Digi-Key
240-2399-1-ND
1
U16
USB to parallel FIFO interface
FTDI
FT245BL
Mouser
Electronics
895-FT245BL
1
Q1
TRANS PNP,
BIPO 3 A, 40 V,
SOT-223
PNP Darlington transistor
ON Semiconductor
NJT4030PT3G
Digi-Key
NJT4030PT3GOSCT-ND
1
Y5
10.000 MHz
Crystal 10.000 MHZ, SMT, 18 pF Citizen America
Corp
HCM49-10.000MABJ-UT
Digi-Key
300-8543-1-ND
3
Y1 to Y3
12.288 MHz
Crystal 12.288 MHZ, SMT, 18 pF Citizen America
Corp
HCM49-12.288MABJ-UT
Digi-Key
300-8550-1-ND
1
Y4
6.000 MHz
Crystal 6.000 MHZ, SMT, 18 pF
Citizen America
Corp
HCM49-6.000MABJ-UT
Digi-Key
300-8535-1-ND
2
J18, J19
2×5
10-way shroud polarized
header
3M
N2510-6002RB
Digi-Key
MHC10K-ND
2
J21, J22
50-pin (2 rows × 50-pin header unshrouded,
25 columns)
0.10" dual row
Sullins Electronics
Corp
PBC25DAAN
Digi-Key
S2011E-25-ND
1
J16
1×5
5-way unshrouded header
single row
Sullins Electronics
Corp
PBC05SAAN; also cut
PBC36SAAN
Digi-Key
S1011E-05-ND
1
J23
60-pin (2 rows
× 30 columns)
60-pin header unshrouded,
0.10" dual row
Sullins Electronics
Corp
PBC30DAAN
Digi-Key
S2011E-30-ND
21
LK1 to LK5,
LK11 to LK13,
LK15 to LK26,
LK28
2-pin header unshrouded
jumper, 0.10"; use shunt
Tyco 881545-2
Sullins Electronics
Corp
PBC02SAAN; or cut
PBC36SAAN
Digi-Key
S1011E-02-ND
7
LK6 to LK10,
LK14, LK27
3-position SIP header
Sullins
PBC03SAAN; or cut
PBC36SAAN
Digi-Key
S1011E-03-ND
1
D3
Blue clear
Blue clear, 25 millicandela,
470 nm (1206)
Lumex Opto
SML-LX1206USBC-TR
Digi-Key
67-1701-1-ND
1
D4
Yellow diffused
Yellow clear, 6.0 millicandela,
585 nm (1206)
Lumex Opto
SML-LX1206YC-TR
Digi-Key
67-1358-1-ND
1
D1
Schottky
Schottky 30 V, 0.5 A, SOD123
diode
On Semiconductor
MBR0530T1G
Digi-Key
MBR0530T1GOSCT-ND
1
U17
8 kb × 14
MCU Flash 4 MHz, 8 kb × 14
TQFP44
Microchip
Technology
PIC16LF877-04/PT
Digi-Key
PIC16LF877-04/PT-ND
CUI, Inc.
DPDT slide
13
J4 to J15, J25
Stereo mini jack, TH
SJ-43514
Digi-Key
CP-43514-ND
1
Q2
NPN general-purpose transistor ON Semiconductor
MMBT3904LT1G
Digi-Key
MMBT3904LT1GOSCTND
1
R183
Resistor network bussed seven
resistors
4606X-101-105LF
Digi-Key
4606X-1-105LF-ND
1.00 MΩ
Bourns, Inc.
Rev. 0 | Page 42 of 44
Evaluation Board User Guide
UG-032
Qty.
Reference
Value
Description
Manufacturer
Part No.
Vendor
Vendor No.
1
R10
10.0 Ω
Resistor network
bussed seven resistors
Bourns, Inc.
4608X-101-103LF
Digi-Key
4608X-1-103LF-ND
1
R184
1.00 MΩ
Resistor network
bussed seven resistors
Bourns, Inc.
4608X-101-105LF
Digi-Key
4608X-1-105LF-ND
10
R7, R9, R14 to
R17, R24 to
R27
Open
Do not stuff
1
J202
50-pin
50-pin plug right angle DIN
dual row
Hirose Electronic
Co., Ltd
PCN10-50P-2.54DS(72)
Digi-Key
H11159-ND
2
J1, J2
RCA jack PCB TH mount right
angle orange
Connect-Tech
Products Corp.
CTP-021A-S-ORANGE
ConnectTech
Products
Corp.
CTP-021A-S-ORANGE
1
J24
Mini power jack, 0.08" right
angle through hole
Switchcraft, Inc.
RAPC722X
Digi-Key
SC1313-ND
1
U7
110 Ω AES/EBU transformer
Scientific
Conversion, Inc.
SC937-02
Scientific
Conversion
SC937-02
1
S1
SPDT
SPDT slide switch PC mount
E-Switch
EG1218
Digi-Key
EG1903-ND
2
S6, S7
10-position
10-position tape seal DIP
switch
CTS Corp
219-10LPST
Digi-Key
CT21910LPST-ND
1
S2
8× SPST
eight-section SPST SMD switch
raised act
CTS Corp
219-8LPST
Digi-Key
CT2198LPST-ND
1
S3
SPST-NO
Tact switch 6 mm gull wing
Tyco/Alcoswitch
FSM6JSMA
Digi-Key
450-1133-ND
1
U6
15 Mbps
15 Mbps fiber optic receiving
module with shutter
Toshiba
TORX147L(F,T)
Digi-Key
TORX147LFT-ND
1
U5
15 Mbps optical transmitter
Toshiba
TOTX141P(F,T)
Digi-Key
TOTX141PFT-ND
1
J17
USB 4-pin B-type receptacle
Tyco
Electronics/AMP
292304-1
Mouser
Electronics
571-292304-1
1
LK29
12.288 MHz
oscillator
ASEP series oscillator
Abracon
ASEP3JL-ND
Digi-Key
ASEP3JL-ND
1
R192
49.9 Ω
Chip resistor, 1%, 100 mW thick Panasonic EC
film (0603)
ERJ-3EKF49R9V
Digi-Key
P49.9HCT-ND
4
6-32 thread
size × 1/4"
screw
Digi-Key
H554-ND
4
6-32 thread
size × 1/4"
standoff
Digi-Key
1903CK-ND
17
Shunt
Digi-Key
A26242-ND
1
2
Shunt LP
Tyco
N/A means not applicable.
Install in top of board backwards.
ESD CAUTION
Rev. 0 | Page 43 of 44
881545-2
UG-032
Evaluation Board User Guide
NOTES
Trademarks and registered trademarks are the property of their respective owners. I2C refers to a communications protocol originally developed by Philips
Semiconductors (now NXP Semiconductors).
Evaluation boards are only intended for device evaluation and not for production purposes. Evaluation boards are supplied “as is” and without warranties of any kind, express,
implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. No license is granted by implication or otherwise under
any patents or other intellectual property by application or use of evaluation boards. Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Analog Devices reserves the
right to change devices or specifications at any time without notice. Trademarks and registered trademarks are the property of their respective owners. Evaluation boards are not
authorized to be used in life support devices or systems.
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
UG08363-0-4/10(0)
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