12-Bit Deep Color with Quad HDMI
Receiver
ADV7614
Data Sheet
FEATURES
APPLICATIONS
Ultralow jitter digital PLL
4:1 multiplexed HDMI receiver
HDMI 1.3a support
36-/30-/24-bit deep color support
Flexible audio interface (DSD, DST,
Dolby® TrueHD, DTS®-HD master audio, and DTS-HD
high resolution audio)
225 MHz HDMI receiver
HDMI repeater support
High-bandwidth digital content protection (HDCP 1.3)
Programmable/adaptive equalizer for cable lengths up to
30 meters
Internal EDID RAM
EDID with HDMI cable power support
CEC support
On-board audio mute controller
General
Highly flexible output interface
12-/10-/8-bit 4:4:4 or 12-/10-/8-bit 4:2:2 pixel output interface
STDI function support standard identification
Any-to-any 3 × 3 color space conversion matrixes
Free-run time generator
2 programmable interrupt request output pins
Color controls
Low standby power
Advanced TVs
AVR video receivers
PDP HDTVs
LCD TVs (HDTV ready)
OLED HDTVs
LCD/DLP front projectors
HDMI switchers
GENERAL DESCRIPTION
The ADV7614 is a high quality, single-chip integrated 4:1
multiplexed High-Definition Multimedia Interface (HDMI®)
receiver.
The ADV7614 incorporates a quad input HDMI receiver that
supports all HDTV formats up to 1080p and displays resolutions
up to UXGA (1600 × 1200 at 60 Hz). The reception of encrypted
video is possible with the inclusion of HDCP. The HDMI
receiver also includes programmable/adaptive equalization that
ensures robust operation of the interface with cable lengths up
to 30 meters.
The ADV7614 provides complete audio support for eight channels of I2S audio, Sony/Philips digital interface format (S/PDIF)
digital audio output, and super audio CD (SACD) and compressed SACD support with direct stream digital (DSD) and
direct stream transfer (DST) output interfaces, respectively.
The HDMI receiver also supports high bit rate (HBR) audio
streaming to allow recovery (and downstream processing) of
compressed lossless audio formats, including Dolby® TrueHD
and DTS®-HD master audio or DTS-HD high resolution audio.
In addition, it also provides an advanced audio functionality,
such as a mute controller that prevents audible extraneous noise
in the audio output.
Fabricated in an advanced CMOS process, the ADV7614 is
provided in a space-saving, 260-ball 15 mm × 15 mm CSP_BGA
surface-mount, RoHS-compliant package. The ADV7614 is
specified over the −40°C to +70°C temperature range.
Rev. C
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADV7614
Data Sheet
TABLE OF CONTENTS
Features........................................................................................... 1
ESD Caution............................................................................... 8
Applications ................................................................................... 1
Pin Configuration and Function Descriptions............................ 9
General Description ...................................................................... 1
Functional Overview................................................................... 16
Revision History ............................................................................ 2
HDMI Receiver........................................................................ 16
Functional Block Diagram............................................................ 3
Component Processor (CP).................................................... 16
Specifications ................................................................................. 4
CP Pixel Data Output Modes.................................................. 16
Analog, Digital, HDMI, and AC Specifications ...................... 4
I2C Interface ............................................................................. 16
Data and I2C Timing Characteristics ....................................... 5
Other Features.......................................................................... 16
Power Specifications.................................................................. 6
Outline Dimensions .................................................................... 17
Absolute Maximum Ratings ......................................................... 8
Ordering Guide........................................................................ 17
Package Thermal Performance ................................................. 8
REVISION HISTORY
9/13—Revision C: Initial Version
Rev. C | Page 2 of 20
Data Sheet
ADV7614
FUNCTIONAL BLOCK DIAGRAM
BACK
END
CSC
SYNC PROCESSING
AND
CLOCK GENERATION
12
12
CONTROL
INTERFACE
I2C
DATA
PREPROCESSOR
AND
COLOR
SPACE
CONTROL
CONVERTER
AND
A
DATA
B
CONTROL
C
COMPONENT
PROCESSOR
OUTPUT FORMATTER
HS, VS
LLC
12
P0 TO P11
P12 TO P23
P24 TO P35
LLC
INT1
INT2
HS
VS_FIELD
DE
SCL
SDA
PACKET /
INFOFRAME
MEMORY
CEC
CONTROLLER
RXA_C±
RXB_C±
RXC_C±
RXD_C±
MUX
RXA_0±
RXA_1±
RXA_2±
EQUALIZER
SAMPLER
RXB_0±
RXB_1±
RXB_2±
EQUALIZER
SAMPLER
36
PLL
RXC_0±
RXC_1±
RXC_2±
EQUALIZER
SAMPLER
RXD_0±
RXD_1±
RXD_2±
EQUALIZER
SAMPLER
DDCA_SDA
DDCA_SCL
DDCB_SDA
DDCB_SCL
DDCC_SDA
DDCC_SCL
DDCD_SDA
DDCD_SCL
RXA_5V
RXB_5V
RXC_5V
RXD_5V
EP_MISO
EP_MOSI
EP_CS
EP_SCK
SHARED_EDID
PWRDN
HDMI
PROCESSOR
I2S0/DSD0B/HBR0
I2S1/DSD1A/HBR1
I2S2/DSD1B/HBR2
I2S3/DSD2A/HBR3
AUDIO
PACKET
PROCESSOR
HDCP
ENGINE
LRCLK/DSD2B/DST_FF
SCLK/DST_CLK
HDCP
EEPROM
MCLKOUT
S/PDIF/DSD0A/DST
EDID
REPEATER
CONTROLLER
ADV7614
Figure 1.
Rev. C | Page 3 of 20
08186-001
CEC
ADV7614
Data Sheet
SPECIFICATIONS
DVDD = 1.8 V ± 5%, DVDDIO = 3.3 V ± 5%, PVDD = 1.8 V ± 5%, TVDD = 3.3 V ± 5%, CVDD = 1.8 V ± 5%, TMIN to TMAX = −40°C to
+70°C, unless otherwise noted.
ANALOG, DIGITAL, HDMI, AND AC SPECIFICATIONS
Table 1.
Parameter
DIGITAL INPUTS
Input High Voltage (VIH )
Input Low Voltage (VIL)
Input Current (IIN )
Input Capacitance (CIN )
DIGITAL INPUTS (5 V TOLERANT) 1
Input High Voltage (VIH )
Input Low Voltage (VIL)
Input Current (IIN )
Test Conditions/Comments
Typ
Max
Unit
0.8
+60
+10
10
V
V
µA
µA
pF
0.8
+60
+82
V
V
µA
µA
2
RESET pin
Other digital inputs
−60
−10
2.6
SHARED_EDID pin
Other 5 V digital inputs
DIGITAL OUTPUTS
Output High Voltage (VOH )
Output Low Voltage (VOL)
High Impedance Leakage Current (ILEAK)
Output Capacitance (COUT)
HDMI
TMDS Differential Pin Capacitance
AC SPECIFICATIONS
Intrapair (+ to −) Differential Input Skew for
TMDS Clock Rates up to 222.75 MHz
Intrapair (+ to −) Differential Input Skew for
TMDS Clock Rates Above 222.75 MHz
Channel-to-Channel Differential Input Skew
TMDS Input Clock Range
Input Clock Jitter Tolerance
1
Min
−150
−82
2.4
0.4
10
20
0.3
V
V
µA
pF
pF
0.4 TBIT
ps
0.15 TBIT + 112
ps
25
0.5
0.2 tPIXEL + 1.78
225
0.25 TBIT
ns
MHz
TBIT
The following pins are 5 V tolerant: DDCA_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL, DDCD_SDA, RXA_5V, RXB_5V, RXC_5V,
RXD_5V, SHARED_EDID, PWRDN , EP_MISO.
Rev. C | Page 4 of 20
Data Sheet
ADV7614
DATA AND I2C TIMING CHARACTERISTICS
DVDD = 1.8 V ± 5%, DVDDIO = 3.3 V ± 5%, PVDD = 1.8 V ± 5%, TVDD = 3.3 V ± 5%, CVDD = 1.8 V ± 5%, TMIN to TMAX = −40°C to
+70°C, unless otherwise noted.
Table 2.
Parameter
VIDEO SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency
Crystal Frequency Stability
LLC Frequency Range
External Clock Source 1
Input High Voltage
Input Low Voltage
RESET FEATURE
Reset Pulse Width
CLOCK OUTPUTS
LLC Mark Space Ratio
I 2 C PORTS (FAST MODE)
xCL Frequency 2
xCL Minimum Pulse Width High2
xCL Minimum Pulse Width Low2
Hold Time (Start Condition)
Setup Time (Start Condition)
xDA Setup Time 2
xCL and xDA Rise Time 2
xCL and xDA Fall Time 2
Setup Time (Stop Condition)
I 2 C PORTS (NORMAL MODE)
xCL Frequency2
xCL Minimum Pulse Width High2
xCL Minimum Pulse Width Low2
Hold Time (Start Condition)
Setup Time (Start Condition)
xDA Setup Time 2
xCL and xDA Rise Time 2
xCL and xDA Fall Time 2
Setup Time (Stop Condition)
DATA AND CONTROL OUTPUTS 3
Data Output Transition Time SDR (CP)
Data Output Transition Time SDR (CP)
VIDEO I 2 S PORT
Master Mode
SCLK Mark Space Ratio
LRCLK Data Transition Time
LRCLK Data Transition Time
I2Sx Data Transition Time 4
I2Sx Data Transition Time 4
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
±50
170
MHz
ppm
MHz
24.576/28.6363
12.825
VIH
VIL
External crystal must operate at 1.8 V
Ball H15 (XTALP) driven with external
clock source
Ball H15 (XTALP) driven with external
clock source
1.2
V
0.4
5
t 9 :t 10
45:55
t1
t2
t3
t4
t5
t6
t7
t8
600
1.3
600
600
100
t1
t2
t3
t4
t5
t6
t7
t8
4.0
4.7
4.0
4.7
250
ms
55:45
% duty
cycle
400
kHz
ns
µs
ns
ns
ns
ns
ns
µs
300
300
0.6
100
t 11
t 12
1000
300
4.0
End of valid data to negative clock edge
Negative clock edge to start of valid data
t 13 :t 14
t 15
t 16
t 17
t 18
0.55
1.0
45:55
End of valid data to negative SCLK edge
Negative SCLK edge to start of valid data
End of valid data to negative SCLK edge
Negative SCLK edge to start of valid data
The XTAL_CTRL bit must be enabled for external oscillator operation. A 1.8 V oscillator must be used.
The prefix x refers to S, DDCA_S, DDCB_S, DDCC_S, and DDCD_S.
3 LLC DLL disabled.
4 The suffix x refers to 0, 1, 2, and 3.
1
2
Rev. C | Page 5 of 20
V
kHz
µs
µs
µs
µs
ns
ns
ns
µs
ns
ns
55:45
10
10
5
5
% duty
cycle
ns
ns
ns
ns
ADV7614
Data Sheet
POWER SPECIFICATIONS
DVDD = 1.8 V ± 5%, DVDDIO = 3.3 V ± 5%, PVDD = 1.8 V ± 5%, TVDD = 3.3 V ± 5%, CVDD = 1.8 V ± 5%, TMIN to TMAX = −40°C to
+70°C, unless otherwise noted.
Table 3.
Parameter
POWER SUPPLIES
Digital Core Power Supply (DVDD)
Digital I/O Power Supply (DVDDIO)
PLL Power Supply (PVDD)
Terminator Power Supply (TVDD)
Comparator Power Supply (CVDD)
CURRENT CONSUMPTION1, 2, 3, 4
Comparator Power Supply (ICVDD)
Min
Typ
Max
Unit
1.71
3.14
1.71
3.14
1.71
1.8
3.3
1.8
3.3
1.8
1.89
3.46
1.89
3.46
1.89
V
V
V
V
V
102.9
3.7
212.4
2.3
29.7
1.3
74.7
0.2
185.3
1.1
121.9
4.0
290.2
2.5
167.0
1.4
87.5
0.22
204.5
1.2
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Digital Core Power Supply (IDVDD)
Digital I/O Power Supply (IDVDDIO)
PLL Power Supply (IPVDD)
Termination Power Supply (ITVDD)
Test Conditions/Comments
1080p 12-bit Deep Color with 4-channel PCM
Power-Down Mode 0
1080p 12-bit Deep Color with 4-channel PCM
Power-Down Mode 0
1080p 12-bit Deep Color with 4-channel PCM
Power-Down Mode 0
1080p 12-bit Deep Color with 4-channel PCM
Power-Down Mode 0
1080p 12-bit Deep Color with 4-channel PCM
Power-Down Mode 0
1
All maximum current values are guaranteed by characterization to assist in power supply design.
Typical current consumption values are recorded with nominal voltage supply levels and a SMPTEBAR pattern.
Maximum current consumption values are recorded with maximum rated voltage supply levels and a Moire X pattern.
4
Termination power supply includes TVDD current consumed off chip.
2
3
Timing Diagrams
t3
t5
t3
xDA
t6
t1
xCL
t7
t4
t8
08186-002
t2
NOTES
1. THE PREFIX x REFERS TO S, DDCA_S, DDCB_S, DDCC_S, AND DDCD_S.
Figure 2. I2C Timing
t9
t10
LLC
t11
08186-003
t12
P0 TO P35, VS,
HS, DE
Figure 3. Pixel Port and Control SDR Output Timing
Rev. C | Page 6 of 20
Data Sheet
ADV7614
t13
SCLK
t14
t15
LRCLK
t16
t17
MSB
MSB – 1
t18
I2Sx
I2S MODE
I2Sx
RIGHT-JUSTIFIED
MODE
t17
MSB
MSB – 1
t18
t17
MSB
LSB
t18
NOTES
1. THE SUFFIX x REFERS TO 0, 1, 2, AND 3.
Figure 4. I2S Timing
Rev. C | Page 7 of 20
08186-004
I2Sx
LEFT-JUSTIFIED
MODE
ADV7614
Data Sheet
ABSOLUTE MAXIMUM RATINGS
PACKAGE THERMAL PERFORMANCE
Table 4.
Parameter
DVDD to GND
PVDD to GND
DVDDIO to GND
CVDD to GND
TVDD to GND
Digital Inputs Voltage to GND
5 V Tolerant Digital Inputs to GND1
Digital Output Voltage to GND
XTAL Pins
Maximum Junction Temperature (TJ MAX)
Storage Temperature
Infrared Reflow Soldering (20 sec)
1
Rating
2.2 V
2.2 V
4.0 V
2.2 V
4.0 V
GND − 0.3 V to
DVDDIO + 0.3 V
5.3 V
GND − 0.3 V to
DVDDIO + 0.3 V
−0.3 V to PVDD
to 0.3 V
125°C
150°C
260°C
The following inputs are 3.3 V inputs but are 5 V tolerant: DDCA_SCL,
DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL,
DDCD_SDA, RXA_5V, RXB_5V, RXC_5V, RXD_5V, SHARED_EDID, PWRDN ,
EP_MISO.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
To reduce power consumption when using the ADV7614, the
user is advised to turn off unused sections of the part.
Due to printed circuit board (PCB) metal variation and, thus,
variation in PCB heat conductivity, the value of θJA may differ
for various PCBs.
The most efficient measurement solution is obtained using the
package surface temperature to estimate the die temperature
because this eliminates the variance associated with the θJA value.
The maximum junction temperature (TJ MAX ) of 125°C must not
be exceeded. The following equation calculates the junction
temperature using the measured package surface temperature
and applies only when no heat sink is used on the device under
test (DUT):
TJ = TS + (ΨJT × WTOTAL)
where:
TS is the package surface temperature (°C).
ΨJT = 0.3°C/W for a 260-ball CSP_BGA.
WTOTAL = ((PVDD × IPVDD) + (0.05 × TVDD × ITVDD) + (CVDD ×
ICVDD) + (DVDD × IDVDD) + (DVDDIO × IDVDDIO)).
Note that for WTOTAL, 5% of TVDD power is dissipated on the
part itself.
ESD CAUTION
Rev. C | Page 8 of 20
Data Sheet
ADV7614
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A
GND
RXD_2–
RXD_1–
RXD_0–
RXD_C–
GND
RXC_2–
RXC_1–
RXC_0–
RXC_C–
TVDD
RXB_2–
RXB_1–
RXB_0–
RXB_C–
TVDD
TVDD
GND
A
B
RXD_5V
RXD_2+
RXD_1+
RXD_0+
RXD_C+
TVDD
RXC_2+
RXC_1+
RXC_0+
RXC_C+
TVDD
RXB_2+
RXB_1+
RXB_0+
RXB_C+
TVDD
RXA_2+
RXA_2–
B
C
PWRDN
TVDD
TVDD
CVDD
GND
TVDD
TVDD
GND
GND
GND
TVDD
TVDD
GND
GND
GND
GND
RXA_1+
RXA_1–
C
D
RXC_5V
RXB_5V
RXA_5V
DDCD_
SDA
DDCD_
SCL
DDCC_
SDA
DDCC_
SCL
CVDD
GND
RTERM
CVDD
DDCB_
SDA
DDCB_
SCL
DDCA_
SCL
DDCA_
SDA
TVDD
RXA_0+
RXA_0–
D
E
DE
CEC
NC
NC
GND
GND
RXA_C+
RXA_C–
E
F
HS
VS_
FIELD
GND
CVDD
TVDD
GND
F
G
P1
P0
EP_CS
EP_SCK
GND
GND
GND
GND
PVDD
PVDD
NC
NC
TEST1
TEST2
G
H
P3
P2
NC
NC
GND
GND
GND
GND
GND
GND
XTALP
PVDD
NC
NC
H
J
GND
GND
MCLK
OUT
SPDIF/
DSD0A/
DST
DVDD
GND
GND
GND
GND
GND
XTALN
PVDD
GND
GND
J
K
P4
P5
LRCLK/
DSD2B/
DST_FF
SCLK/
DST_CLK
DVDD
DVDD
GND
GND
GND
PVDD
PVDD
PVDD
NC
NC
K
L
P6
P7
I2S3/
DSD2A/
HBR3
I2S2/
DSD1B/
HBR2
DVDD
DVDD
GND
GND
GND
PVDD
NC
NC
NC
NC
L
M
P8
GND
GND
GND
DVDD
DVDD
GND
GND
GND
PVDD
NC
NC
GND
GND
M
N
P9
DVDDIO
DVDDIO
DVDDIO
NC
NC
NC
NC
N
I2S0/
I2S1/
PVDD
PVDD
NC
NC
P
EP_MISO EP_MOSI
P
P10
P11
DSD0B/
HBR0
DSD1A/
HBR1
R
P12
P13
GND
GND
SCL
DVDDIO
INT1
NC
DVDDIO
GND
NC
SHARED_
EDID
NC
GND
NC
NC
GND
GND
R
T
P14
P15
GND
GND
P25
DVDDIO
SDA
INT2
DVDDIO
GND
RESET
NC
NC
GND
NC
NC
NC
NC
T
U
P16
P17
P19
P21
P23
GND
P26
TEST3
P28
GND
P31
P33
P35
GND
NC
PVDD
PVDD
NC
U
V
GND
P18
P20
P22
P24
GND
P27
LLC
P29
GND
P30
P32
P34
GND
NC
NC
NC
GND
V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
NC = NO CONNECT. DO NOT CONENCT TO THIS PIN.
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
Mnemonic
GND
RXD_2−
RXD_1−
RXD_0−
RXD_C−
GND
RXC_2−
RXC_1−
RXC_0−
RXC_C−
TVDD
RXB_2−
Type
Ground
HDMI input
HDMI input
HDMI input
HDMI input
Ground
HDMI input
HDMI input
HDMI input
HDMI input
Power
HDMI input
Description
Ground.
Digital Input Channel 2 Complement of Port D in the HDMI Interface.
Digital Input Channel 1 Complement of Port D in the HDMI Interface.
Digital Input Channel 0 Complement of Port D in the HDMI Interface.
Digital Input Clock Complement of Port D in the HDMI Interface.
Ground.
Digital Input Channel 2 Complement of Port C in the HDMI Interface.
Digital Input Channel 1 Complement of Port C in the HDMI Interface.
Digital Input Channel 0 Complement of Port C in the HDMI Interface.
Digital Input Clock Complement of Port C in the HDMI Interface.
Terminator Supply Voltage (3.3 V ).
Digital Input Channel 2 Complement of Port B in the HDMI Interface.
Rev. C | Page 9 of 20
08186-005
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADV7614
Data Sheet
Pin No.
A13
A14
A15
A16
A17
A18
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
C1
Mnemonic
RXB_1−
RXB_0−
RXB_C−
TVDD
TVDD
GND
RXD_5V
RXD_2+
RXD_1+
RXD_0+
RXD_C+
TVDD
RXC_2+
RXC_1+
RXC_0+
RXC_C+
TVDD
RXB_2+
RXB_1+
RXB_0+
RXB_C+
TVDD
RXA_2+
RXA_2−
PWRDN
Type
HDMI input
HDMI input
HDMI input
Power
Power
Ground
HDMI input
HDMI input
HDMI input
HDMI input
HDMI input
Power
HDMI input
HDMI input
HDMI input
HDMI input
Power
HDMI input
HDMI input
HDMI input
HDMI input
Power
HDMI input
HDMI input
Digital input
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
TVDD
TVDD
CVDD
GND
TVDD
TVDD
GND
GND
GND
TVDD
TVDD
GND
GND
GND
GND
RXA_1+
RXA_1−
RXC_5V
RXB_5V
RXA_5V
DDCD_SDA
DDCD_SCL
DDCC_SDA
DDCC_SCL
CVDD
GND
RTERM
Power
Power
Power
Ground
Power
Power
Ground
Ground
Ground
Power
Power
Ground
Ground
Ground
Ground
HDMI input
HDMI input
HDMI input
HDMI input
HDMI input
HDMI input
HDMI input
HDMI input
HDMI input
Power
Ground
Miscellaneous analog
Description
Digital Input Channel 1 Complement of Port B in the HDMI Interface.
Digital Input Channel 0 Complement of Port B in the HDMI Interface.
Digital Input Clock Complement of Port B in the HDMI Interface.
Terminator Supply Voltage (3.3 V ).
Terminator Supply Voltage (3.3 V ).
Ground.
5 V Detect Pin for Port D in the HDMI Interface.
Digital Input Channel 2 True of Port D in the HDMI Interface.
Digital Input Channel 1 True of Port D in the HDMI Interface.
Digital Input Channel 0 True of Port D in the HDMI Interface.
Digital Input Clock True of Port D in the HDMI Interface.
Terminator Supply Voltage (3.3 V ).
Digital Input Channel 2 True of Port C in the HDMI Interface.
Digital Input Channel 1 True of Port C in the HDMI Interface.
Digital Input Channel 0 True of Port C in the HDMI Interface.
Digital Input Clock True of Port C in the HDMI Interface.
Terminator Supply Voltage (3.3 V ).
Digital Input Channel 2 True of Port B in the HDMI Interface.
Digital Input Channel 1 True of Port B in the HDMI Interface.
Digital Input Channel 0 True of Port B in the HDMI Interface.
Digital Input Clock True of Port B in the HDMI Interface.
Terminator Supply Voltage (3.3 V ).
Digital Input Channel 2 True of Port A in the HDMI Interface.
Digital Input Channel 2 Complement of Port A in the HDMI Interface.
Active Low System Power Detect. If low, EDID can be powered from a 5 V signal
of the HDMI port when connected to active equipment.
Terminator Supply Voltage (3.3 V ).
Terminator Supply Voltage (3.3 V ).
Comparator Supply Voltage (1.8 V ).
Ground.
Terminator Supply Voltage (3.3 V ).
Terminator Supply Voltage (3.3 V ).
Ground.
Ground.
Ground.
Terminator Supply Voltage (3.3 V ).
Terminator Supply Voltage (3.3 V ).
Ground.
Ground.
Ground.
Ground.
Digital Input Channel 1 True of Port A in the HDMI interface.
Digital Input Channel 1 Complement of Port A in the HDMI interface.
5 V Detect Pin for Port C in the HDMI Interface.
5 V Detect Pin for Port B in the HDMI Interface.
5 V Detect Pin for Port A in the HDMI Interface.
HDCP Slave Serial Data Port D. DDCD_SDA is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Clock Port D. DDCD_SCL is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Data Port C. DDCC_SDA is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Clock Port C. DDCC_SCL is a 3.3 V input that is 5 V tolerant.
Comparator Supply Voltage (1.8 V ).
Ground.
This pin sets internal termination resistance. Use a 500 Ω resistor between this
pin and GND.
Rev. C | Page 10 of 20
Data Sheet
ADV7614
Pin No.
D11
D12
D13
D14
D15
D16
D17
D18
E1
E2
E3
E4
E15
E16
E17
E18
F1
F2
Mnemonic
CVDD
DDCB_SDA
DDCB_SCL
DDCA_SCL
DDCA_SDA
TVDD
RXA_0+
RXA_0−
DE
CEC
NC
NC
GND
GND
RXA_C+
RXA_C−
HS
VS_FIELD
Type
Power
HDMI input
HDMI input
HDMI input
HDMI input
Power
HDMI input
HDMI input
Digital video output
Digital I/O
No connect
No connect
Ground
Ground
HDMI input
HDMI input
Digital video output
Digital video output
F3
F4
F15
F16
F17
F18
G1
G2
G3
G4
G7
G8
G9
G10
G11
G12
G15
G16
G17
G18
H1
H2
H3
H4
H7
H8
H9
H10
H11
H12
H15
EP_MISO
EP_MOSI
GND
CVDD
TVDD
GND
P1
P0
EP_CS
EP_SCK
GND
GND
GND
GND
PVDD
PVDD
NC
NC
TEST1
TEST2
P3
P2
NC
NC
GND
GND
GND
GND
GND
GND
XTALP
Digital input
Digital output
Ground
Power
Power
Ground
Digital video output
Digital video output
Digital output
Digital output
Ground
Ground
Ground
Ground
Power
Power
No connect
No connect
Test
Test
Digital video output
Digital video output
No connect
No connect
Ground
Ground
Ground
Ground
Ground
Ground
Miscellaneous analog
H16
PVDD
Power
Description
Comparator Supply Voltage (1.8 V ).
HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input that is 5 V tolerant.
Terminator Supply Voltage (3.3 V ).
Digital Input Channel 0 True of Port A in the HDMI Interface.
Digital Input Channel 0 Complement of Port A in the HDMI Interface.
Data Enable. DE is a signal that indicates active pixel data.
Consumer Electronic Control Channel.
Do Not Connect.
Do Not Connect.
Ground.
Ground.
Digital Input Clock True of Port A in the HDMI Interface.
Digital Input Clock Complement of Port A in the HDMI Interface.
Horizontal Synchronization Output Signal in the HDMI Processor.
VS is a vertical synchronization output signal in the HDMI processor. FIELD is a
field synchronization output signal in all interlaced video modes. VS or FIELD
can be configured for this pin.
SPI Master Input/Slave Output for External EDID Interface.
SPI Master Output/Slave Input for External EDID Interface.
Ground.
Comparator Supply Voltage (1.8 V ).
Terminator Supply Voltage (3.3 V ).
Ground.
Video Pixel Output Port.
Video Pixel Output Port.
SPI Chip Select for External EDID Interface.
SPI Clock for External EDID Interface.
Ground.
Ground.
Ground.
Ground.
PLL Supply Voltage (1.8 V ).
PLL Supply Voltage (1.8 V ).
Do Not Connect.
Do Not Connect.
Connect to GND through a 10 kΩ resistor.
Connect to GND through a 10 kΩ resistor.
Video Pixel Output Port.
Video Pixel Output Port.
Do Not Connect.
Do Not Connect.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
This is the input pin for the 28.6363 MHz crystal, or it can be overdriven by an
external 1.8 V, 28.6363 MHz clock oscillator source to clock the ADV7614. A
crystal frequency of 24.576 MHz is also supported.
PLL Supply Voltage (1.8 V ).
Rev. C | Page 11 of 20
ADV7614
Data Sheet
Pin No.
H17
H18
J1
J2
J3
J4
Mnemonic
NC
NC
GND
GND
MCLKOUT
S/PDIF/DSD0A/DST
Type
No connect
No connect
Ground
Ground
Digital output
Digital output
J7
J8
J9
J10
J11
J12
J15
DVDD
GND
GND
GND
GND
GND
XTALN
Power
Ground
Ground
Ground
Ground
Ground
Miscellaneous analog
J16
J17
J18
K1
K2
K3
PVDD
GND
GND
P4
P5
LRCLK/DSD2B/DST_FF
Power
Ground
Ground
Digital video output
Digital video output
Digital output
K4
SCLK/DST_CLK
Digital output
K7
K8
K9
K10
K11
K12
K15
K16
K17
K18
L1
L2
L3
DVDD
DVDD
GND
GND
GND
PVDD
PVDD
PVDD
NC
NC
P6
P7
I2 S3/DSD2A/HBR3
Power
Power
Ground
Ground
Ground
Power
Power
Power
No connect
No connect
Digital video output
Digital video output
Digital output
L4
I2 S2/DSD1B/HBR2
Digital output
L7
L8
L9
L10
L11
L12
L15
L16
DVDD
DVDD
GND
GND
GND
PVDD
NC
NC
Power
Power
Ground
Ground
Ground
Power
No connect
No connect
Description
Do Not Connect.
Do Not Connect.
Ground.
Ground.
Audio Master Clock Output.
S/PDIF Digital Audio Output (S/PDIF).
First DSD Data Channel (DSD0A).
DST Stream (DST).
Digital Supply Voltage (1.8 V ).
Ground.
Ground.
Ground.
Ground.
Ground.
This pin should be connected to the 28.6363 MHz crystal or left as a no connect
pin if an external 1.8 V, 28.6363 MHz clock oscillator source is used to clock the
ADV7614. In crystal mode, the crystal must be a fundamental crystal. A crystal
frequency of 24.576 MHz is also supported.
PLL Supply Voltage (1.8 V ).
Ground.
Ground.
Video Pixel Output Port.
Video Pixel Output Port.
Data Output Clock. Left and Right Audio Channels (LRCLK).
Sixth DSD Data Channel (DSD2B).
DST Frame (DST_FF).
Audio Serial Clock Output (SCLK).
DST Clock (DST_CLK).
Digital Supply Voltage (1.8 V ).
Digital Supply Voltage (1.8 V ).
Ground.
Ground.
Ground.
PLL Supply Voltage (1.8 V ).
PLL Supply Voltage (1.8 V ).
PLL Supply Voltage (1.8 V ).
Do Not Connect.
Do Not Connect.
Video Pixel Output Port.
Video Pixel Output Port.
I2 S Audio (Channel 7 and Channel 8) (I2 S3).
Fifth DSD Data Channel (DSD2A).
Fourth Block of HBR Stream (HBR3).
I2 S Audio (Channel 5 and Channel 6) (I2 S2).
Fourth DSD Data Channel (DSD1B).
Third Block of HBR Stream (HBR2).
Digital Supply Voltage (1.8 V ).
Digital Supply Voltage (1.8 V ).
Ground.
Ground.
Ground.
PLL Supply Voltage (1.8 V ).
Do Not Connect.
Do Not Connect.
Rev. C | Page 12 of 20
Data Sheet
ADV7614
Pin No.
L17
L18
M1
M2
M3
M4
M7
M8
M9
M10
M11
M12
M15
M16
M17
M18
N1
N2
N3
N4
N15
N16
N17
N18
P1
P2
P3
Mnemonic
NC
NC
P8
GND
GND
GND
DVDD
DVDD
GND
GND
GND
PVDD
NC
NC
GND
GND
P9
DVDDIO
DVDDIO
DVDDIO
NC
NC
NC
NC
P10
P11
I2 S0/DSD0B/HBR0
Type
No connect
No connect
Digital video output
Ground
Ground
Ground
Power
Power
Ground
Ground
Ground
Power
No connect
No connect
Ground
Ground
Digital video output
Power
Power
Power
No connect
No connect
No connect
No connect
Digital video output
Digital video output
Digital output
P4
I2 S1/DSD1A/HBR1
Digital output
P15
P16
P17
P18
R1
R2
R3
R4
R5
PVDD
PVDD
NC
NC
P12
P13
GND
GND
SCL
Power
Power
No connect
No connect
Digital video output
Digital video output
Ground
Ground
Digital I/O
R6
R7
DVDDIO
INT1
Power
Digital output
R8
R9
R10
R11
R12
NC
DVDDIO
GND
NC
SHARED_EDID
No connect
Power
Ground
No connect
Digital input
R13
R14
R15
NC
GND
NC
No connect
Ground
No connect
Description
Do Not Connect.
Do Not Connect.
Video Pixel Output Port.
Ground.
Ground.
Ground.
Digital Supply Voltage (1.8 V ).
Digital Supply Voltage (1.8 V ).
Ground.
Ground.
Ground.
PLL Supply Voltage (1.8 V ).
Do Not Connect.
Do Not Connect.
Ground.
Ground.
Video Pixel Output Port.
Digital I/O Supply Voltage (3.3 V ).
Digital I/O Supply Voltage (3.3 V ).
Digital I/O Supply Voltage (3.3 V ).
Do Not Connect.
Do Not Connect.
Do Not Connect.
Do Not Connect.
Video Pixel Output Port.
Video Pixel Output Port.
I2 S Audio (Channel 1 and Channel 2) (I2 S0).
Second DSD Data Channel (DSD0B).
First Block of HBR Stream (HBR0).
I2 S Audio (Channel 3 and Channel 4) (I2 S1).
Third DSD Data Channel (DSD1A).
Second Block of HBR Stream (HBR1).
PLL Supply Voltage (1.8 V ).
PLL Supply Voltage (1.8 V ).
Do Not Connect.
Do Not Connect.
Video Pixel Output Port.
Video Pixel Output Port.
Ground.
Ground.
I2 C Port Serial Clock Input. The maximum clock rate is 400 kHz. SCL is the clock
line for the control port.
Digital I/O Supply Voltage (3.3 V ).
Interrupt Pin 1. This pin can be active low or active high. When status bits change,
this pin is triggered. The events that trigger an interrupt are under user control.
Do Not Connect.
Digital I/O Supply Voltage (3.3 V ).
Ground.
Do Not Connect.
EDID Flag. When high, all four HDMI ports share a common EDID. When low,
Port D does not share a common EDID; Port D operates with a separate EDID.
Do Not Connect.
Ground.
Do Not Connect.
Rev. C | Page 13 of 20
ADV7614
Data Sheet
Pin No.
R16
R17
R18
T1
T2
T3
T4
T5
T6
T7
T8
Mnemonic
NC
GND
GND
P14
P15
GND
GND
P25
DVDDIO
SDA
INT2
Type
No connect
Ground
Ground
Digital video output
Digital video output
Ground
Ground
Digital video output
Power
Digital I/O
Digital output
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
DVDDIO
GND
RESET
NC
NC
GND
NC
NC
NC
NC
P16
P17
P19
P21
P23
GND
P26
TEST3
P28
GND
P31
P33
P35
GND
NC
PVDD
PVDD
NC
GND
P18
P20
P22
P24
GND
P27
LLC
P29
GND
P30
P32
P34
Power
Ground
Digital input
No connect
No connect
Ground
No connect
No connect
No connect
No connect
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Ground
Digital video output
Test
Digital video output
Ground
Digital video output
Digital video output
Digital video output
Ground
No connect
Power
Power
No connect
Ground
Digital video output
Digital video output
Digital video output
Digital video output
Ground
Digital video output
Digital video output
Digital video output
Ground
Digital video output
Digital video output
Digital video output
Description
Do Not Connect.
Ground.
Ground.
Video Pixel Output Port.
Video Pixel Output Port.
Ground.
Ground.
Video Pixel Output Port.
Digital I/O Supply Voltage (3.3 V ).
I2 C Port Serial Data Input/Output Pin. SDA is the data line for the control port.
Interrupt Pin 2. This pin can be active low or active high. When status bits change,
this pin is triggered. The events that trigger an interrupt are under user control.
Digital I/O Supply Voltage (3.3 V ).
Ground.
Chip Reset. Active low. The minimum low time for a reset to take place is 5 ms.
Do Not Connect.
Do Not Connect.
Ground.
Do Not Connect.
Do Not Connect.
Do Not Connect.
Do Not Connect.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Ground.
Video Pixel Output Port.
Connect to GND through a 10 kΩ resistor.
Video Pixel Output Port.
Ground.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Ground.
Do Not Connect.
PLL Supply Voltage (1.8 V ).
PLL Supply Voltage (1.8 V ).
Do Not Connect.
Ground.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Ground.
Video Pixel Output Port.
Line-Locked Output Clock for the Pixel Data (Range Is 13.5 MHz to 170 MHz).
Video Pixel Output Port.
Ground.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Rev. C | Page 14 of 20
Data Sheet
Pin No.
V14
V15
V16
V17
V18
Mnemonic
GND
NC
NC
NC
GND
ADV7614
Type
Ground
No connect
No connect
No connect
Ground
Description
Ground.
Do Not Connect.
Do Not Connect.
Do Not Connect.
Ground.
Rev. C | Page 15 of 20
ADV7614
Data Sheet
FUNCTIONAL OVERVIEW
HDMI RECEIVER
The HDMI receiver on the ADV7614 incorporates active
equalization of the HDMI data signals. This equalization
compensates for the high frequency losses inherent in HDMI
and DVI cabling, especially at longer lengths and higher
frequencies. The equalization is programmable. It is capable
of equalizing for cable lengths up to 30 meters to achieve robust
receiver performance at even the highest HDMI data rates. The
HDMI receiver supports all HDTV formats up to 1080p and all
display resolutions up to UXGA (1600 × 1200 at 60 Hz).
With the inclusion of HDCP, displays can receive encrypted video
content. The HDMI interface of the ADV7614 allows for authentication of a video receiver, decryption of encoded data at the
receiver, and renewability of that authentication during transmission as specified by the HDCP 1.3 protocol.
The HDMI receiver offers advanced audio functionality. It supports multichannel I2S audio for up to eight channels. It also
supports a six-DSD channel interface with each channel carrying
an oversampled 1-bit representation of the audio signal as
delivered on SACD. It incorporates a DST interface that outputs
audio data decoded from DST audio packets. The ADV7614
can also receive HBR audio packet streams and outputs them
through the HBR interface in an S/PDIF format conforming to
the IEC60958 standard. It supports multichannel I2S audio for
up to eight channels. The receiver also contains an audio mute
controller that can detect a variety of conditions that may result
in audible extraneous noise in the audio output. On detection of
these conditions, the audio data can be ramped to prevent audio
clicks or pops.
A fully programmable any-to-any 3 × 3 color space conversion
(CSC) matrix is placed between the HDMI processor and the
CP section. This enables YCrCb-to-RGB and YCrCb-to-RGB
conversions. Many other standards of color space can be
implemented using the color space converter.
CP PIXEL DATA OUTPUT MODES
The output section of the CP is highly flexible. It can be configured in an SDR mode with one data packet per clock cycle
or in a DDR mode where data is presented on the rising and
falling edge of the clock. In SDR mode, a 16-/20-/24-bit 4:2:2 or
24-/30-/36-bit 4:4:4 output is possible. In these modes, the HS,
VS, FIELD, and DE (where applicable) timing reference signals
are provided. In DDR mode, the ADV7614 can be configured in
an 8-/10-/12-bit 4:2:2 YCrCb or 12-bit 4:4:4 RGB/YCrCb pixel
output interface with corresponding timing signals.
I2C INTERFACE
The ADV7614 supports a 2-wire serial (I2C-compatible)
microprocessor bus driving multiple peripherals. The
ADV7614 is controlled by an external I2C master device,
such as a microcontroller.
OTHER FEATURES
In addition to HS, VS, and FIELD output signals with programmable position, polarity, and width, the ADV7614 provides the
following:
•
•
Programmable interrupt request output pins: INT1 and INT2
Low power consumption: 1.8 V digital core, 3.3 V digital
input/output, low power power-down mode, and green
PC mode
15 mm × 15 mm, RoHS-compliant BGA package
COMPONENT PROCESSOR (CP)
•
The video standards supported by the CP are 525i, 625i, 525p,
625p, 720p, 1080i, 1080p, 1250i, VGA up to UXGA at 60 Hz,
and many other standards.
For more detailed product information about the ADV7614,
contact a local Analog Devices, Inc., sales office.
Automatic adjustments within the CP include gain (contrast)
and offset (brightness); manual adjustment controls are also
supported.
Rev. C | Page 16 of 20
Data Sheet
ADV7614
OUTLINE DIMENSIONS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
13.60
BSC SQ
0.80
BSC
BOTTOM VIEW
TOP VIEW
1.50
1.36
1.21
A1 BALL
CORNER
4 2
18 16 14 12 10 8 6
7 5 3
1
17 15 13 11 9
DETAIL A
DETAIL A
0.35 NOM
0.30 MIN
SEATING
PLANE
0.50
0.45
0.40
BALL DIAMETER
1.11
1.01
0.91
COPLANARITY
0.12
COMPLIANT TO JEDEC STANDARDS MO-275-KKAA-1.
11-22-2011-A
A1 BALL
CORNER
15.10
15.00 SQ
14.90
Figure 6. 260-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-260-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
ADV7614BBCZ
EVAL-ADV7614EB1Z
1
2
Temperature Range
−40°C to +70°C
Package Description
260-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
ADV7614BBCZ Front-End Evaluation Board
Package Option
BC-260-1
Z = RoHS Compliant Part.
The ADV7614BBCZ is programmed with internal HDCP keys. Customers must have HDCP adopter status (consult Digital Content Protection, LLC, for licensing
requirements) to purchase any components with internal HDCP keys.
Rev. C | Page 17 of 20
ADV7614
Data Sheet
NOTES
Rev. C | Page 18 of 20
Data Sheet
ADV7614
NOTES
Rev. C | Page 19 of 20
ADV7614
Data Sheet
NOTES
I 2 C refers to a communications protocol originally developed by Phillips Semiconductors (now NXP Semiconductors).
HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and
other countries.
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08186-0-9/13(C)
Rev. C | Page 20 of 20