FUNCTIONAL BLOCK DIAGRAM
3
4
5
6
VDD4A
VGG1A
2
VDD3A
Output power for 1 dB compression (P1dB): 21 dBm typical
Saturated output power (PSAT): 22 dBm typical
Gain: 19 dB typical
Output third-order intercept (IP3): 28 dBm typical
Supply voltage: 4 V at 320 mA
50 Ω matched input/output
Die size: 2.3 mm × 1.8 mm × 0.102 mm
VDD2A
FEATURES
VDD1A
RFOUT
7
HMC1144
APPLICATIONS
11
10
9
VDD4B
8
13143-001
12
VDD3B
RFIN
VDD1B
1
VGG1B
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military and space
Telecommunications infrastructure
Fiber optics
VDD2B
Data Sheet
40 GHz to 70 GHz, GaAs, pHEMT, MMIC,
Medium Power Amplifier
HMC1144
Figure 1.
GENERAL DESCRIPTION
The HMC1144 is a gallium arsenide (GaAs), pseudomorphic
high electron mobility transfer (pHEMT), monolithic microwave
integrated circuit (MMIC), distributed power amplifier that
operates from 40 GHz to 70 GHz. In the lower band of 40 GHz
to 50 GHz, the HMC1144 provides 19 dB (typical) of gain,
28 dBm output IP3, and 19.5 dBm of output power at 1 dB gain
compression. In the upper band of 50 GHz to 70 GHz, the
Rev. A
HMC1144 provides 19 dB (typical) of gain, 32 dBm output IP3,
and 21 dBm of output power at 1 dB gain compression. The
HMC1144 requires 320 mA from a 4 V supply. The HMC1144
amplifier inputs/outputs are internally matched to 50 Ω,
facilitating integration into multichip modules (MCMs). All
data is taken with the chip connected via two 0.025 mm (1 mil)
wire bonds of 0.076 mm (3 mil) minimal length.
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Technical Support
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HMC1144
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................6
Applications ....................................................................................... 1
Theory of Operation ...................................................................... 10
Functional Block Diagram .............................................................. 1
Applications Information .............................................................. 11
General Description ......................................................................... 1
Alternate Biasing Configuration .............................................. 11
Revision History ............................................................................... 2
Electrical Specifications ................................................................... 3
Mounting and Bonding Techniques for Millimeterwave
GaAs MMICs .............................................................................. 12
40 GHz to 50 GHz Frequency Range ......................................... 3
Typical Application Circuit ........................................................... 13
50 GHz to 70 GHz Frequency Range ......................................... 3
Assembly Diagram ..................................................................... 14
Absolute Maximum Ratings ............................................................ 4
Outline Dimensions ....................................................................... 15
ESD Caution .................................................................................. 4
Ordering Guide .......................................................................... 15
Pin Configuration and Function Descriptions ............................. 5
Interface Schematics..................................................................... 5
REVISION HISTORY
1/16—Rev. 0 to Rev. A
Changes to Table 3 ............................................................................ 4
Added Figure 28 to Figure 32; Renumbered Sequentially .......... 8
10/15—Revision 0: Initial Version
Rev. A | Page 2 of 15
Data Sheet
HMC1144
ELECTRICAL SPECIFICATIONS
40 GHz TO 50 GHz FREQUENCY RANGE
TA = 25°C, VDD = VDD1A = VDD2A = VDD3A = VDD4A = 4 V, IDD = IDD1A + IDD2A + IDD3A + IDD4A = 320 mA, unless otherwise stated. Adjust
VGG1B from −2 V to 0 V to achieve IDD = 320 mA typical.
Table 1.
Parameter
FREQUENCY RANGE
GAIN
Gain Variation Over Temperature
RETURN LOSS
Input
Output
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept
SUPPLY CURRENT
Total Supply Current
Total Supply Current vs. VDD
IDD = 290 mA
IDD = 320 mA
IDD = 350 mA
Symbol
P1dB
PSAT
IP3
Test Conditions/Comments
Min
40
17
17
Measurement taken at POUT/tone = 10 dBm
IDD
Typ
Max
50
19
0.023
Unit
GHz
dB
dB/°C
35
16
dB
dB
19.5
21.5
28
dBm
dBm
dBm
320
mA
4
4
4
V
V
V
50 GHz TO 70 GHz FREQUENCY RANGE
TA = 25°C, VDD = VDD1A = VDD2A = VDD3A = VDD4A = 4 V, IDD = IDD1A + IDD2A + IDD3A + IDD4A = 320 mA, unless otherwise stated. Adjust
VGG1B from −2 V to 0 V to achieve IDD = 320 mA typical.
Table 2.
Parameter
FREQUENCY RANGE
GAIN
Gain Variation Over Temperature
RETURN LOSS
Input
Output
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept
SUPPLY CURRENT
Total Supply Current
Total Supply Current vs. VDD
IDD = 290 mA
IDD = 320 mA
IDD = 350 mA
Symbol
P1dB
PSAT
IP3
Test Conditions/Comments
Min
50
17
19
Measurement taken at POUT/tone = 10 dBm
IDD
Rev. A | Page 3 of 15
Typ
Max
70
19
0.016
Unit
GHz
dB
dB/°C
22
25
dB
dB
21
22
32
dBm
dBm
dBm
320
mA
4
4
4
V
V
V
HMC1144
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Drain Bias Voltage (VDD1A to VDD4A)
Gate Bias Voltage (VGG1B)
RF Input Power (RFIN)
Channel Temperature
Continuous Power Dissipation (PDISS),
TA = 85°C (Derate 19.2 mW/°C Above 85°C)
Thermal Resistance, θJA (Channel to
Bottom Die)
Storage Temperature Range
Operating Temperature Range
ESD Sensitivity, Human Body Model (HBM)
Rating
4.5 V
−2 V to 0 V dc
22 dBm
175°C
1.770 W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
50.83°C/W
ESD CAUTION
−65°C to +150°C
−55°C to +85°C
±125 V, Class 0B
Rev. A | Page 4 of 15
Data Sheet
HMC1144
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VGG1A
2
VDD1A VDD2A
3
4
VDD3A
5
VDD4A
6
7
RFOUT
HMC1144
TOP VIEW
(Not to Scale)
RFIN
12
VGG1B
11
10
VDD1B VDD2B
9
VDD3B
8
VDD4B
13143-002
1
Figure 2. Pad Configuration
Table 4. Pad Function Descriptions
Pad No.
1
2
3 to 6
Mnemonic
RFIN
VGG1A
VDD1A to VDD4A
7
8 to 11
RFOUT
VDD4B to VDD1B
12
VGG1B
Die Bottom
GND
Description
RF Input. This pad is ac-coupled and matched to 50 Ω. See Figure 3 for the interface schematic.
Gate Control Pad for Alternate Bias Configuration. See Figure 4 for the interface schematic..
Drain Bias Voltage Pads for the Amplifier. External bypass capacitors of 100 pF and 0.1 µF are required.
See Figure 5 for the interface schematic.
RF Output. This pad is ac-coupled and matched to 50 Ω. See Figure 6 for the interface schematic.
Drain Bias Voltage Pads for Alternate Bias Configuration. External bypass capacitors of 100 pF and 0.1 µF
are required for decoupling. See Figure 7 for the interface schematic.
Gate Control Pad for the Amplifier. External bypass capacitors of 100 pF and 0.1 µF are required. See Figure 8
for the interface schematic.
Die bottom must be connected to RF/dc ground. See Figure 9 for the interface schematic.
13143-003
INTERFACE SCHEMATICS
Figure 3. RFIN Interface Schematic
Figure 7. VDD1B to VDD4B Interface Schematic
13143-004
VGG1A
13143-132
VDD1B TO VDD4B
13143-004
RFIN
VGG1B
Figure 4. VGG1A Interface Schematic
GND
Figure 5. VDD1A to VDD4A Interface Schematic
Figure 9. GND Interface Schematic
13143-006
RFOUT
13143-007
VDD1A TO VDD4A
13143-005
Figure 8. VGG1B Interface Schematic
Figure 6. RFOUT Interface Schematic
Rev. A | Page 5 of 15
HMC1144
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
25
24
15
22
S21
S11
S22
20
GAIN (dB)
RESPONSE (dB)
5
–5
–15
18
16
–25
40
45
50
55
60
FREQUENCY (GHz)
65
70
75
12
40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
FREQUENCY (GHz)
13143-008
–45
35
Figure 10. Response Gain and Return Loss vs. Frequency
Figure 13. Gain vs. Frequency at Various Temperatures
0
0
+25°C
+85°C
–55°C
+25°C
+85°C
–55°C
–10
RETURN LOSS (dB)
RETURN LOSS (dB)
–10
–55°C
+25°C
+85°C
13143-011
14
–35
–20
–30
–20
–30
Figure 11. Input Return Loss vs. Frequency at Various Temperatures
–40
40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
FREQUENCY (GHz)
Figure 14. Output Return Loss vs. Frequency at Various Temperatures
24
22
13143-012
–50
40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
FREQUENCY (GHz)
13143-009
–40
26
150 mA
200 mA
250 mA
290 mA
320 mA
350 mA
24
22
P1dB (dBm)
18
20
18
16
16
14
12
12
40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
FREQUENCY (GHz)
+25°C
+85°C
–55°C
10
40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
FREQUENCY (GHz)
Figure 12. Gain vs. Frequency at Various IDD
Figure 15. P1dB vs. Frequency at Various Temperatures
Rev. A | Page 6 of 15
13143-013
14
13143-133
GAIN (dB)
20
Data Sheet
HMC1144
0
24
–10
PSAT (dBm)
22
20
18
16
14
10
40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
FREQUENCY (GHz)
–30
–40
–50
–60
–70
13143-014
12
+25°C
+85°C
–55°C
–20
Figure 16. PSAT vs. Frequency at Various Temperatures
+25°C
+85°C
–55°C
–80
40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
FREQUENCY (GHz)
13143-017
REVERSE ISOLATION (dB)
26
Figure 19. Reverse Isolation vs. Frequency at Various Temperatures
26
40
24
35
22
IP3 (dBm)
PSAT (dBm)
31
20
18
27
16
23
14
10
40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
FREQUENCY (GHz)
19
+25°C
+85°C
–55°C
15
40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
FREQUENCY (GHz)
Figure 17. PSAT vs. Frequency at Various Supply Currents
13143-018
290mA
320mA
350mA
13143-015
12
Figure 20. Output IP3 vs. Frequency for Various Temperatures at
POUT = 10 dBm/Tone
26
40
24
35
31
IP3 (dBm)
20
18
27
16
23
14
290mA
320mA
350mA
10
40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
FREQUENCY (GHz)
Figure 18. P1dB vs. Frequency at Various Supply Currents
19
290mA
320mA
350mA
15
40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
FREQUENCY (GHz)
13143-019
12
13143-016
P1dB (dBm)
22
Figure 21. Output IP3 vs. Frequency for Various Supply Currents at
POUT = 10 dBm/Tone
Rev. A | Page 7 of 15
HMC1144
Data Sheet
0
55
50
–10
RETURN LOSS (dB)
40
35
40GHz
45GHz
50GHz
55GHz
60GHz
65GHz
70GHz
25
8
–20
–30
–40
20
6
200mA
250mA
320mA
10
POUT/TONE (dBm)
12
14
12
40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
FREQUENCY (GHz)
Figure 22. Output Third-Order Intermodulation (IMD3) vs. POUT/Tone for
Various Frequencies at VDD = 4 V
13143-123
30
13143-020
IMD3 (dBc)
45
Figure 25. Input Return Loss vs. Frequency at Various IDD
24
0
–5
22
RETURN LOSS (dB)
–10
GAIN (dB)
20
18
2.5V
3.0V
3.5V
4.0V
16
–15
–20
–25
–30
2.5V
3.0V
3.5V
4.0V
14
FREQUENCY (GHz)
–40
40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
13143-121
12
40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
FREQUENCY (GHz)
Figure 23. Gain vs. Frequency at Various VDD
13143-124
–35
Figure 26. Output Return Loss vs. Frequency at Various VDD
0
0
–5
–10
RETURN LOSS (dB)
–20
–30
200mA
250mA
320mA
–15
–20
–25
–30
–40
–50
40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
FREQUENCY (GHz)
–40
40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
FREQUENCY (GHz)
Figure 27. Output Return Loss vs. Frequency at Various IDD
Figure 24. Input Return Loss vs. Frequency at Various VDD
Rev. A | Page 8 of 15
13143-125
–35
13143-122
RETURN LOSS (dB)
–10
2.5V
3.0V
3.5V
4.0V
Data Sheet
HMC1144
25
520
20
470
1.8
370
5
GAIN 320
POUT
PAE
IDD
270
6
8
0
–10
–8
–6
–4
–2
0
2
INPUT POWER (dBm)
4
1.6
1.5
1.4
1.3
1.2
1.0
–10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2
INPUT POWER (dBm)
Figure 28. Power Compression at 45 GHz
3
4
5
6
7
Figure 31. Power Dissipation vs. Input Power at 85°C
for Various Frequencies
10
520
25
65GHz
55GHz
45GHz
1.1
13143-204
10
POWER DISSIPATION (W)
420
IDD (mA)
15
13143-201
POUT (dBm), GAIN (dB), PAE (%)
1.7
10
370
5
GAIN 320
POUT
PAE
IDD
270
6
4
–8
–6
–4
–2
0
INPUT POWER (dBm)
2
470
15
420
10
370
5
GAIN 320
POUT
PAE
IDD
270
4
6
2
3
25°C
0
50
IDD (mA)
20
–4
–2
0
INPUT POWER (dBm)
4
1
13143-203
POUT (dBm), GAIN (dB), PAE (%)
520
–6
5
55
60
65
FREQUENCY (GHz)
70
Figure 32. Noise Figure vs. Frequency at 25°C
25
–8
6
2
Figure 29. Power Compression at 55 GHz
0
–10
7
Figure 30. Power Compression at 65 GHz
Rev. A | Page 9 of 15
75
13143-205
420
NOISE FIGURE (dB)
15
0
–10
8
470
IDD (mA)
20
13143-202
POUT (dBm), GAIN (dB), PAE (%)
9
HMC1144
Data Sheet
THEORY OF OPERATION
The architecture of the HMC1144 power amplifier is shown in
Figure 33. The HMC1144 uses two cascaded, four-stage amplifiers
operating in quadrature between two 90° hybrids. This balanced
amplifier approach forms an amplifier with a combined gain of
19 dB and a saturated output power (PSAT) of 22 dBm. The 90°
hybrids ensure that the input and output return losses are greater
than 15 dB. See the application circuits shown in Figure 37 and
Figure 38 for further details on biasing the various blocks.
RFOUT
13143-028
RFIN
Figure 33. HMC1144 Architecture
Rev. A | Page 10 of 15
Data Sheet
HMC1144
APPLICATIONS INFORMATION
The VDD = 4 V and IDD = 320 mA bias conditions are the operating
points recommended to optimize the overall performance.
Unless otherwise noted, the data shown was taken using the
recommended bias condition. Operation of the HMC1144 at
different bias conditions may provide performance that differs
from what is shown in the Typical Performance Characteristics
section. Biasing the HMC1144 for higher drain current typically
results in higher P1dB, output IP3, and gain, but at the expense
of increased power consumption.
The HMC1144 is a GaAs, pHEMT, MMIC power amplifier.
Capacitive bypassing is required for VDD1A through VDD4A and
VDD1B through VDD4B (see Figure 32). VGG1B is the gate bias
pad for all four gain stages. Apply a gate bias voltage to VGG1B
and use capacitive bypassing as shown in Figure 32.
All measurements for this device were taken using the typical
application circuit (see Figure 32) and configured as shown in
the assembly diagram (see Figure 34).
The following is the recommended bias sequence during
power-up:
1.
2.
3.
4.
5.
ALTERNATE BIASING CONFIGURATION
It is possible to bias the gate from the north (instead of the
south) and bias the drain from the south (instead of the north).
Although this alternate bias configuration was not measured
during production testing and was evaluated minimally during
product validation, it does offer flexibility in cases where it is
more convenient to have the gate and drain bias approach the
die from a different direction (see Figure 33).
Connect to ground.
Set the gate bias voltage to −2 V.
Set all the drain bias voltages, VDD = 4 V.
Increase the gate bias voltage to achieve a quiescent
current, IDD = 320 mA.
Apply the RF signal.
The following is the recommended bias sequence during
power-down:
3.
4.
Turn off the RF signal.
Decrease the gate bias voltage to −2 V to achieve
IDD = 0 mA (approximately).
Decrease all of the drain bias voltages to 0 V.
Increase the gate bias voltage to 0 V.
VDD2B
VDD1B
VDD4A
VDD3A
VDD2A
VDD1A
VDD4B
VDD3B
RFIN
RFOUT
1A
1B
2A
2B
3A
3B
4A
4B
13143-021
1.
2.
In the alternate bias configuration, capacitive bypassing is
required for the VGG1A pad to which the bias voltage is applied,
as well as for all eight VDDxA/VDDxB pads.
VGG1A
VGG1B
Figure 34. Simplified Block Diagram
Rev. A | Page 11 of 15
HMC1144
Data Sheet
Handling Precautions
MOUNTING AND BONDING TECHNIQUES FOR
MILLIMETERWAVE GaAs MMICS
Attach the die directly to the ground plane eutectically or with
conductive epoxy (see the Handling Precautions section, the
Mounting section, and the Wire Bonding section).
Microstrip, 50 Ω, transmission lines on 0.127 mm (5 mil) thick
alumina, thin film substrates are recommended for bringing the
radio frequency to and from the chip (see Figure 30). When using
0.254 mm (10 mil) thick alumina, thin film substrates, raise the
die 0.150 mm (6 mil) to ensure that the surface of the die is
coplanar with the surface of the substrate. One way to accomplish
this is to attach the 0.102 mm (4 mil) thick die to a 0.150 mm
(6 mil) thick, molybdenum (Mo) heat spreader (moly tab),
which can then be attached to the ground plane (see Figure 31).
To avoid permanent damage, follow these storage, cleanliness,
static sensitivity, transient, and general handling precautions:
•
•
•
•
•
0.102mm (0.004") THICK GaAs MMIC
WIRE BOND
0.076mm
(0.003")
Place all bare die in either waffle or gel-based ESD
protective containers and then seal the die in an ESD
protective bag for shipment. After the sealed ESD
protective bag is opened, store all die in a dry nitrogen
environment.
Handle the chips in a clean environment. Do not attempt
to clean the chip using liquid cleaning systems.
Follow ESD precautions to protect against ESD strikes.
While bias is applied, suppress instrument and bias supply
transients. Use shielded signal and bias cables to minimize
inductive pickup.
Handle the chip along the edges with a vacuum collet or
with a sharp pair of bent tweezers. The surface of the chip
may have fragile air bridges and must not be touched with
vacuum collet, tweezers, or fingers.
Mounting
The chip is back metallized and can be die mounted with AuSn
eutectic preforms or with electrically conductive epoxy. Ensure
that the mounting surface is clean and flat.
RF GROUND PLANE
When a eutectic die is attached, an 80% gold/20% tin preform is
recommended with a work surface temperature of 255°C and a
tool temperature of 265°C. When hot 90% nitrogen/10% hydrogen
gas is applied, ensure that the tool tip temperature is 290°C. Do
not expose the chip to a temperature greater than 320°C for
more than 20 sec. For attachment, no more than 3 sec of
scrubbing is required.
13143-030
0.127mm (0.005") THICK ALUMINA
THIN FILM SUBSTRATE
Figure 35. Routing RF Signals
0.102mm (0.004") THICK GaAs MMIC
WIRE BOND
0.076mm
(0.003")
When an epoxy die is attached, apply a minimum amount of
epoxy to the mounting surface so that a thin epoxy fillet is
observed around the perimeter of the chip after it is placed into
position. Cure the epoxy per the schedule of the manufacturer.
RF GROUND PLANE
Wire Bonding
13143-031
0.150mm (0.005") THICK
MOLY TAB
0.254mm (0.010") THICK ALUMINA
THIN FILM SUBSTRATE
Figure 36. Routing RF Signals Using Moly Tab
Place microstrip substrates as close to the die as possible to
minimize bond wire length. Typical die to substrate spacing is
0.076 mm to 0.152 mm (3 mil to 6 mil).
RF bonds made with two 1 mil wires are recommended. Ensure
that these bonds are thermosonically bonded with a force of
40 g to 60 g. DC bonds of 0.001˝ (0.025 mm) in diameter,
thermosonically bonded, are recommended. Create ball bonds
with a force of 40 g to 50 g and wedge bonds with a force of 18 g
to 22 g. Create all bonds with a nominal stage temperature of
150°C. Apply a minimum amount of ultrasonic energy to achieve
reliable bonds. Keep all bonds as short as possible, less than 12 mil
(0.31 mm).
Rev. A | Page 12 of 15
Data Sheet
HMC1144
TYPICAL APPLICATION CIRCUIT
VDD
0.1µF
0.1µF
100pF
100pF
100pF
100pF
3
4
5
6
RFIN
1
RFOUT
7
8
9
10
11
12
100pF
100pF
100pF
100pF
VGG1B
100pF
0.1µF
0.1µF
13143-023
0.1µF
THESE CAPACITORS ARE FOR DECOUPLING ONLY.
NO DC BIAS APPLIED.
Figure 37. Typical Application Circuit
THESE CAPACITORS ARE FOR DECOUPLING ONLY.
NO DC BIAS APPLIED.
0.1µF
0.1µF
VGG1A
0.1µF
100pF
100pF
100pF
100pF
100pF
2
3
4
5
6
RFIN
1
8
7
RFOUT
9
10
11
100pF
100pF
100pF
100pF
0.1µF
Figure 38. Alternate Bias Application Circuit
Rev. A | Page 13 of 15
0.1µF
13143-130
VDD1 TO VDD4A
HMC1144
Data Sheet
ASSEMBLY DIAGRAM
TO VDD SUPPLY
0.1µF
0.1µF
ALL BOND WIRES ARE
1mil DIAMETER
100pF
100pF
100pF
100pF
3mil NOMINAL GAP
50Ω TRANSMISSION LINE
0.1µF
100pF
100pF
0.1µF
TO VGG1B SUPPLY
Figure 39. Assembly Diagram
Rev. A | Page 14 of 15
100pF
100pF
0.1µF
13143-024
100pF
Data Sheet
HMC1144
OUTLINE DIMENSIONS
2.300
0.206
0.203
0.201
2
0.201
0.199
3
0.200
0.199
4
5
0.093
0.200
0.400
6
0.130
0.888
7
0.130
0.130
1.800
1
0.902
0.130
0.447
11
12
10
0.102
9
8
TOP VIEW
0.093
0.206
0.203
0.201
0.199
0.201
0.199
0.200
0.400
0.200
0.043
09-09-2015-A
(CIRCUIT SIDE)
Figure 40. 12-Pad Bare Die [CHIP]
(C-12-2)
Dimensions shown in millimeter
ORDERING GUIDE
Model
HMC1144
Temperature Range
−55°C to +85°C
Package Description
12-Pad Bare Die [CHIP]
©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13143-0-1/16(A)
Rev. A | Page 15 of 15
Package Option
C-12-2