High Speed, 200 dB Range,
Logarithmic Converter
ADL5304
Data Sheet
FEATURES
A single positive supply of 5 V is all that is required for operation
over a specified 1 pA to 3 mA input range. Dual-supply operation
extends the specified input current range to 10 mA.
Optimized for very fast response at all input currents
Overall bandwidth of >4 MHz for inputs >1 µA
Bandwidth: 25 kHz at input of 1 nA and 350 kHz at 10 nA
10 decades of input range: 1 pA to 10 mA
Law conformance: ±0.25 dB from 100 pA to 100 µA
Log ratio or fixed-intercept operation
Precision voltage references and reference current
Adaptive photodiode (PD) bias for low dark current
Programmable log slope and intercept
Default log slope of 10 mV/dB at VLOG pin
Single- or dual-supply operation
The ADL5304 accepts two current inputs to the logarithmic
argument. The numerator input, INUM, flows in the collector of an
NPN transistor, connected in a feedback path around a low offset
JFET amplifier. The denominator current, IDEN, is treated in the
same way, which allows for log ratio operation. The input summing
nodes (INUM and IDEN) operate at a constant default voltage of
1.5 V. The VSM1 to VSM4 pins flank the INUM and IDEN inputs
to provide a guard voltage to minimize leakage currents.
Adaptive photodiode biasing is provided for optical measurements.
A monitor current 1.1 times INUM is output at the IMON pin, and
an external resistor, RMNTR, at 10 times the photodiode series
resistance (RS) applies a voltage across the photodiode that
1st order keeps the internal PD junction at 0 V to minimize
dark current.
APPLICATIONS
High accuracy optical power measurement
Wide range baseband log compression
Versatile detector for high speed APC loops
GENERAL DESCRIPTION
The VLOG output is buffered and can be rescaled through
internal gain setting resistors. The internal ILOG varies from
−400 µA to +400 µA as INUM changes over 10 decades from 1 pA
to 10 mA. This corresponds to 0.5 V to 2.5 V at the VLOG pin
in the default configuration shown in Figure 1.
The ADL5304 is a high speed logarithmic converter with fast
response and low noise over a 200 dB (1 pA to 10 mA) measurement range. The ADL5304 provides a nominal logarithmic slope of
10 mV/dB (200 mV/decade); other values are easily configured.
Logarithmic intercept can be programmed over a wide range
with the internal 100 nA current source or externally for log ratio
applications. The default intercept value of 3.162 fA places the
midpoint of the measurement range of 100 nA at VLOG = 1.5 V.
Accurate 1.5 V (Pin 1P5V) and 2.0 V (Pin 2VLT) reference outputs
allow precise repositioning of the intercept using external resistors.
The ADL5304 is available in a 32-lead, 5 mm × 5 mm LFCSP
and specified for operation from −40°C to +85°C.
SIMPLIFIED BLOCK DIAGRAM
IMON
VNUM
INNM
32
30
BSDC 2VLT VPOS
1P5V
31
26
28
17
RMNTR
VSM1
VSM2
2
3
100nA
DCBI
27
2V
24
BIAS AND
VREF
23
1.5V
MONITOR AND
PD BIAS
(1.1× INUM )
29
1.5V
22
INPS
INMS
VLOG
ADL5304
INUM
4
IREF
VSM3
VSM4
ILOG
21
5kΩ
TEMPERATURE
COMPENSATION
5
6
5kΩ
20
19
VDEN
18
1.5V
SCL2
7.5kΩ
7
8
SCL1
SCL3
ACOM
COMM NMFS VNEG DNFS ACOM HFCP
9
VDEN
10
11
INDN
12
13
1kΩ
VNEG
14
1kΩ
15
16
09459-001
IDEN
VNUM
Figure 1.
Rev. A
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ADL5304
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Terminology .................................................................................... 16
Applications ....................................................................................... 1
Theory of Operation ...................................................................... 17
General Description ......................................................................... 1
Basic Concepts ............................................................................ 17
Simplified Block Diagram ............................................................... 1
Optical Measurements ............................................................... 17
Revision History ............................................................................... 2
Circuit Description .................................................................... 18
Specifications..................................................................................... 3
Applications Information .............................................................. 25
Absolute Maximum Ratings............................................................ 5
Using the ADL5304 .................................................................... 25
ESD Caution .................................................................................. 5
Using a Negative Supply ............................................................ 26
Pin Configuration and Function Descriptions ............................. 6
Evaluation Board Schematic and Silkscreens ............................. 27
Typical Performance Characteristics ............................................. 7
Outline Dimensions ....................................................................... 29
Test Circuits ..................................................................................... 13
Ordering Guide .......................................................................... 29
REVISION HISTORY
3/16—Rev. 0 to Rev. A
Changes to Specified Current Range Parameter, Table 1 ............ 3
Changes to Figure 2 and Table 3 ..................................................... 6
Changes to Figure 58 ...................................................................... 27
Updated Outline Dimensions ....................................................... 29
Changes to Ordering Guide .......................................................... 29
9/11—Revision 0: Initial Version
Rev. A | Page 2 of 32
Data Sheet
ADL5304
SPECIFICATIONS
VPOS = 5 V, VNEG = 0 V, TA = 25°C; IDEN = IREF; VSM1 to VSM4, 1P5V, DCBI, and INPS tied together; SCL1 = VLOG; SCL2 = INMS;
SCL3 = open; scale = 200 mV/dec; VLOG output load RL > 2 kΩ, unless otherwise noted. Upper case indicates a pin name (for example,
VLOG) and subscripted indicates signal name (for example, VLOG).
Table 1.
Parameter
INPUT INTERFACES
Specified Current Range
Temperature Drift (INUM and IDEN)
Input Guard Offset Voltage
LOGARITHMIC OUTPUT
Logarithmic Slope, VY
Logarithmic Intercept, IZ 2
Logarithmic Offset
Logarithmic Law Conformance Error
VLOG OUTPUT
Output Buffer Offset Voltage
Output Buffer Bias Current
Incremental Input Resistance
Output Range
Output Noise Spectral Density 3
Small Signal Bandwidth
Falling Edge Settling Times 4
Nominal Voltage Swing
Output Impedance
REFERENCE OUTPUTS
1P5V (Referenced to ACOM)
Output Current
2VLT (Referenced to ACOM)
Output Current
IREF 5
PHOTODIODE BIAS
Midrange Value
Maximum Value
Test Conditions/Comments
INUM, IDEN, VSMx pins
Flows toward each input pin (INUM and IDEN),
−5 V ≤ VNEG ≤ −2 V
VNEG = 0 V
−40°C < TA < +85°C
VINUM − VVSUM
VLOG pin, referenced to ACOM; input applied to
INUM 1
25°C
−40°C < TA < +85°C
Extrapolated input current at VLOG = 0 V
Difference between VLOG and VSUM with INUM = IDEN
−40°C < TA < +85°C
Maximum deviation from best fit over
1 nA to 100 µA range
INPS, INMS, VLOG, SCL1, SCL2, SCL3 pins
Min
Max
Unit
1 × 10−12
1 × 10−3
A
1 × 10−12
3 × 10−3
A
mV/°C
mV
−2
195
−2
25°C
−40°C < TA < +85°C
Sourcing only
25°C
−40°C < TA < +85°C
IMON pin; IMON = 1.1 × INUM
At a photodiode current = INUM = 100 nA
At INUM = 1 mA (RS ≤ 100 Ω), RMNTR = 10 × RS
(RS = photodiode series resistance)
IMON Compliance
Rev. A | Page 3 of 32
0.01
±0.6
200
+2
205
+3
3.162
−8
−0.7
−3
Flowing out of the INPS pin
Pin INPS
RL open
INUM > 1 nA
INUM = 1 nA
INUM = 10 nA
INUM = 100 nA
INUM > 1 µA
INUM = 100 nA to 10 nA
INUM = 1 µA to 100 nA
INUM = 10 µA to 1 µA
INUM > 10 µA
For input current range of 1 pA to 10 mA
Frequency < 1 MHz
1P5V, 2VLT, IREF pins
25°C
−40°C < TA < +85°C
Typ
+5
25
±0.2
+0.1
−1.3
12
VNEG + 0.2
+0.7
+3
VPOS − 0.2
<6
25
350
1.2
4
10
2.2
0.5
<0.5
0.5
2.5
<2
1.495
−10
1.995
1.500
30
2.000
31
0
1.505
+5
2.005
20
100
−70
10.5
110
11
0
3.0
11.5
mV/dec
mV/dec
fA
mV
µV/°C
dB
mV
µA
MΩ
V
µV/√Hz
kHz
kHz
MHz
MHz
µs
µs
µs
µs
V
Ω
V
µV/°C
mA
V
µV/°C
mA
nA
pA/°C
nA
mA
V
ADL5304
Parameter
POWER SUPPLY
VPOS
Quiescent Current
VNEG 6
Quiescent Current
Data Sheet
Test Conditions/Comments
VPOS, VNEG
INUM = IDEN = 10 µA; VPOS = 5 V, VNEG = 0 V
4.5 V ≤ VPOS ≤ 5.5 V
Nominal 0 V for single supply
INUM = IDEN = 10 µA; VPOS = 5 V, VNEG = 0 V
VNEG = −5 V
Min
Typ
Max
Unit
4.5
5.0
13.5
5.5
16
17
−5
V
mA
mA
V
mA
mA
10
0
−8.5
−10.5
−7.3
−6
Slope is of the same magnitude but opposite sign for input applied to IDEN.
IZ = IREF/10(VOFS/VY). Note that the error of IZ is dependent on three parameters, IREF, VOFS, and VY. All three of those are trimmed.
3
Output noise and small signal bandwidth are functions of input current; measured from the INUM input to the VLOG output. See the Typical Performance
Characteristics section.
4
High-to-low currents (falling edge) represent the worst-case settling condition. Low-to-high currents (rising edge) settling times are approximately 2× faster than the
falling edge settling. Settling time is measured to 1 dB error (10 mV/dB; VLOG settles to within 10 mV of the final value).
5
IREF applied to IDEN together with 1P5V determines the logarithmic intercept current, IZ, and thereby the accuracy of the intercept.
6
Using dual-supply operation with the VSMx, DCBI, and INPS pins at ground, VNEG needs to be in the −2 V to −5 V range for proper device function.
1
2
Rev. A | Page 4 of 32
Data Sheet
ADL5304
ABSOLUTE MAXIMUM RATINGS
Rating
+6 V
−6 V
20 mA
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
61.6°C/W
1.2°C/W
0.6 W
ESD CAUTION
Table 2.
Parameter
VPOS
VNEG
Input Current to INUM, IDEN
Thermal Data, 2-Layer JEDEC Board No Air
Flow (Exposed Pad Soldered to PCB)
θJA
θJC
Maximum Power Dissipation (Exposed
Pad Soldered to PC Board)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 60 sec)
125°C
−40°C to +85°C
−65°C to +150°C
300°C
Rev. A | Page 5 of 32
ADL5304
Data Sheet
32
31
30
29
28
27
26
25
VNUM
INNM
IMON
VPOS
BSDC
DCBI
1P5V
NIC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
ADL5304
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
INPS
INMS
VLOG
SCL1
SCL2
SCL3
ACOM
2VLT
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. CONNECT THE EXPOSED PADDLE TO THE VSM1 TO
VSM4 PINS TO PROVIDE LOW LEAKAGE GUARD.
09459-002
VDEN
INDN
COMM
NMFS
VNEG
DNFS
ACOM
HFCP
9
10
11
12
13
14
15
16
NIC
VSM1
VSM2
INUM
IDEN
IREF
VSM3
VSM4
Figure 2. 32-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1, 25
2, 3, 7, 8
Mnemonic
NIC
VSM1 to VSM4
4
5
6
9
INUM
IDEN
IREF
VDEN
10
11
12
13
14
15, 18
16
17
19
20
21
22
23
24
26
27
INDN
COMM
NMFS
VNEG
DNFS
ACOM
HFCP
2VLT
SCL3
SCL2
SCL1
VLOG
INMS
INPS
1P5V
DCBI
28
29
30
31
32
BSDC
VPOS
IMON
INNM
VNUM
0
EPAD
Description
No Internal Connection.
Guard Pins for the INUM and IDEN Inputs. Connect these pins to the 1P5V, DCBI, and INPS pins for default
single-supply setup; connect to ground if INUM (photodiode bias) is desired to be at ground (must have −5 V
< VNEG < −2 V).
Numerator Current Input.
Denominator Current Input. Connect to the IREF pin for most applications.
100 nA Trimmed Reference Current Output. Connect to the IDEN pin for most applications.
Voltage Output of Denominator Log Amplifier. Connect this pin to the INDN pin and decouple with an
external 0.1 µF capacitor to ground.
Denominator Voltage Input to Temperature Compensation Circuit.
Main Ground.
Numerator Speed Bias (Nominal 1 kΩ Resistor to VNEG Pin).
Negative Supply.
Denominator Speed Bias (Nominal 1 kΩ Resistor to VNEG Pin).
Analog Common, Low Noise Reference Ground. Important that both pins are always grounded.
High Frequency Compensation.
2.0 V Reference Output.
7.5 kΩ Scaling Resistor (See Figure 1). Default is NIC.
5 kΩ Scaling Resistor (See Figure 1). Default is to connect to the INMS pin.
5 kΩ Scaling Resistor (See Figure 1). Default is to connect to the VLOG pin.
Primary Logarithmic Output. For INUM = IDEN, the VLOG pin is at the voltage applied to the INPS pin.
Output Buffer Amplifier Inverting Input.
Output Buffer Amplifier Noninverting Input. The INPS, DCBI, and VSM1 to VSM4 pins must be tied together.
1.5 V Reference Output. Connect to the INPS, DCBI, and VSM1 to VSM4 pins for single-supply operation.
Approximately 1.3 mA Bias Current. Connect this pin to the VSM1 to VSM4 pins. See Pin 2, Pin 3, Pin 7, and Pin 8
description.
Internal Bias Node. Decouple with a series connection of 4 Ω and 1 µF to ground.
Positive Supply.
Photodiode Monitor Output. IMON = 1.1 × INUM.
Numerator Voltage Input to Temperature Compensation Circuit.
Voltage Output of Numerator Log Amplifier. Connect this pin to the INNM pin. For the fastest response, do
not add an external capacitor.
Exposed paddle. Connect the exposed paddle to the VSM1 to VSM4 pins to provide low leakage guard.
Rev. A | Page 6 of 32
Data Sheet
ADL5304
TYPICAL PERFORMANCE CHARACTERISTICS
VPOS = 5 V, VNEG = 0 V, TA = 25°C; IDEN = IREF; VSM1 to VSM4, 1P5V, DCBI, and INPS tied together; SCL1 = VLOG; SCL2 = INMS;
SCL3 = open; scale = 200 mV/dec; VLOG output load RL > 2 kΩ, unless otherwise noted.
3
3.0
2
2.0
1.5
1.0
100p
1n
100n 1μ
10μ
INUM CURRENT (A)
10n
100μ
1m
10m
1n
10n 100n 1μ
10μ
INUM CURRENT (A)
100μ
1m
10m
2.0
1.5
1.0
1
0
–1
+85°C
+70°C
+25°C
0°C
–40°C
–2
100p
1n
100n 1μ
10μ
IDEN CURRENT (A)
10n
100μ
1m
10m
–3
1p
09459-004
10p
10p
100p
1n
10n 100n 1μ
10μ
IDEN CURRENT (A)
100μ
1m
10m
09459-007
ERROR (dB); 10mV/dB
Figure 7. Law Conformance Error vs. IDEN for Multiple Temperatures;
INUM = 100 nA; Normalized to 25°C
Figure 4. VLOG vs. IDEN for Multiple Temperatures; INUM = 100 nA
3
3.5
100pA
1nA
10nA
100nA
1µA
10µA
100µA
1mA
1mA
100µA
10µA
1µA
100nA
10nA
1nA
100pA
ERROR (dB); 10mV/dB
2
2.0
1.5
1.0
1
0
–1
–2
0.5
10p
100p
1n
100n 1μ
10μ
INUM CURRENT (A)
10n
100μ
1m
10m
–3
1p
09459-005
0
1p
10p
100p
1n
10n 100n 1μ
10μ
INUM CURRENT (A)
100μ
1m
10m
09459-008
VLOG OUTPUT (V)
100p
2
0.5
VLOG OUTPUT (V)
10p
3
+85°C
+70°C
+25°C
0°C
–40°C
2.5
2.5
+85°C
+70°C
+25°C
0°C
–40°C
Figure 6. Law Conformance Error vs. INUM for Multiple Temperatures;
Normalized to 25°C
3.0
3.0
–1
–3
1p
09459-003
10p
Figure 3. VLOG vs. INUM for Multiple Temperatures
0
1p
0
–2
0.5
0
1p
1
09459-006
ERROR (dB); 10mV/dB
VLOG OUTPUT (V)
2.5
+85°C
+70°C
+25°C
0°C
–40°C
Figure 8. Law Conformance Error vs. INUM for Multiple Values of IDEN
(Decade Steps from 100 pA to 1 mA)
Figure 5. VLOG vs. INUM for Multiple Values of IDEN
(Decade Steps from 100 pA to 1 mA)
Rev. A | Page 7 of 32
ADL5304
Data Sheet
3
3.5
1mA
100µA
10µA
1µA
100nA
10nA
1nA
100pA
1.5
1.0
100p
1n
100n 1μ
10μ
IDEN CURRENT (A)
10n
100μ
1m
10m
–3
1p
09459-009
10p
100p
1n
10n 100n 1μ
10μ
IDEN CURRENT (A)
100μ
1m
10m
3.0
3.0
+3σ
–3σ
2.5
2.0
1.5
1.5
ERROR (dB); 10mV/dB
2.0
1.0
0.5
0
–0.5
–1.0
1.0
0.5
0
–0.5
–1.0
–1.5
–1.5
–2.0
–2.0
–2.5
–2.5
10p
100p
1n
10n
100n 1μ
INUM (A)
10μ
100μ
1m
±3σ +85°C
±3σ –40°C
2.5
10m
–3.0
1p
09459-065
ERROR (dB); 10mV/dB
10p
Figure 12. Law Conformance Error vs. IDEN for Multiple Values of INUM
(Decade Steps from 100 pA to 1 mA)
Figure 9. VLOG vs. IDEN for Multiple Values of INUM
(Decade Steps from 100 pA to 1 mA)
–3.0
1p
1mA
100µA
10µA
1µA
100nA
10nA
1nA
100pA
–1
–2
0.5
0
1p
0
09459-010
2.0
1
10p
100p
1n
10n
100n 1μ
INUM (A)
10μ
100μ
5
3.0
±3σ 70°C
±3σ 0°C
2.0
10m
Figure 13. Law Conformance Error Distribution vs. INUM for −40°C and +85°C
(3 σ Either Side of Mean)
Figure 10. Law Conformance Error Distribution vs. INUM
(3 σ Either Side of Mean)
2.5
1m
09459-013
VLOG OUTPUT (V)
2.5
2
ERROR (dB); 10mV/dB
3.0
+3σ
–3σ
4
3
INPUT OFFSET (mV)
ERROR (dB); 10mV/dB
1.5
1.0
0.5
0
–0.5
–1.0
2
1
0
–1
–2
–1.5
–3
–2.0
10p
100p
1n
10n
100n 1μ
INUM (A)
10μ
100μ
1m
10m
–5
–40
09459-011
–3.0
1p
Figure 11. Law Conformance Error Distribution vs. INUM for 0°C and 70°C
(3 σ Either Side of Mean)
Rev. A | Page 8 of 32
–20
0
20
40
TEMPERATURE (°C)
60
80
Figure 14. (VINUM − VSUM) vs. INUM for Multiple Temperatures
09459-014
–4
–2.5
Data Sheet
ADL5304
103
300
TYPICAL
+3σ
–3σ
250
101
200
100
COUNT
99
150
100
98
50
97
0
60
40
20
TEMPERATURE (°C)
80
0
1.00
Figure 15. IREF Current vs. Temperature
Figure 18. IMON Histogram at INUM = 1 mA
5
5
+3σ
–3σ
3
3
2
2
1
0
–1
–2
1
0
–1
–4
–4
–20
0
20
40
TEMPERATURE (°C)
60
80
09459-016
–3
–5
–40
0
40
20
TEMPERATURE (°C)
60
80
Figure 19. 2VLT Drift vs. Temperature
2.000
1.515
1.995
REFERENCE VOLTAGE (V)
1.510
1.505
1.500
1.495
1.990
1.985
1.980
1.975
0 1 2 3 4 5
LOAD CURRENT (mA)
6
7
8
9
10
1.970
–20
09459-017
1.490
–5 –4 –3 –2 –1
–20
09459-019
–2
–3
Figure 16. 1P5V Drift vs. Temperature
REFERENCE VOLTAGE (V)
+3σ
–3σ
4
2VLT DRIFT (mV)
1P5V DRIFT (mV)
4
–5
–40
1.20
1.10
1.15
IMON CURRENT (mA)
1.05
09459-018
–20
09459-015
96
–40
Figure 17. 1P5V vs. ILOAD (Positive Current Defined into 1P5V Pin)
–15
–10
LOAD CURRENT (mA)
–5
0
Figure 20. 2VLT vs. ILOAD (Positive Current Defined into 2VLT Pin)
Rev. A | Page 9 of 32
09459-020
IREF CURRENT (nA)
102
ADL5304
Data Sheet
10
10
NORMALIZED RESPONSE (dB)
5
–20
–30
1mA
100µA
10µA
1µA
100nA
10nA
1nA
–40
–50
–60
–70
100
1k
0
–5
–10
–15
–20
10k
100k
1M
FREQUENCY (Hz)
10M
100M
1mA
100µA
10µA
1µA
100nA
10nA
–25
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
Figure 21. Small Signal AC Response from INUM to VLOG for INUM in
Decade Steps from 1 nA to 1 mA, IDEN = 100 nA
Figure 24. Small Signal AC Response from IDEN to VLOG for IDEN in
Decade Steps from 10 nA to 1 mA; INUM = 100 nA
100
100
100pA
1nA
10nA
100nA
1µA
10µA
100µA
1mA
EQUIP LIMIT
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
10
SPOT NOISE (µV rms/ Hz)
SPOT NOISE (µV rms/ Hz)
10
1
0.1
09459-027
–10
09459-024
NORMALIZED RESPONSE (dB)
0
1
0.1
0.001
100p
Figure 22. Spot Noise Spectral Density at VLOG vs. Frequency for INUM in
Decade Steps from 1 nA to 1 mA (Noise at lower frequencies, where NSD is
flat, is limited by resistance used to generate dc INUM current. See the Noise vs.
Current section for further explanation.)
10n
100n
1µ
INUM (A)
10µ
100µ
40
4
1mA TO 10mA
2.5
VLOG OUTPUT ERROR (mV)
10µA TO 100µA
2.1
1µA TO 10µA
1.9
100nA TO 1µA
1.7
10nA TO 100nA
1.5
1nA TO 10nA
1.3
100nA TO 10nA
1µA TO 100nA
10µA TO 1µA
100µA TO 10µA
1mA TO 100µA
INPUT
30
100µA TO 1mA
2.3
1m
Figure 25. Spot Noise Spectral Density at VLOG vs. INUM in Decade Frequency
Steps from 100 Hz to 10 MHz
2.7
VLOG (V)
1n
20
3
2
10
1
0
0
–10
–1
–20
–2
–30
–3
ERROR (dB); 10mV/dB
10M
1M
09459-028
STEP IS ANALYZER ARTIFACT
0.01
100
1k
10k
100k
FREQUENCY (Hz)
09459-029
0.01
0.9
0
10
20
30
TIME (µs)
40
50
60
–40
–2
09459-026
0.7
Figure 23. Pulse Response for INUM in Decade Steps from 1 nA to 1 mA,
IDEN = 100 nA
Rev. A | Page 10 of 32
0
2
4
6
TIME (µs)
8
10
–4
12
Figure 26. Normalized Falling Edge Settling of INUM to Within 1 dB
(Error = 10 mV/dB)
09459-033
1.1
Data Sheet
ADL5304
2.3
10
2.1
8
1.9
6
4
DELTA VLOG (mV)
1.7
10nA TO 100nA
1.5
100nA TO 1µA
1.3
1µA TO 10µA
10µA TO 100µA
0.9
100µA TO 1mA
0.7
10
20
30
TIME (µs)
–2
–4
–8
0.3
0
0
–6
1mA TO 10mA
0.5
2
40
50
60
–10
–40
–20
0
20
40
TEMPERATURE (°C)
60
80
09459-130
1.1
09459-030
VLOG (V)
+3σ
–3σ
Figure 30. Logarithmic Offset Drift vs. Temperature
(3 σ to Either Side of Mean)
Figure 27. Pulse Response for IDEN in Decade Steps from 1 nA to 1 mA;
INUM = 100 nA
250
10m
200
100µ
150
10µ
100
1µ
50
100n
0
20
40
TIME (µs)
80
60
0
–1.0
1.0
200
3
2
150
COUNT
1
0
100
–1
–2
50
–3
–5
–40
–20
0
20
40
TEMPERATURE (°C)
60
80
0
1.496
1.498
1.500
1.502
1P5V VOLTAGE (V)
Figure 32. 1P5V Histogram
Figure 29. Slope Drift vs. Temperature for 200 mV/dec
(3 σ to Either Side of Mean)
Rev. A | Page 11 of 32
1.504
09459-132
–4
09459-129
DELTA SLOPE (mV/dec)
0.5
250
+3σ
–3σ
4
0
INUM VOS (mV)
Figure 31. (VNUM − VSUM) Histogram at 25°C
Figure 28. IMON Pulse Response vs. INUM
5
–0.5
09459-131
COUNT
1m
09459-032
IMON CURRENT (A)
1.1µA TO 11µA
11µA TO 110µA
110µA TO 1.1mA
ADL5304
Data Sheet
180
300
160
250
140
120
COUNT
COUNT
200
150
100
100
80
60
40
50
1.998
2.000
2.002
2.004
2VLT VOLTAGE (V)
0
1.495
09459-133
0
1.996
1.503
1.505
Figure 36. Distribution of VLOG for INUM = IDEN = 100 nA (Nominally 1.500 V)
20
250
15
SUPPLY CURRENT (mA)
300
200
150
100
50
10
2
VPOS SINGLE SUPPLY
VNEG SINGLE SUPPLY
VPOS DUAL SUPPLY
VNEG DUAL SUPPLY
0
–5
–10
197.5
200.0
202.5
205.0
INUM SLOPE (mV/dec)
–15
09459-134
0
195.0
–40
140
120
100
80
60
40
97.5
100.0
102.5
IREF CURRENT (nA)
105.0
09459-135
20
95.0
0
20
40
60
80
TEMPERATURE (°c)
Figure 34. Distribution of Logarithmic Slope (Nominally 200 mV/dec)
0
–20
Figure 35. Distribution of IREF (Nominally 100 nA)
Rev. A | Page 12 of 32
Figure 37. Supply Current vs. Temperature (|VPOS|, |VVNEG|)
09459-137
COUNT
1.500
VOFFSET (V)
Figure 33. 2VLT Histogram
COUNT
1.498
09459-136
20
Data Sheet
ADL5304
TEST CIRCUITS
KEITHLEY 236 SMU
SOURCE CURRENT
MEASURE VOLTAGE
AGILENT 34970A
DATA ACQUISITION UNIT
VSUM
VPOS
VNEG
1P5V
2VLT
KEITHLEY 236 SMU
SOURCE CURRENT
MEASURE VOLTAGE
IMON
VNUM
30
INNM
32
BSDC 2VLT VPOS
1P5V
31
26
28
VSM1
VSM2
2
3
100nA
27
2V
24
BIAS AND
VREF
23
1.5V
MONITOR AND
PD BIAS
(1.1× INUM )
DCBI
29
17
1.5V
22
INPS
INMS
VLOG
ADL5304
INUM
4
VNUM
ILOG
21
5kΩ
IDEN
TEMPERATURE
COMPENSATION
5
VSM3
VSM4
6
20
19 SCL3
VDEN
18
1.5V
SCL2
7.5kΩ
7
8
SCL1
ACOM
COMM NMFS VNEG DNFS ACOM HFCP
9
10
VDEN
11
12
INDN
13
14
1kΩ
15
16
1kΩ
0.1µF
09459-038
IREF
5kΩ
0.1µF
VNEG
Figure 38. Setup for Measuring Logarithmic/Slope/Offset Conformance
HP3577B
NETWORK ANALYZER
OUTPUT INPUT R INPUT A
50Ω
AD8138
EVALUATION BOARD
MODIFIED TO PROVIDE
DC OFFSET
J2
J3
50Ω
INPUT
HP11667B
SPLITTER
J4
IMON
VNUM
BSDC 2VLT VPOS
1P5V
INNM
32
30
31
26
28
17
VSM1
VSM2
1kΩ TO 10MΩ
TO SET
CURRENT
2
3
100nA
24
BIAS AND
VREF
23
1.5V
22
INPS
INMS
VLOG
ADL5304
INUM
4
50Ω
TERM
DCBI
27
2V
1.5V
MONITOR AND
PD BIAS
(1.1× INUM )
29
VNUM
ILOG
21
5kΩ
IDEN
TEMPERATURE
COMPENSATION
5
IREF
VSM3
VSM4
6
5kΩ
20
8
SCL2
7.5kΩ
19 SCL3
VDEN
7
18
1.5V
SCL1
ACOM
COMM NMFS VNEG DNFS ACOM HFCP
10
9
VDEN
11
INDN
12
13
1kΩ
0.1µF
VNEG
Figure 39. Setup for Measuring Bandwidth
Rev. A | Page 13 of 32
14
1kΩ
15
16
0.1µF
09459-039
J1
ADL5304
Data Sheet
LECROY SDA6000
AGILENT 33250A
PULSE GENERATOR
PULSE
OUTPUT
TRIGGER
OUTPUT
SCOPE INPUT
50Ω AP1M 1MΩ
TRIGGER
INPUT
INPUT
HP11667B
SPLITTER
IMON
VNUM
30
INNM
32
BSDC 2VLT VPOS
1P5V
31
26
28
2V
24
BIAS AND
VREF
23
1.5V
VSM1
VSM2
2
3
100nA
1.5V
22
INMS
VLOG
ADL5304
INUM
4
50Ω
TERM
INPS
VNUM
ILOG
21
5kΩ
IDEN
TEMPERATURE
COMPENSATION
5
IREF
VSM3
VSM4
6
5kΩ
20
8
SCL2
7.5kΩ
19
VDEN
7
18
1.5V
SCL1
SCL3
ACOM
COMM NMFS VNEG DNFS ACOM HFCP
9
VDEN
10
11
12
INDN
13
14
1kΩ
15
16
1kΩ
0.1µF
09459-040
1kΩ TO 10MΩ
TO SET
CURRENT
MONITOR AND
PD BIAS
(1.1× INUM )
DCBI
27
29
17
0.1µF
VNEG
Figure 40. Setup for Measuring Pulse Settling
LECROY SDA6000
BCP MODEL 400
1300nm LASER
LASER
OUTPUT
AGILENT 33250A
PULSE GENERATOR
MODULATION
INPUT
PULSE
OUTPUT
TRIGGER
OUTPUT
TRIGGER
INPUT
SCOPE INPUT
AP1M 1MΩ
JDS FITEL HA9
ATTENUATOR
IMON
VNUM
8/125µm
SINGLE MODE
FIBER
BSDC 2VLT VPOS
1P5V
INNM
32
30
31
26
17
28
100Ω
VSM1
VSM2
2
3
100nA
DCBI
27
2V
24
BIAS AND
VREF
23
1.5V
MONITOR AND
PD BIAS
(1.1× INUM )
29
1.5V
22
INPS
INMS
VLOG
ADL5304
INUM
4
ILOG
21
5kΩ
IDEN
TEMPERATURE
COMPENSATION
5
IREF
VSM3
VSM4
6
5kΩ
20
8
SCL2
7.5kΩ
19
VDEN
7
18
1.5V
SCL1
SCL3
ACOM
COMM NMFS VNEG DNFS ACOM HFCP
10
9
VDEN
INDN
11
12
13
1kΩ
0.1µF
VNEG
Figure 41. Setup for Measuring Photodiode Pulse Response
Rev. A | Page 14 of 32
14
1kΩ
15
16
0.1µF
09459-041
ABB HAFO 1A227
VNUM
Data Sheet
ADL5304
KEITHLEY 236 SMU
SOURCE CURRENT
MEASURE VOLTAGE
KEITHLEY 236 SMU
SOURCE CURRENT
MEASURE VOLTAGE
IMON
VNUM
INNM
BSDC 2VLT VPOS
1P5V
31
32
30
28
26
17
VSM1
VSM2
2
3
100nA
27
2V
24
BIAS AND
VREF
23
1.5V
MONITOR AND
PD BIAS
(1.1× INUM )
DCBI
29
1.5V
22
INPS
INMS
VLOG
ADL5304
INUM
4
VNUM
ILOG
21
5kΩ
IDEN
TEMPERATURE
COMPENSATION
5
VSM3
VSM4
6
20
19 SCL3
VDEN
18
1.5V
SCL2
7.5kΩ
7
8
SCL1
ACOM
COMM NMFS VNEG DNFS ACOM HFCP
10
9
VDEN
12
11
INDN
13
15
14
1kΩ
16
1kΩ
0.1µF
09459-042
IREF
5kΩ
0.1µF
VNEG
Figure 42. Setup for Measuring Output
LECROY SDA6000
AGILENT 33250A
PULSE GENERATOR
TRIGGER
OUTPUT
TRIGGER
INPUT
SCOPE INPUT
50Ω AP1M 1MΩ
INPUT
1kΩ TO 100kΩ
LOAD
HP11667B
SPLITTER
IMON
VNUM
30
INNM
BSDC 2VLT VPOS
1P5V
31
32
17
28
26
VSM1
VSM2
1kΩ TO 10MΩ
TO SET
CURRENT
2
3
100nA
24
BIAS AND
VREF
23
1.5V
22
INPS
INMS
VLOG
ADL5304
INUM
4
50Ω
TERM
DCBI
27
2V
1.5V
MONITOR AND
PD BIAS
(1.1× INUM )
29
VNUM
ILOG
21
5kΩ
IDEN
TEMPERATURE
COMPENSATION
5
IREF
VSM3
VSM4
6
5kΩ
20
8
SCL2
7.5kΩ
19
VDEN
7
18
1.5V
SCL1
SCL3
ACOM
COMM NMFS VNEG DNFS ACOM HFCP
10
9
VDEN
11
12
INDN
13
1kΩ
14
1kΩ
0.1µF
VNEG
Figure 43. Setup for Measuring IMON Pulse Response
Rev. A | Page 15 of 32
15
16
0.1µF
09459-043
PULSE
OUTPUT
ADL5304
Data Sheet
TERMINOLOGY
IPD = ρ × POPT
(1)
where typical values for ρ of InGaAs p-intrinsic-n (PIN) photodiodes are in the range of 0.6 A/W to 1 A/W. In the case of 1 A/W,
this means that for 1 mW of incident optical power, POPT, the
PD delivers 1 mA of current, IPD.
When the photodiode current input to the ADL5304 is divided
by the responsivity, the log slope directly represents the change
in input optical power, POPT.
Dark Current
All reverse-biased diodes develop a current due to the random
generation of electrons/holes in the depletion region. In photodiodes, this current occurs with no incident light falling on the
diode and is called the dark current, IDK. Dark current limits the
minimum signal that can be reliably detected. For high speed
InGaAs PIN photodiodes, the IDK is typically around 5 nA. For
a photodiode with a responsivity of 1 A/W, a 5 nA IDK limits
minimum measureable optical power to −53 dBm.
Logarithmic Function
The logarithmic function is
I
VLOG = VY × log10  NUM
 IZ




(2)
Logarithmic Slope
Logarithmic slope is the change in output voltage (VLOG) for a
given change in input current usually shown as a semi-log
graph where one input current (INUM or IDEN) is plotted on a log
scale, and the output voltage (VLOG) is plotted on a linear scale.
The other input current is fixed. Typically, slope is denoted as
VY with units of mV/decade or mV/dB. For the ADL5304, in
the default configuration, VY = 200 mV/decade (10 mV/dB).
Logarithmic Intercept
Logarithmic intercept, IZ, is an extrapolated value representing
the input current where VLOG = 0 V. In single-supply operation
(the VSMx pins = DCBI = INPS = 1P5V), VLOG is always
positive, and when the ADL5304 is operating in the default
configuration of IDEN = IREF = 100 nA, the logarithmic intercept
occurs at INUM = 3.162 fA.
For example, if connected to ground, then the intercept is at IZ =
IDEN = INUM for which log(INUM/IDEN) = 0. This is how most
people interpret the function log(x).
The most practical way to define intercept is to simply always use
log10(INUM/IDEN) = 0 as the reference point. The only consequence is
that a VOFS needs to be introduced depending on how the output
buffer gain and offset is set up.
I
VLOG = VY × log10  NUM
 I DEN

 + VOFS


(3)
For the default single-supply setup, as shown in Figure 1, VY =
0.2 V/decade and VOFS = 1.5 V (derived from the 1P5V pin),
and IDEN is supplied by the on-chip trimmed IREF = 100 nA.
The relationship between IZ and VOFS is as follows:
IZ =
I DEN
 VOFS


10  VY




=
I REF
 V1P 5V


10  VY




=
100 nA
(4)
 1.5V 


10  0.2V/dec 
Because IREF and VY are trimmed for the default setup with VOFS =
1.500 V, IZ should also be a stable quantity; however, because it is a
calculated value determined by the IREF, V1P5V, and VY parameters,
its distribution is the combination of the three parameters and
wider than the original parameters.
The ideal single- and dual-supply ADL5304 responses are
shown in Figure 44.
Rev. A | Page 16 of 32
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
1p
SINGLE SUPPLY VSUM = 1.5V
INUM = IDEN
200mV/DEC
DUAL SUPPLY VSUM = 0V
INUM = IDEN
200mV/DEC
10p
100p
1n
10n
100n
1µ
10µ
100µ
INUM INPUT CURRENT (A)
Figure 44. Ideal Transfer Function
1m
10m
09459-054
Photodiode Responsivity
Photodiode (PD) responsivity, ρ, is a constant that correlates
optical power (POPT) with PD current (IPD).
In the case of dual-supply operation of the device, the intercept
can be shifted to different values depending on where the VSM1 to
VSM4, DCBI, and INPS pins are biased; the only recommended
values are either 1.5 V via connection to the 1P5V pin, as in the case
of single-supply operation, or ground when a dual supply is used.
VLOG OUTPUT VOLTAGE (V)
Optical Power
Optical power is defined as photon energy per unit of time
measured as radiant flux (Φ) or radiant power, which is radiant
energy (Q) per unit time.
Data Sheet
ADL5304
THEORY OF OPERATION
BASIC CONCEPTS
The ADL5304 exploits the logarithmic relationship between base
emitter voltage, VBE, and the collector current, IC, of a bipolar
junction transistor (see Equation 5). This is the fundamental basis
of the extended class of translinear circuits. A log amp based on this
unique property of the bipolar transistor is called a translinear log
amp to distinguish it from log amps designed for RF applications,
which use different principles while having similar objectives.
VBE = VT log(IC/IS)
(5)
Two scaling quantities appear in Equation 5: the thermal voltage,
VT = kT/q, and the saturation current, IS. The thermal voltage is
of crucial importance in determining the logarithmic slope in a
translinear log amp. VT has a process invariant value of 25.69 mV
at T = 25°C and varies in proportion to the absolute temperature
(PTAT). Saturation current, unlike VT, is a process and device
dependent parameter. Saturation current is typically approximately
10−16 A at 25°C, but exhibits enormous variation over temperature,
by a factor of more than a billion.
The temperature dependence of saturation current is compensated
in the ADL5304 by using a second reference transistor, having
an identical variation, to stabilize the intercept by using the
difference between the two VBEs.
Input currents, INUM and IDEN, are the numerator and denominator
of the logarithmic argument that follows:
ΔVBE = VT log (INUM/IDEN)
(6)
In log ratio applications, both INUM and IDEN may each vary over
the full specified range of 1 pA to 10 mA. However, in default
operation, IDEN takes the internally preset current of IREF = 100 nA.
Equation 6 shows that the ΔVBE is still PTAT, but the required
logarithmic slope must be temperature stable; therefore, this is
corrected using proprietary circuit techniques. Using this
correction the relationship between a photodiode current, IPD,
applied to INUM, and the voltage appearing at the output at
VLOG is
VLOG = VY log10(IPD/IZ)
(7)
where:
VY is the log slope voltage (and, for the case of base-10 logarithms,
it is also the volts per decade ).
IZ is the extrapolated log intercept.
The relationship between VY and ΔVBE is a factor close to 3.333
in the default configuration from (VNUM − VDEN) to the output of
VLOG. Because a decade change in the input current ratio results
in close to a 60 mV/decade change in ΔVBE; multiplying this by
3.333 results in 0.2 V/decade. During fabrication, VY is trimmed
to 0.2 V/decade (10 mV/dB), IREF to 100 nA, VOFS to 1.500 V,
and IZ to 3.162 fA. When IPD = 1 pA, the output VLOG has a value
of 0.5 V (see Figure 44). IZ is small because VLOG is always above
ground potential even at the lowest end of the dynamic range,
when using VOFS = 1.500 V. If a negative supply is used, this
voltage can cross zero at the intercept value.
The output for the value of IPD can be calculated using Equation 8.
For example, with an input current of 100 nA,
VLOG = 0.2 V log10(100 nA/3.162 fA) = 1.500 V
(8)
The slope and intercept can be adjusted to suit the application,
to either higher or lower values, without significant loss of
calibration accuracy.
OPTICAL MEASUREMENTS
It is important to understand the transducer aspects of a photodiode when interpreting the photodiode current relative to the
incident optical power.
In purely electrical circuits, current applied to a resistive load
results in a power proportional to the square of the current. For
a photodiode interface, however, there is a difference in scaling
because photon-generated photodiode current (IPD) flows in an
element biased at a fixed voltage. IPD is equal to the optical
power (POPT) absorbed in the detector times the responsivity of
the photodiode (ρ).
IPD = ρ × POPT
(9)
A similar relationship exists between the intercept current, IZ,
and effective intercept power, PZ.
IZ = ρ × P Z
(10)
Therefore, the VOUT equation for the ADL5304 may be written as
VLOG = VYlog10(POPT/PZ)
(11)
For the ADL5304 operating in its default mode, an IZ of 3.162 fA
corresponds to a PZ of 3.95 fW for a diode having a responsivity
of 0.8 A/W. An optical power of 12.5 µW therefore generates
VLOG = 0.2 V log10(12.5 µW/3.95 fW) = 1.900 V
In optical applications, the interpretation of VLOG is as an
equivalent optical power; therefore, the slope for calculation
purposes remains 10 mV/dB (for either current or power).
Rev. A | Page 17 of 32
(12)
ADL5304
Data Sheet
Decibel Scaling
IMON VNUM
30
When signal power is expressed in decibels above a reference level
(for example, dBm, when the reference is 1 mW), logarithmic
conversion has already been implicitly performed. Therefore, the
log ratio in the previous expressions becomes a simple difference.
Be careful in assigning variable names, because P is often used to
denote actual power as well as this same power expressed in
decibels. These are very different quantities. Misunderstandings
can be avoided by using D to denote decibel powers.
RMNTR
PD
1.5V
VREF
VSM2
2
3
1.5V
Q3
VNUM
Q1
INUM
4
IDEN
Y
SHIELD
TEMP
COMP
5
Q2
IREF
(13)
7
8
(14)
the same result calculated with Equation 12.
1.5V
VSM4
9
VDEN
09459-055
VSM3
Using the previous example and assuming a reference power
of 1 mW, a POPT of 12.5 μW corresponds to a DOPT of
10 log10(12.5 μW/1 mW) = −19.03 dBm; the equivalent intercept
power of 3.95 fW corresponds to a DZ of −114.03 dBm. Therefore,
ILOG
VDEN
6
where:
VLOG = 20 mV (−19.03 − (−114.03)) = 1.900 V
VSM1
1P5V
26
100nA
SHIELD
of a power measurement), it can be written
DOPT is the optical power expressed in decibels above a reference
level.
DZ denotes the equivalent intercept power relative to the same level.
31
MONITOR AND
PD BIAS
(1.1× INUM )
When VY (the volts/decade ) is converted to its decibel value,
V  = VY/10 (because there are 10 dB per decade in the context
VLOG = 20 mV(DOPT − DZ)
INNM
32
10
INDN
Figure 45. Simplified Front-End Schematic
In conventional translinear log amps, the collector and base of
Q1 are both held at ground potential, this is not possible in a
single-supply part.
A second transistor, Q2, operates at a collector current of IDEN.
In most applications, this is the reference of IREF = 100 nA,
supplied internally and laser trimmed.
The difference between the two VBEs with Q1 accepting a
photodiode current of INUM = IPD is
CIRCUIT DESCRIPTION
The ADL5304 addresses a wide variety of interfacing conditions
to meet the needs of fiber optic supervisory systems, as well as
many nonoptical applications. This section explains the general
structure of this log amp. The ADL5304 is an order of magnitude
faster than any previous log amp that Analog Devices, Inc., has
made, through careful FET amp design; the key limitation in
the speed at low currents.
Figure 45 is a simplified schematic of the front-end section of
the ADL5304. The numerator current, INUM, is received at the
INUM pin. The voltage at this node is equal to that on the two
adjacent guard pins, VSM2 and IDEN, differing only by the offset
voltage of the JFET op amp that supports the operation of the
Translinear Device Q1 that converts the INUM current to a
logarithmic voltage. VSM2 is needed to provide the collectoremitter bias for Q1, and it is preset to 1.5 V via the external
connection to Pin 1P5V.
VBE1 − VBE2 = VT log10(IPD/IREF)
(15)
By adding an accurate PTAT voltage of magnitude,
VOFS = VT log10(IREF/IZ) = 1.500 V
(16)
resulting in
VBE1 − VBE2 + VOFS = VT [log10(IPD/IREF) + log10(IREF/IZ)]
= (kT/q) log10(IPD/IZ)
(17)
The temperature variation of kT/q is then eliminated by an
analog divider that essentially puts a variable proportional to
temperature underneath the T in Equation 17 and raising the
magnitude of kT/q to a stable value of 0.2 V. Therefore, for
photodiode applications,
VLOG = 0.2 V log10(IPD/IZ)
(18)
When the VSM1to VSM4, DCBI, and INPS pins are tied to
ground and VNEG < −2 V, the offset (VOFS) is removed, leaving
the more general form.
VLOG = 0.2 V log10(INUM/IDEN)
Rev. A | Page 18 of 32
(19)
Data Sheet
ADL5304
Bandwidth vs. Current
Both the response time and wideband noise of translinear log
amps are functions of the transistor collector current, IC, and
only slightly amenable to improvement by circuit design. The
bandwidth falls at low values of IC due to the effects of junction
capacitances in Q1 and the decrease in transconductance (gm)
of a bipolar transistor, which is a linear function of IC, or in the
case of a photodiode application, the photocurrent, IPD. The
corresponding incremental emitter resistance is
re = 1/gm = VT/IPD = kT/qIPD
(20)
and becomes extremely high at low currents (260 MΩ at IC =
100 pA). Therefore, even minute capacitances associated with
the transistor can generate very long time constants.
If the net effect of these capacitances is represented loosely as
CJ, the corresponding low-pass corner frequency is
f−3dB = qIPD/2πkTCJ
(21)
showing the proportionality of bandwidth to current. Using a
value of 0.3 pF for CJ, this becomes 20 MHz/µA. The small signal
bandwidth at IPD = 100 pA is thus only 2 kHz. However,
whereas this simple model can be useful in making the basic
point, it excludes many other effects that limit its accuracy. At high
currents, the subsequent signal processing limits the maximum
overall bandwidth.
Noise vs. Current
For an ideal bipolar transistor, the voltage noise spectral density,
SNSD, referred to VBE, and caused by shot-noise mechanisms,
evaluates to
SNSD = 14.6/√IC nV/√Hz (TA = 27°C)
(22)
where IC is in µA. For example, at an IC of 1 nA, SNSD evaluates to
approximately 0.5 µV/√Hz.
10µV
1µV
Note how at low frequencies the NSD flattens for input currents
less than 10 nA, this noise is limited by the resistor that makes
the dc current. A 10 MΩ resistor was used for these three currents
with a dc bias voltage across the resistor of 1 mV, 10 mV, and
100 mV, respectively.
A 10 MΩ resistor makes a noise current of 40.7 fA/√Hz, which is
converted via the gm of the logging transistor into a noise voltage.
This voltage adds to the noise voltage of the bipolar transistor itself,
as shown in Figure 46. The re of the transistor is 1/gm and equal
to 25.85 MΩ at IC equals 1 nA. Together with the noise current of
the source resistor, this makes a noise voltage at the emitter of the
logging transistor (VNUM) of 1.05 µV/√Hz; this contrasts with
the noise voltage of the transistor itself of 0.46 µV/√Hz
(approximately 0.5 µV/√Hz). The total combined noise is
approximately 1.15 µV/√Hz.
The effect of the 10 MΩ resistor at 100 pA of dc current becomes
even more pronounced because the noise at VNUM due to the
source resistor is 10.5 µV/√Hz, whereas the transistor only
contributes 1.46 µV/√Hz for a total of 10.6 µV/√Hz.
Therefore, unless the resistor that makes the dc current becomes
very large, in general, measurement at the lower currents is
limited by the noise of the source resistor. This problem does not
exist when using a photodiode because the resistance of the
photodiode increases at the same rate as the logging transistor
(see Figure 47).
100nV
10nV
1nV
100pV
100p
1n
10n
100n
1µ
10µ
100µ
IC (A)
1m
10m
09459-056
NOISE SPECTRAL DENSITY (V/ Hz)
NOISE SPECTRAL DENSITY OF VBE
Assuming a 20 kHz net system bandwidth at this current, the
integrated noise voltage is 70 µV rms. The theoretical noise of
VBE vs. IC is shown in Figure 46. However, the log scaling of the
VBE is approximately 3 mV/dB, and in the ADL5304, this is
increased to a slope of 10 mV/dB at the VLOG pin. Therefore,
the noise at VLOG, predicted by Equation 22, is multiplied by a
factor of 3.33. Secondary sources of noise, mostly in the analog
divider used for temperature stabilization of the slope and the
input FET buffer amplifiers, add to this basic noise. The measured
data are shown in Figure 22.
Figure 46. Noise Spectral Density of VBE vs. IC
Rev. A | Page 19 of 32
ADL5304
Data Sheet
R&S FSEA30
SPECTRUM ANALYZER
20MHz TO
3.5GHz
INPUT
COAX SHIELD BIASED TO
VLOG DC LEVEL
DUT 5V
IMON
VNUM
30
VSM1
VSM2
BUFFER +9V
INUM
AD8597
1MΩ log
CONDUCTIVE PLASTIC
BUFFER –9V
DUT 5V
10kΩ LINEAR 15 TURN
IDEN
IREF
VSM3
VSM4
31
26
28
17
100nA
29
VPOS
DCBI
27
2V
24
BIAS AND
VREF
23
1.5V
MONITOR AND
PD BIAS
(1.1× INUM )
2
3
32
BSDC 2VLT
1P5V
INNM
1.5V
22
SHIELD
BIAS
INPS
INMS
VLOG
COAX SHIELD
BROKEN
ADL5304
VNUM
4
ILOG
21
5kΩ
TEMPERATURE
COMPENSATION
5
6
5kΩ
20
19
VDEN
18
1.5V
SCL2
7.5kΩ
7
8
SCL1
SCL3
ACOM
COMM NMFS VNEG DNFS ACOM HFCP
9
4kΩ METAL FILM
10
11
12
INDN
VDEN
13
14
1kΩ
15
16
0.1µF
1kΩ
0.1µF
VNEG
+
–
9V
DUT 5V
BUFFER –9V
–
9V
+
+
1kΩ LINEAR 15 TURN
7805
9V
–
09459-047
BUFFER +9V
SHIELD BIAS
SHIELDED ENCLOSURE
Figure 47. Setup for Measuring Noise for INUM = 100 pA, INUM = 1 nA, and INUM = 10 nA
Filtering to Improve Noise and Dynamic Behavior
C2N
The noise at the output of a log amp, particularly at low current
levels, leads to uncertainty in the measurement. Noise amplitude
is limited by the finite bandwidth.
VSM1
C1N
VSM2
INUM
2
3
31
26
22
6
VSM4
8
VDEN
1.5V
21
ILOG 5kΩ
5kΩ
20
7.5kΩ
19
18
9
VLOG
C2D
SCL1
SCL2
SCL3
ACOM
10
VDEN
INDN
RD
C3D
Figure 48. Possible External Filtering Locations
Rev. A | Page 20 of 32
INPS
INMS
CFB
VNUM
7
23
BIAS
4
VSM3
24
100nA
1.5V
5
C1D
DCBI
27
1.5V
MONITOR AND
PD BIAS
(1.1× INUM )
IDEN
IREF
1P5V
INNM
32
09459-057
Typically, capacitors are not used on the numerator side (INUM)
to keep the speed of the device as high as possible. On the
denominator side (IDEN), additional filtering is useful to reduce
noise. In applications where INUM is used as the reference to the
logarithmic equation and IDEN is a variable, for example, where a
reverse logarithmic slope is desired, filtering can be done on the
numerator side (INUM).
VNUM
TEMPERATURE
COMPENSATION
If measurement speed is not of primary concern, additional
filtering can reduce noise. Figure 48 shows the recommended
locations for additional external filtering. Note the ADL5304
consists of a current-to-voltage (transimpedance) conversion
(INUM or IDEN to VNUM − VDEN), followed by a voltage-to-current
conversion (VNUM − VDEN to ILOG), and then followed by another
current-to-voltage conversion (ILOG to VLOG).
C3N
RN
Data Sheet
ADL5304
The C1D capacitor effectively reduces the bandwidth of the
denominator input stage. A few picofarads of capacitance
(<5 pF) reduce the bandwidth significantly for currents below
approximately 1 µA, though whereas 1 nF to 10 nF are normally
enough to reduce the bandwidth up to the maximum 10 mA of
input current. When measurement speed is of primary importance,
it is better to add filtering after the FET amp outputs, in which
case, C2D, RD, and C3D are the best locations. The resistor in this
case should not be much larger than 1 kΩ because there is a
bias current that is approximately 35 µA that flows from the
temperature compensation block into each of the VDEN and
VNUM pins. Inserting a resistor, as shown in Figure 48, lifts up
the voltages at the INNM and/or INDN pins and potentially causes
headroom problems in the temperature compensation block.
FROM 1.5V VREF
IMON
VSM1
RMNTR
VNUM
32
30
CMON
2
VSM2
MONITOR AND
PD BIAS
(1.1× INUM )
1.5V
3
Q3
PD
100nA
SHIELD
Q1
INUM
4
IDEN
SHIELD
5
Q2
6
IREF
7
VSM3
1.5V
Figure 49. Adaptive Photodiode Bias
Adding a capacitor, CFB, adds additional filtering at the buffer
output. This capacitor also helps to optimize the pulse response
by placing a zero across the feedback resistor (2.5 kΩ in the
default configuration). A good value to start with is 22 pF, this
introduces a zero at 2.9 MHz that can improve the pulse responses
for input currents above approximately 100 µA.
One example of dual-supply operation is shown in Figure 50, where
the 2.000 V (the 2VLT pin) reference ensures a precisely controlled,
reverse bias across the PD. The user can use other reverse bias
voltages but needs to provide them separately. Note that when the
VSMx pins are grounded, the DCBI and INPS pins must also be
grounded.
8
VSM4
9
VDEN
IMON
Photodiode Bias
VNUM
30
If the adaptive bias is not used, the IMON pin must be connected
to ground. It is easy to provide a 0.5 V reverse bias across the
diode by using the 2VLT reference and connecting it to the
cathode. Because the ADL5304 forces the voltage at INUM very
close to 1.500 V, the trimmed 2.000 V ensures a precise 0.5 V
reverse bias for the PD.
Rev. A | Page 21 of 32
VSM1
FROM 2.0V
VREF
2
32
MONITOR AND
PD BIAS
(1.1× INUM )
VSM2
3
Q3
PD
100nA
SHIELD
Q1
INUM
4
SHIELD
IDEN
5
Q2
6
IREF
7
VSM3
8
VSM4
9
VDEN
09459-150
The ADL5304 provides for adaptive photodiode bias. A
monitoring transistor, Q3, connected in parallel with Q1 (see
Figure 49), samples 1/10th the input current, INUM. This sampled
current is multiplied by a factor of 11 to give an effective output
current at the IMON pin of 1.1 times INUM. Because the photodiode
produces INUM, the additional current has to flow in an external
resistor, RMNTR, equal to 10 × RS, where RS is the value of the
internal parasitic series resistance of the photodiode. This
ensures that the actual junction of the photodiode is biased as
close as possible to 0 V to minimize dark current. The CMON
capacitor provides potential filtering and dynamic currents
during fast transients. The value for best bias response depends
on the photodiode used and should be determined
experimentally. Nominally, CMON = 0.
09459-058
When IDEN is used as the reference, as is normally done, then it
is recommended that C1D is zero, C2D is a 0.1 µF ceramic
decoupling capacitor, RD is a short, and C3D is not placed.
Figure 50. PD Bias with VSUM at Ground and Using 2.000 V
ADL5304
Data Sheet
Reference Outputs
1P5V
The ADL5304 has three trimmed precision references, two
voltages, and one current (IREF). The voltages are 1.500 V and
2.000 V at the 1P5V and 2VLT pins, respectively. The 1P5V
reference is intended to provide the bias to the VSM1 to VSM4,
DCBI, and INPS pins; it can sink up to 10 mA and source a
maximum of about 5 mA.
Buffer Amplifier
A buffer amplifier completes the signal chain that takes the ILOG
current from the temperature compensation block and converts
it to a voltage at the VLOG pin. The buffer amplifier gain and
offset can be configured to provide different logarithmic slope and
intercept at the VLOG output. On-chip resistors provide optimized
scale factors and intercepts via the SCL1, SCL2, and SCL3 pins.
For example, in Figure 51, the default setup provides a scale of
0.2 V/decade and an intercept of 3.162 fA. VOFS = VLOG = 1.5 V
when the internal ILOG = 0 A, which corresponds to INUM = IDEN. ILOG
varies from −400 μA to +400 μA with a scale of 80 μA/decade over
the full 200 dB input current range. In the default configuration,
ILOG is negative for INUM > IDEN and positive for INUM < IDEN. If the
input current is applied to the IDEN pin and the reference current
(IREF) to the INUM pin, the slope of VLOG is negative and the range
is inverted, that is, VLOG is 2.5 V for IDEN = 1 pA, and VLOG is 0.5 V
for IDEN = 10 mA.
27
INPS
1.5V
24
BIAS
23
INMS
22
The 2VLT reference can source up to 20 mA of current, but it
cannot sink any current. The primary use of the 2.0 V reference
is for photodiode bias, or to generate reference currents other
than the 100 nA provided by IREF. Together with a precision resistor,
the 1.5 V and 2.0 V references can reliably generate any current
up to approximately 5 mA.
VLOG
21
TEMPERATURE
COMPENSATION
ILOG
5kΩ
5kΩ
20
7.5kΩ
SCL1
SCL2
19 SCL3
15
ACOM
09459-060
The IREF current, nominally 100 nA, flows out of the IREF pin and
is primarily used as an input to the IDEN pin to provide the
denominator current, IDEN. The choice of 100 nA places it in the
middle of the 1 pA to 10 mA range. IREF can also be used as the
input to the INUM pin and thereby invert the basic log response of
the ADL5304. If IDEN = IREF, VLOG increases with increasing INUM.
Whereas if INUM = IREF and the input current is applied to IDEN,
VLOG decreases with increasing IDEN.
DCBI
26
Figure 51. Buffer Amplifier in Default Configuration
The buffer amplifier is a voltage feedback op amp with supplies
between VPOS and VNEG. For single-supply operation, the
VNEG pin is tied to ground, and the INPS pin, the positive
input of the op amp, to the 1P5V pin.
If a ground referenced input is desired at the INUM or IDEN
pins, then the INPS and DCBI pins together with the VSMx
pins must be tied to ground, and VNEG needs to be less than
−2 V. If larger slopes are required, VPOS can increase to +5 V,
and VNEG can increase to −5 V. For example, if the SCL3 pin is
connected to VLOG, and SCL1 and SCL2 remain open, the
internal 7.5 kΩ resistor, together with the 80 μA/decade ILOG,
provides a slope of 0.6 V/decade at the VLOG pin. Implementation
of slopes of 0.2 V/decade to 0.8 V/decade is easily accomplished.
Setting the Log Slope and Intercept
The choice of optimal slope and intercept depends on the
application and supply voltage(s). For example, when an input
current range of less than the full 200 dB is desired, a higher slope
can be chosen to better use the full voltage span available at
VLOG, and perhaps optimally position it to suit the input capacity
of a subsequent analog-to-digital converter (ADC). Very high
slopes, such as 0.8 V/decade, can be realized, allowing a smaller
range of IPD to be measured at high sensitivity.
Any other intercept and slope can be realized using external
resistors, but these do not, in general, form accurate ratios to
the on-chip resistors. Therefore, some inaccuracies should be
expected. If the SCL1, SCL2, and SCL3 pins are not connected
and a resistor is placed between the INMS and VLOG pins, the
ILOG current is forced through the external resistor and thereby
has a log slope that is 80 μA/decade times REXT; VOFS is equal to
the voltage applied to the INPS pin.
Rev. A | Page 22 of 32
Data Sheet
ADL5304
Table 4. VLOG Scaling Options
Option
Single-Supply Operation (VNEG = 0 V;
VSMx = DCBI = INPS = 1P5V)
11
2
3
4
5
6
7
8
Dual-Supply Operation (VNEG < −2 V;
VSMx = DCBI = INPS = Ground)
92
10
11
12
13
1
2
Pin SCL1
Pin SCL2
Pin SCL3
Pin INPS
Pin INMS
VY (V/dec)
IZ (A)
VOFS (V)
VLOG
VLOG
VLOG
VLOG
VLOG
Open
Open
VLOG
INMS
INMS
INMS
Open
Open
Open
VLOG
INMS
Open
VLOG
Ground
Ground
Open
VLOG
Open
2VLT
1P5V
1P5V
1P5V
1P5V
1P5V
1P5V
1P5V
1P5V
SCL2
SCL2
SCL2
Open
Open
Open
Open
SCL2
0.2
0.15
0.2
0.4
0.4
0.6
0.8
0.2
3.16 f
0.01 f
0.01 f
56.2 f
17.8 p
316 p
1.33 n
21.6 f
1.5
1.5
2.0
2.5
1.5
1.5
1.5
1.333
VLOG
VLOG
VLOG
Open
Open
INMS
INMS
Open
Open
VLOG
Open
VLOG
Open
VLOG
Open
Ground
Ground
Ground
Ground
Ground
SCL2
SCL2
Open
Open
Open
0.2
0.15
0.4
0.6
0.8
100 n
100 n
100 n
100 n
100 n
0
0
0
0
0
Default setup for single supply and VSMx = 1.5 V.
Default setup for dual supply and VSMx = ground.
The default setups are noted in Table 4.
Slope Inversion
Other intercepts are achieved by injecting different currents
into the IDEN pin, for example, if IDEN = 1 μA, as shown in
Figure 52, the VLOG transfer function is simply shifted by one
decade to the right. One way of doing this is to put a precision
500 kΩ resistor between the 2VLT and IDEN pins in the singlesupply default setup. The intercept is moved up to 31.62 fA, and
all output voltages for a given INUM are lowered by one decade,
that is, by 0.2 V at VLOG. For example, the new IDEN = 1 μA, and
VLOG = 1.3 V for INUM = 100 nA.
Table 4 lists only those slopes that are positive because this is the
expected normal operation in measurement mode. The slopes can
be inverted by two methods. By using INUM = IREF = 100 nA, in
which case, the intercepts, IZ, are at larger currents mirrored from
the values shown in Table 4 around the 100 nA reference current.
For example, for the default setup with VY = 0.2 V/decade and
IZ = 3.162 fA, swapping INUM and IDEN connections result in
VY = −0.2 V/decade and IZ = 3.162 A.
This is particularly useful if the slope is already as desired but
the desired intercept cannot be achieved with the on-chip
resistors. Only a shift toward the right makes sense because a
shift to the left requires excessively large resistors.
IMON VNUM
2VLT
17
VSM2
31
1P5V
1.5V
VREF
2
VSM1
3
1.5V
RMNTR
Q3
4
VSM4
TEMP
COMP
5
Q2
SHIELD
ILOG
31
MONITOR AND
PD BIAS
(1.1× INUM )
SHIELD
VNUM
TEMP
COMP
5
Q2
VDEN
6
IREF
7
8
Q3
Q1
INUM
IDEN
VDEN
6
3
4
7
1.5V
VSM3
9
VDEN
10
INDN
09459-061
IREF
VSM3
INNM
32
100nA
VNUM
Q1
INUM
IDEN
VSM2
PD
100nA
SHIELD
VNUM
30
2
PD
SHIELD
IMON
FROM
1.5V VREF
26
Figure 52. Intercept Shifted One Decade Right via External Resistor,
Reference Current IDEN = 1 μA
8
VSM4
9
10
VDEN
Figure 53. Simple Slope Inversion Method
Rev. A | Page 23 of 32
INDN
09459-062
VSM1
INNM
32
MONITOR AND
PD BIAS
(1.1× INUM )
500kΩ
RMNTR
30
The second method is to simply swap the connections between
the VNUM and VDEN pins and the inputs to the temperature
compensation cell (INNM and INDN), as shown in Figure 53
(compare to Figure 52). This technique is particularly useful if
both negative log slope and adaptive photodiode biasing via
IMON are desired together.
ADL5304
Data Sheet
Log Ratio Operation
Because the ADL5304 has two equal inputs, INUM and IDEN, log
ratio operation is possible. The only difference between INUM
and IDEN is that the IMON current derives from the INUM signal and
allows adaptive photodiode bias at this input only. Assuming
that the ratio INUM/IDEN can, in general, be either greater or less
than unity, VLOG can be of either polarity, requiring a negative
supply in some cases. The value of VLOG depends on the
minimum ratio and the slope chosen for the application.
For example, if the ratio can vary from 1:1000 to 1000:1 and a slope
of 20 mV/dB is required, the peak swing is ±1.2 V around VOFS.
Option 5 in Table 4 provides this with an intercept IZ of 17.8 pA
(VOFS = 1.5 V) with VLOG = ±1.2 V around VOFS = 1.5 V, which
results in 0.3 V ≤ VLOG ≤ 2.7 V.
Rev. A | Page 24 of 32
Data Sheet
ADL5304
APPLICATIONS INFORMATION
USING THE ADL5304
Using the Adaptive Bias
The basic connections for single-supply operation are shown in
Figure 55. Supply decoupling is not critical and the suggested values
are conservative; however, it is recommended that a ferrite bead
be placed in the supply lines together with a 0.1 μF decoupling
capacitor. Ferrite beads are preferable to resistors because they do
not produce a dc voltage drop that can affect reference levels. In
Figure 55, the slope is 10 mV/dB or 0.2 V/decade, and the intercept
is 3.162 fA. For the full dynamic range of 200 dB (100 dB optical),
VLOG varies from 0.5 V to 2.5 V (see small diagram at the output
in Figure 55) with VLOG = VOFS = 1.5 V, when INUM = IDEN. Because
the IDEN pin is connected to the IREF pin, IDEN = 100 nA.
Figure 55 also shows the setup for the adaptive photodiode bias.
If this is not desired, ground the IMON pin, remove RMNTR, and
provide the desired bias voltage greater than 1.5 V to the cathode of
the PD. As noted in the Photodiode Bias section, the on-chip 2 V
reference can be used for this purpose and provides an exact 0.5 V
reverse bias together with the 1.5 V that is forced by the FET
amp to the anode via the INUM pin.
The positive bias on the photodiode cathode must be adequate
to support the peak current, which is limited by its internal series
resistance, RS. Typical values of RS are 5 Ω. A model of a representative photodiode (JDSU EPM 605) is shown in Figure 54.
1nH
5nH
2
0.55pF
PD
0.13pF
CASE
0.5pF
1.5nH
Rs
5nH
1
Figure 54. Photodiode Model
It is desirable to use a small bias at very low levels of
illumination to minimize the error due to current leakage
across the diode terminals. The adaptive bias achieves this
automatically even for larger currents through the addition
of the external resistor, RMNTR, that is 10 times RS. In case of
uncertainty in RS, an RMNTR that is slightly greater than 10 times
RS is recommended. In the limit, when RMNTR is not present at
all, the voltage at the IMON pin increases until the current
source saturates and absorbs the excess 10% of current that the
IMON output generates. However, this defeats the purpose of
the adaptive bias; therefore, users must ensure that RMNTR is
present when using the adaptive bias.
1µF
VPOS
FB
0.1µF
0.1µF
0.1µF
4.02Ω
IMPORTANT: ~1mA
BIAS CURRENT FLOWS OUT
OF DCBI. NEEDS TO BE
CONNECTED TO 1P5V.
VNUM INNM
IMON
1P5V
30
2
31
26
BSDC
28
100nA
VPOS DCBI
17
29
27
24
2V
1.5V
MONITOR AND
PD BIAS
(1.1× INUM )
2VLT
BIAS AND
VREF
23
RMNTR
PD
SHIELD
SHIELD
VSM2
1.5V
INUM
IDEN
IREF
22
3
INPS
INMS
VLOG
2.5V
1.5V
0.5V
1p 100n 10m
RLOAD
ADL5304
4
VNUM
21
TEMPERATURE
COMPENSATION
5
6
ILOG
5kΩ
5kΩ
20
VDEN
19 SCL3
18
COMM NMFS
VDEN
0.1µF
9
10
SCL2
7.5kΩ
7
VSM3
1.5V
8
VSM4
1.5V
SCL1
INDN
11
12
VNEG DNFS
13
RNMFS
ACOM HFCP
14
15
RDNFS
16
0.1µF
Figure 55. Basic Connections for Single-Supply Operation
Rev. A | Page 25 of 32
ACOM
09459-064
VSM1
1.5V
32
09459-063
0.5pF
ADL5304
Data Sheet
Summing Node Voltage
It is important to reiterate that the VSM1 to VSM4, DCBI, and
INPS pins always need to be tied together. Failure to do so results
in erroneous outputs at VLOG.
Some pulse response measurement results with an actual photodiode (1A227, 0.8 A/W, 0.7 pF) are shown in Figure 56 and
Figure 57 for the setup in Figure 55.
2.3
The VSMx pins must be well decoupled to provide a good
ac ground.
LASER
LIMIT
2.1
1µA
1.9
100nA
VLOG OUTPUT (V)
Leakage
VSM2 and VSM3 are critical nodes because they are used by the
FET amplifiers to define the voltages on the INUM and IDEN pins.
Furthermore, the voltage applied to VSM2 and VSM3 is also used
to drive the shield around the inputs, which becomes critical at low
currents (<1 nA) to minimize leakage. A voltage difference
between the INUM and VSM2 pins of 1 mV together with a
leakage resistor of 100 MΩ results in a current of 10 pA. If the
current flows into the device, this leakage current limits the
lowest measurable input current.
The VLOG output is somewhat sensitive to loading and does not
like to drive large capacitances or very small resistors, for this
reason, it is recommended to keep CLOAD < 5 pF and RLOAD > 10 kΩ.
Dynamic Response
The ADL5304 does not require input compensation networks to
stabilize the circuit. However, a negative going current can happen
during normal dynamic operation, for example, during current
steps that decreases from larger to smaller values. During a large
step, the input loop can temporarily open causing a transient
invalid VLOG output. Loop recovery time is directly related to the
input current; therefore, the smaller the input current, the longer it
takes for the ADL5304 to recover. Careful design that reduces
parasitic capacitance at the INUM and IDEN inputs helps to
reduce this recovery time; however, this behavior cannot be
eliminated because it is characteristic of translinear log amps.
1nA
1.3
100pA
1.1
10pA
0.5
0
20
40
60
80
100
TIME (µs)
09459-035
0.7
Figure 56. Photodiode Response for Input Currents of Approximately
10 pA to >1 µA Where Laser Limit Encountered
1.3
100pA
10pA
1pA
1.1
0.9
0.7
0.5
0.3
0
2
4
6
TIME (ms)
8
10
09459-034
VLOG Output
10nA
1.5
0.9
VLOG OUTPUT (V)
Even worse, if the current is negative (that is, pulls current out
of the input pin), the input voltage pulls low, and the FET amp
output rails positive. This can happen rather easily when the input
is biased at 1.5 V. For example, a 1 GΩ resistor between the input
pin and ground generates a 1.5 nA current that flows from the
input pin to ground and thereby pulls the input nodes low. A
log amp input is unidirectional, and it can accept current in
only one direction. A current that flows in the wrong direction
breaks the loop that biases the inputs. For this reason, if currents
of less than about 1 nA are to be measured, it is critical that a
guard be used, and that the boards are cleaned of any contaminants
including solder flux. In the case where the leakage is so large
that it cannot be overcome by the input current, the VLOG output
rails to the negative or positive ends of the output range,
depending on whether it is INUM or IDEN that has the leakage.
1.7
Figure 57. Increased Time Scale to Show Measurements Down to INUM
Approximately 1 pA (Approximately 1.25 pW; −89.03 dBm)
USING A NEGATIVE SUPPLY
In most applications of the ADL5304, a single supply is adequate.
A single supply also provides the lowest power operation. Dual
supplies are needed if the user wants to bias the anode of the
photodiode at ground, as was shown in Figure 50.
The negative supply needs to absorb the device bias current, the
load current of the buffer, and the maximum input currents.
With the summing node moved to ground, the ADL5304 can be
used as a voltage-input log amp, using a suitably scaled resistor
from the voltage source to the INUM pin. The logarithmic
accuracy for small voltages is limited by the offset of the JFET
op amp, appearing between this pin and VSUM. The IDEN pin
can likewise be driven from a voltage signal.
When very large input currents (INUM or IDEN greater than
approximately 5 mA) and very low temperatures (−40°C) are
expected, use a negative voltage on VNEG.
Rev. A | Page 26 of 32
AGND
VSUM
0
0
DNI
R41
R40
INUM
VSUM
JOHNSON142-0701-851
IDEN
INUM
IDEN
VSUM
AGND
5432
1
VSUM WILL SHIELD NETS INUM & IDEN
JOHNSON142-0701-851
5432
1
2VLT
SAMTECTSW10608GS3PIN
P3
DNI
0
R14
1
2
3
R34
499
DNI
DNI
AGND
C5
0.1UF
AGND
C1
0.1UF
C10
0
DNI
R1
100PF
DNI
YEL
2VLT
R3
0
DNI
R9
0
VNUM
VSUM
AGND
1
2
3
4
5
6
7
8
0
R12
47PF
DNI
C11
100
R15
49.9
DNI
R4
0
DNI
R5
C2
0.1UF
0
R13
VDEN
NIC
VSM1
VSM2
INUM
IDEN
IREF
VSM3
VSM4
R32
200
24
23
22
21
20
19
18
17
2VLT
SCL1
SCL2
SCL3
INMS
AGND
R18
0
DNI
R19
0
200
R22
C7
0.1UF
VNEG
0.1UF
C6
1K
1K
R35
R36
C8
0.1UF
VNG
200
R39
22PF
C12
GRY
R25
0
1P5V
AGND
C9
0.1UF
AGND
R24
0
1P5V
VSUM
AGND
GEN_QFN32_5X5_PAD3_1X3_1
INPS
INMS
VLOG
SCL1
SCL2
SCL3
ACOM
2VLT
R31
4.02
C3
1UF
BSDC
U1
C4
0.1UF
BSDC
BLU
ADL5304
VNG
E2
PDBS
E1
IMON
BLK
21
PAD
21
VPS
32
31
30
29
28
75 OHMS
27
26
25
VNUM
INNM
IMON
VPOS
BSDC
DCBI
1P5V
NIC
VDEN
INDN
COMM
NMFS
VNEG
DNFS
ACOM
HFCP
Rev. A | Page 27 of 32
9
10
11
12
13
14
15
16
Figure 58. Evaluation Board Schematic
75 OHMS
0
DNI
R26
R27
0
DNI
GND1
BLK
200
R29
R28
TBD0603
DNI
VNEG
1P5V
VLOG
VSUM_
BSDC
2VOLT
VPOS
453
R16
200
R30
GND2
BLK
2VOLT
P1
22-12-2124
DNI
P4
GND3
BLK
2VLT
BLU
GND4
BLK
JOHNSON142-0701-851
VLOG
AGND
AGND
5432
1
VLOG
1
2
1
2
3
4
5
6
7
8
9
10
11
12
826936-2
AGND
RED
AGND
VNEG
VNEGVLOG_VPOS
VIOLET
ORG
EVALUATION BOARD SCHEMATIC AND SILKSCREENS
09459-202
VPOS
Data Sheet
ADL5304
Data Sheet
09459-200
ADL5304
09459-201
Figure 59. Evaluation Board, Primary Side
Figure 60. Evaluation Board, Secondary Side
Rev. A | Page 28 of 32
Data Sheet
ADL5304
OUTLINE DIMENSIONS
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
0.30
0.25
0.18
32
25
24
1
0.50
BSC
PIN 1
INDICATOR
2.85
2.70 SQ
2.55
EXPOSED
PAD
17
8
0.80
0.75
0.70
PKG-004332
SEATING
PLANE
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
9
BOTTOM VIEW
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-2.
08-22-2013-A
TOP VIEW
0.50
0.40
0.30
Figure 61. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-21)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADL5304ACPZ-R2
ADL5304ACPZ-R7
ADL5304ACPZ-RL
ADL5304-EVALZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP], 7” Tape and Reel
32-Lead Lead Frame Chip Scale Package [LFCSP], 13” Tape and Reel
Evaluation Board
Z = RoHS Compliant Part.
Rev. A | Page 29 of 32
Ordering
Quantity
250
1500
5000
Package
Option
CP-32-21
CP-32-21
CP-32-21
ADL5304
Data Sheet
NOTES
Rev. A | Page 30 of 32
Data Sheet
ADL5304
NOTES
Rev. A | Page 31 of 32
ADL5304
Data Sheet
NOTES
©2011–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09459-0-3/16(A)
Rev. A | Page 32 of 32