Evaluation Board User Guide
UG-284
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
ADAU1373 Evaluation Board User Guide
configured as two differential outputs. The headphone output is
stereo true-ground-centered with efficient Class-G architecture.
The efficient stereo filterless Class-D switching amplifier provides around 1 W stereo power for speakers. The differential
receiver amplifier can be used to connect the separate receiver
speaker.
PACKAGE CONTENTS
ADAU1373 evaluation board
5 V ac-to-dc power adapter
Evaluation board user guide
DOCUMENTS NEEDED
ADAU1373 data sheet
AN-1006 Application Note, Using the EVAL-ADUSB2EBZ
GENERAL DESCRIPTION
The ADAU1373 is a low power audio codec that supports stereo
record and playback. It provides eight single-ended or four
differential analog inputs with PGA for adjusting the gain. The
support for two stereo digital microphone inputs is provided so
that, in total, four digital microphones can be connected. In
addition, three serial digital audio in/out ports are provided
with ASRCs to support various sampling rates at the
input/output ports, allowing flexible system design.
The analog output side consists of line outputs, a headphone
output, a speaker output, and a receiver output. The two stereo
single-ended line level outputs are included, which can be
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
The ADAU1373 evaluation board includes the complete
application circuit for the ADAU1373. The board is featured
with USBi connection to the SigmaStudio™ graphical development tool running on a host PC, which is used to program the
ADAU1373.
Included in this user guide is a detailed description for the
ADAU1373 evaluation board. It is recommended that the
ADAU1373 data sheet be read along with this user guide. Full
details about the part are available in the ADAU1373 data sheet,
which provides more detailed information about the specifications, internal block diagrams, and application guidance for the
codec IC.
Rev. 0 | Page 1 of 24
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Evaluation Board User Guide
TABLE OF CONTENTS
Package Contents .............................................................................. 1 Evaluation Board Hardware .............................................................5 Documents Needed .......................................................................... 1 Power Supplies ...............................................................................5 General Description ......................................................................... 1 Digital Audio Interface and Digital Microphone Interface .....7 Revision History ............................................................................... 2 Analog Input and Output .............................................................9 Setting Up the Board—Quick Start ................................................ 3 Clock and Control Port ............................................................. 10 SigmaStudio Software Installation ............................................. 3 Evaluation Board Schematics and Artwork ................................ 11 Hardware Setup, USBi.................................................................. 3 Ordering Information .................................................................... 20 Powering the Board ...................................................................... 3 Bill of Materials ........................................................................... 20 Setting Up the Registers in SigmaStudio ................................... 3 Related Links ................................................................................... 21 REVISION HISTORY
6/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
Evaluation Board User Guide
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SETTING UP THE BOARD—QUICK START
SigmaStudio SOFTWARE INSTALLATION
POWERING THE BOARD
To install the SigmaStudio software, follow these steps:
1.
1.
2.
3.
Open the provided .zip file and extract the files to your PC.
Alternatively, insert the SigmaStudio CD into the PC
optical drive and locate the SigmaStudio folder on the CD.
If Microsoft .NET Framework Version 3.5 is not already
installed on the PC, install it by double-clicking
dotnetfx.exe.
Install SigmaStudio by double-clicking setup.exe and
following the prompts. A computer restart is not required.
3.
SETTING UP THE REGISTERS IN SigmaStudio
The codec is configured with SigmaStudio software. To set up
the registers in SigmaStudio, follow these steps:
HARDWARE SETUP, USBi
To set up the USBi hardware, follow these steps:
Plug the USBi ribbon cable into Header J23.
Connect the USB cable to your computer and to the USBi.
When prompted for drivers, follow these steps:
a) Select Install from a list or a specific location.
b) Select Search for the best driver in these locations.
c) Select the box for Include this location in the search.
The USBi driver is located in C:\Program Files\Analog
Devices Inc\Sigma Studio\USB drivers.
d) Click Next.
e) If prompted to choose a driver, select CyUSB.sys.
f) If the PC is running Windows® XP and you receive the
message that the software has not passed Windows
logo testing, click Continue Anyway.
1.
2.
3.
4.
Create a new project. Select New Project under the File
menu. The Hardware Configuration tab opens.
Click and drag an ADAU1373 cell and a USBi cell into the
blank work area.
Connect the USBi cell to the ADAU1373 cell by clicking
and dragging from the top blue output pin of the USBi cell
to the green input pin of the ADAU1373 cell. The window
should now resemble Figure 1.
In the IC 1 - ADAU1373_REVB_V1.13 tab, configure the
ADAU1373 registers by clicking the intuitive graphic user
interface (GUI) elements in the Input A to Input D,
Analog Input Signal Routing, and Mic Bias Control
sections to set up the proper datapath (see Figure 2).
The SigmaStudio software includes help information. Press the
F1 key to open the help window.
09899-001
1.
2.
3.
2.
Plug the external dc power adapter into J34 to input 5 V dc
power to the board.
Short Jumpers J40, J33, J31, and J32 to select the on-board
LDO-generated voltages that are connected to SPKVDD,
HPVDD, AVDD, and DVDD, respectively.
Set Jumpers J43, J36, J39, J37, and J38 to select the required
voltage (1.8 V, 2.4 V, or 3.3 V) connected to each IOVDDx
(x = 1 to 5).
Figure 1. Hardware Configuration Tab—USBi Connection
Rev. 0 | Page 3 of 24
Evaluation Board User Guide
09899-002
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Figure 2. Hardware Configuration Tab—Register Setup
Rev. 0 | Page 4 of 24
Evaluation Board User Guide
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EVALUATION BOARD HARDWARE
POWER SUPPLIES
IOVDD5
FOR
I2C/SPI
IOVDD2
FOR
DAI B
IOVDD1
FOR
DAI A
SPKVDD
IOVDD4
FOR
DMIC
IOVDD3
FOR
DAI C
HPVDD
5V DC INPUT
AVDD
09899-003
DVDD
Figure 3. Power Supply
The evaluation board requires an external 5 V dc power adapter
plugged into J34. This 5 V dc input drives the on-board LDOs
to generate 1.5 V, 1.8 V, 2.4 V, 3.3 V, or 3.6 V, which feeds into
the ADAU1373 and other on-board circuits. The power
supplies the ADAU1373 requires are listed in Table 1.
Off
Table 1. ADAU1373 Power Supplies
Power Supply
AVDD
HPVDD
SPKVDD
DVDD
IOVDD1 to IOVDD5
LDO Voltage
1.8 V
1.8 V
3.6 V
1.5 V
1.8 V, 2.4 V, or 3.3 V
Function
On-board LDO-generated 1.8 V connected to
HPVDD
External power supply connected to Test Pin HPVDD
and Test Pin GND
J32 is for DVDD power supply selection. The selection options
are shown in Table 4.
Table 4. J32
If voltages other than the default LDO output are needed, external
power supplies can be used for this purpose. Each power supply
for the ADAU1373 has a set of jumpers to select the LDO
output or external power supply.
J31 is for AVDD power supply selection. The selection options
are shown in Table 2.
Table 2. J31
Jumper
Position
On
Off
Table 3. J33
Jumper
Position
On
Function
On-board LDO-generated 1.8 V connected to AVDD
External power supply connected to Test Pin AVDD
and Test Pin GND
J33 is for HPVDD power supply selection. The selection table is
shown in Table 3.
Jumper
Position
On
Off
Function
On-board LDO-generated 1.5 V connected to DVDD
External power supply connected to Test Pin DVDD
and Test Pin GND
J40 is for SPKVDD power supply selection. The selection
options are shown in Table 5.
Table 5. J40
Jumper
Position
On
Off
Function
On-board LDO-generated 3.6 V connected to
SPKVDD
External power supply connected to SPKVDD: J41
for SPKVDD and J42 for GND
J43 is for IOVDD1 power supply selection, which powers
Digital Audio Interface A. The selection options are shown in
Table 6.
Rev. 0 | Page 5 of 24
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Evaluation Board User Guide
Table 6. J43
Jumper
Position1
1-2
3-4
5-6
Off
1
J37 is for IOVDD4 power supply selection, which powers the
digital microphone interface. The selection options are shown
in Table 9.
Function
On-board LDO-generated 1.8 V connected to
IOVDD1
On-board LDO-generated 3.3 V connected to
IOVDD1
On-board LDO-generated 2.4 V connected to
IOVDD1
External power supply connected to
Test Pin IOVDD1 and Test Pin GND
Table 9. J37
Jumper
Position1
1-2
3-4
5-6
Jumper Position x-y means Pin x and Pin y are connected together via a
jumper capacitor.
J36 is for IOVDD2 power supply selection, which powers digital
Audio Interface B. The selection options are shown in Table 7.
Off
1
Table 7. J36
Jumper
Position1
1-2
3-4
5-6
Off
1
Table 10. J38
Jumper
Position1
1-2
3-4
5-6
Jumper Position x-y means Pin x and Pin y are connected together via a
jumper capacitor.
J39 is for IOVDD3 power supply selection, which powers digital
Audio Interface C. The selection options are shown in Table 8.
Off
1
Jumper
Position1
1-2
3-4
5-6
Off
1
Jumper Position x-y means Pin x and Pin y are connected together via a
jumper capacitor.
J38 is for IOVDD5 power supply selection, which powers the
I2C/SPI port. The selection options are shown in Table 10.
Function
On-board LDO-generated 1.8 V connected to
IOVDD2
On-board LDO-generated 3.3 V connected to
IOVDD2
On-board LDO-generated 2.4 V connected to
IOVDD2
External power supply connected to
Test Pin IOVDD2 and Test Pin GND
Table 8. J39
Function
On-board LDO-generated 1.8 V connected to
IOVDD4
On-board LDO-generated 3.3 V connected to
IOVDD4
On-board LDO-generated 2.4 V connected to
IOVDD4
External power supply connected to
Test Pin IOVDD4 and Test Pin GND
Function
On-board LDO-generated 1.8 V connected to
IOVDD5
On-board LDO-generated 3.3 V connected to
IOVDD5
On-board LDO-generated 2.4 V connected to
IOVDD5
External power supply connected to
Test Pin IOVDD5 and Test Pin GND
Jumper Position x-y means Pin x and Pin y are connected together via a
jumper capacitor.
Function
On-board LDO-generated 1.8 V connected to
IOVDD3
On-board LDO-generated 3.3 V connected to
IOVDD3
On-board LDO-generated 2.4 V connected to
IOVDD3
External power supply connected to
Test Pin IOVDD3 and Test Pin GND
Jumper Position x-y means Pin x and Pin y are connected together via a
jumper capacitor.
Rev. 0 | Page 6 of 24
Evaluation Board User Guide
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DIGITAL AUDIO INTERFACE AND DIGITAL MICROPHONE INTERFACE
DIGITAL AUDIO
INTERFACE A
DIGITAL MIC
INTERFACE 1
DIGITAL AUDIO
INTERFACE B
DIGITAL AUDIO
INTERFACE C
09899-004
DIGITAL MIC
INTERFACE 2
Figure 4. Digital Audio Interface and Digital Microphone Interface
1
The evaluation board provides three digital audio interfaces
(J28 to J30) and two digital microphone interfaces (J44/J45
and J46/J47).
The pin definitions for J28, J29, and J30 are shown in Figure 5,
Figure 6, and Figure 7, respectively.
2 NC
GND 3
4 GPIO3
GND 5
6 C_BCLK
GND 7
8 C_LRC
2 MCLK1
GND 9
10 C_DACDAT
GND 3
4 GPIO1
GND 11
12 C_ADCDAT
GND 5
6 A_BCLK
GND 7
8 A_LRC
GND 9
10 A_DACDAT
GND 11
12 A_ADCDAT
NC = NO CONNECT. DO NOT
CONNECT TO THIS PIN.
Figure 7. Pin Definitions for J30
The pin definitions for J44 are listed in Table 11.
GND 3
4 GPIO2
GND 5
6 B_BCLK
GND 7
8 B_LRC
GND 9
10 B_DACDAT
GND 11
12 B_ADCDAT
09899-017
2
2 MCLK2
Table 11. J44
Pin No.
1
2
3
4
5
6
Figure 5. Pin Definitions for J28
GND 1
09899-018
GND 1
1
GND 1
2
09899-016
1
2
Figure 6. Pin Definitions for J29
Rev. 0 | Page 7 of 24
Signal
IOVDD4
DMIC_DATA1
LR_SEL (high)
NC
DMIC_CLK
GND
UG-284
Evaluation Board User Guide
The pin definitions for J45 are listed in Table 12.
The pin definitions for J47 are listed in Table 14.
Table 12. J45
Table 14. J47
Pin No.
1
2
3
4
5
6
Signal
IOVDD4
DMIC_DATA1
LR_SEL (low)
NC
DMIC_CLK
GND
Pin No.
1
2
3
4
5
6
The pin definitions for J46 are listed in Table 13.
Table 13. J46
Pin No.
1
2
3
4
5
6
Signal
IOVDD4
DMIC_DATA1
LR_SEL (high)
NC
DMIC_CLK
GND
Rev. 0 | Page 8 of 24
Signal
IOVDD4
DMIC_DATA1
LR_SEL (low)
NC
DMIC_CLK
GND
Evaluation Board User Guide
UG-284
ANALOG INPUT AND OUTPUT
ANALOG
INPUT 4
ANALOG
INPUT 3
ANALOG
INPUT 2
ANALOG
INPUT 1
EARPIECE
OUTPUT
ANALOG
OUTPUT 1
ANALOG
OUTPUT 2
HEADPHONE
OUTPUT
09899-005
SPEAKER
OUTPUT
Figure 8. Analog Input and Output Interface
On the board, there are four analog inputs (J4, J5, J8, and J9).
Near each input, there is a three-way jumper that selects which
bias voltage is routed to this input pair. These jumpers are J2, J3,
J6, and J7. The configurations are shown in Figure 9, and the
definitions of these jumper configurations are listed in Table 15,
Table 16, Table 17, and Table 18, respectively.
MICB2
MICB1
MICB1
POSITION A
POSITION B
Table 15. J2
Table 18. J7
Function
Microphone Bias 1 connected to Analog Input 1
Microphone Bias 2 connected to Analog Input 1
Table 16. J3
Position
A
B
Function
Microphone Bias 1 connected to Analog Input 3
Microphone Bias 2 connected to Analog Input 3
Function
Microphone Bias 1 connected to Analog Input 4
Microphone Bias 2 connected to Analog Input 4
On the board, there are two analog outputs (J10 and J11),
one earpiece output for mono differential signals (J18), one
headphone output (J12), and two pairs of speaker outputs
(J13/J14 and J15/J16).
Figure 9. Configuration for Jumpers J2, J3, J6, and J7
Position
A
B
Position
A
B
Position
A
B
09899-019
MICB2
Table 17. J6
Function
Microphone Bias 1 connected to Analog Input 2
Microphone Bias 2 connected to Analog Input 2
Rev. 0 | Page 9 of 24
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Evaluation Board User Guide
CLOCK AND CONTROL PORT
EXTERNAL I2C
EXTERNAL
ADAPTER
CLOCK
RESET CONNECTOR
IMPUT
I2C ADDRESS
SELECTION
I2C/SPI
SELECTION
MCLK2
SELECTION
JUMPER
09899-006
MCLK1
SELECTION
JUMPER
Figure 10. Clock and Control Port
There are two master clock input pins for the ADAU1373:
MCLK1 and MCLK2. For each master clock, there are three
clock sources that can be selected by Jumper 21 and Jumper 22.
POSITION A
OSC SMA1 PSIA
Table 20. J22
OSC SMA1 PSIA
1
1
1
2
2
2
POSITION B
POSITION C
09899-023
OSC SMA1 PSIA
J22 is for MCLK2 selection. The position definitions are shown
in Figure 11 and Table 20.
Figure 11. Configuration for Jumpers 21 and 22
J21 is for MCLK1 selection. The position definitions are shown
Figure 11 and Table 19.
Jumper
Position
A
B
C
Function
Use an on-board 12.288 MHz oscillator as MCLK2.
Use an external SMA clock input as MCLK2.
Use an audio precision PSIA MCLK input connected
to J29 as MCLK2.
Table 19. J21
J23 is for the external I2C/SPI controller (USBi board) connection. J24 selects the control port mode of the ADAU1373. The
position definitions of this jumper are shown in Table 21.
Jumper
Position
A
B
C
Jumper Position
On
Off
Function
Use an on-board 12.288 MHz oscillator as MCLK1.
Use an external SMA clock input as MCLK1.
Use an audio precision PSIA MCLK input connected
to J28 as MCLK1.
Table 21. J24
Function
I2C mode
SPI mode
J25 selects the I2C device address of the ADAU1373. The
position definitions of this jumper are shown in Table 22.
Table 22. J25
Jumper Position
On
Off
Rev. 0 | Page 10 of 24
Function
I2C devices address = 0x1C.
I2C devices address = 0x1A.
LHP
RHP
SGND
BSTEN
VBAT
RSPKP
RSPKN
LSPKP
LSPKN
EPP
EPN
ROUTP
ROUTN
INFB2
LOUTP
LOUTN
INFB1
MICB1
MICB2
AIN4P
AIN4N
AIN3P
AIN3N
AIN2P
AIN2N
AIN1P
AIN1N
C8
C9
C7
D8
E7
D7
D9
E8
H6
J6
J4
J3
J2
H1
G4
F9
G8
G9
G7
MICB1
MICB2
LOUTP
LOUTN
INFB1
ROUTP
ROUTN
INFB2
EPP
EPN
LSPKP
LSPKN
RSPKP
RSPKN
BSTEN
VBAT
LHP
RHP
SGND
GND
B5
A5
AIN4P
AIN4N
C17
1uf
B9
B6
A6
B7
A7
AIN2P
AIN2N
AIN3P
AIN3N
B8
A8
AIN1P
AIN1N
VMID
LHP
RHP
SGND
BSTEN
VBATSENSE
RSPKP
RSPKN
LSPKP
LSPKN
EPP
EPN
ROUTP
ROUTN
INFB2
LOUTP
LOUTN
INFB1
MICB1
MICB2
AIN4P
AIN4N
AIN3P
AIN3N
AIN2P
AIN2N
AIN1P
AIN1N
U1
GND
SW1
ADAU1373_WLCSP
SDB
IOVDD3
GPIO3
C_BCLK
C_LRC
C_ADCDAT
C_DACDAT
SDB
JACKDECT
E1
F5
F2
F1
G3
F3
G6
G5
0.1uF
0.1uF
R2
100K
IOVDD5
IOVDD2
MCLK2
GPIO2
B_BCLK
B_LRC
B_ADCDAT
B_DACDAT
F4
D1
E6
E4
E2
E3
F6
C1
C2
D6
D2
D3
D4
D5
IOVDD1
MCLK1
GPIO1
A_BCLK
A_LRC
A_ADCDAT
A_DACDAT
IOVDD4
DMICCLK
DMIC1
DMIC2
IOVDD5
MODE
CSB
SCL
SDA
GPIO4
C19
JACKDECT
SDB
IOVDD3
GPIO3
C_BCLK
C_LRC
C_ADCDAT
C_DACDAT
IOVDD2
MCLK2
GPIO2
B_BCLK
B_LRC
B_ADCDAT
B_DACDAT
IOVDD1
MCLK1
GPIO1
A_BCLK
A_LRC
A_ADCDAT
A_DACDAT
A3
A4
B4
C6
B3
A2
B2
C5
C3
C4
C18
GND
R1
100K
IOVDD5
MODE
CSB
SCL
SDA
GPIO4
IOVDD4
DMICCLK
DMIC1
DMIC2
DVDD
IOVDD5
A9
E9
AVDD1
AVDD2
DGND1
DGND2
A1
E5
AVDD
G1
G2
H2
H3
AGND1
AGND2
SPKVDD1
SPKVDD2
SPKVDD3
SPKVDD4
HPGND
J8
H8
2
F7
F8
CPVSS
H7
CPVSS
HPVDD
CPVSS
CPVDD
H9
CPVDD
CPVDD
J9
CF1
1
SPKVDD
CF1
CF1
J7
CF2
SPKGND1
SPKGND2
SPKGND3
SPKGND4
H4
H5
J1
J5
4
HPVDD
CF2
CF2
B1
DVDD
3
Figure 12. Schematic of the ADAU1373 Evaluation Board, ADAU1373 Chip
2
GND
1
Rev. 0 | Page 11 of 24
J1
JACKDECT
JACKDECT
SDB
GPIO3
C_BCLK
C_LRC
C_ADCDAT
C_DACDAT
MCLK2
GPIO2
B_BCLK
B_LRC
B_ADCDAT
B_DACDAT
MCLK1
GPIO1
A_BCLK
A_LRC
A_ADCDAT
A_DACDAT
DMICCLK
DMIC1
DMIC2
MODE
CSB
SCL
SDA
GPIO4
CPVDD
CPVSS
CF2
CF1
GND
GND
C15
2.2uF
C8
2.2uF
C4
2.2uF
GND
C12
0.1uf
SPKVDD
GND
C9
0.1uf
DVDD
GND
C7
0.1uf
HPVDD
GND
C2
0.1uf
C13
10uf
C10
2.2uf
C5
2.2uf
C3
2.2uf
GND
C16
0.1uf
IOVDD5
GND
C14
0.1uf
IOVDD4
GND
C11
0.1uf
IOVDD3
GND
C6
0.1uf
IOVDD2
GND
C1
0.1uf
IOVDD1
09899-007
AVDD
Evaluation Board User Guide
UG-284
EVALUATION BOARD SCHEMATICS AND ARTWORK
Figure 13. Schematic of the ADAU1373 Evaluation Board—Line Input
AUDIOJACK
J8
AUDIOJACK
J4
3
1
2
3
1
2
GND
GND
R98
NC
TP67
1
TP65
1
R96
NC
TP61
1
TP59
1
1
0R
TP63
TP69
J6
R11
0R
R9
0R
R7
0R
R5
J2
1
1
1
3
GND
1
GND
3
GND
1
GND
C35
220p F, NC
C31
220p F, NC
MB2
MB1
C27
220p F, NC
C23
220p F, NC
MB2
MB1
1uF
C34
1uF
C30
1uF
C26
1uF
C22
2K2
R4
2K2
R3
AIN3N
AIN3P
AIN1N
AIN1P
C21
0.1uF
C20
0.1uF
GND
TP57
TP58
1
AIN3N
AIN3P
AIN1N
AIN1P
1
2
2
2
2
3
3
MICB2
MICB1
AUDIOJACK
J9
AUDIOJACK
J5
3
1
2
3
1
2
GND
GND
R99
NC
1
TP68
1
TP66
R97
NC
1
TP62
1
TP60
0R
TP70
J7
R12
0R
2
TP64
J3
R10
0R
R8
0R
R6
1
1
1
1
2
2
2
3
GND
1
GND
3
3
GND
1
GND
3
Rev. 0 | Page 12 of 24
C37
220p F, NC
C33
220p F, NC
MB2
MB1
C29
220p F, NC
C25
220p F, NC
MB2
MB1
1uF
C36
1uF
C32
1uF
C28
1uF
C24
AIN4N
AIN4P
AIN2N
AIN2P
AIN4N
AIN4P
AIN2N
AIN2P
09899-008
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Evaluation Board User Guide
SGND
RHP
LHP
INFB2
ROUTN
Figure 14. Schematic of the ADAU1373 Evaluation Board—Line and Headphone Output
TP77
TP78
TP79
GND
R25
0R,NC
SGND
RHP
LHP
INFB2
ROUTN
R23
0R
R21
0R
R19
2.2uF
C42
1uF
C40
0R
R15
100K, NC
R20
NC
GND
R13
100K, NC
C44
NC
TP73
1
1uF
1
TP71
GND
0R
R22
NC
J10
TP75
AUDIOJACK
R17
3
1
2
C45
NC
GND
1
INFB1
ROUTP
LOUTP
J12
0R
TP80
AUDIOJACK
R24
3
1
2
INFB1
ROUTP
LOUTP
GND
2.2uF
C43
1uF
C41
1uF
C39
GND
R14
100K, NC
TP72
TP74
1
R16
100K, NC
1
LOUTN
1
1
1
Rev. 0 | Page 13 of 24
1
J11
0R
TP76
AUDIOJACK
R18
3
1
2
GND
1
C38
09899-009
LOUTN
Evaluation Board User Guide
UG-284
Figure 15. Schematic of the ADAU1373 Evaluation Board—Speaker and Receiver Output
LSPKN
LSPKP
TP81
TP83
1
1
EPN
EPP
LSPKN
LSPKP
NC
NC
R33
R32
C52
1
R29
0R
L3
TP56
0R
L1
NC
NC
TP89
GND
0R
0R
C50
1nF, NC
C48
1nF, NC
GND
GND
TP87
TP88
1
1
J15
J13
J18
RSPKN
RSPKP
TP82
TP84
1
1
RSPKN
R28
NC
RSPKP
NC
GND
BSTEN
J19
BSTEN
TP86
VBAT
VBAT
GND
GND
GND
2.2uH
C51
1nF, NC
C49
1nF, NC
L5
SPKVDD
R31
100K
NC
R30
0R
L4
0R
C53
NC
NC
L2
C47
R27
TP85
1
GND
1
1
1
GND
1
2
C54
10uf
J16
J14
1
1
2
2
C46
J17
09899-010
R26
1
1
2
1
1
2
Rev. 0 | Page 14 of 24
1
UG-284
Evaluation Board User Guide
Figure 16. Schematic of the ADAU1373 Evaluation Board—Clock
SMA
R38
100K
GND
C58
0.1uf
1
4
OE
VDD
U3
600Z
L6
GND
12.288MHz
GND
OUT
3V3
R36
NC
2
3
GND
0R
PSIA_MCLK2
PSIA_MCLK1
4
6
3
5
6
5
2
4
3
1
2
1
J22
J21
112896M_CLK
SMA_CLK
PSIA_MCLK2
112896M_CLK
SMA_CLK
PSIA_MCLK1
A
3V3
A
3V3
1
GND
FXLP34P5X
2
U4
1
GND
FXLP34P5X
2
U2
5
VCC
R35
1
VCCI
1
VCCI
1
2
3
4
5
TP93
Y
0R
0R
4 R39
IOVDD2
TP91
Y
4 R37
IOVDD1
MCLK2
MCLK1
TP92
TP90
1
R34
NC
MCLK2
MCLK1
GND
3V3
C55
0.1uf
GND
C56
0.1uf
IOVDD1
GND
C57
0.1uf
IOVDD2
09899-011
J20
VCC
GND
3
5
GND
3
Rev. 0 | Page 15 of 24
1
3V3
Evaluation Board User Guide
UG-284
R42
NC
10 10
DMICCLK
DMIC1
9
8
GND
7
6
8
5
3
6
4
4
1
TP98
0R
R52
9
7
5
3
1
TP100
R50
R48
NC
100K
GND
DMCLK
DMIC1
IOVDD4
R43
NC
2
6
5
4
3
2
1
J25
CON1x6
6
5
4
3
2
1
J44
1
GND
6
5
4
3
2
1
6
5
4
3
2
1
J45
CON1x6
R44
NC
D
S
0R
2
IOVDD5
D
S
2
DMIC2
0R R106
N-MOSFET
3
Q3, NC
3
R51
R45
2K2
GND
100K
IOVDD4
R41
2K2
IOVDD5
DMCLK
DMIC2
R49
2K2
TP99
R104
2
D
S
N-MOSFET
0R R105
Q2, NC
IOVDD5
N-MOSFET
3
1
Q1, NC
G
1
1
2
R40
NC
G
G
6
5
4
3
2
1
TP94
TP95
1
TP97
1
CON1x6
6
5
4
3
2
1
J46
1
6
5
4
3
2
1
J47
CON1x6
6
5
4
3
2
1
CSB
SDA
SCL
GND
J24
R46
100K
IOVDD5
2
1
IOVDD5
MODE
MODE
GPIO4
IOVDD5
GPIO4
R47
TP96 100K
1
2
1
3V3
09899-012
J23
1
Rev. 0 | Page 16 of 24
1
UG-284
Evaluation Board User Guide
Figure 17. Schematic of the ADAU1373 Evaluation Board—I2C Port and Digital Microphone Interface
GND
8
10
12
7
9
11
6
12
11
5
10
9
4
8
7
2
6
5
3
4
3
1
J30
GND
2
1
J28
C_ADCDAT_J
49R9
R75
R79
0R
R81
49R9
R80
49R9
0R
C_LRC_J
0R
R76
0R
R74
0R
R71
R78
49R9
R77
C_BCLK_J
A_ADCDAT_J
49R9
R69
49R9
R67
A_LRC_J
49R9
R63
A_BCLK_J
49R9
R59
0R
R65
0R
R61
0R
GND
A_LRC
C_BCLK
GND
GPIO3
22pF
GND
C_LRC
C70
22pF
GND
C_ADCDAT
C72
GND
C_DACDAT
22pF
C71
GND
A_BCLK
TP103
TP105
TP107
TP109
TP114
TP115
TP120
TP121
IOVDD1
C_ADCDAT
C_DACDAT
C_LRC
C_BCLK
GPIO3
IOVDD3
A_ADCDAT
A_DACDAT
A_LRC
A_BCLK
GPIO1
R55 100K
R73 100K
TP111
TP113
GND
A_ADCDAT
22pF
C69
22pF
C67
GND
GPIO1
GND
A_DACDAT
22pF
C65
22pF
C63
22pF
C61
22pF
R57
C59
1
1
1
1
1
1
49R9
1
R53
GND
6
5
11
9
12
10
8
4
3
7
2
1
J29
GND
TP119
TP118
22pF
C68
TP117
0R
R72
49R9
0R
R66
0R
R62
0R
R58
22pF
C60
TP116
B_ADCDAT_J
R70
49R9
R68
B_LRC_J
49R9
R64
B_BCLK_J
49R9
R60
49R9
R54
1
PSIA_MCLK1
1
1
1
1
Figure 18. Schematic of the ADAU1373 Evaluation Board—Digital Audio Interface
1
1
Rev. 0 | Page 17 of 24
1
GND
B_LRC
B_BCLK
GND
GPIO2
GND
B_ADCDAT
22pF
GND
B_DACDAT
C66
22pF
C64
22pF
C62
GND
PSIA_MCLK2
TP102
TP104
1
TP106
1
TP108
1
TP110
1
TP112
1
1
TP101
IOVDD2
B_ADCDAT
B_DACDAT
B_LRC
B_BCLK
GPIO2
R56 100K
PSIA_MCLK2
09899-013
PSIA_MCLK1
Evaluation Board User Guide
UG-284
5
6
7
8
5
6
7
8
U5
ADP1715_1V8
GND0 EN
GND1
IN
GND2 OUT
GND3 ADJ
U7
ADP1715_1V8
1
2
3
4
1
2
3
4
10nF
C83
10nF
C73
0.1uF
C81
0.1uF
C74
5V
GND
10uf
C82
2
J33
GND
10uf
C75
2
J31
1
1K
R86
1
1K
Q6
MMBT3904
1
R87
10K
GREEN
D3
Q4
MMBT3904
1
R84
10K
GREEN
D1
HPVDD
AVDD
TP124
Figure 19. Schematic of the ADAU1373 Evaluation Board—Power Supply
1
TP127
0.1uf
C84
TP126
1
0.1uf
C76
TP122
5
6
7
8
U6
3
2
1
1
2
3
4
PowerJack
J34
ADP1715_1V5
GND0 EN
GND1
IN
GND2 OUT
GND3 ADJ
10nF
C79
J35
0.1uF
C77
5V
600Z
L7
GND
10uf
C78
2
J32
1
GND
C96
1nF
1K
R83
5V
Q5
MMBT3904
1
R85
10K
GREEN
D2
DVDD
1
TP125
0.1uf
C80
TP123
1
R82
3
2
GND0 EN
IN
GND1
GND2 OUT
GND3 ADJ
5V
09899-014
3
2
3
2
1
1
Rev. 0 | Page 18 of 24
2
1
UG-284
Evaluation Board User Guide
2V4
C94
10uf
0.1uF
5V
CON2x3
5
3
1
J43
C93
3V3
1V8
ADP1715_3V3
6
4
2
1
2
3
4
1
2
3
4
0.1uF
C87
GND
ADP1708
8
7
6
5
TP137
EN
ADJ
GND SENSE
IN1
OUT1
IN2
OUT2
U11
GND
1
TP132 IOVDD1
10nF
C85
1
3V3
R95
1k
3.48K
R93
2V4
10uf
C88
1
J40
1K
2
R92
6
4
2
TP133
GND
1
D6
GND
1
Q9
MMBT3904
1
R94
10K
TP136
IOVDD2
2V4
10uf
C95
SPKVDD
TP128
1
TP130
3V3
GREEN
1
Q7
MMBT3904
R90
10K
GREEN
CON2x3
5
3
1
J36
10uf
C86
1V8
1K
3
2
1
GND0 EN
GND1
IN
GND2 OUT
GND3 ADJ
1
1
CON2x3
6
4
3
5
2
1
J39
TP145
TP143
3V3
1V8
J41
J42
U9
GND
1
TP139
5
6
7
8
ADP1715_1V8
GND0 EN
GND1
IN
GND2 OUT
GND3 ADJ
TP134 IOVDD3
5
6
7
8
1
2V4
ADP1715_ADJ
6
5
R102
1K
CON2x3
4
2
10uf
C92
3
1
J37
0.1uF
C89
1
2
3
4
1V8
U10
3V3
10nF
C90
GND0 EN
GND1
IN
GND2 OUT
GND3 ADJ
1
2
3
4
5V
R103
2K
5V
GND
1
TP135
1K
C98
10uf
0.1uF
1
10uf
C97
R100
3V3
1V8
1V8
GND
1K
2V4
1
Q8
MMBT3904
R91
10K
GREEN
D5
C100
TP140
IOVDD4
10uf
C91
R89
3
2
5
6
7
8
PAD
9
1
TP129
6
5
Q10
MMBT3904
1
R101
10K
GREEN
D7
CON2x3
4
2
3
1
J38
TP131
1
D4
3
2
GND
1
TP142
TP141
IOVDD5
TP144
2V4
GND
1
TP138
1
R88
1
5V
3
2
Figure 20. Schematic of the ADAU1373 Evaluation Board—Power Supply
1
1
Rev. 0 | Page 19 of 24
09899-015
U8
Evaluation Board User Guide
UG-284
UG-284
Evaluation Board User Guide
ORDERING INFORMATION
BILL OF MATERIALS
Table 23.
Qty
9
3
13
1
12
21
3
6
4
8
14
5
7
8
7
6
3
4
1
7
1
3
1
4
4
1
2
3
7
11
33
9
7
1
4
18
1
5
2
Part Reference
C1, C11, C12, C14, C16, C2, C6, C7, C9
C10, C3, C5,
C13, C54, C75, C78, C82, C86, C88, C91, C92,
C94, C95, C97, C98
C17
C22, C24, C26, C28, C30, C32, C34, C36, C38,
C39, C40, C41
C18, C19, C20, C21, C42, C43, C55, C56, C57,
C58, C74, C76, C77, C80, C81, C84, C87, C89,
C93, C96, C100
C4, C8, C15
C44, C45, C46, C47, C52, C53
C48, C49, C50, C51
C23, C25, C27, C29, C31, C33, C35, C37
C59, C60, C61, C62, C63, C64, C65, C66, C67,
C68, C69, C70, C71, C72
C73, C79, C83, C85, C90
D1, D2, D3, D4, D5, D6, D7,
J1, J19, J24, J25, J31, J32, J33, J40
J10, J11, J12, J4, J5, J8, J9
J13, J14, J15, J16, J41, J42
J17, J18, J35
J2, J3, J6, J7
J20
J21, J22, J36, J37, J38, J39, J43
J23
J28, J29, J30
J34
J44, J45, J46, J47
L1, L2, L3, L4
L5
L6, L7
Q1, Q2, Q3
Q10, Q4, Q5, Q6, Q7, Q8, Q9
R1, R2, R31, R38, R46, R47, R50, R51, R55, R56,
R73
R10, R104, R105, R106, R11, R12, R17, R18,
R19, R21, R23, R24, R35, R37, R39, R5, R52,
R57, R58, R6, R61, R62, R65, R66, R7, R71, R72,
R74, R76, R78, R8, R81, R9
R100, R102, R82, R83, R86, R88, R89, R92, R95
R101, R84, R85, R87, R90, R91, R94
R103
R13, R14, R15, R16
R20, R22, R26, R27, R28, R29, R30, R34, R36,
R40, R42, R43, R44, R48, R96, R97, R98, R99
R25
R3, R4, R41, R45, R49
R32, R33
Description
MLCC, 0.1 μF, 0402
MLCC, 2.2 μF, 0603
MLCC, 10 μF, 0805
Manufacturer
Panasonic
Panasonic
Panasonic
Part Number
ECJ-0EX1C104K
ECJ-1VB1A225K
ECJ-2FF1A106Z
MLCC, 1 μF, 0402
MLCC, 1 μF, 0603
Panasonic
Panasonic
ECJ-0EB1A105M
ECJ-1VB1A105K
MLCC, 0.1 μF, 0603
Panasonic
ECJ-1VB1H104K
MLCC, 2.2 μF, 0402
Capacitor (open)
Capacitor (open)
Capacitor (open)
Capacitor (open)
Panasonic
ECJ-0EB0J225M
MLCC, 10 nF, 0603
LED, green
Jumper, 2 mm pitch
Stereo audio jack
Binding post connector
Jumper, 2.54 mm pitch
Header, 3-way (1 × 3)
SMA header
Header, 6-way (2 × 3)
Header, 10-way (2 × 5), polarized
Header, 12-way (2 × 6)
Power jack
Header, 6-way (1 × 6)
Chip resistor, 0 Ω, 0805
Inductor (open)
Chip ferrite bead, 600 Ω at 100 MHz
N-MOSFET (open)
Transistor, NPN, SOT23
Panasonic
Lumex
ECJ-1VB1H103K
SML-LXT0805GW-TR
CUI
Johnson/Emerson
SJ-3523-SMT
111-2223-001
MULTICOMP
60-04 TGG
Switchcraft Inc.
RAPC712
Panasonic
ERJ-6GEY0R00V
TDK
MPZ1608S601A
MMBT3904LT1G
Chip resistor, 100 kΩ, 0603
ON
Semiconductor
Panasonic
Chip resistor, 0 Ω, 0603
Panasonic
ERJ-3GEY0R00V
Chip resistor, 1 kΩ, 0603
Chip resistor, 10 kΩ, 0603
Chip resistor, 2 kΩ, 0603
Chip resistor (open)
Chip resistor (open)
Panasonic
Panasonic
Panasonic
ERJ-3EKF1001V
ERJ-3EKF1002V
ERJ-3EKF2001V
Panasonic
Panasonic
ERJ-3EKF2201V
ERJ-6GEY0R00V
Chip resistor (open)
Chip resistor, 2.2 kΩ, 0603
Chip resistor, 0 Ω, 0805
Rev. 0 | Page 20 of 24
ERJ-3EKF1003V
Evaluation Board User Guide
Qty
14
1
1
1
1
1
2
1
3
1
1
Part Reference
R53, R54, R59, R60, R63, R64, R67, R68, R69,
R70, R75, R77, R79, R80,
R93
SW1
U1
U10
U11
U2, U4
U3
U5, U7, U9
U6
U8
UG-284
Description
Chip resistor (open)
Manufacturer
Part Number
3.48 kΩ
Push-button
ADAU1373
Low dropout voltage regulator
Low dropout voltage regulator
Translator, 1-bit, unidirectional
Oscillator, 12.288 MHz
Low dropout voltage regulator
Low dropout voltage regulator
Low dropout voltage regulator
Panasonic
ERJ-3EKF3481V
ADI
ADI
ADI
Fairchild
Abracon
ADI
ADI
ADI
ADP1715_ADJ
ADP1708
FXLP34P5X
ASFL1-12.288MHZ-EC-T
ADP1715_1V8
ADP1715_1V5
ADP1715_3V3
RELATED LINKS
Resource
ADAU1373
AN-1006
ADP1715
ADP1708
Description
Product Page, Low Power Codec with Speaker and Headphone Amplifier
Application Note, Using the EVAL-ADUSB2EBZ
Product Page, 500 mA Low-Dropout CMOS Linear Regulator with Soft Start
Product Page, 1 A, Low Dropout, CMOS Linear Regulator
Rev. 0 | Page 21 of 24
UG-284
Evaluation Board User Guide
NOTES
Rev. 0 | Page 22 of 24
Evaluation Board User Guide
UG-284
NOTES
Rev. 0 | Page 23 of 24
UG-284
Evaluation Board User Guide
NOTES
ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
Legal Terms and Conditions
By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions
set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you
have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc.
(“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal,
temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided
for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional
limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term
“Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including
ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may
not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to
promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any
occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board.
Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice
to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO
WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED
TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL
PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF
THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE
AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable
United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of
Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby
submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed.
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
UG09899-0-6/11(0)
Rev. 0 | Page 24 of 24