2 ADC/8 DAC with PLL,
192 kHz, 24-Bit Codec
ADAU1328
Data Sheet
FEATURES
GENERAL DESCRIPTION
PLL generated or direct master clock
Low EMI design
108 dB DAC/107 dB ADC dynamic range and SNR
−94 dB THD + N
Single 3.3 V supply
Tolerance for 5 V logic inputs
Supports 24 bits and 8 kHz to 192 kHz sample rates
Differential ADC input
Single-ended DAC output
Log volume control with autoramp function
SPI® controllable for flexibility
Software controllable clickless mute
Software power-down
Right justified, left justified, I2S and TDM modes
Master and slave modes up to 16-channel in/out
48-lead LQFP
The ADAU1328 is a high performance, single-chip codec that
provides two analog-to-digital converters (ADCs) with differential
input and eight digital-to-analog converters (DACs) with
single-ended output using the Analog Devices, Inc. patented
multibit sigma-delta (Σ-Δ) architecture. An SPI port is included,
allowing a microcontroller to adjust volume and many other
parameters. The ADAU1328 operates from 3.3 V digital and
analog supplies. The ADAU1328 is available in a 48-lead
(single-ended output) LQFP. Other members of this family
include a differential DAC output version.
The ADAU1328 is designed for low EMI. This consideration is
apparent in both the system and circuit design architectures.
By using the on-board PLL to derive the master clock from the
LR clock or from an external crystal, the ADAU1328 eliminates
the need for a separate high frequency master clock and can
also be used with a suppressed bit clock. The digital-to-analog
and analog-to-digital converters are designed using the latest
ADI continuous time architectures to further minimize EMI. By
using 3.3 V supplies, power consumption is minimized, further
reducing emissions.
APPLICATIONS
Home theater systems
Set-top boxes
Digital audio effects processors
FUNCTIONAL BLOCK DIAGRAM
DIGITAL AUDIO
INPUT/OUTPUT
ADAU1328
SERIAL DATA PORT
DAC
DAC
SDATA
OUT
ADC
DEC
FILTER
48/96/
192kHz
ADC
SDATA
IN
CLOCKS
TIMING MANAGEMENT
AND CONTROL
(CLOCK AND PLL)
DAC
DIGITAL
FILTER
AND
VOLUME
CONTROL
DAC
DAC
DAC
DAC
DAC
12.488MHz
CONTROL
PORT
SPI
6.144MHz
CONTROL DATA
INPUT/OUTPUT
06102-001
PRECISION
VOLTAGE
REFERENCE
Figure 1.
Rev. B
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Tel: 781.329.4700
©2006-2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADAU1328
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog-to-Digital Converters (ADCs) .................................... 13
Applications ....................................................................................... 1
Digital-to-Analog Converters (DACs) .................................... 13
General Description ......................................................................... 1
Clock Signals ............................................................................... 13
Functional Block Diagram .............................................................. 1
Reset and Power-Down ............................................................. 14
Revision History ............................................................................... 2
Serial Control Port ..................................................................... 14
Specifications..................................................................................... 3
Power Supply and Voltage Reference....................................... 15
Test Conditions ............................................................................. 3
Serial Data Ports—Data Format ............................................... 15
Analog Performance Specifications ........................................... 3
Time-Division Multiplexed (TDM) Modes ............................ 15
Crystal Oscillator Specifications................................................. 4
Daisy-Chain Mode ..................................................................... 19
Digital Input/Output Specifications........................................... 4
Control Registers ............................................................................ 24
Power Supply Specifications........................................................ 5
Definitions ................................................................................... 24
Digital Filters ................................................................................. 6
PLL and Clock Control Registers ............................................. 24
Timing Specifications .................................................................. 6
DAC Control Registers .............................................................. 25
Absolute Maximum Ratings ............................................................ 8
ADC Control Registers.............................................................. 27
Thermal Resistance ...................................................................... 8
Additional Modes ....................................................................... 29
ESD Caution .................................................................................. 8
Application Circuits ....................................................................... 30
Pin Configuration and Function Descriptions ............................. 9
Outline Dimensions ....................................................................... 31
Typical Performance Characteristics ........................................... 11
Ordering Guide .......................................................................... 31
Theory of Operation ...................................................................... 13
REVISION HISTORY
2/13—Rev. A to Rev. B
Changes to tCLH Parameter, Comments Column, Table 6............ 7
Changes to Serial Control Port Section ....................................... 14
7/11—Rev. 0 to Rev. A
Deleted References to I2C ............................................. Throughout
Changes to Table 9, DSDATAx/ASDATAx Pin Descriptions ..... 9
Updated Outline Dimensions ....................................................... 31
6/06—Revision 0: Initial Version
Rev. B | Page 2 of 32
Data Sheet
ADAU1328
SPECIFICATIONS
TEST CONDITIONS
Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.
Supply Voltages (AVDD, DVDD)
Temperature Range 1
Master Clock
Input Sample Rate
Measurement Bandwidth
Word Width
Load Capacitance (Digital Output)
Load Current (Digital Output)
Input Voltage HI
Input Voltage LO
1
3.3 V
As specified in Table 1
12.288 MHz (48 kHz fS, 256 × fS mode)
48 kHz
20 Hz to 20 kHz
24 bits
20 pF
±1 mA or 1.5 kΩ to ½ DVDD supply
2.0 V
0.8 V
Functionally guaranteed at −40°C to +85°C case temperature.
ANALOG PERFORMANCE SPECIFICATIONS
Specifications guaranteed at 25°C (ambient).
Table 1.
Parameter
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
Gain Error
Interchannel Gain Mismatch
Offset Error
Gain Drift
Interchannel Isolation
CMRR
Input Resistance
Input Capacitance
Input Common-Mode Bias Voltage
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
With A-Weighted Filter (Avg)
Total Harmonic Distortion + Noise
Single-Ended Version
Conditions
Min
All ADCs
20 Hz to 20 kHz, −60 dB input
98
100
−1 dBFS
−10
−0.25
−10
100 mV rms, 1 kHz
100 mV rms, 20 kHz
Typ
Max
Unit
24
Bits
102
105
−96
dB
dB
dB
%
dB
mV
ppm/°C
dB
dB
dB
kΩ
pF
V
0
100
−110
55
55
14
10
1.5
−87
+10
+0.25
+10
20 Hz to 20 kHz, −60 dB input
98
100
0 dBFS
Two channels running
Eight channels running
Full-Scale Output Voltage
Gain Error
Interchannel Gain Mismatch
Offset Error
Gain Drift
Interchannel Isolation
104
106
108
−92
−86
0.88 (2.48)
−10
−0.2
−16
−30
−4
100
Rev. B | Page 3 of 32
dB
dB
dB
−75
+10
+0.2
16
30
dB
dB
V rms (V p-p)
%
dB
mV
ppm/°C
dB
ADAU1328
Parameter
Interchannel Phase Deviation
Volume Control Step
Volume Control Range
De-emphasis Gain Error
Output Resistance at Each Pin
REFERENCE
Internal Reference Voltage
External Reference Voltage
Common-Mode Reference Output
Data Sheet
Conditions
Min
Typ
0
0.375
95
Max
Unit
Degrees
dB
dB
dB
Ω
±0.6
100
FILTR pin
FILTR pin
CM pin
1.32
1.50
1.50
1.50
V
V
V
1.68
CRYSTAL OSCILLATOR SPECIFICATIONS
Table 2.
Parameter
Transconductance
Min
Typ
3.5
Max
Unit
Mmhos
DIGITAL INPUT/OUTPUT SPECIFICATIONS
−40°C < TA < +85°C, DVDD = 3.3 V ± 10%.
Table 3.
Parameter
Input Voltage HI (VIH)
Input Voltage HI (VIH)
Input Voltage LO (VIL)
Input Leakage
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
Input Capacitance
Conditions/Comments
MCLKI pin
IIH @ VIH = 2.4 V
IIL @ VIL = 0.8 V
IOH = 1 mA
IOL = 1 mA
Rev. B | Page 4 of 32
Min
2.0
2.2
Typ
Max
0.8
10
10
DVDD − 0.60
0.4
5
Unit
V
V
V
µA
µA
V
V
pF
Data Sheet
ADAU1328
POWER SUPPLY SPECIFICATIONS
Table 4.
Parameter
SUPPLIES
Voltage
Digital Current
Normal Operation
Power-Down
Analog Current
Normal Operation
Power-Down
DISSIPATION
Operation
All Supplies
Digital Supply
Analog Supply
Power-Down, All Supplies
POWER SUPPLY REJECTION RATIO
Signal at Analog Supply Pins
Conditions/Comments
Min
Typ
Max
Unit
DVDD
AVDD
MCLK = 256 fS
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
fS = 48 kHz to 192 kHz
3.0
3.0
3.3
3.3
3.6
3.6
V
V
56
65
95
2.0
mA
mA
mA
mA
74
23
mA
mA
429
185
244
83
mW
mW
mW
mW
50
50
dB
dB
MCLK = 256 fS, 48 kHz
1 kHz, 200 mV p-p
20 kHz, 200 mV p-p
Rev. B | Page 5 of 32
ADAU1328
Data Sheet
DIGITAL FILTERS
Table 5.
Parameter
ADC DECIMATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
DAC INTERPOLATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
Mode
All modes, typ @ 48 kHz
Factor
Min
0.4375 fS
Typ
Max
Unit
21
±0.015
24
27
0.5 fS
0.5625 fS
kHz
dB
kHz
kHz
dB
µs
79
22.9844/fS
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
0.4535 fS
0.3646 fS
0.3646 fS
479
22
kHz
kHz
kHz
dB
dB
dB
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
µs
µs
µs
35
70
±0.01
±0.05
±0.1
0.5 fS
0.5 fS
0.5 fS
0.5465 fS
0.6354 fS
0.6354 fS
24
48
96
26
61
122
70
70
70
25/fS
11/fS
8/fS
521
115
42
TIMING SPECIFICATIONS
−40°C < TA < +85°C, DVDD = 3.3 V ± 10%.
Table 6.
Parameter
INPUT MASTER CLOCK (MCLK) AND RESET
tMH
Condition
Comments
Min
Max
Unit
MCLK duty cycle
DAC/ADC clock source = PLL clock @
256 fS, 384 fS, 512 fS, 768 fS
DAC/ADC clock source = direct MCLK @
512 fS (bypass on-chip PLL)
PLL mode, 256 fS reference
Direct 512 fS mode
40
60
%
40
60
%
6.9
13.8
27.6
MHz
MHz
ns
tMCLK
10
60
ms
%
tMH
fMCLK
fMCLK
tPDR
tPDRR
PLL
Lock Time
256 fS VCO Clock, Output Duty Cycle MCLKO pin
MCLK frequency
RST low
RST recovery
Reset to active output
15
4096
MCLK and LRCLK input
40
Rev. B | Page 6 of 32
Data Sheet
Parameter
SPI PORT
tCCH
tCCL
fCCLK
tCDS
tCDH
tCLS
tCLH
tCLHIGH
tCOE
tCOD
tCOH
tCOTS
DAC SERIAL PORT
tDBH
tDBL
tDLS
tDLH
tDLS
tDDS
tDDH
ADC SERIAL PORT
tABH
tABL
tALS
tALH
tALS
tABDD
AUXILIARY INTERFACE
tAXDS
tAXDH
tDXDD
tXBH
tXBL
tDLS
tDLH
ADAU1328
Condition
Comments
See Figure 11
CCLK high
CCLK low
CCLK frequency
CDATA setup
CDATA hold
CLATCH setup
CLATCH hold
CLATCH high
COUT enable
COUT delay
COUT hold
COUT tri-state
DBCLK high
DBCLK low
DLRCLK setup
DLRCLK hold
DLRCLK skew
DSDATA setup
DSDATA hold
ABCLK high
ABCLK low
ALRCLK setup
ALRCLK hold
ALRCLK skew
ASDATA delay
AAUXDATA setup
AAUXDATA hold
DAUXDATA delay
AUXBCLK high
AUXBCLK low
AUXLRCLK setup
AUXLRCLK hold
Min
Max
35
35
fCCLK = 1/tCCP, only tCCP shown in Figure 11
To CCLK rising
From CCLK rising
To CCLK rising
From CCLK rising
Not shown in Figure 11
From CCLK falling
From CCLK falling
From CCLK falling, not shown in Figure 11
From CCLK falling
See Figure 24
Slave mode
Slave mode
To DBCLK rising, slave mode
From DBCLK rising, slave mode
From DBCLK falling, master mode
To DBCLK rising
From DBCLK rising
See Figure 25
Slave mode
Slave mode
To ABCLK rising, slave mode
From ABCLK rising, slave mode
From ABCLK falling, master mode
From ABCLK falling
To AUXBCLK rising
From AUXBCLK rising
From AUXBCLK falling
To AUXBCLK rising
From AUXBCLK rising
Rev. B | Page 7 of 32
10
10
10
10
10
10
30
30
30
30
10
10
10
5
−8
10
5
10
10
10
5
−8
+8
+8
18
10
5
18
10
10
10
5
Unit
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADAU1328
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter
Analog (AVDD)
Digital (DVDD)
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Operating Temperature Range (Case)
Storage Temperature Range
Rating
−0.3 V to +3.6 V
−0.3 V to +3.6 V
±20 mA
–0.3 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−40°C to +85°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA represents thermal resistance, junction-to-ambient; θJC
represents the thermal resistance, junction-to-case. All
characteristics are for a 4-layer board.
Table 8. Thermal Resistance
Package Type
48-Lead LQFP
ESD CAUTION
Rev. B | Page 8 of 32
θJA
50.1
θJC
17
Unit
°C/W
Data Sheet
ADAU1328
42
41
40
39
38
37
AGND
1
36
AGND
MCLKI/XI
2
35
FILTR
MCLKO/XO
3
34
AGND
AGND
4
33
AVDD
AVDD
5
ADAU1328
32
AGND
OL3
6
OR3
TOP VIEW
(Not to Scale)
7
OL4
8
29
OR1
OR4
9
28
OL1
PD/RST 10
27
CLATCH/ADR1
DSDATA4 11
26
CCLK/SCL
DGND 12
25
DGND
18
19
20
21
22
23
24
ASDATA1
ABCLK
ALRCLK
CIN/ADR0
COUT/SDA
DSDATA2
17
DLRCLK
DVDD
16
ASDATA2
15
DBCLK
14
DSDATA1
13
DSDATA3
SINGLE-ENDED
OUTPUT
31
OR2
30
OL2
06102-020
ADC1LN
43
AVDD
ADC1RP
44
ADC1LP
ADC1RN
45
CM
ADC2LP
46
ADC2RP
47
ADC2LN
LF
48
ADC2RN
AVDD
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 9. Pin Function Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
In/Out
I
I
O
I
I
O
O
O
O
I
I/O
Mnemonic
AGND
MCLKI/XI
MCLKO/XO
AGND
AVDD
OL3
OR3
OL4
OR4
PD/RST
DSDATA4
12
13
14
I
I
I/O
DGND
DVDD
DSDATA3
15
I/O
DSDATA2
16
17
18
19
I
I/O
I/O
I/O
DSDATA1
DBCLK
DLRCLK
ASDATA2
20
21
22
O
I/O
I/O
ASDATA1
ABCLK
ALRCLK
Description
Analog Ground.
Master Clock Input/Crystal Oscillator Input.
Master Clock Output/Crystal Oscillator Output.
Analog Ground.
Analog Power Supply. Connect to analog 3.3 V supply.
DAC 3 Left Output.
DAC 3 Right Output.
DAC 4 Left Output.
DAC 4 Right Output.
Power-Down Reset (Active Low).
DAC Serial Data Input 4. Data input to DAC4 data in/TDM DAC2 data out (dual-line mode)/AUX
DAC2 data out (to external DAC2).
Digital Ground.
Digital Power Supply. Connect to digital 3.3 V supply.
DAC Serial Data Input 3. Data input to DAC3 data in/TDM DAC2 data in (dual-line mode)/AUX ADC2
data in (from external ADC2).
DAC Serial Data Input 2. Data input to DAC2 data in/TDM DAC data out/AUX ADC1 data in (from
external ADC1).
DAC Serial Data Input 1. Data input to DAC1 data in/TDM DAC data in/TDM data in.
Bit Clock for DACs.
LR Clock for DACs.
ADC Serial Data Output 2. Data output from ADC2/TDM ADC data in/AUX DAC1 data out (to
external DAC1).
ADC Serial Data Output 1. Data output from ADC1/TDM ADC data out/TDM data out.
Bit Clock for ADCs.
LR Clock for ADCs.
Rev. B | Page 9 of 32
ADAU1328
Pin No.
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
In/Out
I
I/O
I
I
I
O
O
O
O
I
I
I
O
I
I
O
I
I
I
I
I
I
I
I
O
I
Data Sheet
Mnemonic
CIN/ADR0
COUT/SDA
DGND
CCLK/SCL
CLATCH/ADR1
OL1
OR1
OL2
OR2
AGND
AVDD
AGND
FILTR
AGND
AVDD
CM
ADC1LP
ADC1LN
ADC1RP
ADC1RN
ADC2LP
ADC2LN
ADC2RP
ADC2RN
LF
AVDD
Description
Control Data Input (SPI).
Control Data Output (SPI).
Digital Ground.
Control Clock Input (SPI).
Latch Input for Control Data (SPI).
DAC 1 Left Output.
DAC 1 Right Output.
DAC 2 Left Output.
DAC 2 Right Output.
Analog Ground.
Analog Power Supply. Connect to analog 3.3 V supply.
Analog Ground.
Voltage Reference Filter Capacitor Connection. Bypass with 10 µF||100 nF to AGND.
Analog Ground.
Analog Power Supply. Connect to analog 3.3 V supply.
Common-Mode Reference Filter Capacitor Connection. Bypass with 47 µF||100 nF to AGND.
ADC1 Left Positive Input.
ADC1 Left Negative Input.
ADC1 Right Positive Input.
ADC1 Right Negative Input.
ADC2 Left Positive Input.
ADC2 Left Negative Input.
ADC2 Right Positive Input.
ADC2 Right Negative Input.
PLL Loop Filter. Return to AVDD.
Analog Power Supply. Connect to analog 3.3 V supply.
Rev. B | Page 10 of 32
Data Sheet
ADAU1328
TYPICAL PERFORMANCE CHARACTERISTICS
0.10
0
0.08
0.06
MAGNITUDE (dB)
MAGNITUDE (dB)
0.04
0.02
0
–0.02
–0.04
–50
–100
–0.06
–150
0
0
06102-002
–0.10
2000 4000 6000 8000 10000 12000 14000 16000 18000
FREQUENCY (Hz)
12
24
36
48
FREQUENCY (kHz)
Figure 3. ADC Pass-Band Filter Response, 48 kHz
06102-005
–0.08
Figure 6. DAC Stop-Band Filter Response, 48 kHz
0.10
0
–10
–20
0.05
MAGNITUDE (dB)
MAGNITUDE (dB)
–30
–40
–50
–60
–70
0
–0.05
–80
–0.10
06102-003
0
5000 10000 15000 20000 25000 30000 35000 40000
FREQUENCY (Hz)
0
24
48
72
96
FREQUENCY (kHz)
Figure 4. ADC Stop-Band Filter Response, 48 kHz
06102-006
–90
–100
Figure 7. DAC Pass-Band Filter Response, 96 kHz
0.06
0
MAGNITUDE (dB)
0.02
0
–0.02
–50
–100
–150
–0.06
0
8
16
FREQUENCY (kHz)
24
Figure 5. DAC Pass-Band Filter Response, 48 kHz
0
24
48
72
FREQUENCY (kHz)
Figure 8. DAC Stop-Band Filter Response, 96 kHz
Rev. B | Page 11 of 32
96
06102-007
–0.04
06102-004
MAGNITUDE (dB)
0.04
ADAU1328
Data Sheet
0.5
0
0.4
0.3
–2
MAGNITUDE (dB)
0.1
0
–0.1
–4
–6
–0.2
–8
–0.3
–0.5
0
8
16
32
64
FREQUENCY (kHz)
–10
48
64
80
FREQUENCY (kHz)
Figure 10. DAC Stop-Band Filter Response, 192 kHz
Figure 9. DAC Pass-Band Filter Response, 192 kHz
Rev. B | Page 12 of 32
96
06102-009
–0.4
06102-008
MAGNITUDE (dB)
0.2
Data Sheet
ADAU1328
THEORY OF OPERATION
ANALOG-TO-DIGITAL CONVERTERS (ADCs)
There are two ADC channels in the ADAU1328 configured as
two stereo pairs with differential inputs. The ADCs can operate
at a nominal sample rate of 48 kHz, 96 kHz, or 192 kHz. The
ADCs include on-board digital antialiasing filters with 79 dB
stop-band attenuation and linear phase response, operating at
an oversampling ratio of 128 (48 kHz, 96 kHz, and 192 kHz
modes). Digital outputs are supplied through two serial data
output pins (one for each stereo pair) and a common frame
(ALRCLK) and bit (ABCLK) clock. Alternatively, one of the
TDM modes can be used to access up to 16 channels on a single
TDM data line.
The ADCs must be driven from a differential signal source for
best performance. The input pins of the ADCs connect to
internal switched capacitors. To isolate the external driving op
amp from the glitches caused by the internal switched capacitors,
each input pin should be isolated by using a series connected,
external, 100 Ω resistor together with a 1 nF capacitor connected
from each input to ground. This capacitor must be of high quality,
for example, ceramic NPO or polypropylene film.
The differential inputs have a nominal common-mode voltage
of 1.5 V. The voltage at the common-mode reference pin (CM)
can be used to bias external op amps to buffer the input signals
(see the Power Supply and Voltage Reference section). The
inputs can also be ac-coupled and do not need an external dc
bias to CM.
A digital high-pass filter can be switched in line with the ADCs
under serial control to remove residual dc offsets. It has a
1.4 Hz, 6 dB per octave cutoff at a 48 kHz sample rate. The
cutoff frequency scales directly with sample frequency.
DIGITAL-TO-ANALOG CONVERTERS (DACs)
The ADAU1328 DAC channels are arranged as single-ended,
four stereo pairs giving eight analog outputs for minimum
external components. The DACs include on-board digital
reconstruction filters with 70 dB stop-band attenuation and linear
phase response, operating at an oversampling ratio of 4 (48 kHz or
96 kHz modes) or 2 (192 kHz mode). Each channel has its own
independently programmable attenuator, adjustable in 255 steps
in increments of 0.375 dB. Digital inputs are supplied through
four serial data input pins (one for each stereo pair) and a
common frame (DLRCLK) and bit (DBCLK) clock. Alternatively,
one of the TDM modes can be used to access up to 16 channels
on a single TDM data line.
Each output pin has a nominal common-mode dc level of 1.5 V
and swings ±1.27 V for a 0 dBFS digital input signal. A single op
amp, third-order, external, low-pass filter is recommended to
remove high frequency noise present on the output pins. The
use of op amps with low slew rate or low bandwidth can cause
high frequency noise and tones to fold down into the audio
band; therefore, exercise care in selecting these components.
The voltage at CM, the common-mode reference pin, can be
used to bias the external op amps that buffer the output signals
(see the Power Supply and Voltage Reference section).
CLOCK SIGNALS
The on-chip phase locked loop (PLL) can be selected to
reference the input sample rate from either of the LRCLK pins
or 256, 384, 512, or 768 times the sample rate, referenced to the
48 kHz mode from the MCLKI pin. The default at power-up is
256 × fS from MCLKI. In 96 kHz mode, the master clock frequency stays at the same absolute frequency; therefore, the
actual multiplication rate is divided by 2. In 192 kHz mode,
the actual multiplication rate is divided by 4. For example, if a
device in the ADAU1328 family is programmed in 256 × fS mode,
the frequency of the master clock input is 256 × 48 kHz =
12.288 MHz. If the ADAU1328 is then switched to 96 kHz
operation (by writing to the SPI port), the frequency of the
master clock should remain at 12.288 MHz, which is now 128 ×
fS. In 192 kHz mode, this becomes 64 × fS.
The internal clock for the ADCs is 256 × fS for all clock modes.
The internal clock for the DACs varies by mode: 512 × fS (48 kHz
mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz mode). By
default, the on-board PLL generates this internal master clock
from an external clock. A direct 512 × fS (referenced to 48 kHz
mode) master clock can be used for either the ADCs or DACs if
selected in PLL and Clock Control 1 Register.
Note that it is not possible to use a direct clock for the ADCs set
to the 192 kHz mode. It is required that the on-chip PLL be
used in this mode.
The PLL can be powered down in PLL and Clock Control 0
Register. To ensure reliable locking when changing PLL modes,
or if the reference clock is unstable at power-on, power down
the PLL and then power it back up when the reference clock has
stabilized.
The internal MCLK can be disabled in PLL and Clock Control 0
Register to reduce power dissipation when the ADAU1328 is
idle. The clock should be stable before it is enabled. Unless a
standalone mode is selected (see the Serial Control Port
section), the clock is disabled by reset and must be enabled by
writing to the SPI port for normal operation.
Rev. B | Page 13 of 32
ADAU1328
Data Sheet
To maintain the highest performance possible, it is recommended
that the clock jitter of the internal master clock signal be limited
to less than 300 ps rms time interval error (TIE). Even at these
levels, extra noise or tones can appear in the DAC outputs if the
jitter spectrum contains large spectral peaks. If the internal PLL
is not being used, it is highly recommended that an independent
crystal oscillator generate the master clock. In addition, it is
especially important that the clock signal not be passed through
an FPGA, CPLD, or other large digital chip (such as a DSP)
before being applied to the ADAU1328. In most cases, this
induces clock jitter due to the sharing of common power and
ground connections with other unrelated digital output signals.
When the PLL is used, jitter in the reference clock is attenuated
above a certain frequency depending on the loop filter.
RESET AND POWER-DOWN
Reset sets all the control registers to their default settings. To
avoid pops, reset does not power down the analog outputs.
After reset is deasserted, and the PLL acquires lock condition,
an initialization routine runs inside the ADAU1328. This
initialization lasts for approximately 256 MCLKs.
The power-down bits in the PLL and Clock Control 0, DAC
Control 1, and ADC Control 1 registers power down the
respective sections. All other register settings are retained.
The reset pin should be pulled low by an external resistor to
guarantee proper startup.
SERIAL CONTROL PORT
The ADAU1328 has an SPI control port that permits programming
and reading back of the internal control registers for the ADCs,
DACs, and clock system. A standalone mode is available for
operation without serial control, standalone is configured at
reset by connecting CIN, CCLK and CLATCH to ground. In
standalone mode, all registers are set to default, except the internal
MCLK enable which is set to 1. The ADC ABCLK and ALRCLK
clock ports are set to master/slave by the connecting the COUT
pin to either DVDD or ground. Standalone mode only supports
stereo mode with an I2S data format and 256 fS MCLK rate. Refer
to Table 10 for details. If CIN, CCLK, and CLATCH are not
grounded, the ADAU1328 SPI port is active. It is recommended
to use a weak pull-up resistor on CLATCH in applications that
have a microcontroller. This pull-up resistor ensures that the
ADAU1328 recognizes the presence of a microcontroller.
The SPI control port of the ADAU1328 is a 4-wire serial control
port. The format is similar to the Motorola SPI format except
the input data-word is 24 bits wide. The serial bit clock and
latch can be completely asynchronous to the sample rate of the
ADCs and DACs. Figure 11 shows the format of the SPI signal.
The first byte is a global address with a read/write bit. For the
ADAU1328, the address is 0x04, shifted left 1 bit due to the
R/W bit. The second byte is the ADAU1328 register address
and the third byte is the data.
Table 10. Standalone Mode Selection
ADC Clocks
Slave
Master
CIN/ADR0
0
0
COUT/SDA
0
1
CCLK/SCL
0
0
tCLS
tCCH tCCL
tCCP
CLATCH
CLATCH/ADR1
0
0
tCLH
tCOTS
CCLK
tCDS tCDH
COUT
D23
D22
D9
tCOE
D9
D8
D0
D8
D0
06102-010
CIN
tCOD
Figure 11. Format of SPI Signal
Rev. B | Page 14 of 32
Data Sheet
ADAU1328
POWER SUPPLY AND VOLTAGE REFERENCE
TIME-DIVISION MULTIPLEXED (TDM) MODES
The ADAU1328 is designed for 3.3 V supplies. Separate power
supply pins are provided for the analog and digital sections.
These pins should be bypassed with 100 nF ceramic chip
capacitors, as close to the pins as possible, to minimize noise
pickup. A bulk aluminum electrolytic capacitor of at least 22 μF
should also be provided on the same PC board as the codec. For
critical applications, improved performance is obtained with
separate supplies for the analog and digital sections. If this is
not possible, it is recommended that the analog and digital
supplies be isolated by means of a ferrite bead in series with each
supply. It is important that the analog supply be as clean as possible.
The ADAU1328 serial ports also have several different TDM
serial data modes. The first and most commonly used
configurations are shown in Figure 12 and Figure 13. In Figure 12,
the ADC serial port outputs one data stream consisting of four
on-chip ADCs followed by four unused slots. In Figure 13, the
eight on-chip DAC data slots are packed into one TDM stream.
In this mode, both DBCLK and ABCLK are 256 fS.
The ADC and DAC internal voltage reference (VREF) is brought
out on FILTR and should be bypassed as close as possible to the
chip, with a parallel combination of 10 μF and 100 nF. Any
external current drawn should be limited to less than 50 μA.
The internal reference can be disabled in PLL and Clock
Control 1 Register, and FILTR can be driven from an external
source. This can be used to scale the DAC output to the clipping
level of a power amplifier based on its power supply voltage.
The ADC input gain varies by the inverse ratio. The total gain
from ADC input to DAC output remains constant.
The CM pin is the internal common-mode reference. It should
be bypassed as close as possible to the chip, with a parallel
combination of 47 μF and 100 nF. This voltage can be used to
bias external op amps to the common-mode voltage of the input
and output signal pins. The output current should be limited to
less than 0.5 mA source and 2 mA sink.
SERIAL DATA PORTS—DATA FORMAT
The ADAU1328 allows systems with more than eight DAC
channels to be easily configured by the use of an auxiliary serial
data port. The DAC TDM-AUX mode is shown in Figure 14. In
this mode, the AUX channels are the last four slots of the TDM
data stream. These slots are extracted and output to the AUX serial
port. It should be noted that due to the high DBCLK frequency, this
mode is available only in the 48 kHz/44.1 kHz/32 kHz sample rate.
The ADAU1328 also allows system configurations with more
than four ADC channels, as shown in Figure 15 and Figure 16,
which show using 8 ADCs and 16 ADCs, respectively. Again,
due to the high ABCLK frequency, this mode is available only
in the 48 kHz/44.1 kHz/32 kHz sample rate.
Combining the AUX DAC and ADC modes results in a system
configuration of 8 ADCs and 12 DACs. The system, then, consists of two external stereo ADCs, two external stereo DACs,
and one ADAU1328. This mode is shown in Figure 17
(combined AUX DAC and ADC modes).
LRCLK
256 BCLKs
BCLK
32 BCLKs
DATA
SLOT 1
LEFT 1
The eight DAC channels use a common serial bit clock (DBCLK)
and a common left-right framing clock (DLRCLK) in the serial
data port. The four ADC channels use a common serial bit clock
(ABCLK) and left-right framing clock (ALRCLK) in the serial
data port. The clock signals are all synchronous with the sample
rate. The normal stereo serial modes are shown in Figure 23.
SLOT 2
RIGHT 1
SLOT 3
LEFT 2
SLOT 4
RIGHT 2
SLOT 5
SLOT 6
SLOT 7
SLOT 8
LRCLK
BCLK
MSB
MSB–1
MSB–2
06102-016
All digital inputs are compatible with TTL and CMOS levels.
All outputs are driven from the 3.3 V DVDD supply and are
compatible with TTL and 3.3 V CMOS levels.
The I/O pins of the serial ports are defined according to the
serial mode selected. For a detailed description of the function
of each pin in TDM and AUX modes, see Table 11.
DATA
Figure 12. ADC TDM (8-Channel I2S Mode)
LRCLK
256 BCLKs
BCLK
32 BCLK
DATA
Rev. B | Page 15 of 32
SLOT 1
LEFT 1
SLOT 2
RIGHT 1
SLOT 3
LEFT 2
SLOT 4
RIGHT 2
SLOT 5
LEFT 3
SLOT 6
RIGHT 3
SLOT 7
LEFT 4
SLOT 8
RIGHT 4
LRCLK
BCLK
MSB
MSB–1
MSB–2
DATA
Figure 13. DAC TDM (8-Channel I2S Mode)
06102-017
The ADC and DAC serial data modes default to I2S. The ports
can also be programmed for left justified, right justified, and
TDM modes. The word width is 24 bits by default and can be
programmed for 16 or 20 bits. The DAC serial formats are
programmable according to DAC Control 0 Register. The
polarity of the DBCLK and DLRCLK is programmable according
to DAC Control 1 Register. The ADC serial formats and serial
clock polarity are programmable according to ADC Control 1
Register. Both DAC and ADC serial ports are programmable to
become the bus masters according to DAC Control 1 Register
and Control 2 Register. By default, both ADC and DAC serial
ports are in the slave mode.
ADAU1328
Data Sheet
Table 11. Pin Function Changes in TDM and AUX Modes
Mnemonic
ASDATA1
ASDATA2
DSDATA1
DSDATA2
DSDATA3
DSDATA4
ALRCLK
ABCLK
DLRCLK
DBCLK
Stereo Modes
ADC1 Data Out
ADC2 Data Out
DAC1 Data In
DAC2 Data In
DAC3 Data In
DAC4 Data In
ADC LRCLK In/Out
ADC BCLK In/Out
DAC LRCLK In/Out
DAC BCLK In/Out
TDM Modes
ADC TDM Data Out
ADC TDM Data In
DAC TDM Data In
DAC TDM Data Out
DAC TDM Data In 2 (Dual-Line Mode)
DAC TDM Data Out 2 (Dual-Line Mode)
ADC TDM Frame Sync In/Out
ADC TDM BCLK In/Out
DAC TDM Frame Sync In/Out
DAC TDM BCLK In/Out
AUX Modes
TDM Data Out
AUX Data Out 1 (to External DAC 1)
TDM Data In
AUX Data In 1 (from External ADC 1)
AUX Data In 2 (from External ADC 2)
AUX Data Out 2 (to External DAC 2)
TDM Frame Sync In/Out
TDM BCLK In/Out
AUX LRCLK In/Out
AUX BCLK In/Out
ALRCLK
ABCLK
DSDATA1
(TDM_IN)
EMPTY
EMPTY
EMPTY
AUXILIARY DAC CHANNELS
WILL APPEAR AT
AUX DAC PORTS
8-ON-CHIP DAC CHANNELS
UNUSED SLOTS
EMPTY
DAC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
DAC L4
DAC R4
AUX L1
AUX R1
AUX L2
AUX R2
32 BITS
MSB
DLRCLK
(AUX PORT)
LEFT
RIGHT
ASDATA2
(AUX1_OUT)
MSB
MSB
DSDATA4
(AUX2_OUT)
MSB
MSB
Figure 14. 16-Channel DAC TDM-AUX Mode
Rev. B | Page 16 of 32
06102-051
DBCLK
(AUX PORT)
Data Sheet
ADAU1328
ALRCLK
ABCLK
8-ON-CHIP DAC CHANNELS
DSDATA1
(TDM_IN)
DAC L1
ASDATA1
(TDM_OUT)
ADC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
ADC R2
AUX L1
AUX R1
4-ON-CHIP ADC CHANNELS
ADC R1
DAC L4
DAC R4
4-AUX ADC CHANNELS
ADC L2
AUX L2
AUX R2
32 BITS
MSB
DLRCLK
(AUX PORT)
LEFT
RIGHT
DBCLK
(AUX PORT)
MSB
DSDATA3
(AUX2_IN)
MSB
MSB
06102-050
DSDATA2
(AUX1_IN)
MSB
Figure 15. 8-Channel AUX ADC Mode
ALRCLK
ABCLK
4 ON-CHIP ADC CHANNELS
ASDATA1
(TDM_OUT)
ADC L1
ADC R1
ADC L2
AUXILIARY ADC CHANNELS
ADC R2 AUX L1
AUX R1
AUX L2
UNUSED SLOTS
AUX R2 UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED
32 BITS
MSB
DLRCLK
(AUX PORT)
RIGHT
LEFT
DSDATA2
(AUX1_IN)
MSB
MSB
DSDATA3
(AUX2_IN)
MSB
MSB
Figure 16. 16-Channel AUX ADC Mode
Rev. B | Page 17 of 32
06102-052
DBCLK
(AUX PORT)
ADAU1328
Data Sheet
ALRCLK
ABCLK
DSDATA1
(TDM_IN)
EMPTY
ASDATA1
(TDM_OUT)
ADC L1
EMPTY
EMPTY
EMPTY
4 ON-CHIP ADC CHANNELS
DLRCLK
(AUX PORT)
ADC R1
ADC L2
AUXILIARY DAC CHANNELS
APPEAR AT
AUX DAC PORTS
8 ON-CHIP DAC CHANNELS
UNUSED SLOTS
ADC R2
DAC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
AUXILIARY ADC CHANNELS
AUX L1
AUX R1
AUX L2
DAC L4
DAC R4
AUX L1
AUX R1
AUX L2
AUX R2
UNUSED SLOTS
AUX R2 UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED
LEFT
RIGHT
DSDATA2
(AUX1_IN)
MSB
MSB
DSDATA3
(AUX2_IN)
MSB
MSB
ASDATA2
(AUX1_OUT)
MSB
MSB
DSDATA4
(AUX2_OUT)
MSB
MSB
Figure 17. Combined AUX DAC and ADC Mode
Rev. B | Page 18 of 32
06102-053
DBCLK
(AUX PORT)
Data Sheet
ADAU1328
DAISY-CHAIN MODE
The dual-line TDM mode can also be used to send data at a
192 kHz sample rate into the ADAU1328, as shown in Figure 20.
There are two configurations for the ADC port to work in
daisy-chain mode. The first one is with an ABCLK at 256 fS
shown in Figure 21. The second configuration is shown in
Figure 22. Note that in the 512 fS ABCLK mode, the ADC
channels occupy the first eight slots; the second eight slots are
empty. The TDM_IN of the first ADAU1328 must be grounded
in all modes of operation.
The ADAU1328 also allows a daisy-chain configuration to
expand the system to 8 ADCs and 16 DACs (see Figure 18). In
this mode, the DBCLK frequency is 512 fS. The first eight slots
of the DAC TDM data stream belong to the first ADAU1328 in
the chain and the last eight slots belong to the second ADAU1328.
The second ADAU1328 is the device attached to the DSP
TDM port.
To accommodate 16 channels at a 96 kHz sample rate, the
ADAU1328 can be configured into a dual-line, DAC TDM
mode, as shown in Figure 19. This mode allows a slower
DBCLK than normally required by the one-line TDM mode.
The I/O pins of the serial ports are defined according to the
serial mode selected. See Table 12 for a detailed description of
the function of each pin. See Figure 26 for a typical ADAU1328
configuration with two external stereo DACs and two external
stereo ADCs.
Again, the first four channels of each TDM input belong to the
first ADAU1328 in the chain and the last four channels belong
to the second ADAU1328.
Figure 23 through Figure 25 show the serial mode formats. For
maximum flexibility, the polarity of LRCLK and BCLK are
programmable. In these figures, all of the clocks are shown with
their normal polarity. The default mode is I2S.
DLRCLK
DBCLK
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
DSDATA1 (TDM_IN)
OF THE SECOND ADAU1328
DAC L1
DAC R1
DAC L2
DSDATA2 (TDM_OUT)
OF THE SECOND ADAU1328
THIS IS THE TDM
TO THE FIRST ADAU1328
DAC R2
DAC L3
DAC R3
DAC L4
DAC R4
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
DAC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
DAC L4
DAC R4
DAC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
DAC L4
DAC R4
8 UNUSED SLOTS
FIRST
ADAU1328
SECOND
ADAU1328
DSP
MSB
Figure 18. Single-Line DAC TDM Daisy-Chain Mode (Applicable to 48 kHz Sample Rate, 16-Channel, Two ADAU1328 Daisy Chain)
Rev. B | Page 19 of 32
06102-054
32 BITS
ADAU1328
Data Sheet
DLRCLK
DBCLK
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
DSDATA1
(IN)
DAC L1
DAC R1
DAC L2
DAC R2
DSDATA2
(OUT)
DSDATA3
(IN)
DAC L3
DAC R3
DAC L4
DAC R4
DSDATA4
(OUT)
DAC L1
DAC R1
DAC L2
DAC R2
DAC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
DAC L4
DAC R4
DAC L3
DAC R3
DAC L4
DAC R4
32 BITS
FIRST
ADAU1328
SECOND
ADAU1328
06102-055
MSB
DSP
Figure 19. Dual-Line DAC TDM Mode (Applicable to 96 kHz Sample Rate, 16-Channel, Two ADAU1328 Daisy Chain); DSDATA3 and DSDATA4 Are the Daisy Chain
DLRCLK
DBCLK
DSDATA1
DAC L1
DAC R1
DAC L2
DAC R2
DSDATA2
DAC L3
DAC R3
DAC L4
DAC R4
06102-058
32 BITS
MSB
Figure 20. Dual-Line DAC TDM Mode (Applicable to 192 kHz Sample Rate, 8-Channel Mode)
ALRCLK
ABCLK
4 ADC CHANNELS OF SECOND IC IN THE CHAIN
ASDATA1 (TDM_OUT
OF THE SECOND ADAU1328
IN THE CHAIN)
ADC L1
ADC R1
ADC L2
ADC R2
ASDATA2 (TDM_IN
OF THE SECOND ADAU1328
IN THE CHAIN)
ADC L1
ADC R1
ADC L2
ADC R2
4 ADC CHANNELS OF FIRST IC IN THE CHAIN
ADC L1
ADC R1
ADC L2
ADC R2
32 BITS
SECOND
ADAU1328
DSP
MSB
Figure 21. Dual-Line ADC TDM Daisy-Chain Mode (256 fS ABCLK, Two ADAU1328 Daisy Chain)
Rev. B | Page 20 of 32
06102-056
FIRST
ADAU1328
Data Sheet
ADAU1328
ALRCLK
ABCLK
4 ADC CHANNELS OF
SECOND IC IN THE CHAIN
4 ADC CHANNELS OF
FIRST IC IN THE CHAIN
ASDATA1 (TDM_OUT
OF THE SECOND ADAU1328
IN THE CHAIN)
ADC L1
ADC R1
ADC L2
ADC R2
ASDATA2 (TDM_IN
OF THE SECOND ADAU1328
IN THE CHAIN)
ADC L1
ADC R1
ADC L2
ADC R2
ADC L1
ADC R1
ADC L2
ADC R2
32 BITS
SECOND
ADAU1328
DSP
06102-057
FIRST
ADAU1328
MSB
Figure 22. Dual-Line ADC TDM Daisy-Chain Mode (512 fS ABCLK, Two ADAU1328 Daisy Chain)
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
SDATA
MSB
MSB
LSB
LSB
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
SDATA
MSB
MSB
LSB
LSB
I2S MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
SDATA
MSB
MSB
LSB
LSB
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
LRCLK
BCLK
MSB
MSB
LSB
LSB
DSP MODE—16 BITS TO 24 BITS PER CHANNEL
1/fS
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE, WHICH IS 2 × fS.
3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 23. Stereo Serial Modes
Rev. B | Page 21 of 32
06102-013
SDATA
ADAU1328
Data Sheet
tDBH
DBCLK
tDBL
tDLH
tDLS
DLRCLK
tDDS
DSDATA
LEFT-JUSTIFIED
MODE
MSB–1
MSB
tDDH
tDDS
DSDATA
I2S-JUSTIFIED
MODE
MSB
tDDH
LSB
MSB
tDDH
tDDH
06102-014
tDDS
tDDS
DSDATA
RIGHT-JUSTIFIED
MODE
Figure 24. DAC Serial Timing
tABH
ABCLK
tABL
tALH
tALS
ALRCLK
tABDD
ASDATA
LEFT-JUSTIFIED
MODE
MSB
MSB–1
tABDD
ASDATA
I2S-JUSTIFIED
MODE
MSB
ASDATA
RIGHT-JUSTIFIED
MODE
MSB
Figure 25. ADC Serial Timing
Rev. B | Page 22 of 32
LSB
06102-015
tABDD
Data Sheet
ADAU1328
Table 12. Pin Function Changes in TDM and AUX Modes (Replication of Table 11)
Stereo Modes
ADC1 Data Out
ADC2 Data Out
DAC1 Data In
DAC2 Data In
DAC3 Data In
DAC4 Data In
ADC LRCLK In/Out
ADC BCLK In/Out
DAC LRCLK In/Out
DAC BCLK In/Out
TDM Modes
ADC TDM Data Out
ADC TDM Data In
DAC TDM Data In
DAC TDM Data Out
DAC TDM Data In 2 (Dual-Line Mode)
DAC TDM Data Out 2 (Dual-Line Mode)
ADC TDM Frame Sync In/Out
ADC TDM BCLK In/Out
DAC TDM Frame Sync In/Out
DAC TDM BCLK In/Out
TxDATA
TxCLK
TFS (NC)
RxDATA
SHARC
RxCLK
12.288MHz
LRCLK
AUX
ADC 1
AUX Modes
TDM Data Out
AUX Data Out 1 (to External DAC 1)
TDM Data In
AUX Data In 1 (from External ADC 1)
AUX Data In 2 (from External ADC 2)
AUX Data Out 2 (to External DAC 2)
TDM Frame Sync In/Out
TDM BCLK In/Out
AUX LRCLK In/Out
AUX BCLK In/Out
SHARC IS RUNNING IN SLAVE MODE
(INTERRUPT-DRIVEN)
30MHz
FSYNC-TDM (RFS)
LRCLK
BCLK
BCLK
DATA
ASDATA1 ALRCLK ABCLK DSDATA1
MCLK
AUX
DATA DAC 1
MCLK
DBCLK
DLRCLK
ADAU1328
LRCLK
LRCLK
AUX
ADC 2
BCLK
DSDATA2
DATA
DSDATA3
MCLK
MCLK
TDM MASTER
AUX MASTER
ASDATA2
DSDATA4
BCLK
AUX
DATA DAC 2
MCLK
Figure 26. Example of AUX Mode Connection to SHARC® (ADAU1328 as TDM Master/AUX Master Shown)
Rev. B | Page 23 of 32
06102-019
Mnemonic
ASDATA1
ASDATA2
DSDATA1
DSDATA2
DSDATA3
DSDATA4
ALRCLK
ABCLK
DLRCLK
DBCLK
ADAU1328
Data Sheet
CONTROL REGISTERS
DEFINITIONS
The global address for the ADAU1328 is 0x04, shifted left 1 bit due to the R/W bit. All registers are reset to 0, except for the DAC volume
registers that are set to full volume.
Note that the first setting in each control register parameter is the default setting.
Table 13. Register Format
Bit
Global Address
R/W
Register Address
Data
23:17
16
15:8
7:0
Table 14. Register Addresses and Functions
Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Function
PLL and Clock Control 0
PLL and Clock Control 1
DAC Control 0
DAC Control 1
DAC Control 2
DAC individual channel mutes
DAC 1L volume control
DAC 1R volume control
DAC 2L volume control
DAC 2R volume control
DAC 3L volume control
DAC 3R volume control
DAC 4L volume control
DAC 4R volume control
ADC Control 0
ADC Control 1
ADC Control 2
PLL AND CLOCK CONTROL REGISTERS
Table 15. PLL and Clock Control 0
Bit
0
2:1
4:3
6:5
7
Value
0
1
00
01
10
11
00
01
10
11
00
01
10
11
0
1
Function
Normal operation
Power-down
INPUT 256 (×44.1 kHz or 48 kHz)
INPUT 384 (×44.1 kHz or 48 kHz)
INPUT 512 (×44.1 kHz or 48 kHz)
INPUT 768 (×44.1 kHz or 48 kHz)
XTAL oscillator enabled
256 × fS VCO output
512 × fS VCO output
Off
MCLK
DLRCLK
ALRCLK
Reserved
Disable: ADC and DAC idle
Enable: ADC and DAC active
Description
PLL power-down
MCLK pin functionality (PLL active)
MCLKO pin
PLL input
Internal MCLK enable
Rev. B | Page 24 of 32
Data Sheet
ADAU1328
Table 16. PLL and Clock Control 1
Bit
0
1
2
3
7:4
Value
0
1
0
1
0
1
0
1
0000
Function
PLL clock
MCLK
PLL clock
MCLK
Enabled
Disabled
Not locked
Locked
Reserved
Description
DAC clock source select
ADC clock source select
On-chip voltage reference
PLL lock indicator (read-only)
DAC CONTROL REGISTERS
Table 17. DAC Control 0
Bit
0
2:1
5:3
7:6
Value
0
1
00
01
10
11
000
001
010
011
100
101
110
111
00
01
10
11
Function
Normal
Power-down
32 kHz/44.1 kHz/48 kHz
64 kHz/88.2 kHz/96 kHz
128 kHz/176.4 kHz/192 kHz
Reserved
1
0
8
12
16
Reserved
Reserved
Reserved
Stereo (normal)
TDM (daisy chain)
DAC AUX mode (ADC-, DAC-, TDM-coupled)
Dual-line TDM
Description
Power-down
Sample rate
SDATA delay (BCLK periods)
Serial format
Table 18. DAC Control 1
Bit
0
2:1
3
4
5
6
7
Value
0
1
00
01
10
11
0
1
0
1
0
1
0
1
0
1
Function
Latch in midcycle (normal)
Latch in at end of cycle (pipeline)
64 (2 channels)
128 (4 channels)
256 (8 channels)
512 (16 channels)
Left low
Left high
Slave
Master
Slave
Master
DBCLK pin
Internally generated
Normal
Inverted
Description
BCLK active edge (TDM in)
BCLKs per frame
LRCLK polarity
LRCLK master/slave
BCLK master/slave
BCLK source
BCLK polarity
Rev. B | Page 25 of 32
ADAU1328
Data Sheet
Table 19. DAC Control 2
Bit
0
2:1
4:3
5
7:6
Value
0
1
00
01
10
11
00
01
10
11
0
1
00
Function
Unmute
Mute
Flat
48 kHz curve
44.1 kHz curve
32 kHz curve
24
20
Reserved
16
Noninverted
Inverted
Reserved
Description
Master mute
De-emphasis (32 kHz/44.1 kHz/48 kHz mode only)
Word width
DAC output polarity
Table 20. DAC Individual Channel Mutes
Bit
0
1
2
3
4
5
6
7
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Function
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Description
DAC 1 left mute
DAC 1 right mute
DAC 2 left mute
DAC 2 right mute
DAC 3 left mute
DAC 3 right mute
DAC 4 left mute
DAC 4 right mute
Table 21. DAC Volume Controls
Bit
7:0
Value
0
1 to 254
255
Function
No attenuation
−3/8 dB per step
Full attenuation
Description
DAC volume control
Rev. B | Page 26 of 32
Data Sheet
ADAU1328
ADC CONTROL REGISTERS
Table 22. ADC Control 0
Bit
0
1
2
3
4
5
7:6
Value
0
1
0
1
0
1
0
1
0
1
0
1
00
01
10
11
Function
Normal
Power-down
Off
On
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
32 kHz/44.1 kHz/48 kHz
64 kHz/88.2 kHz/96 kHz
128 kHz/176.4 kHz/192 kHz
Reserved
Description
Power-down
Function
24
20
Reserved
16
1
0
8
12
16
Reserved
Reserved
Reserved
Stereo
TDM (daisy chain)
ADC AUX mode (ADC-, DAC-, TDM-coupled)
Reserved
Latch in midcycle (normal)
Latch in at end of cycle (pipeline)
Description
Word width
High-pass filter
ADC 1L mute
ADC 1R mute
ADC 2L mute
ADC 2R mute
Output sample rate
Table 23. ADC Control 1
Bit
1:0
4:2
6:5
7
Value
00
01
10
11
000
001
010
011
100
101
110
111
00
01
10
11
0
1
Rev. B | Page 27 of 32
SDATA delay (BCLK periods)
Serial format
BCLK active edge (TDM in)
ADAU1328
Data Sheet
Table 24. ADC Control 2
Bit
0
1
2
3
5:4
6
7
Value
0
1
0
1
0
1
0
1
00
01
10
11
0
1
0
1
Function
50/50 (allows 32-/24-/20-/16-BCLK/channel)
Pulse (32-BCLK/channel)
Drive out on falling edge (DEF)
Drive out on rising edge
Left low
Left high
Slave
Master
64
128
256
512
Slave
Master
ABCLK pin
Internally generated
Rev. B | Page 28 of 32
Description
LRCLK format
BCLK polarity
LRCLK polarity
LRCLK master/slave
BCLKs per frame
BCLK master/slave
BCLK source
Data Sheet
ADAU1328
ADDITIONAL MODES
The ADAU1328 offers several additional modes for board level
design enhancements. To reduce the EMI in board level design,
serial data can be transmitted without an explicit BCLK. See
Figure 27 for an example of a DAC TDM data transmission
mode that does not require high speed DBCLK. This configuration
is applicable when the ADAU1328 master clock is generated by
the PLL with the DLRCLK as the PLL reference frequency.
To relax the requirement for the setup time of the ADAU1328
in cases of high speed TDM data transmission, the ADAU1328
can latch in the data using the falling edge of DBCLK. This
effectively dedicates the entire BCLK period to the setup time.
This mode is useful in cases where the source has a large delay
time in the serial data driver. Figure 28 shows this pipeline
mode of data transmission.
Both the BLCK-less and pipeline modes are available on the
ADC serial data port.
DLRCLK
32 BITS
INTERNAL
DBCLK
DSDATA
DLRCLK
06102-059
INTERNAL
DBCLK
TDM-DSDATA
Figure 27. Serial DAC Data Transmission in TDM Format Without DBCLK
(Applicable Only If PLL Locks to DLRCLK. This Mode Is Also Available in the ADC Serial Data Port)
DLRCLK
DBCLK
DSDATA
06102-060
DATA MUST BE VALID
AT THIS BCLK EDGE
MSB
Figure 28. I2S Pipeline Mode in DAC Serial Data Transmission
(Applicable in Stereo and TDM Useful for High Frequency TDM Transmission.
This Model Is Also Available in the ADC Serial Data Port.)
Rev. B | Page 29 of 32
ADAU1328
Data Sheet
APPLICATION CIRCUITS
LRCLK
LF
LF
39nF
+
5.6nF
2.2nF
562Ω
AVDD2
AVDD2
Figure 30. Recommended Loop Filters for LRCLK or MCLK PLL Reference
240pF
NPO
100pF
3
–
OP275
DAC OUT
+
270pF
NPO
4.7µF 237Ω
+
120pF
5
2
1
5.76kΩ
6
3
4.75kΩ 4.75kΩ
OP275
7
1nF
NPO
4.7µF 237Ω
+
+
11kΩ
ADCxP
1
604Ω 4.7µF
–
4.99kΩ
+
3.3nF
NPO
AUDIO
OUTPUT
49.9kΩ
4.99kΩ
Figure 31. Typical DAC Output Filter Circuit (Single-Ended, Noninverting)
1nF
NPO
100pF
5.76kΩ
–
ADCxN
+
OP275
DAC
OUT
68pF
NPO
2
11kΩ
3.01kΩ
CM
270pF
NPO
Figure 29. Typical ADC Input Filter Circuit
0.1µF
3
–
OP275
+
1
604Ω 4.7µF
+
2.2nF
NPO
AUDIO
OUTPUT
49.9kΩ
Figure 32. Typical DAC Output Filter Circuit (Single-Ended, Inverting)
Rev. B | Page 30 of 32
06102-025
2
06102-024
5.76kΩ
5.76kΩ
06102-023
600Z
390nF
3.32kΩ
120pF
AUDIO
INPUT
MCLK
06102-027
Typical applications circuits are shown in Figure 29 through
Figure 32. Figure 29 shows a typical ADC input filter circuit.
Recommended loop filters for LR clock and master clock as the
PLL reference are shown in Figure 30. Output filters for the
DAC outputs are shown in Figure 31 and Figure 32 for the
noninverting and inverting cases, respectively.
Data Sheet
ADAU1328
OUTLINE DIMENSIONS
0.75
0.60
0.45
9.20
9.00 SQ
8.80
1.60
MAX
37
48
36
1
PIN 1
7.20
7.00 SQ
6.80
TOP VIEW
0.15
0.05
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
SEATING
PLANE
(PINS DOWN)
25
12
13
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
24
0.27
0.22
0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
051706-A
1.45
1.40
1.35
Figure 33. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
ADAU1328BSTZ
ADAU1328BSTZ-RL
EVAL-AD1938AZ
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
48-Lead LQFP
48-Lead LQFP, 13” Tape and Reel
Evaluation Board
Package Option
ST-48
ST-48
Z = RoHS Compliant Part.
Use the EVAL-AD1938AZ as the evaluation board for the ADAU1328. The AD1938 is an automotive grade functional equivalent to the ADAU1328, featuring two
additional ADC channels.
Rev. B | Page 31 of 32
ADAU1328
Data Sheet
NOTES
©2006-2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06102-0-2/13(B)
Rev. B | Page 32 of 32