EVAL-ADAS3023EDZ User Guide
UG-515
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Evaluation Board for the ADAS3023 16-Bit, 8-Channel,
Simultaneous Sampling Data Acquisition System
FEATURES
Full-featured evaluation board for the ADAS3023
Versatile analog signal conditioning circuitry
On-board reference, clock oscillator, and buffers
Converter evaluation and development board (EVAL-CED1Z)
compatible
PC software for control and data analysis (time and
frequency domain)
KIT CONTENTS
EVAL-ADAS3023EDZ evaluation board
ADDITIONAL EQUIPMENT NEEDED
EVAL-CED1Z board
Precision signal source
World-compatible 7 V dc supply (enclosed with EVAL-CED1Z)
USB cable
EVALUATION BOARD DESCRIPTION
The EVAL-ADAS3023EDZ is an evaluation board for the
ADAS3023 16-bit data acquisition system (DAS). This device
integrates an 8-channel low leakage track and hold, a high
impedance programmable gain instrumentation amplifier (PGIA)
stage with high common-mode rejection, a precision 16-bit
successive approximation (no latency) analog-to-digital
converter, and precision 4.096 V reference. It is capable of
converting two channels simultaneously up to 500,000 samples per
second (500 kSPS) throughput.
The evaluation board is designed to demonstrate the performance of the ADAS3023 and to provide an easy-to-understand
interface for a variety of system applications. A full description
of this product is available in the product data sheet and should
be consulted when utilizing this evaluation board.
The evaluation board is intended to be used with the Analog
Devices, Inc., converter evaluation and development (CED)
board, EVAL-CED1Z, a USB-based capture board connected
to P4, the 96-pin interface.
On-board components include a high precision, buffered band
gap 4.096 V reference (ADR434), a reference buffer (AD8032),
passive signal conditioning circuitry, and an FPGA for
deserializing the serial conversion results and configuring
the ADAS3023 via a 4-wire serial interface.
The P3 connector allows users to test their own interface with
or without the optional Altera FPGA, U6 (programmed using
the P2 and passive serial EEPROM, U5).
FPGA
PROGRAMMING
PORT
ADAS3023
PROTOTYPE AREA
FPGA
96-PIN
INTERFACE
POWER
SERIAL
INTERFACE
40-PIN IDC
Figure 1. EVAL-ADAS3023EDZ Evaluation Board
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
Rev. B | Page 1 of 30
11221-001
ANALOG
INPUTS
UG-515
EVAL-ADAS3023EDZ User Guide
TABLE OF CONTENTS
Features .............................................................................................. 1
Jumpers and Test Points ...............................................................6
Kit Contents....................................................................................... 1
Evaluation Board Software ...............................................................8
Additional Equipment Needed ....................................................... 1
Software Installation .....................................................................8
Evaluation Board Description......................................................... 1
Powering Up the Board ............................................................. 11
Revision History ............................................................................... 2
Running the Software with the Hardware Connected .......... 11
Evaluation Board Hardware ............................................................ 3
Software Operation .................................................................... 12
Overview........................................................................................ 3
Time Domain Tab ...................................................................... 16
Device Description ....................................................................... 3
Histogram Tab ............................................................................ 17
Jumpers, Solder Pads, and Test Points ....................................... 3
Spectrum Tab .............................................................................. 18
Analog Interface ........................................................................... 3
Summary Tab .............................................................................. 19
FPGA .............................................................................................. 4
Evaluation Board Schematics and Artwork ................................ 20
Reference ....................................................................................... 4
Products on this Evaluation Board .............................................. 28
Evaluation Board Schematics/PCB Layout ............................... 5
Bill of Materials ........................................................................... 28
Basic Hardware Setup .................................................................. 5
Related Links ................................................................................... 30
REVISION HISTORY
9/14—Rev. A to Rev. B
Reorganized Layout ....................................................... Throughout
Changes to Reference Section ......................................................... 4
Changes to Basic Hardware Setup Section .................................... 5
Changes to Software Installation Section, System Requirements
Section, and Website Download Section ....................................... 8
Replaced Figure 4 ............................................................................. 8
Added Figure 5, Figure 6, and Figure 7, Renumbered
Sequentially ....................................................................................... 8
Removed USB Drivers Section ....................................................... 8
Added Figure 8 to Figure 13............................................................ 9
Changes to Running the Software with the Hardware
Connected Section.......................................................................... 11
Removed AC Testing Section .............................................................
Changes to Software Operation Section ...................................... 12
Added File Menu (Label 1) Section, Edit Menu (Label 2)
Section, Help Menu (Label 3) Section, Throughput (Label 4)
Section, Samples (Label 5) Section, Single Capture (Label 6)
and Continuous Capture (Label 7) Section, and Tabs Section . 12
Removed Configuring the ADAS3023 Device Section, Channel
Pairing Section, Figure 11, Figure 12, and Figure 13;
Renumbered Sequentially.............................................................. 12
Changes to Figure 18 ...................................................................... 13
Added Figure 19.............................................................................. 13
Added Figure 20 to Figure 22 ....................................................... 14
Added Figure 23.............................................................................. 15
Removed Histogram Display Section, Time Domain Display
Section, Figure 15, and Figure 16 ................................................. 14
Changes to Start Up Section and Input Channel Section,
Programmable Gain Section, and Software Controls Section....... 15
Added Time Domain Tab Section and Figure 24 ...................... 16
Changes to Histogram Tab Section and Figure 25..................... 17
Added DC Testing Section and AC Testing Section .................. 17
Changes to Spectrum Tab Section and Figure 26 ...................... 18
Changes to Summary Tab Section and Figure 27 ...................... 19
Changes to Related Links Section ................................................ 30
5/13—Rev. 0 to Rev. A
Changes to Title and Evaluation Board Description Section ......1
Changes to Device Description Section .........................................3
Removed CD-ROM Section ............................................................8
Changes to Running the Software with the Hardware
Connected Section ......................................................................... 10
Changes to Figure 10 and Changes to Start Up Section ............ 11
Changes to Figure 14...................................................................... 13
Changes to Figure 16...................................................................... 14
Changes to Figure 17...................................................................... 15
Changes to Figure 18...................................................................... 16
Changes to Figure 19...................................................................... 17
4/13—Revision 0: Initial Version
Rev. B | Page 2 of 30
EVAL-ADAS3023EDZ User Guide
UG-515
EVALUATION BOARD HARDWARE
OVERVIEW
The EVAL-ADAS3023EDZ evaluation board is designed to
offer simple evaluation of this integrated device. From a block
diagram perspective, the board uses a set of analog input test
points (or an IDC header), some passive footprints for RC
filtering and external reference, the ADAS3023 device, a serial
interface to the on-board FPGA, and power that can be
supplied locally or via EVAL-CED1Z or externally. Note that
the ADAS3023 device also has an on-chip reference; however,
external circuitry is provided for those who need to test other
suitable options.
The small prototyping area can be useful for building additional
circuitry, if desired. Each block has a specific function as
defined in the following sections.
DEVICE DESCRIPTION
Table 1. Typical Input Range Selection
Single-Ended Signals1
0 V to 1 V
0 V to 2.5 V
0 V to 5 V
0 V to 10 V
1
Manufactured using the Analog Devices patented high voltage
iCMOS® process, the ADAS3023 is a complete data acquisition
system (DAS) on a single chip that is capable of converting two
channels simultaneously up to 500 kSPS. This part allows the
differential voltage range up to ±20.48 V when using ±15 V
supplies. The ADAS3023 can resolve the full-scale differential
voltages of ±2.56 V, ±5.12 V, ±10.24 V, and ±20.48 V, and it can
be configured to sample two, four, six, or eight channels
simultaneously.
The key difference between the ADAS3022 and ADAS3023
is that the ADAS3023 does not offer the AUX± channels and
temperature sensor (using the CFG register) In addition, the
BUSY/SDO2 (Pin 19) functionality of the ADAS3023 is
different.
The ADAS3022/ADAS3023 devices become pin compatible
and can be exchanged on the same footprint if the no connect
(NC) pins (Pin 14/Pin 29/Pin 30 on the ADAS3022) and AUX±
(Pin 5 and Pin 40 on the ADAS3022) are tied to AGND, and if
the SDO2 (using the CFG register) of the ADAS3023 is not
enabled, so that the user can actually work with either one of
these options using the same evaluation board. Leaving these
pins floating is not recommended. Note that the differential
paired mode does not exist in the ADAS3023 and, therefore, its
2/4/6/8 channels are always referenced to COM.
The ADAS3023 is an ideal replacement for a typical 16-bit,
simultaneous sampling precision data acquisition system that
simplifies the design challenges by eliminating signal buffering,
level shifting, amplification/attenuation, common-mode
rejection, settling time, or any of the other analog signal
conditioning challenges while allowing smaller form factor,
faster time to market, and lower costs.
Data communication to and from the ADAS3023 occurs
asynchronously without any pipeline delay using a common
4-wire serial interface compatible with SPI, FPGA, and DSP.
A rising edge on CNV samples the differential analog inputs of
a channel or channel pair. The ADAS3023 configuration register
allows the user to configure the number of enabled channels, the
differential input voltage range, and the interface mode using the
evaluation board and software as detailed in this user guide.
Complete specifications for the ADAS3023 are provided in the
product data sheet and should be consulted in conjunction with
this user guide when using the evaluation board. Full details on
the EVAL-CED1Z are available on the Analog Devices website.
Input Range, VIN (V)
±1.28 V
±2.56 V
±5.12 V
±10.24 V
See the ADAS3023 data sheet for more information
JUMPERS, SOLDER PADS, AND TEST POINTS
Numerous solder pads and test points are provided on the
evaluation board and are detailed fully in Table 4, Table 5,
and Table 6. Note the nomenclature for this evaluation board
for a signal that is also connected to an IDC connector would
be signal_I. The two 3-pin user selectable jumpers are used for
the ADCs reference selection and are fully described in the
Reference section.
ANALOG INTERFACE
The analog interface is provided with test points for each of the
analog inputs IN[7:0] and COM (that is, IN0_I is common to
both the test point and to P1). The passive device footprints
can be used for filtering, if desired. A simple RC filter made up
of 22 Ω and 2700 pF NPO capacitors is provided. Note that
the use of stable dielectric capacitors, such as NPO or COG, is
required in the analog signal path to preserve the ADAS3023
distortion. Using X5R or other capacitors in the analog signal
path greatly reduces the performance of the system. Also, note
that many bench top arbitrary waveform generators (AWGs)
use 12-bit or 14-bit digital-to-analog converter outputs such
that the 16-bit ADAS3023 devices digitize this directly resulting
in erroneous looking data. If such an AWG is used, a high-order
band-pass filter should be used to filter the unwanted noise
from these sources.
The P31 center pin is connected to the ADAS3023 COM input,
which can be routed to P1 or GND using P31. For channel
‐to‐
COM configuration, set the jumper across Pin 1 and Pin 2 to
route to P1. For channel pairs configuration, set the jumper
across Pin 2 to Pin 3 to route to GND. This is useful for singleended applications.
For dynamic performance, an FFT test can be done by applying
a very low distortion ac source, such as an Audio Precision
System 2702. This source can be set for balanced or unbalanced,
and can be floated or grounded depending on the user’s choice.
Rev. B | Page 3 of 30
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EVAL-ADAS3023EDZ User Guide
FPGA
The on-board FPGA performs a number of digital functions,
one of them being the sample rate conversion controlled
using the software. Another function is deserializing the
serial conversion results as the CED data capture board uses
a 16-bit parallel interface. If desired, the deserialized data can
be monitored on the 96-pin edge connecter P1, BD[15:0].
The CED uses a buffered busy signal, BBUSY, as the general
interrupt for the data transfer to the CED board.
buffered with U20, the AD8032; both of these are set to the
factory default setting.
Table 2. Factory Reference Jumper Configuration
Jumper
Setting
P5
P9
REFIN to GND1
REF to BUF (U20)
1
The connection is made through R102 = 10 k to GND.
To use another reference source, there are two methods:
The FPGA also provides the necessary ADAS3023 asynchronous control signals for RESET and power down (PD).
•
For an external unbuffered reference, remove the P9
jumper and connect a source to the REF test point.
The signals from the FPGA to the ADAS3023 can be bypassed
by modifying the default solder pad connections. As shown in
Figure 2, each digital signal on the ADAS3023 is connected to
the larger (top) pad of the three. The default configuration is
the small pad and larger pad (no text) which connects the
FPGA to the ADAS3023 (CNV, BUSY, and SDO signals
shown). The labeled pads, CNV_I, BUSY_I, SDO_I, and so on,
are the signals that are routed to P3. To use P3 instead of the
FPGA, unsolder the default connections and resolder from the
large pad to the xxx_I pads. The FPGA will remain powered;
however, if all the signals are bypassed in this fashion, it will not
have any influence on the ADAS3023.
•
Since the ADR434 is a standard 8-lead SOIC, it can also
be removed and replaced with the user’s reference. In this
case, the user reference and the U20 AD8032 buffer can
be used as a reference source.
DEFAULT
Internal 4.096 V Reference
The ADC has an internal 4.096 V precision reference and
can be used on most applications. When enabled, 4.096 V will
be present on the ADAS3023 REFx pin and test point, REF.
In addition, a voltage will also be present on the ADAS3023
REFIN pin and test point, REFIN. The voltage present on
REFIN can be used for other purposes, such as to provide the
bias voltage; however, it would need a suitable buffer as the
output impedance of the REFIN is on the order of a few kilo
ohms and loading this voltage down will degrade the internal
reference’s performance.
Table 3. Internal Reference Jumper Configuration
11221-003
CONNECTION TO P3
Setting
P5
P9
Open
Open
Note that the ADAS3023 configuration register needs to be
updated either using the included software or by writing the
appropriate bits to enable the internal reference.
Figure 2. Digital Interface Solder Pads—Partial View
Serial Interface
The 4-wire serial interface consisting of CS, DIN, SCK, and
SDO is present on the digital interface test points and is
controlled by the FPGA. The FPGA can be bypassed by using
the solder pads.
REFERENCE
The ADAS3023 has an internal 4.096 V reference, along with an
internal buffer, useful for using an external reference or one can
use an external 4.096 V reference directly, such as the ADR434
provided on the evaluation board. The evaluation board can be
configured to use any of these references. Two jumpers (P5
and P7) are used for setting the reference in conjunction with
software control.
External Reference–Factory Configuration
The evaluation board includes the ADR434, A1, which is a
4.096 V precision voltage reference. This reference can drive
the ADC REF1 or REF2 (REFx) pin directly or it can also be
Jumper
Internal Reference Buffer
The internal reference buffer is useful when using an external
2.5 V reference. When using the internal reference buffer,
applying 2.5 V to REFIN, which is directly connected to the
ADC’s REFIN pin, produces 4.096 V at the ADCs REFx pin
and REF test point.
POWER SUPPLIES AND GROUNDING
The on-board ADP3334 low dropout regulators are provided
for 2.5 V, 3.3 V, and 5 V and also for the FPGA I/O supply
which is user configurable and set to 3.3 V by default. The
FPGA core is supplied by a pair of ADP1715 devices set for
1.2 V. Additional power is supplies via the CED board for an
alternative +5 V analog and digital 3.3 V/5 V digital through P4.
Rev. B | Page 4 of 30
EVAL-ADAS3023EDZ User Guide
UG-515
Figure 3 shows a photograph of the connections made between
the ADAS3023 daughter board and the EVAL-CED1Z board.
The ADAS3023 requires ±15 V supplies for VDDH and VSSH.
These must be supplied by the user using a standard lab supply
ensuring that the return paths are at the same potential. Refer to
CN-0201 for the complete information on generating these
±15 V supplies from a +5 V single supply. The differential input
common-mode voltage (VCM) range changes according to the
maximum input range selected and the high voltage power
supplies (VDDH and VSSH). In other words, the specified
operating input voltage of any input pin requires 2.5 V of
headroom from the VDDH and VSSH supplies.
3.
The evaluation board ground plane consists of a solid plane
on one PCB layer shared on another layer with the power plane.
To attain high-resolution performance, the board was designed
to ensure that all digital ground return paths do not cross the
analog ground return paths, that is, all analog on one side and
digital on the other.
4.
1.
2.
EVALUATION BOARD SCHEMATICS/PCB LAYOUT
The evaluation board is a 6-layer board carefully laid out and
tested to demonstrate the specific high accuracy performance
of the ADAS3023 devices. The Evaluation Board Schematics
and Artwork section of this user guide shows the schematics of
the evaluation board.
Before connecting power, ensure that the EVALADAS3023EDZ and the EVAL-CED1Z boards are
connected firmly together.
Connect the power supplies on the EVAL-ADAS3023EDZ
board. The EVAL-ADAS3023EDZ requires external power
supplies of ±15 V. Connect them from a bench top power
supply.
Connect the EVAL-CED1Z board to the PC via the USB
cable enclosed in the EVAL-CED1Z kit. If using a
Windows® XP platform, you may need to search for the
EVAL-CED1Z drivers. Choose to automatically search for
the drivers for the EVAL-CED1Z board if prompted by the
operating system.
Proceed to the Software Installation section to install the
software. Note that the EVAL-CED1Z board must not
be connected to the PC’s USB port until the software is
installed. The 7 V dc supply can be connected, however,
to check that the board has power (green LED lit).
BASIC HARDWARE SETUP
The ADAS3023 evaluation board connects to the EVAL-CED1Z
converter evaluation and demonstration board. The EVALCED1Z board is the controller board, which is the communication link between the PC and the main evaluation board.
EVAL-CED1Z
PC
EVAL-ADAS3023EDZ
SIGNAL SOURCE
USB
11221-002
TO WALL WART
Figure 3. Hardware Configuration—Setting Up the EVAL-ADAS3023EDZ
Rev. B | Page 5 of 30
UG-515
EVAL-ADAS3023EDZ User Guide
JUMPERS AND TEST POINTS
Three-pin jumpers are used to configure the ADC reference. Refer to the Reference section for further details and settings.
Table 4. Pin Jumper Descriptions
Jumper
P5
Default
REFIN to
GND
P7
REF to
BUF
P31
COM to
PIN 1
Function
REFIN Select. Buffered reference input selection. Use in conjunction with P7.
Note that the ADAS3023 REFx pin and any other circuit traces/test points will produce 4.096 V when using the
buffered reference configuration; P7 must be left in the open position.
REFIN to A2: Uses the on-board ADR381, A2 (2.5 V) reference. The ADAS3023 must use the buffered reference
configuration.
REFIN to GND: Disables the ADAS3023 internal reference. The ADAS3023 must use the full external reference
configuration.
Open: For use either when using the ADAS3023 on-chip reference or when applying an external 2.5 V source. When
using the on chip reference, a voltage is present on Pin 2 and any other circuit traces/test points. When using an
external source, the ADAS3023 must use the buffered reference configuration.
REF Select. External 4.096 V reference input selection. Use in conjunction with P5. Note that the ADAS3023 REFIN
pin and any other circuit traces/test points produce 2.5 V when using the internal or external reference
configuration and P5 must be left in the open position.
REF to A1: Uses the on-board ADR434, A1 (4.096 V), reference. The ADAS3023 must use the external reference
configuration.
REF to BUF: Uses the on-board ADR434 followed by the AD8032, U20 unity gain buffer. This allows some adjustment
to the reference voltage by use of some resistors around the AD8032. The ADAS3023 must use the external
reference configuration.
Open: For use when using the ADAS3023 on-chip reference or an externally applied source connected directly to
Pin 2 or the REF test point.
COM Input Select. Center pin connected to ADAS3023 COM pin. Center pin to PIN1 routes COM to P1. Center to
PIN3 routes COM to GND.
Solder pads jumpers are factory configured and can be changed by the user.
Table 5. Analog and Digital Solder Pads Descriptions
Jumper
P9
P16
P17
P18
P19
P27
P28
P29
P25
Name
SDO
DIN
CNV
SCK
BUSY
RESET
PD
CS
DSPCLK
Default
1 to 3
1 to 3
1 to 3
1 to 3
1 to 3
1 to 3
1 to 3
1 to 3
Soldered
Function
SDO Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P34.
DIN Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P35.
CNV Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P36.
SCK Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P33.
BUSY Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P37.
RESET Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P38.
PD Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P39.
CS Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P40.
CED Clock Source.
Rev. B | Page 6 of 30
EVAL-ADAS3023EDZ User Guide
UG-515
Table 6. Power Supply Solder Pads
Jumper
P6
P13
P8
P10
P11
P12
Name
VDDH
VSSH
AVDD
–
–
VIO
Default
Soldered
Soldered
+5VA
Soldered
Soldered
Open
P14
P15
P33
P34
P35
P22
P23
P24
P26
P30
DVDD
VDRVVDRV+
U4 V+
U4 V−
−15V
−5VA
+5VA
+5VD
+15V
+5VD
−5VA
+5VA
VDRV+
VDRV−
Soldered
Soldered
Soldered
Soldered
Soldered
Function
VDDH Supply.
VSSH Supply.
AVDD Supply. Selection of +5 V A, analog supply from the CED board or +5 V from U3.
VIO Supply. This solder pad can be used to power the FPGA VIO and ADAS3023 VIO together.
FPGA VIO Supply. Supplied from U8, 3.3 V, dedicated digital supply.
VIO Supply. Selection of 2.5 V (2V5), 3.3 V (3V3), or DVDD (5V). Note that the ADAS3023 digital outputs are set to
this level and are directly wired to the FPGA, U6, which is 3.3 V max. When using the 5 V setting, the ADAS3023
outputs, SDO and BUSY must be resistively divided using the 0603 pads provided on the evaluation board. For
this reason, P10 is used as the default.
DVDD Supply. Selection of +5 V digital, +5 V D, and +5 V from U3.
U20 V−/P34 Supply. Selection of −5 V A, analog supply from the CED board or GND.
U20 V+/P35 Supply. Selection of +5 V A, analog supply from the CED board or +5 V from U3.
U4 V+ Supply. Selection of VDRV+ or U2.
U4 V− Supply. Selection of VDRV− or GND.
−15 V CED Supply.
−5 V A (Analog) CED Supply.
+5 V A (Analog) CED Supply.
+5 V D (Digital) CED Supply.
+15 V (Analog) CED Supply.
Table 7. Test Points (By Signal Type)
Test Point
IN0_I
IN1_I
IN2_I
IN3_I
IN4_I
IN5_I
IN6_I
IN7_I
COM_I
REF
REFIN
CNV
BUSY
SDO
SCK
PD
RESET
DIN
CSB
MSCL
VDDH
VSSH
AVDD
DVDD
VIO
+5VA
−5VA
+15V
−15V
+5VD
GND(s)
Type
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Digital Input
Digital Output
Digital Output
Digital Input
Digital Input
Digital Input
Digital Input
Digital Input
Digital Output
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Description
Path for IN0 Input.
Path for IN1 Input.
Path for IN2 Input.
Path for IN3 Input.
Path for IN4 Input.
Path for IN5 Input.
Path for IN6 Input.
Path for IN7 Input.
Path for COM Input.
Direct Connection to ADAS3023 REFx Pin.
Direct Connection to ADAS3023 REFIN Pin.
Direct Connection to ADAS3023 CNV Pin.
Direct Connection to ADAS3023 BUSY Pin.
Direct Connection to ADAS3023 SDO Pin.
Direct Connection to ADAS3023 SCK Pin.
Direct Connection to ADAS3023 PD Pin.
Direct Connection to ADAS3023 RESET Pin.
Direct Connection to ADAS3023 DIN Pin.
Direct Connection to ADAS3023 CS Pin.
Eval Board Master Clock Form Y3, 100 MHz Oscillator.
Direct Connection to ADAS3023 VDDH Pin.
Direct Connection to ADAS3023 VSSH Pin.
Direct Connection to ADAS3023 AVDD Pin.
Direct Connection to ADAS3023 DVDD Pin.
Direct Connection to ADAS3023 VIO Pin.
Connected to P24; CED +5 V A.
Connected to P23; CED −5 V A.
Connected to P30; CED +5 V A.
Connected to P22; CED −5 V A.
Connected to P26; CED +5 V D.
Connected to Eval Board GND Plane.
Rev. B | Page 7 of 30
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EVAL-ADAS3023EDZ User Guide
EVALUATION BOARD SOFTWARE
SOFTWARE INSTALLATION
Close major Windows applications prior to installing the software.
System Requirements
•
•
•
Windows® XP (SP2, 32-bit), Windows Vista® (32-bit or
64-bit), or Windows 7 (32-bit or 64-bit)
USB 2.0 (for CED board)
Administrator privileges
The evaluation board software is available for download from
the evaluation board page on Analog Devices website. Click the
setup.exe file to run the install. The default location for the
software is C:\Program Files (x86)\Analog Devices\
ADAS3023 Evaluation Software.
11221-205
Website Download
Figure 5. ADAS3023 Evaluation Software Destination Directory
To ensure that the evaluation system is correctly recognized
when connected to the PC, install the evaluation software
before connecting the evaluation board and the EVAL-CED1Z
board to the USB port of the PC.
There are two portions of the software installation process:
•
•
ADAS3023 evaluation board software installation
EVAL-CED1Z board driver installation
Figure 4 to Figure 9 show the separate steps to install the
ADAS3023 evaluation software. Figure 10 to Figure 12 show
the separate steps to install the EVAL-CED1Z drivers.
11221-206
Proceed through all of the installation steps to allow the
software and drivers to be placed in the appropriate locations.
Only connect the EVAL-CED1Z board to the PC after the
software and drivers are installed.
11221-204
11221-207
Figure 6. ADAS3023 Evaluation Software License Agreement
Figure 7. ADAS3023 Evaluation Software Start Installation
Evaluation
Figure 4. ADAS3023 Evaluation Software Installer
Rev. B | Page 8 of 30
UG-515
11221-211
11221-208
EVAL-ADAS3023EDZ User Guide
Figure 8. ADAS3023 Evaluation Software, Installation in Progress
11221-209
Figure 11. CED Drivers Install Setup Wizard, Installation in Progress
11221-212
Figure 9. ADAS3023 Evaluation Software Installer, Installation Complete
11221-213
Figure 12. CED Drivers Install Setup Wizard, Installation Complete
11221-210
Figure 13. Computer Restart Notice
Figure 10. CED Drivers Install Setup Wizard
Rev. B | Page 9 of 30
UG-515
EVAL-ADAS3023EDZ User Guide
On some PCs, the Found New Hardware Wizard may open. If
so, follow the same procedure to install it properly.
The USB device can be opened to view the uninstalled
properties.
11064-006
The Device Manager can be used to verify that the driver was
installed successfully.
Figure 14. Device Manager
Troubleshooting the Installation
11064-008
If the driver was not installed successfully, the Device Manager
displays a question mark for Other devices because Windows
does not recognize the EVAL-CED1Z board.
Figure 16. USB Device Properties
11064-007
This is usually the case if the software and drivers were installed
by a user without administrator privileges. If so, log on as an
administrator with full privileges and reinstall the software.
Figure 15. Device Manager Troubleshooting
Rev. B | Page 10 of 30
EVAL-ADAS3023EDZ User Guide
UG-515
POWERING UP THE BOARD
The evaluation board, as configured from the factory, uses the
local LDOs for power where necessary. A ±15 V dc lab supply
must be connected to the board. Test points (yellow and white)
are provided for these external supplies.
This evaluation software is located at <local_drive>:\Program
Files\Analog Devices\ADAS3023 Evaluation Software.
To launch the software, click Start>All Programs>Analog
Devices\ADAS3023 Evaluation Software. You can then apply
the signal source and capture the data.
To uninstall the program, click Start>Control Panel>Add or
Remove Programs>Analog Devices ADAS3023 Evaluation
Software.
11221-009
See Figure 19 to Figure 27 for further details and features of the
software.
Figure 17. Test Points
RUNNING THE SOFTWARE WITH THE HARDWARE
CONNECTED
The evaluation board includes software for analyzing the
ADAS3023. The EVAL-CED1Z is required when using the
software. The software is used to perform the following tests:
•
•
•
Histogram tests for determining code transition noise (dc)
Time domain analysis
Fast Fourier transforms (FFT) for signal-to-noise ratio
(SNR), SNR and distortion (SINAD), total harmonic
distortion (THD), and spurious free dynamic range (SFDR)
Rev. B | Page 11 of 30
UG-515
EVAL-ADAS3023EDZ User Guide
SOFTWARE OPERATION
Throughput (Label 4)
This section describes the full software operation and all windows
that appear. When the software is launched, the panel opens
and the software searches for hardware connected to the PC.
The user software panel launches, as shown in Figure 18. The
labels listed in this section correspond to the numbered labels
in Figure 18.
The default throughput (sampling frequency) is 104 kSPS. The
ADAS3023 is capable of operating a maximum sample
frequency up to 1000 kSPS.
File Menu (Label 1)
The File menu, labeled 1 in Figure 18, provides the following:
•
•
•
•
Save Captured Data saves data to a .csv file.
Take Screenshot saves the current screen.
Print prints the window to the default printer.
Exit quits the application.
Help Menu (Label 3)
The Help menu, labeled 3 in Figure 18, offers help from the
following sources:
•
•
•
•
Single Capture (Label 6) and Continuous Capture
(Label 7)
Tabs
There are four tabs available for displaying the data in different
formats.
The Edit menu, labeled 2 in Figure 18, provides the following:
Initialize to Default Values: This option resets the
software to its initial state.
Select the number of Samples to analyze when running the
software. This number is limited to 65,536 samples.
Single Capture performs a single capture, whereas Continuous
Capture performs a continuous capture from the ADC.
Edit Menu (Label 2)
•
Samples (Label 5)
•
•
•
•
Time Domain
Histogram
Spectrum
Summary
To exit the software, click File>Exit.
Analog Devices website
User Guide
Context Help
About
Rev. B | Page 12 of 30
EVAL-ADAS3023EDZ User Guide
3
5
6
7
10
4
9
8
11
11221-218
2
Figure 18. Setup Screen
11221-219
1
UG-515
Figure 19. Dialog Box for Label 8, Number of Input Channels Settings
Rev. B | Page 13 of 30
EVAL-ADAS3023EDZ User Guide
11221-220
UG-515
11221-222
Figure 20. Dialog Box for Label 9, PGIA Settings
11221-221
Figure 21. Dialog Box for Label 10, Conversion Mode Settings
Figure 22. Dialog Box for Label 10, SDO2/BUSY Settings
Rev. B | Page 14 of 30
UG-515
11221-223
EVAL-ADAS3023EDZ User Guide
Figure 23. Dialog Box for Label 11, Reference Settings
Start Up
Refer to the numbered labels in Figure 18. Click the blue
buttons to reveal the dialog boxes shown in Figure 19 through
Figure 23.
To begin evaluating the device, the on-board supplies must be
enabled.
•
•
•
•
•
RESET resets the ADAS3023 device to a known state.
Click RESET twice: once to reset the ADAS3023 and
again to bring it out of the reset state. Note that the
CFG is also reset to the default condition.
Reference Selection: At this time, it is recommended
to use the evaluation board’s externally generated
reference (default). To select the on-chip reference,
remove the P5 and P7 jumpers and click the button in
the REF block to display the Reference Settings
dialog box, then choose REFERENCE ENABLED.
PD (0) places the ADAS3023 device in power-down.
This does not need to take place when starting the
software.
Serial Data Output 2 (SDO2) Option: The ADAS3023
busy signal is always output on the BUSY/SDO2 pin
when CS is logic high. If SDO2 is enabled when CS is
brought low after the EOC, the SDO outputs the data
from Channel 0, Channel 1, Channel 2, and Channel 3
and SDO2 outputs the data from Channel 4, Channel 5,
Channel 6, and Channel 7 after 16 SCK rising edges.
The conversion result output on this pin synchronizes
to the SCK falling edges. Click SDO2 DISABLED
once to display SDO2 ENABLED.
Click OK: If the default configuration (number of
channels, PGIA, reference, and SDO2 settings) is
acceptable, clicking OK writes to the ADAS3023
configuration register (CFG). The ADAS3023 device
is configurable using a 16-bit on-chip register, CFG
(refer to the ADAS3023 data sheet for more details).
Note that after changing any of the CFG register
settings, OK button must be clicked for the new
setting to take effect.
Input Channel
To select the number of input channels to be simultaneously
sampled, make a selection from the pull-down menu. (see
Figure 19).
Programmable Gain
The most useful and innovative feature of the ADAS3023 is the
on-chip programmable gain instrumentation amplifier. This
amplifier has the added flexibility of allowing for inputs ranging
from ±2.56 V to ±20.48 V. Select the appropriate setting for the
input voltage span, not including any common-mode signals,
since they are rejected. Note that the ADAS3023 devices do not
need the usual level shifting that is common in SAR ADC
systems. The ADAS3023 devices can accommodate singleended unipolar and bipolar input signal types.
Software Controls
Within any of the chart panels, these controls are used to
control the display.
Rev. B | Page 15 of 30
Controls the cursor.
Controls zooming in and out.
Controls panning.
UG-515
EVAL-ADAS3023EDZ User Guide
TIME DOMAIN TAB
11221-224
Figure 24 illustrates the Time Domain tab. The ADAS3023
output is twos complement output; however, the software
outputs the results in straight binary.
Note that Label 1 shows the Waveform Analysis that reports
the amplitude recorded from the captured signal in addition to
the frequency of the signal tone, and Label 2 shows that Y-axis
units can be displayed in volts or code (LSB).
Figure 24. Time Domain Tab
Rev. B | Page 16 of 30
EVAL-ADAS3023EDZ User Guide
UG-515
HISTOGRAM TAB
The histogram is most often used for dc testing or ac testing,
where a user tests the ADC for the code distribution for dc input
and computes the mean and standard deviation, or transition
noise, of the converter, and displays the results. Raw data is
captured and passed to the PC for statistical computations.
Figure 25 shows the Histogram tab.
To perform a histogram test,
1.
Select the Histogram tab.
2.
Click Single Capture or Continuous Capture.
DC Testing
filter the signal to make the dc source noise compatible with
that of the ADC. Note that 0805 and 0603 SMT pads are
provided in each signal path and can be used for filtering the
source, if necessary.
AC Testing
Figure 25 shows the histogram for a 1 kHz sine wave applied to
the analog inputs IN[7:0]_I via test points or P1 from a quality
precision signal source, such as Audio Precision. It may be
required to filter the input signal from the ac source. There is no
suggested band-pass filter, but consider all choices carefully.
The Waveform Analysis (Label 1) chart displays the various
measured histogram values for the ADAS3023.
11221-225
To test other dc values, apply a source to the selected analog
inputs IN[7:0]_I via test points or P1. It may be required to
Figure 25. Histogram Tab
Rev. B | Page 17 of 30
UG-515
EVAL-ADAS3023EDZ User Guide
SPECTRUM TAB
Figure 26 shows the FFT spectrum capture tab. This tab tests
the traditional ac characteristics of the converter and displays a
fast Fourier transform (FFT) of the results. As in the histogram
test, raw data is captured and passed to the PC where the FFT is
performed, displaying SNR, SINAD, THD, and SFDR.
•
•
The top part of the image displays the FFT results
including SNR, dynamic range, THD, SINAD, and noise
performance (see Label 1).
The lower part of the image displays the fundamental
frequency and amplitude in addition to the 2nd to 5th
harmonics (see Label 2).
11221-226
To perform an ac test, apply a sinusoidal signal to the evaluation
board to any pair of the analog inputs IN[7:0]_I, either via test
points or P1. Very low distortion—a better than 130 dB input
signal source, such as Audio Precision)—is required to allow
true evaluation of the part. One possibility is to filter the input
signal from the ac source. There is no suggested band-pass
filter, but carefully consider the choices. Figure 26 displays the
results of the captured data.
Figure 26. FFT Spectrum with FFT Results (Top) and with Harmonic Content Results (Bottom)
Rev. B | Page 18 of 30
EVAL-ADAS3023EDZ User Guide
UG-515
SUMMARY TAB
11221-227
Figure 27 shows the Summary tab, which summarizes all the
data capture information and displays it in one panel with a
synopsis of the information, including key performance
parameters such as SNR, THD, and SINAD.
Figure 27. Summary Tab
Rev. B | Page 19 of 30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
P1
GND
AUX–I
GND
DNI
R61
50Ω
1
GND
DNI
R60
50Ω
IN0_I
BLU
AUX+I
3M30326-6002HB
1
GND
COM_I
BLU
1
CH4I
GND
DNI
R66
50Ω
1
COMI
CH7I
GND
DNI
R67
50Ω
GND
DNI
R68
50Ω
1
R39
90.9Ω
0Ω
GND
0Ω
C56
TBD0805
R40
90.9Ω
R49
C55
TBD0805
R48
GND
2 TBD0805
C54
90.Ω9
0Ω
DNI 1
R38
C10
2700pF
R47
DNI
GND
GND
90.9Ω
0Ω
C53
2700pF
R37
R46
DNI
C52
2 TBD0805
90.9Ω
0Ω
DNI 1
C48
GND
C50
2700pF
GND
C49
2700pF
2 TBD0805
DNI 1
C47
2700pF
GND
GND
C46
2700pF
C64
2 TBD0805
C63
2700pF
GND
C62
2700pF
C51
2700pF
R36
DNI 1
C61
2 TBD0805
DNI 1
C60
2700pF
GND
GND
C59
2700pF
GND
R45
DNI
C58
2 TBD0805
DNI 1
C57
2700pF
GND
GND
GND
90.9Ω
90.9Ω
R34
0Ω
2700pF
2 TBD0805
C5
C4
2700pF
R35
DNI
DNI
DNI
R44
0Ω
R43
GND
GND
R51
90.9Ω
0
C3
2700pF
R42
DNI
2 TBD0805
C2
R50
DNI 1
90.9Ω
C1
2700pF
GND
0
DNI
PSTRNKPE4117
GND
2 3 4 5
R41
IN4_I
BLU
CH3I
IN6_I
1 BLU
GND
DNI
R65
50Ω
IN7_I
BLU
CH6I
GND
DNI
R64
50Ω
CH1I
CH2I
IN3_I
1 BLU
IN5_I
1 BLU
CH5I
GND
DNI
R63
50Ω
IN2_I
1 BLU
GND
DNI
R62
50Ω
CH0I
PSTRNKPE4117
GND
2 3 4 5
IN1_I
1 BLU
PSTRNKPE4117
P31
IN7
IN6
IN5
IN4
IN3
IN2
IN1
IN0
1
AUX–
VSSH
AUX+I
AUX–I
COM
COM_2
GND
1
IN7
1
IN6
1
IN5
1
IN4
1
IN3
1
IN2
1
IN1_2
1
IN0_2
VDDH
VSSH
R82
AUX–I
BLU
VCM_AUX
R33
49Ω9
GND
VCM_AUX
TBD0805
R95
R52
TBD0805
499Ω
1
GND
R81
TBD0805
R80
TBD0805
1
AUX+I
BLU
PD
DIG1
RESET
DIN
CSB
IN0 1
IN1 2
IN2 3
IN3 4
AUX+ 5
IN4 6
IN5 7
IN6 8
IN7 9
COM 10
TBD0402
R94
GND
C38C92
0.1µF
0.1µF
DUT CIRCUITS
GND
ADAS3XXX
R85
R86
GND
R54
499Ω
GND
499Ω
R84
TBD0805
GND
GND
R53
499Ω
499Ω
R38
TBD0805
GND
GND
AVDD
DVDD
ACAP
DCAP
SCK
VIO
SDO
BUSY_AUX
CNV
499Ω
U4
R87
1
TBD0805
U4
7
ADA4841-2YRZ
5
499Ω
R88
TBD0805
C94
DNI
ADA4841-2YRZ
6
3
2
30
29
28
27
26
25
24
23
22
21
REFIN
GND
GND
22Ω
R58
R79
499Ω
22Ω
R57
IN0
IN1
IN2
IN3
AUX+
IN4
IN5
IN6
IN7
COM
ACAP
1 YEL
GND
+2.5V
P20
1
2
3
4
4PJUMPER
DCAP
1 YEL
AUXPARTFOOTPRINT
GND
AUX+
GND
AUX–
C91
TBD0805
DNI
COMMON MODE CAP
1
2
3
4
5
6
7
8
9
10
11
12
GEN_QFN40_6X6_PAD
C93
U7
RCAP
REF
RCAP
1 YEL
RCAP
2 3 4 5
ACAP
COM
1 COMI
R71
R2
IN1
1 CH1I
C41
DCAP
IN0
1 CH0I
1
2
3
PAD
40
39
38
37
36
35
34
33
32
31
C42
AUX–
VDDH
VSSH
TBD0603
TBD0603
C43
C44
11
12
13
14
15
16
17
18
19
20
TBD0805
TBD0805
REF
REFIN
RCAP
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
U9
GND
AVDD
DVDD
ACAP GND
DCAP
C68
TBD0603
C67
TBD0603
ADA4841-2YRZ
AMPVEE
U4
8
V+
V–
4
10µF
C84
10µF
C72
0.1µF
C71
0.1µF
C70
0.1µF
GND
GND
P35
1
2
3
P34
1
2
3
C77
0.1µF
C76
0.1µF
C75
0.1µF
AMPVEE
DO NOT INSTALL IF VEE = GND
P
C89
0.1µF N
P
C45
0.1µF N
AMPVCC
RCAP
ACAP
AVDD
SUPPLY DECOUPLING
PLACE CLOSE TO THE DUT
GND
C47
10µF
C96
10µF
C73
0.1µF
REF DECOUPLING
C65
0.1µF
C66
TBD0603
REF
REF
REFIN
GEN_48LQFP
36
35
34
33
32
31
30
29
28
27
26
25
AMPVCC
CSB
DIN
RESET
DIG1
PD
SCK
VIO
SDO
BUSY_AUX
CNV
Rev. B | Page 20 of 30
2700pF
Figure 28. Schematic, DUT, Analog
2700pF
VDRV–
GND
VDRV+
AUX_AMPVCC
AMPVCC
C81
TBD0603
VIO
C80
TBD0603
DCAP
AMPVEE
C82
10µF
C79
TBD0603
DVDD
C78
0.1µF
UG-515
EVAL-ADAS3023EDZ User Guide
EVALUATION BOARD SCHEMATICS AND ARTWORK
11221-020
P14
VSSH
+3.3V
DVDD
+2.5V
GND
AVDD
BLU
P12
VIO
GND
C15
10µF
GND
C16
10µF
GND
+15V
–15V
GND
+15V
P33
VIO_FPGA
EN_5V_N
+5VA
+5V
VIO
1 BLU
VDRV1 BLU
GND
C14
10µF
DVDD
1 BLU
GND
C13
10µF
VDRV–
AVDD
1
C12
10µF
GND
VSSH
1 BLU
VIO_FPGA
0Ω
2
10kΩ
R11
–5VA
0Ω
+5VD
+5VD
+5VD
1 RED
GND
C23
10µF
VDRV+
BLU
1
R90
R24
-5VA
–5VA
1 WHT
1
10kΩ
R10
VDRV+
+5VA
RED
+5VA
GND
+15V
–15V
GND+5VA
GND1
+15V
-15V
GND
1 BLK 1 YELWHT 1
1 BLK
1
–5VA
P15
+5VD
+5VDVDD
+5VA
+5V
P8
–15V
P13
C11
10µF
GND
TBD0805
R25
R69
2.2µF
GND
GND
GND
GND
GND
GND2
GND3
1 BLK 1 BLK
GND
GND
GND
GND6
GND5
BLK 1 BLK
2.2µF
1
GND
U3
ADP3334ACPZ
7 IN1 OUT1 1
8
2
IN2 OUT2
6
3
SD_N FB
PAD GND
5
PAD
GND
C29
AVDD
+15V
C30
1 2
+15V
C26
TBD0805 C27
1 2
1000pF
2
1000pF
EN_3.3V_N
R13
140kΩ
1
C32
JP1
2
0
0Ω
R22
64.9kΩ
210kΩ
C33
1
2
1
2
1
2
3
1
2
3
1
2
3
+5V
+3.3V
AVDD
0Ω
+15V R96
VIO_FPGA
EN_2P5V_N
GND
GND
3
VDD_REF381
1 RED
A2
ADR381ARTZ
1 VIN VOUT 2
GND
TP
TP1
VIN
NC2
NC1 VOUT
GND TRIM
8
7
6
5
1
0Ω
2
R97
R12
10kΩ
TBD0805
1
R91
1
P5
1
2
3
JP2
2
0
REF381_OUT
RED
ADR434ARMZ
1
2
3
4
A1
EXTERNALREFERENCE
0Ω
1 R20 2
2.2µF
2.2µF
VDDH
1
2
3
4
1
2
3
GND
R102
10kΩ
REFIN
REFIN
1 RED
10
R23
R98
10kΩ
TBD0805
C28
C85
GND
0Ω
R92
TBD0805
DNI
GND
1 R21 2
0Ω
0Ω
–IN
OUT 1
3 +IN
AD8032
2
U20
0kΩ
R7
C83
TBD0805
+2.5V
1
REF
RED
FPGA SUPPLIES
GND
U11
R5 ADP1715ARMZ-R7
1kΩ 1
EN
2 IN
OUT 3
4 ADJ
GND
R6
5 6 7 8
2kΩ
LDO ADJUSTED TO 1.2V
GND
U10
R3
ADP1715ARMZ-R7
1kΩ
1 EN
2 IN
OUT 3
4 ADJ
GND
R4
5 6 7 8
2kΩ
LDO ADJUSTED TO1.2V
1 R8 2
0Ω
1 R9 2
0Ω
REF
GND
C88
0.1µF
R28
59K
36.5kΩ
R27
GND
8
+VS
–VS
4
VDRV+
0
GND
–IN
OUT 7
5 +IN
AD8032
6
R70
GND
REGULATES FPGA VIO SUPPLIES TO 3.3V (MAX ALLOWED)
U8
ADP3334ACPZ
+5VD
7 IN1 OUT1 1
8 IN2 OUT2 2
6 SD_N FB 3
R55
140kΩ
PAD GND
5
PAD
+5VD
+5VD
U20
AD8032
R101 AUX_AMPVCC
REFIN CONNECTION:
OPEN: INTERNAL 2.5V BAND GAP
1:EXTERNAL 2.5V BAND GAP, INT REF BUF
3:EXTERNAL 4.096 REFERENCE,
INT REF BUF DISABLED
P7
REF
0Ω
DNI
R93
GND
PAD GND
5
PAD
U2
ADP3334ACPZ
7 IN1 OUT1 1
8 IN2 OUT2 2
6 SD_N FB 3
GND
7 IN1 OUT1 1
8 IN2 OUT2 2
6
3
SD_N FB
PAD GND
5
PAD
U1
ADP3334ACPZ
R29
1 R14 2
78.7kΩ
1 R152
1 R16 2
C31
C86
TBD0805
+15V
C37
R99
1 R19 2
0Ω
C35
C17
R26
2.2µF
DNI
1 2
1000pF
1000pF
C40
U12
ADP3334ACPZ
7 IN1 OUT1 1
8
2
IN2 OUT2
6
3
SD_N FB
PAD GND
5
PAD
C36
C87
1 R17 2
300kΩ
C34
TBD0805 TBD0805
VDDH
1 BLU
0.1µF
2.2µF
2.2µF
R1
C19
1 2
P6
10µF
0.1µF
C39
1 R18 2
60.4kΩ
R100
C24
1 2
C25
1 2
ANALOG SUPPLIES
C20
3
2
1
Rev. B | Page 21 of 30
TBD0805
Figure 29. Schematic, Power
0.1µF
TBD0805
2.2µF
2.2µF
2
2
2
2
C18
1 2
C7
2.2µF
2.2µF
2.2µF
C21
1 2
C22
1 2
C8
0.1µF
0.1µF
2.2µF
2.2µF
1000pF
1
VCM_AUX
R56
1
1
C9
1
78.7kΩ
1
2.2µF
SUPPLYOPTIONS
VIO_FPGA
VPLL
VFPGA
EVAL-ADAS3023EDZ User Guide
UG-515
11221-021
GND
C107
100pF
0Ω
R31
CSB
PD
RESET
VIO
BUSY_AUX R30
0Ω
CNV
DIN
VIO
VIO
R128
0Ω
VIO
10kΩ
R126
GND
GND
GND
GND
GND
GND
15kΩ
DNI
GND
10kΩ
DNI
R32
R125
R72
R73
R74
3
2
1
P16
P17
DIN_I
SDO_I
P19
CNV_I
P27
BUSY_I
P28
RESET_I
P29
PD_I
CSB_I
0.1µF
C108
5
CNV
DIN
SCK
SDO
CNV
1 BLU
DIN
1 BLU
SCK
1 BLU
SDO
1 BLU
VIO_FPGA
U6
ASDI
ASDO C3
D4
GND
F3
4 EPCS4SI8N
E1
E2
GND
K2
K1
K4
K5
M1
L1
F4
N_CSO
L2
J4
M2
M3
N1
N2
L3
P1
P2
P3
C1
L4
M4
C2
D5
EN_3.3V_N
E5
E3
EN_5V_N
EN_2P5V_N E4
D3
G2
CSB
RESET
PD
R121
10kΩ
1
1
1
CSB
BLU
RESET
BLU
PD
BLU
GND
L6
VCCD_PLL1
IO
CLK0
IO
CLK1
IO
CLK2
IO
CLK3
IO
DATA0
IO
VPLL
VPLL
GND
IO
DCLK
IO
IO
NCE
IO
NCONFIG
IO
IO
TCK
IO
TDI
TMS
IO
IO
IO
IO BANK_1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
TDO
GND_PLL1
N5L5
BUSY
BLU
1
DIG1
GND
R122
10kΩ
DIG1
BUSY_AUX1
PS_DCLK
1
GND
2
PS_CDONE_N
3
VIO_FPGA
4
PS_CONFIG_N
5
PS_STATUS_N
6
DATA
7
N_CSO
8
ASDO
9
GND
10
3M2510-5002UB
P2
ASDO
3 7 U5
VCC
N_CSO
1
nCS 8
2 DATA
PS_DCLK 6
DCLK DATA
GND
GND
P21
1
2
3
GND
EP2C5F256C7N
F2
H5
G1
G5 PS_STATUS_N
J5 PS_CONFIG_N
F1 DATA
H4 PS_DCLK
H2 MCLK
H1
J2
J1
VCCIO3
GND
POWER_FPGA
VCCIO2
VCCIO1
VIO_FPGA
VCCINT
VIO
BANK_2
B16
G14
K14
R16
TBD0603
DNI
15kΩ
DNI
TBD0603
DNI
TBD0603
DNI
10kΩ
R130
R103
10kΩ
TBD0603
DNI
R75
R76
R77
R78
R132
10kΩ
DNI
10kΩ
DNI
10kΩ
DNI
10kΩ
DNI
P10
VFPGA
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
P11
G9
H7
H10
J7
P3
OH_D0
OH_D1
OH_D2
OH_D3
OH_D4
OH_D5
OH_D6
OH_D7
2
2
1
2
VCCIO1
B1
G3
K3
R1
BANK_4
OH_D8
OH_D9
OH_D10
OH_D11
OH_D12
OH_D13
OH_D14
OH_D15
C110
C109
1
2
VIO_FPGA
A2
A15
C7
C10
E7
E10
LA_CLK1
LA_CLK2
1000pF
GND
U6
MSEL0
MSEL1
J13
K12
DSPCLK H16
H15
J15
J16
LA_CLK2
LA_CLK1
EP2C5F256C7N
VCCIO4
M7
M10
P7
P10
T2
T15
G8
C9
E8
E9
H3
H14
J3
J14
M8
M9
P8
H8
P9
R2
R15
T1
T16
J9
K9
H9
J8
A1
A16
B2
B15
C8
M5
R3 IO VCCA_PLL1
CLAMP_ENT3 IO
P5 IO
P4 IO
T4 IO
R4 IO
T5
IO
U6
R5 IO
T6 IO
N8 IO
T7 IO
R7 IO
L7 IO
L8 IO
T8 IO
R8 IO
OH_D15 T9 IO
OH_D14 R9 IO
OH_D13 N9 IO
OH_D12 N10 IO
OH_D11 T11 IO
OH_D10 R11 IO
OH_D9 P11 IO
OH_D8 L9 IO
OH_D7 L10 IO
OH_D6 R10 IO
OH_D5 T10 IO
OH_D4 K11 IO
OH_D3 K10 IO
OH_D2 N11 IO
OH_D1 P12 IO
OH_D0 P13 IO
T12 IO
R12 IO
L12 IO
T13 IO
R13 IO
T14 IO
R14 IO
M11
IO
L11 IO
GNDA_PLL1
EP2C5F256C7N M6
R59
3M2540-6002UB
VIO_FPGA
GND
GND
GND
2
VIO_FPGA
R134
10kΩ
GND
C112
0.1µF
C114
0.1µF
0.1µF
C117
L13 PS_CDONE_N
H13 BD<0>
D15 BD<1>
D16 BD<2>
E16 BD<3>
C14 BD<4>
D13 BD<5>
E14 BD<6>
D14 BD<7>
N12 BD<8>
M12 BD<9>
N13 BD<10>
N14
P14 BD<12>
P15 BD<13>
P16 BD<14>
N15 BD<15>
N16 AD<0>
M15 AD<1>
M16 AD<2>
M14 AD<3>
L14 AD<4>
L15
L16 BD<11>
K16
K15 BWR_N
H12 BRESET
J12 CONTROL
G16 BBUSY
G15 BRD_N
F15 BCS_N VIO_FPGA
F16 ADCOK
J11 PLLOK
H11
R135
G12
10kΩ
G13
M13
EP2C5F256C7N
VFPGA
VPLL
U6
F11
VCCD_PLL2
CLK4 CONF_DONE
CLK5
IO
CLK6
IO
CLK7
IO
IO
MSEL0
IO
MSEL1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
BANK_3
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
NSTATUS
GND_PLL2
F12 D12
GND
C113
SDO
0.1µF
VPLL
C116
VIO_FPGA
0.1µF
GND
C118
P9
C120
GND
0.1µF
2
0.1µF
VIO
0.1µF
C119
C122
GND
2
GND
0.1µF
VIO_FPGA
0.1µF
VIO_FPGAVIO_FPGA
R136
0Ω
10kΩ
R141
10kΩ
R140
10kΩ
R139
R138
GND
R137
0Ω
0.1µF
C123
PLLOK
ADCOK
AC
GND
R150
0Ω
VIO_FPGA
GND
R151
0Ω
GND
ADCOK
GND
ADCOK
CR1
AC
CR2
GND
GND
GND
GND
GND
GND
VCCIO1
604Ω
R89
604Ω
R145
10kΩ
10kΩ
BRESET R142
10kΩ
CONTROL R143
10kΩ
DSPCLK R144
BWR_N
BRD_N
BBUSY
BCS_N
MSEL0MSEL1
C121
C124
SCK_I
C125
SCK
0.1µF
2
2
C126
1000pF
E12
U6
VCCA_PLL2 B14
IO
IO A14
IO C13
IO C12
IO B13
IO A13
B11
IO
IO B12
IO A12
IO A11
IO C11
IO G10
IO G11
IO B10
IO A10
IO F10
IO F9
D11
IO
IO D10
IO A9
IO B9
IO A8
IO A7
IO B7
IO F7
IO F8
IO D8
IO B6
A6
IO
IO G6
IO G7
IO D6
IO C6
IO C5
IO C4
IO B5
IO A5
IO B4
IO A4
A3
IO
IO B3
IO E6
IO F6
GNDA_PLL2
E11 EP2C5F256C7N
C111
SCK_I
SDO_I
DIN_I
CNV_I
BUSY_I
RESET_I
PD_I
CSB_I
C127
MCLK
MCLK
1 YEL
MCLK
0.1µF
2
2
100MHZ Y3
4 V+
3
1 EN OUT
C115
C129
P18
0.1µF
0.1µF
VIO
0.1µF
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
0.1µF
Rev. B | Page 22 of 30
1
C128
1
C130
Figure 30. Schematic, FPGA
C131
1
1
0.1µF
1
1
0.1µF
1
0.1µF
UG-515
EVAL-ADAS3023EDZ User Guide
11221-022
0.1µF
EVAL-ADAS3023EDZ User Guide
UG-515
CONTROL
1
VDIG
1
2
1
BRESET
BD<12>
DSPCLK_CED
–15V
-5VA
+5VA
1
2
P24
P23
1
2
1
2
P22
DSPCLK
–5VA_CED
+5VA_CED
BD<8>
BD<9>
BD<10>
BD<11>
BD<13>
–5VA_CED
+5VA_CED
1
GND
BWR_N
1
VDIG
BWR_N
BCS_N
AD<4>
AD<2>
AD<0>
BBUSY
1
BBUSY
BD<14>
BD<15>
+15V
ERNI533402
ERNI533402
GND
BCS_N
+15V_CED
–5VA_CED
+5VA_CED
ERNI533402
GND
Figure 31. Schematic, 96-Pin Interface
11221-024
P25
AD<3>
BRESET AD<1>
BD<2>
BD<3>
BD<4>
VDIG
BD<5>
BD<6>
BD<7>
P4
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
11221-023
1
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
BD<0>
BD<1>
P30
1
2
BRD_N
+5VD
BRD_N
P4
CONTROL
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
1
2
P26
P4
Figure 32. Silkscreen, Top
Rev. B | Page 23 of 30
EVAL-ADAS3023EDZ User Guide
11221-025
UG-515
11221-026
Figure 33. Silkscreen, Bottom
Figure 34. Top Layer 1
Rev. B | Page 24 of 30
UG-515
11221-027
EVAL-ADAS3023EDZ User Guide
11221-028
Figure 35. GND Layer 2
Figure 36. Signal Layer 3
Rev. B | Page 25 of 30
EVAL-ADAS3023EDZ User Guide
11221-029
UG-515
11221-030
Figure 37. Signal Layer 4
Figure 38. Power Layer 5
Rev. B | Page 26 of 30
UG-515
11221-031
EVAL-ADAS3023EDZ User Guide
Figure 39. Bottom Layer 6
Rev. B | Page 27 of 30
UG-515
EVAL-ADAS3023EDZ User Guide
PRODUCTS ON THIS EVALUATION BOARD
BILL OF MATERIALS
Table 8.
Qty
5
2
1
1
1
1
1
1
1
22
2
1
6
6
11
7
11
9
8
15
10
2
7
1
4
6
6
9
18
2
2
14
25
2
9
1
Reference Description
U1 to U3, U8, U12
U10, U11
U20
U4
A1
A2
U6
U5
Y3
C108, C111 to C131
C45, C89
C107
C17, C20, C24, C25, C36, C88
C66 to C68, C79 to C81
C38,C65, C70, C71, C72, C73,
C75, C76, C77, C78, C92
C8, C29 to C31, C86, C109, C110
C43,C44, C46, C47, C49, C50,
C57, C59, C60, C62, C63
C1, C3, C4, C6, C10, C51, C53,
C55, C56
C2, C5, C48, C52, C54, C58,
C61, C64
C7, C9, C18, C19, C21, C22,
C26 to C28, C32 to C34, C37,
C85, C87
C11 to C16, C23, C35, C69, C74
C84, C90
C39 to C42, C91, C93, C94
R94
R32, R72, R73, R103
R2, R71, R125, R126, R136,
R151
R30, R31, R59, R137, R137,
R151
R60 to R68
R74 to R78, R121, R122, R128,
R130, R132, R134, R138 to
R144
R125, R126
R13, R55
R1, R24 to R26, R29, R80 to
R82, R85, R86, R95, R97, R99,
R100
R7 to R9, R19 to R23, R41 to
R49, R69, R70, R90 to R93, R96,
R101
R57, R58
R34 to R40, R50, R55
R27
Part Description
IC-ADI LDO
IC-ADI LDO
IC-ADI OPAMP
IC-ADI OPAMP
IC-ADI REFERENCE
IC-ADI REFERENCE
IC-CYCLONE II
IC SERIAL CONFIG
IC CRYSTAL OSC
CAP X7R 0402
CAP X7R 0508
CAP NP0 0603
CAP X8R 0603
CAP X7R 0603
CAP X7R 0805
Value
–
–
–
–
–
–
–
–
100 MHZ
0.1 µF
0.1 µF
100 pF
0.1 µF
Manufacturer
Analog Devices
Analog Devices
Analog Devices
Analog Devices
Analog Devices
Analog Devices
Altera Devices
Altera Devices
C-MAC
Murata
TDK
Phycomp
Murata
Part Number
ADP3334ACPZ
ADP1715ARMZ
AD8032ARZ
ADA4841-2YRZ
ADR434ARMZ
ADR381ARTZ
EP2C5F256C7N
EPCS4SI8N
SPXO009437-CFPS-73
GRM155R71C104KA88D
C1220X7R1E104K
2238 867 15101
GRM188R7E104KA01D
Instructions
0.1 µF
Murata
GRM21BR71H104KA01L
CAP C0G 0805
CAP NPO 0805
1000 pF
2700 pF
Murata
Murata
GRM2165C2A102JA01D
GRM2165C1H272JA01D
CAP NPO 0805
2700 pF
Murata
GRM2165C1H272JA01D
DNI
CAP NPO 0805
5600 pF
Murata
GRM2195C1H562JA01D
DNI
CAP X5R 0805
2.2 µF
Murata
GRM21BR71E225KA73L
CAP X5R 0805
CAP TANT
CAP 0805
10 µF
10 µF
Murata
AVX
Murata
GRM21BR61C106KE15L
TAJA106K010RNJ
–
DNI
RES 0402
RES 0603
RES 0603
0
–
–
Panasonic-ECG
Panasonic-ECG
Panasonic-ECG
ERJ-2GE0R00X
–
–
DNI
DNI
RES 0603
0
Panasonic-ECG
ERJ-3GEY0R00V
RES 0603, 5%
RES 0603, 5%
50
10 K
Panasonic-ECG
Panasonic-ECG
ERJ-3EKF49R9V
ERJ-3EKF1002V
RES 0603, 5%
RES 0603, 1%
RES 0805
15 K
140 K
–
Yageo
Panasonic-ECG
Panasonic-ECG
RC0603FR-0715KL
DNI
–
DNI
RES 0805
0
Panasonic-ECG
ERJ-6GEY0R00V
RES 0805, 1%
RES 0805, 1%
RES 0805, 1%
22
90.9
365
Panasonic-ECG
Panasonic-ECG
Panasonic-ECG
ERJ-6ENF22R0V
ERJ-6ENF90R9V
ERJ-6ENF3652V
DNI
DNI
Rev. B | Page 28 of 30
EVAL-ADAS3023EDZ User Guide
Qty
9
1
2
2
2
6
1
2
1
1
1
2
3
1
1
1
1
6
2
4
2
26
Reference Description
R33, R52 to R54, R79, R83, R84,
R87, R88
R28
R89, R145
R3, R5
R4, R6
R10 to R12, R98, R102, R135
R16
R14, R56
R18
R17
R15
CR1,CR2
P5, P7, P31
P2
P1
P3
P4
GND(S)
+15 V, MCLK
REF, +5 V A, +5 V D, REFIN
−15 V, −5 VA
PD, CNV, CSB, DIN,
SCK, SDO, VIO,
AVDD, BUSY, DVDD,
VDDH, VSSH,
AUX+I, AUX−I,
COM_I, IN0_I−IN7_I,
RESET, VDRV+,
VDRV−
UG-515
Part Description
RES 0805, 1%
Value
499
Manufacturer
Panasonic-ECG
Part Number
ERJ-6ENF4990V
RES 0805, 1%
RES 0805, 1%
RES 0805, 5%
RES 0805, 5%
RES 0805, 5%
RES 0805, 1%
RES 0805, 1%
RES 0805, 1%
RES 0805, 1%
RES 0805, 1%
LED
CONN-3 PIN MALE
CONN-10 PIN MALE
CONN-26 PIN MALE
CONN-40 PIN MALE
CONN-96 PIN MALE
Test point, black
Test point, yellow
Test point, red
Test point, white
Test point, blue
590
604
1K
2K
10 K
64.9 K
78.7 K
95.3 K
107 K
210 K
Green
Breakaway
RA, shroud
Shroud
RA, shroud
RA, DIN
–
–
–
–
–
Panasonic-ECG
Panasonic-ECG
Panasonic-ECG
Panasonic-ECG
Panasonic-ECG
Panasonic-ECG
Panasonic-ECG
Panasonic-ECG
Yageo
Panasonic-ECG
CML
Samtec
3M
3M
3M
ERNI
Components Corp.
Components Corp.
Components Corp.
Components Corp.
Components Corp.
ERJ-6ENF5902V
ERJ-6ENF6040V
ERJ-6ENF1001V
ERJ-6ENF2001V
ERJ-6ENF1002V
ERJ-6ENF6492V
ERJ-6ENF7872V
ERJ-6ENF6042V
RC0805FR-07300KL
ERJ-6ENF2103V
CMD28-21VGCTR8T1
TSW-103-08-G-S
2510-5002UB
30326-6002HB
2540-6002UB
533402
TP-104-01-00
TP-104-01-04
TP-104-01-02
TP-104-01-09
TP-104-01-06
Rev. B | Page 29 of 30
Instructions
UG-515
EVAL-ADAS3023EDZ User Guide
RELATED LINKS
Resource
ADAS3023
AD8032
ADR434
ADP1715
ADP3334
EVAL-CED1Z
AN-931
CN0201
Description
Product Page, ADAS3023, 16-Bit, 8-Channel Simultaneous Sampling Data Acquisition System
Product Page, AD8031/AD8032, Low Power, Low Noise Amplifier
Product Page, ADR434, 4.096 Precision Reference
Product Page, ADP1715, 500 mA Low Dropout CMOS Linear Regulator with Soft Start
Product Page, ADP3334, High Accuracy Low IQ, 500 mA, ANYCAP®, Adjustable Low Dropout Regulator
Product Page, Converter and Evaluation Development board
Application Note, Understanding PulSAR ADC Support Circuitry
Circuit from the Lab, Complete 5 V, Single-Supply, 8-Channel Multiplexed Data Acquisition System with PGIA for
Industrial Signal Levels
ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
Legal Terms and Conditions
By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions
set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you
have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc.
(“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal,
temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided
for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional
limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term
“Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including
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