8
6
7
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS
NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR
USED IN FURNISHING INFORMATION TO OTHERS, OR FOR ANY OTHER
PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES.
2
3
4
5
1
REVISIONS
JUMPER TABLE
JP#
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY ANALOG DEVICES.
ON
OFF
REV
DESCRIPTION
A
INITIAL RELEASE
DATE
APPROVED
12OCT12
A. BROWNE
1
2
3
RELAY CONTROL CHART
D
D
4
CONTROL
CODE
DEVICE
FUNCTION
CONNECTOR
5
* SEE ASSEMBLY INSTRUCTIONS
C
C
B
B
TEMPLATE ENGINEER
DATE
HARDWARE SERVICES
R. MACDONALD
HW TYPE
: Characterization Board
Product(s) : AD9683-250, AD9683-170, AD6677-250
P-SPEC
: N/A
HARDWARE SYSTEMS
J. BURKE
TEST ENGINEER
J. KEANE
A
COMPONENT ENGINEER
PACKAGE
: 32-lead n/a n/a-family
: n/a-pitch n/a Style
TESTER
SOCKET
HANDLER
: N/A
: SG-MLF32A-7004
: N/A
A. MABAET
TEST PROCESS
N/A
HARDWARE RELEASE
R. AMARILLE
DESIGNER
12OCT12
A. BAWAR
12OCT12
A. BROWNE
BK/BD SPEC.
SOCKET OEM
OEM PART#
HANDLER
7
6
5
4
TBD
TESTER TEMPLATE
no_template
TOLERANCES
DECIMALS
X.XX +-0.010
X.XXX +-0.005
CHECKER
N/A
8
MASTER PROJECT TEMPLATE
UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES
PTD ENGINEER
P.O SPEC.
A N A LO G
D EV C E S
SCHEMATIC
N/A
3
FRACTIONS
+-1/32
ANGLES
+-2
2
A
REV.
DRAWING NO.
A
02_035115
SIZE
DD
SCALE
CODE ID NO.
1:1
CodeID
SHEET
1
1
OF
7
8
6
7
2
3
4
5
1
REVISIONS
AD9683/AD6677 EVAL/APPS BOARD
R109
SYNC_SE
REV
0
R115
D
DIN
SYNCINB+
SYNCINB+
0
7
8
DNI
R116
SYNCINB-
0
GND
R117
SYNC+_FPGA
0
R118
SYNC-_FPGA
SYNCINB-
0
DNI
NC
4
3
5
6
AGND
10K
R113
DNI
DOUT_POS
DOUT_NEG
DNI
R112
AGND
AGND
VCC
2
0
U102
1
10K
R111
49.9
AGND
DNI
49.9
DNI
R108
D
R114
0
2 3 4 5
APPROVED
C116
0.1UF
R110
1
DATE
3P3V_DIGITAL
DNI
SYNC
DESCRIPTION
ADN4661BRZ
RSTB
R140
AGND
RSTB_FPGA
0
DNI
PDWN
DUT
R119
10K
VCM
AGND
1
SYSREF-
RSTB
VCM
AVDD
AVDD
AVDD
VIN+
VINAVDD
AVDD
RF_CLK
KP_3P3V
CLKCLK+
AVDD SKTLFCSP32
SYSREF+
SYSREFAVDD
RSTB
DNI
AGND
C122
1UF
U101
DNI
PDWN
CSB
SCLK
SDIO
FD
DGND
9 DGND
10 DVDD
11 SYNCINB+
12 SYNCINB13 DRGND
14 DRVDD
15 SERDOUT16 SERDOUT+
SYSREF+
R105
1
100
DNI
1
2
3
4
5
6
7
8
RF_CLK
CLKAVDD CLK+
DNI
AVDD
1
SYSREF+
SYSREF-
DVDD
24
23
22
21
20
19
18
17
KP_3P3V
PDWN
DUT_CSB
DUT_SCLK
DUT_SDIO
FD
R106
0
AGND
DNI
FD
1
R121
0
C125
0.1UF
AGND
C243
1UF
DNI
AGND
0
DNI
DNI
C112
0.001UF
0.001UF
C138
1UF
C131
1UF
C135
0.1UF
C132
1UF
C119
1UF
B
SERDOUT_N_FPGA
OUT1
0
SYSREF+_FPGA
R125
R126
SYNCINB+
DNI
SYSREF-
0
SYSREF-_FPGA
SYNCINB+
1
5 4 3 2
SYSREF+
SYNCINB-
1
SERDOUT_P_FPGA
SYSREF_SE
AGND
C129
0.1UF
C128
0.1UF
AGND
100
C113
C127
0.1UF
C244
0.1UF
SYNCINBDNI
R107
R102
AGND
SERDOUT-
C1
1UF
DRVDD
5 4 3 2
C103
0.001UF
AVDD
DNI
DVDD
DRVDD
SERDOUTSERDOUT+
OUT+
SERDOUT-
ADL5202_A2
AGND
1
SERDOUT+
C136
0.1UF
AGND
DVDD
B
C134
0.1UF
C123
1UF
DVDD
DVDD DNI
1
C102
0.001UF
C
DVDD
PAD
32
31
30
29
28
27
26
25
AGND
1
2
RSTB
SERDOUT+
LAYOUT: DECOUPLING QUANTITY MAY VARY LAYOUT DEPENDING
1
P101
RSTB
VCM
AVDD
DNI
DNI
AGND
VIN-
C
PDWN
C117
0.1UF
SG-MLF32A-7004
VIN+
AGND
DNI
P3
1
2
THE FOOTPRINT FOR THIS SOCKED NEEDS TO BE CHECKED AGAINST THE DRAWING
AGND
0
DVDD
PDWN
PDWN_FPGA
R139
R128
0
SYSREF SE TO DE
DNI
SYSREF
R129
1
0
DNI
3P3V_DIGITAL
DNI
AGND
49.9
R127
2 3 4 5
C133
0.1UF
AGND
U104
1
10K
R132
A
R131
R134
2
DOUT_POS
DOUT_NEG
DIN
0
7
8
A
SYSREF+
0
DNI
R135
0
AN A LO G
DE V CES
SYSREF-
DNI
GND
NC
4
3
5
6
10K
DNI
R133
AGND
VCC
ADN4661BRZ
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
SCHEMATIC
HW TYPE
: Characterization Board
Product(s) : AD9683-250, AD9683-170, AD6677-250
P-SPEC
: N/A
DESIGN VIEW
REV
DRAWING NO.
<DESIGN_VIEW>
A
02_035115
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
AGND
OF ANALOG DEVICES.
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
8
7
6
5
4
3
A. BROWNE
2
SIZE
SCALE
D
1:1
SHEET
1
2
OF 7
8
6
7
2
3
4
5
1
2
3
4
6
5
SK33A-TP
10UF
CR201
A
C
P
1.1A
C201
N
AGND
PGND
REV
DESCRIPTION
DATE
APPROVED
POWER
D
AGND
P202
E212
1
1
2
U201
ADP1708ARDZ-R7
P
2
402
C209
1UF
PAD
AGND
AGND
AGND
C
E215
DVDD
1
1
AGND
1
2
3
4
5
6
E208
PAD
N
P208
1
2
39OHM
Z5.531.3625.0
10UF
P203
3P3V_DIGITAL
2
1
3P3V_ANALOG
2
39OHM
N
39OHM
E216
10UF
C207
10UF
R206
100K
2
0.1UF
C238
1
P
NC
PAD
39OHM
0.1UF
C240
C206
22UF
EN
E204
1
2
3
4
DRVDD
2
P
1
2
U203
ADP7104
8
VIN
VOUT
7
PG
SENSE
6
GND
GND
5
10UF
P
EP
N
R224
C236
39OHM
1
2
P204
2P5V
GND
C208
1UF
10UF
N
1
AVDD
U207 ADP125ARHZ-R7
8
1
VIN
VOUT
7
2
VIN
VOUT
6
3
NC
ADJ
5
4
EN
39OHM
1
C
E203
2
PAD
AGND
E214
P210
3P3V_DIGITAL
0.1UF
C234
AGND
AGND
39OHM
C233
39OHM
0.1UF
3P3V_ANALOG
DVDD
2
P
1
2P5 SUPPLY REQUIRED FOR INTERFACE TO HAD V6
100
PAD
C205
10UF
2
R223
NC
1
DNI
C204
22UF
EN
E213
Z5.531.3625.0
E202
R205
100K
AGND
1
2
3
4
5
6
1
2
CR204
A
C
1
2
3
4
10UF
N
P1
39OHM
P209
S2A-TP
0.1UF
C232
5V_SUPPORT
AGND
U202
ADP7104
8
VIN
VOUT
7
PG
SENSE
6
GND
GND
5
C231
2
C235
2 PAD
39OHM
1
4.7UF
C202
E201
5
6
C203
EN
SENSE
IN
OUT
IN2
OUT2
ADJ
GND1 PAD
4.7UF
10K
1.91K
R202
R203
3P3V_DIGITAL
1
7
3
4
8
VIN
2
C237
D
C239
PJ-202A
2
261
1
1
2
3
CR202
A
C VIN
CR203
F201
FL201
BNX016-01
1
R201
P201
LNJ314G8TRA (GREEN)
REVISIONS
5V_SUPPORT
P
2
R216
0
1
L201
2
39OHM
R230
N
EN
SENSE
IN
OUT
IN2
OUT2
ADJ
GND1 PAD
R213
13K
SW4
R215
TBD0603
C215
2 PAD
C221
22UF
AGND
DNI
39OHM
1
2
VOUTB
R218
0
1
39OHM
R219
0
E211
DNI
L202
DVDD
2
E209
C219
TBD0603
DNI
AGND
1
AGND
AGND
100PF
E207
5
6
P207
C220
22UF
DNI
1500PF
C216
PAD
ADP2114_PRELIM
DNI
P206
1
2
12
PGOOD2
7
COMP2
18
SW3
17
TO EVALUATE SHARING OF AVDD AND DVDD
18K
SW2
2.2UH
B
AGND
1
2
1
7
3
4
8
R217
0
E210
DNI
AGND
39OHM
E206
1
C214
JP203
2
0
10UF
39OHM
0.1UF
C242
2 PAD
4.7UF
2200PF
100PF
1
VOUTA
AGND
A
2
AGND
R221
EN2
2.2UH
0
R220
TBD0603
1.00K
DNI
R222
VIN
1
AVDD
39OHM
U205
ADP1708ARDZ-R7
R229
24K
C228
R214
10.5K
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
27
26
25
14
15
16
U206
PAD
0.01UF
R212
15K
C218
AGND
A
C213
29
PGOOD1
2
COMP1
24
SW1
23
PGND1
PGND2
PGND3
PGND4
R211
15K
SCFG
FREQ
SYNC_CLKOUT
OPCFG
EN1
V1SET
FB1
SS1
EN2
V2SET
FB2
SS2
GND
22
21
20
19
0.01UF
C217
AGND
R210
4.64K
4
3
5
6
28
EN1
31
VOUTA 32
30
13
EN2
10
9
VOUTB
11
VDD
1
AGND
R209
27K
R208
100K
AGND
8
R225
1.00K
0
DNI
2
18K
C230
R207
100K
4.7UF
1UF
EN1
1
AGND
C212
R204
E217
E205
5
6
C241
R228
EN
SENSE
IN
OUT
IN2
OUT2
ADJ
GND1 PAD
AGND
2
C225
1
7
3
4
8
AGND
VIN
AGND
1
2
S2A-TP
JP201
2
0
4.7UF
S2A-TP
1
4.7UF
CR206
A
C
OPTIONAL
SWITCHING
SUPPLY
10
B
C211
22UF
R226
C210
22UF
CR205
A
C
P205
U204
ADP1708ARDZ-R7
R227
24K
C227
AGND
DNI
39OHM
C223
22UF
C224
22UF
AN A LO G
DE V CES
DNI
C222
TBD0603
AGND
AGND
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
DNI
AGND
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
SCHEMATIC
HW TYPE
: Characterization Board
Product(s) : AD9683-250, AD9683-170, AD6677-250
P-SPEC
: N/A
DESIGN VIEW
<DESIGN_VIEW>
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
7
6
A
02_035115
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
8
REV
DRAWING NO.
5
4
3
A. BROWNE
2
SIZE
SCALE
D
1:1
SHEET
1
3
OF 7
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
ANALOG INPUT
D
AMP_OUT+
8.2PF
PASSIVE PATH
C303
D
AGND
3
5
4
SEC
1
1
PRI
T303
22
0
R313
36
C301
VCM
AGND
C306
0.1UF
SHARE PADS
AGND
R319
VIN+
0.1UF
R314 AGND
36
R316
R320
22
VIN-
0
R312
0
24.9
4
ETC1-1-13
AGND
3
AGND
0.1UF
R315
R318
T302
ETC1-1-13
DNI
PRI
R301
49.9
SEC
2 3 4 5
C
8.2PF
C305
24.9
R311
0
C302
AIN
SHARE PADS
5
C
AIN
1
R317
DNI
AMP_OUT-
8.2PF
C304
DNI
AGND
B
B
A
A
AN A LO G
DE V CES
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
SCHEMATIC
HW TYPE
: Characterization Board
Product(s) : AD9683-250, AD9683-170, AD6677-250
P-SPEC
: N/A
DESIGN VIEW
REV
DRAWING NO.
<DESIGN_VIEW>
A
02_035115
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
8
7
6
5
4
3
A. BROWNE
2
SIZE
SCALE
D
1:1
SHEET
1
4
OF 7
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
ACTIVE PATH - CHANNEL B REMOVED,NO COMPONENT CHANGES
3P3V_ANALOG
D
C413
0.1UF
C414
0.1UF
D
C419
0.1UF
AGND
3P3V_ANALOG
R432
1K
5V_SUPPORT
5V_SUPPORT
P400
AGND
THESE RLCS ARE PLACE HOLDERS... PLACE CORRECT VALUES & COMPONENTS...
C415
R410
R429
1K
3P3V_ANALOG
0
1200PF
DNI
DNI
AGND
R427
1K
C441
0.1UF
C
R401
VOUTA-
0
DNI
6
AGND
3
0.1UF
36
VINA35
0.1UF
1 T401
C401
2
J404
DNI
R405
130
0
2 3 4 5
R437
49.9
VOUTB-
VINB+
37
14
6
5
4
C403
R404
AMP_IN_A+
DNI
VOUTB+
ADL5202ACPZ
15
VINB16
TC4-1W+
1
U401
VINA+
AGND
4
VOUTA+
C402
R403
0
VPOS
PWUPA
DNI
LATCHA
LATCHB
PM
MODE0
MODE1
0.1UF
DNI
DNI
AGND
GND
DNI
R430
1K
R431
1K
R433
1K
R434
1K
PAD
17
PWUPB
7
18
33
PAD
AGND
UPDN_DAT_A/A0
UPDN_CLK_A/A1
FA_A/A2
CSA_N/A3
A4
A5
UPDN_DAT_B/B0
UPDN_CLK_B/B1
GS0/FA_B/B2
GS1/CSB_N/B3
SCLK/B4
SDIO/B5
29
31
30
32
20
22
19
21
38
39
40
1
2
3
13
12
11
10
9
8
1UH
34
23
24
25
26
27
28
L401
5V_SUPPORT
R446
1K
L403
L405
120NH
120NH
DNI
AGND
DNI
0
DNI
DNI
DNI
1200PF
DNI
C418
22PF
C417
2.7PF
C416
R411
AMP_OUT-
DNI
DNI
5V_SUPPORT
3P3V_ANALOG
R445
1K
150
1
2
3
SAMTECTSW10608GS3PIN
C411
0.1UF
150
C409
0.1UF
R412
C408
0.1UF
R443
C407
0.1UF
1UH
C412
10UF
L402
C410
10UF
L404
L406
120NH
120NH
DNI
DNI
AMP_OUT+
C
DNI
A0
A1
ADL5202_A2
A3
A4
A5
B0
B1
ADL5202_B2
B3
B4
B5
3P3V_ANALOG
R428
AGND
1K
AGND
B
3P3V_ANALOG
R416
10K
R417
10K
R418
10K
R419
10K
R420
10K
3P3V_ANALOG
R413
10K
R421
10K
A0
R422
10K
R423
10K
R424
10K
R425
10K
R439
ADL5202_CSA
0
R440
ADL5202_CSB
0
R441
KP_SCLK
0
R442
KP_SDIO
0
R409
10K
B0
A1
B1
ADL5202_A2
ADL5202_B2
A3
A
B
A
B3
A4
B4
A5
B5
AN A LO G
DE V CES
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
SCHEMATIC
HW TYPE
: Characterization Board
Product(s) : AD9683-250, AD9683-170, AD6677-250
P-SPEC
: N/A
DESIGN VIEW
REV
DRAWING NO.
<DESIGN_VIEW>
A
02_035115
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
8
7
6
5
4
3
A. BROWNE
2
SIZE
SCALE
D
1:1
SHEET
1
5
OF 7
6
7
REVISIONS
3P3V_DIGITAL
CLK_IN+
VDD_5V
VCC
1 TRISTATE CTRL
OUT
C530
GND
DIN
REFCLK-
0
R525
DOUT_NEG
GND
C521
10UF
N
0
OUT5+
OUT5OUT6+
OUT6RESETB
PDB
3P3V_DIGITAL
1
2
JPR0402
OUT7-
5
1
PRI
SEC
4
3
R549 DNI
4
3
MABA-007159-000000
REFCLK2-
AGND
REFCLK2+
R546
0
DNI
100
R541
DNI
100
R540
82.5
R539
82.5
R538
CLKIN
0
J502
5 4 3 2
0.1UF
C522
AGND
0.1UF
DNI
CLK_OUT+
SEC
R545
100
PRI
1
49.9
T504
R542
R569
5
1
ETC1-1-13
AGND
390PF
C523
AGND
CLKIN_B
AGND
0.1UF
REFCLK+
R551
A
REFCLK1-
0
R552
REFCLK1+
0
AN A LO G
DE V CES
ADN4661BRZ
OUT3-
R526 DNI
OUT3+
0
R527 DNI
REFCLKTHIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
REFCLK+
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
0
SCHEMATIC
HW TYPE
: Characterization Board
Product(s) : AD9683-250, AD9683-170, AD6677-250
P-SPEC
: N/A
DESIGN VIEW
REV
DRAWING NO.
<DESIGN_VIEW>
A
02_035115
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
7
5.11K
C519
NC
4
3
5
6
10K
AGND
REF CLK
8
DNI
J501
T501
0
R524
7
DOUT_POS
8
AGND
FD
C518
OUT7+
CLK+
AGND
0
R563
DNI
0
R27
1
2
P505
AGND
C533
U503
0.1UF
80MEGHZ
AGND
0.1UF
0
R550 DNI
2
R555
1K
3
1350MEGHZ
AGND
2
3
R570
100
2
DNI
CLK_IN-
VCC
10K
DNI
GND
R567
33
C531
0.1UF
R562
4 Y502
DNI
3P3V_DIGITAL
1
C536
0.1UF
DNI
0
0
DNI
R565
DNI
0
R579
R560
DNI
R557
49.9
R580
0
DNI
A
P501
1
2
AGND
CR503
0
3P3V_ANALOG
0.1UF
1
AGND
390PF
C535
OPT
B
3P3V_DIGITAL
127
3
0
AGND
6
10
OUT
R537
R528
ADDITIONAL
CLOCK OUTPUT
127
SEC
R523
1
2
P503
AGND
R536
PRI
T503
AGND
AGND
DNI
VCC
VT
1
3
4
5
7
8
9
11
12
13
15
16
1
C599
1
2
P504
390PF
5
4
2
VCO_VTA
R566
33
MABA-007159-000000
AGND
JP3
Y500
14
DNI
AGND
2 3 4 5
R505
0
AGND
AGND
AGND
0
AGND
CLK+
1
10K
C520
0.1UF
1
2
CLK-
0
0
DNI
49.9
R556
DNI
AGND
C532
R522
390PF
2 3 4 5
DNI
R568
DNI
0
R564
C598
R561
B
3P3V_DIGITAL
VDD_5V
P502
0
R504
R1
Z5.530.3225.0
C
P
LAYOUT: SMA'S SHOULD BE 575 MILS CENTER TO CENTER
LAYOUT: SHARE PADS WITH ACTIVE CLOCK PATH R'S
OUT3+
OUT3OUT4+
OUT4-
SAMTECTSW10608GS3PIN
CLK_OUT-
CLK1
R503
0.1UF
R571
AD9525
3P3V_DIGITAL
VCO/CLK INPUT
PASSIVE CLOCK
CLK
P500
RF_CLK
5V_SUPPORT
SDO
SDI
SCLK
CSB_9525_BUFF
AGND
1
2
3
AGND
AGND
CLK_OUT+
CLK_OUT-
STATUS LEDS
T500
OUT7+
OUT7REF_MON
3P3V_DIGITAL
AGND
3P3V_DIGITAL
PLACE LEDS ON THE TOP SIDE OF THE BOARD
74LVC14AD
AD9525ABCPZ
36
35
34
33
32
31
30
29
28
27
26
25
VDD3
OUT7
DNI
OUT7_N
REFMON
VDD3
SYNC_OUT
SYNC_OUT_N
GND
SDO
SDIO
SCLK
CS_N
10K
DNI
AGND
R502
120NH
DNI
74LVC14AD
C512
0
C513
0.1UF
DNI
DNI
AGND
R554
120NH
DNI
L502
CR501
R511
8
49.9
L501
DNI
9
STATUS
DNI
7
R577
DNI
120NH
4
REF_SEL
U501
74LVC14AD
U501
VSS
DNI
0.1UF
C515
0.1UF
3
VDD
100
L503
U501
A
C
300
SML-LX1206GW-TR (GREEN)
14
R529
DNI
C514
AGND
DNI
3P3V_DIGITAL
SMA-J-P-X-ST-EM1
A
C
SML-LX1206GW-TR (GREEN)
74LVC14AD
DNI
STATUS
4.12K
AGND
49.9
0.1UF
82.5
R535
82.5
1
R510
6
74LVC14AD
AGND
R553
0
100
SEC
5
CR500
OUT1_N
OUT1
VDD3
OUT0_N
OUT0
OUT_RSET
CLKIN
CLKIN_N
VDD3
STATUS
REFC
REF_SEL
CP_RSET
REFA+
REFA-
C505
0.1UF
R530
PRI
5
R534
R531
0
3
2
OUT0OUT0+
OUT_RSET
CLKIN
CLKIN_B
3P3V_DIGITAL
STATUS
R500
REFMON
1
2
3
4
5
6
7
8
9
10
11
12
VDD_CP
CP
GND
CP_RSET
REFA
REFA_N
GND
VDD3
REFB
REFB_N
PD_N
RESET_N
10000PF
47000PF
C511
C510
OUT1+
4
1
U501
300
AGND
127
R533
127
R532
C517
REF_MON
3P3V_DIGITAL
ETC1-1-13
AGND
OUT1OUT1+
U500
13
14
15
16
17
18
19
20
21
22
23
24
27
RF CLK OUTPUT
0.1UF
AGND
U501
RF_CLK
OUT1-
200
AGND
AGND
1
C516
200
VCO_VTA
AGND
3P3V_DIGITAL
R578
OUT6-
AGND
2 3 4 5
C
3P3V_DIGITAL
AGND
66.5
R515
0.022UF
C508
R517
1UF
C509
CP
D
200
R573
OUT4-
200
0.1UF
OUT6+
200
R519
OUT0-
R576
R543
R516
0
CP / VCO CONNECTION
OUT4+
AGND
VDD_P13
CP
TBD0402
DNI
49.9
VDD_P13
200
R572
200
REFA-
R514
VDD_5V
R518
OUT0+
0.1UF
C507
CLK_IN-
L500
200
PAD
48
47
46
45
44
43
42
41
40
39
38
37
AGND
DNI
R575
OUT5-
R544
AGND
R512
PIN 32
R521
OUT3-
AGND
REFA+
100
PIN 46
200
10K
DNI
49.9
R513
PIN 41
PIN 36
200
PAD
OUT2
OUT2_N
VDD3
OUT3
OUT3_N
OUT4
OUT4_N
VDD3
OUT5
OUT5_N
OUT6
OUT6_N
OUTPUT
TERMS
R574
OUT5+
C506
CLK_IN+
PIN 3
R520
OUT3+
10K
0.1UF
R501
0.1UF
APPROVED
DATE
127
0.1UF
DESCRIPTION
3P3V_DIGITAL
82.5
0.1UF
REFERENCE
INPUT
R507
0.1UF
ACTIVE CLOCK PATH
R509
C504
127
C503
82.5
C502
R506
C501
REV
R508
C500
AGND
D
1
1
3P3V_DIGITAL
2
3
4
5
2 3 4 5
8
6
5
4
3
A. BROWNE
2
SIZE
SCALE
D
1:1
SHEET
1
6
OF 7
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
APPROVED
DATE
DVDD
DVDD
R603
1.1K
5
SDI
1 A1
Y1
3 A2
Y2 4
10
6
KP_FUSE_BLOW_EN
SDO
KP_SDIO
GND
100K
R602
10K
R601
U601
NC7WZ07P6X
VCC
U603
ADG734BRUZ
2
DUT_SDIO
DNI
AGND
AGND
19
17
D
3P3V_DIGITAL
IN
1
KP_3P3
R608
18
KP_3P3V
3P3V_DIGITAL
1
0
C602
0.1UF
LAYOUT: PLACE C602 NEAR DUT
NOTE: THIS SYMBOL IS DRAWN GIVEN INPUT 1 LOGIC
DNI
1
SA
SB
D
TP601
AGND
20
DUT_SD
8 D
DNI
9 SA
7 SB
R606
1.1K
R605
1.1K
IN
AGND
10K
R604
2P5V
U603
ADG734BRUZ
C601
0.1UF
DVDD
D
KP_CONTRL_EN
R607
C603
0.1UF
U603
16
0
VDD
15 NC15
6 GND
5 VSS
AGND
6
CSB
3 A2
Y2
4
NC7WZ16P6X
R611
10K
GND
2
AGND
AGND
DNI
13 D
KP_SCLK
100K
Y1
R609
1 A1
U603
ADG734BRUZ
11
DUT_CSB
12 SA
14 SB
3 D
DUT_SC
VCC
SCLK
IN
1
2 SA
4 SB
100K
5
KP_CSB
AGND
DNI
AGND
1
AGND
U602
ADG734BRUZ
DNI
DUT_CS
R612
C
R614
10K
C604
0.1UF
10K
R610
DVDD
IN
U603
ADG734BRUZ
KP_CONTRL_EN
AGND
DUT_SCLK
C
1
DNI
R613
R615
0
0
AGND
LAYOUT: ROUTE ALL TRACES TO THE TYCO CONN ON TOP OF BOARD
USING HADV6
NC7WZ16P6X
REFCLK1+
AGND
SERDOUT_P_FPGA
REFCLK2+
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
P601 P601
BG1
BG2
BG3
BG4
BG5
BG6
BG7
BG8
BG9
BG10
A
SERDOUT_N_FPGA
REFCLK2-
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
PLUG HEADER
P601
REFCLK1-
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
DG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
C606
100K
R625
R623
100K
R621
100K
R619
PLUG HEADER
100K
DNI
WP
U605_A1
U605_A2
SCLK_BD_ID
WP
VCC
1
A0
2
A1
3
5
A2
SDA
6
SCL
7
WP
AGND
AGND
AGND
SDA_BD_ID
VSS
4
AGND
B
U605
24LC32A-I/ST
AGND
P602 P602
BG1
BG2
BG3
BG4
BG5
BG6
BG7
BG8
BG9
BG10
6469169-1
AGND
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
DNI
U605_A2
8
U605_A0
100K
P601
2
P602
DNI
U605_A1
R624
GND
DNI
U605_A0
100K
P602
AGND
R622
4
0.1UF
3P3V_ANALOG
100K
Y2
PLUG HEADER
3 A2
3P3V_ANALOG
R620
CSB_9525_BUFF
SYSREF+_FPGA
SYNC+_FPGA
B1
B2
B3
B4
B5
B6 SYSREF-_FPGA
B7 SYNC-_FPGA
B8
B9
B10
100K
CSB_9525
KP_CON
SYNC_SE
SYSREF_SE
FD
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
PLUG HEADER
6
1
AGND
AGND
PLUG HEADER
Y1
RSTB_FPGA
PDWN_FPGA
ADL5202_CSA
DNI
SDO
SDI
SCLK
KP_SCLK
KP_CSB
KP_SDIO
ADL5202_CSB
PLUG HEADER
1 A1
DNI
1
R618
VCC
DNI
1
DNI
P602
P602
SCLK
PLUG HEADER
KP_CONTRL_EN
B3
B4
B5
B6
B7
B8
B9
B10
SDI
PLUG HEADER
DNI 1
CSB_9525
CSB
PLUG HEADER
U604
5
CSB
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
PLUG HEADER
B
100K
AGND
R617
10K
C605
0.1UF
1
R616
SDA_BD_ID
KP_FUS
DNI
B1KP_FUSE_BLOW_EN 1
B2 SCLK_BD_ID
PLUG HEADER
3P3V_DIGITAL
SDO
PLUG HEADER
P601
P601
DG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
A
AGND
AN A LO G
DE V CES
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
SCHEMATIC
HW TYPE
: Characterization Board
Product(s) : AD9683-250, AD9683-170, AD6677-250
P-SPEC
: N/A
DESIGN VIEW
REV
DRAWING NO.
<DESIGN_VIEW>
A
02_035115
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
8
7
6
5
4
3
A. BROWNE
2
SIZE
SCALE
D
1:1
SHEET
1
7
OF 7