14-Bit, 80 MSPS, A/D Converter
AD9444
FEATURES
APPLICATIONS
Multicarrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar, infared imaging
Communications instrumentation
GENERAL DESCRIPTION
The AD9444 is a 14-bit monolithic, sampling analog-to-digital
converter (ADC) with an on-chip, track-and-hold circuit and is
optimized for power, small size, and ease of use. The product
operates at up to an 80 MSPS conversion rate and is optimized
for multicarrier, multimode receivers, such as those found in
cellular infrastructure equipment.
The ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for
many applications. Data outputs are LVDS-compatible (ANSI644) or CMOS-compatible and include the means to reduce
the overall current needed for short trace distances.
AGND AVDD1 AVDD2
DRGND DRVDD
DFS
AD9444
DCS MODE
BUFFER
VIN+
VIN–
CLK+
CLK–
T/H
CLOCK
AND TIMING
MANAGEMENT
PIPELINE
ADC
OUTPUT MODE
14
CMOS
OR
LVDS
OUTPUT
STAGING
2
OR
28
D13–D0
2
DCO
REF
05089-001
80 MSPS guaranteed sampling rate
100 dB two-tone SFDR with 69.3 MHz and 70.3 MHz
73.1 dB SNR with 70 MHz input
97 dBc SFDR with 70 MHz input
Excellent linearity
DNL = ±0.4 LSB typical
INL = ±0.6 LSB typical
1.2 W power dissipation
3.3 V and 5 V supply operation
2.0 V p-p differential full-scale input
LVDS outputs (ANSI-644 compatible)
Data format select
Output clock available
FUNCTIONAL BLOCK DIAGRAM
VREF SENSE REFT REFB
Figure 1.
Optional features allow users to implement various selectable
operating conditions, including data format select and output
data mode.
The AD9444 is available in a 100-lead surface-mount plastic
package (100-lead TQFP/EP) specified over the industrial
temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. High performance: Outstanding SFDR performance for multicarrier, multimode 3G and 4G cellular base station
receivers.
2. Ease of use: On-chip reference and track-and-hold. An
output clock simplifies data capture.
3. Packaged in a Pb-free, 100-lead TQFP/EP.
4. Clock DCS maintains overall ADC performance over a wide
range of clock pulse widths.
5. OR (out-of-range) outputs indicate when the signal is beyond
the selected input range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD9444
TABLE OF CONTENTS
DC Specifications ............................................................................. 3
Clock Input Considerations...................................................... 22
AC Specifications.............................................................................. 4
Power Considerations................................................................ 23
Digital Specifications........................................................................ 5
Digital Outputs ........................................................................... 23
Switching Specifications .................................................................. 6
Timing ......................................................................................... 23
Explanation of Test Levels........................................................... 7
Operational Mode Selection ..................................................... 23
Absolute Maximum Ratings............................................................ 8
Evaluation Board ........................................................................ 24
ESD Caution.................................................................................. 8
LVDS Evaluation Board Schematics ........................................ 25
Definitions of Specifications ........................................................... 9
LVDS Mode Evaluation Board Bill of Materials (BOM) ...... 30
Pin Configurations and Function Descriptions ......................... 10
CMOS Evaluation Board Schematics ...................................... 32
Equivalent Circuits ......................................................................... 14
CMOS Mode Evaluation Board Bill of Materials (BOM)..... 37
Typical Performance Characteristics ........................................... 15
Outline Dimensions ....................................................................... 39
Theory of Operation ...................................................................... 20
Ordering Guide .......................................................................... 39
Analog Input and Reference Overview ................................... 20
REVISION HISTORY
10/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 40
AD9444
DC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed
reference (1.0 V mode), AIN = −0.5 dBFS, DCS on, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error1
Differential Nonlinearity (DNL)2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error
Gain Error
VOLTAGE REFERENCE
Output Voltage1
Load Regulation @ 1.0 mA
Reference Input Current (External 1.0 V Reference)
INPUT REFERRED NOISE
ANALOG INPUT
Input Span
Input Common-Mode Voltage
Input Resistance3
Input Capacitance3
POWER SUPPLIES
Supply Voltage
AVDD1
AVDD2
DRVDD—LVDS Outputs
DRVDD—CMOS Outputs
Supply Current
AVDD1
AVDD22
IDRVDD2—LVDS Outputs
IDRVDD2—CMOS Outputs
PSRR
Offset
Gain
POWER CONSUMPTION
DC Input—LVDS Outputs
DC Input—CMOS Outputs
Sine Wave Input2—LVDS Outputs
Sine Wave Input2—CMOS Outputs
AD9444BSVZ-80
Typ
Max
14
Temp
Full
Test Level
VI
Full
Full
Full
Full
25°C
Full
VI
VI
VI
VI
I
VI
Full
Full
V
V
Full
Full
Full
25°C
VI
V
VI
V
Full
Full
Full
Full
V
V
V
V
Full
Full
Full
Full
IV
IV
IV
IV
Full
Full
Full
Full
VI
VI
VI
V
217
71
55
12
Full
Full
V
V
1
0.2
Full
Full
Full
Full
VI
V
VI
V
1.21
1.07
1.25
1.11
1
Min
6
−3.0
−0.8
−1.3
−1.7
Guaranteed
±0.3
±0.4
±0.4
±0.6
6
+3.0
+0.8
+1.3
+1.7
12
0.002
0.87
1.0
±2
80
1.0
3.3
5.0
3.3
mV
% FSR
LSB
LSB
LSB
µV/°C
%FS/°C
1.13
125
2
3.5
1
2.5
3.14
4.75
3.0
3.0
Unit
Bits
V
mV
µA
LSB rms
V p-p
V
kΩ
pF
3.46
5.25
3.6
3.6
V
V
V
V
240
80
62
mA
mA
mA
mA
mV/V
%/V
1.4
W
W
W
W
The internal voltage reference is trimmed at final test to minimize the gain error of the AD9444.
Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and
approximately 5 pF loading on each output bit for CMOS output mode.
3
Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input
structure.
2
Rev. 0 | Page 3 of 40
AD9444
AC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed
reference (1.0 V mode), AIN = −0.5 dBFS, DCS on, unless otherwise noted.
Table 2.
Parameter
SIGNAL-TO-NOISE-RATIO (SNR)
fIN = 10 MHz
fIN = 35 MHz
fIN = 70 MHz
fIN = 100 MHz
SIGNAL-TO-NOISE-AND DISTORTION (SINAD)
fIN = 10 MHz
fIN = 35 MHz
fIN = 70 MHz
fIN = 100 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
fIN = 35 MHz
fIN = 70 MHz
fIN = 100 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 10 MHz
fIN = 35 MHz
fIN = 70 MHz
fIN = 100 MHz
WORST HARMONIC, SECOND OR THIRD
fIN = 10 MHz
fIN = 35 MHz
fIN = 70 MHz
fIN = 100 MHz
WORST SPUR EXCLUDING SECOND OR HARMONICS
fIN = 10 MHz
fIN = 35 MHz
fIN = 70 MHz
fIN = 100 MHz
TWO-TONE SFDR
fIN = 10.8 MHz @ −7 dBFS, 9.8 MHz @ −7 dBFS
fIN = 70.3 MHz @ −7 dBFS, 69.3 MHz @ −7 dBFS
ANALOG BANDWIDTH
AD9444BSVZ-80
Typ
Max
Temp
Test Level
Min
25°C
Full
25°C
Full
25°C
Full
25°C
IV
IV
I
IV
IV
IV
V
73.0
72.7
72.4
72.3
72.3
72.0
25°C
Full
25°C
Full
25°C
Full
25°C
IV
IV
I
IV
IV
IV
V
73.0
72.7
72.4
72.2
72.2
72.0
25°C
25°C
25°C
25°C
V
V
V
V
25°C
Full
25°C
Full
25°C
Full
25°C
IV
IV
I
IV
IV
IV
V
25°C
Full
25°C
Full
25°C
Full
25°C
IV
IV
I
IV
IV
IV
V
−97
25°C
Full
25°C
Full
25°C
Full
25°C
IV
IV
I
IV
IV
IV
V
−102
25°C
25°C
Full
V
V
V
Rev. 0 | Page 4 of 40
74.0
dB
dB
dB
dB
dB
dB
dB
73.7
73.1
72.3
91
87
91
87
90
87
Unit
74.0
72.3
dB
dB
dB
dB
dB
dB
dB
12.1
12.0
11.9
11.8
Bits
Bits
Bits
Bits
97
dBc
dBc
dBc
dBc
dBc
dBc
dBc
73.7
73.1
97
97
96
−97
−97
−91
−87
−91
−87
−90
−87
dBc
dBc
dBc
dBc
dBc
dBc
dBc
−93
−93
−93
−93
−93
−93
dBc
dBc
dBc
dBc
dBc
dBc
dBc
−96
−103
−102
−99
−102
−100
650
dBFS
dBFS
MHz
AD9444
DIGITAL SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDSBIAS = 3.74 kΩ, unless otherwise noted.
Table 3.
Parameter
CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
DIGITAL OUTPUT BITS—CMOS Mode (D0 to D13, OTR)1
DRVDD = 3.3 V
High Level Output Voltage
Low Level Output Voltage
DIGITAL OUTPUT BITS LVDS Mode (D0 to D13, OTR)
VOD Differential Output Voltage2
VOS Output Offset Voltage
CLOCK INPUTS (CLK+, CLK−)
Differential Input Voltage
Common-Mode Voltage
Differential Input Resistance
Differential Input Capacitance
1
2
AD9444BSVZ-80
Typ
Max
Temp
Test Level
Min
Full
Full
Full
Full
Full
IV
IV
VI
VI
V
2.0
Full
Full
IV
IV
3.25
Full
Full
VI
VI
247
1.125
Full
Full
Full
Full
IV
VI
V
V
0.2
1.3
8
Output voltage levels measured with 5 pF load on each output.
LVDS RTERM = 100 Ω.
Rev. 0 | Page 5 of 40
0.8
+200
+10
−10
2
1.5
10
4
Unit
V
V
µA
µA
pF
0.2
V
V
545
1.375
mV
V
1.6
12
V
V
kΩ
pF
AD9444
SWITCHING SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse Width High1 (tCLKH)
CLK Pulse Width Low1 (tCLKL)
DATA OUTPUT PARAMETERS
Output Propagation Delay—CMOS (tPD)2 (DX, DCO+)
Output Propagation Delay—LVDS (tPD)3 (DX+, DCO+)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Temp
Test Level
Full
Full
Full
Full
Full
VI
V
V
V
V
Full
Full
Full
Full
Full
IV
VI
V
V
V
AD9444BSVZ-80
Min
Typ
Max
80
10
12.5
4
4
3
3
5.25
5
12
0.2
8
7.5
Unit
MSPS
MSPS
ns
ns
ns
ns
ns
Cycles
ns
ps rms
1
With duty cycle stabilizer (DCS) enabled.
Output propagation delay is measured from clock 50% transition to data 50% transition, with 5 pF load.
3
LVDS RTERM = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
2
N–1
N
N+1
AIN
tCLKL
tCLKH
1/fS
CLK+
CLK–
tPD
N–12
DATA OUT
N
N–11
N+1
12 CLOCK CYCLES
05089-002
DCO+
DCO–
tCPD
Figure 2. LVDS Mode Timing Diagram
Rev. 0 | Page 6 of 40
AD9444
N
N–1
N+1
VIN
N+2
tCLKL
tCLKH
CLK–
CLK+
tPD
12 CYCLES
N-12
DX
N-11
N-1
N
tDCOPD
05089-003
DCO+
DCO–
Figure 3. CMOS Timing Diagram
EXPLANATION OF TEST LEVELS
Test Level
I
II
III
IV
V
VI
Definitions
100% production tested.
100% production tested at 25°C and sample tested at specified temperatures.
Sample tested only.
Parameter is guaranteed by design and characterization testing.
Parameter is a typical value only.
100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.
Rev. 0 | Page 7 of 40
AD9444
ABSOLUTE MAXIMUM RATINGS
Thermal Resistance
Table 5.
With
Respect to
Parameter
ELECTRICAL
AVDD1
AGND
AVDD2
AGND
DRVDD
DGND
AGND
DGND
AVDD1
DRVDD
AVDD2
DRVDD
AVDD2
AVDD1
D0 to D13
DGND
CLK, MODE
AGND
VIN+, VIN−
AGND
VREF
AGND
SENSE
AGND
REFT, REFB
AGND
ENVIRONMENTAL
Storage Temperature
Operating Temperature Range
Lead Temperature Range
(Soldering 10 sec)
Junction Temperature
Min
Max
Unit
−0.3
−0.3
−0.3
−0.3
−4
−4
−4
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
+4
+6
+4
+0.3
+4
+6
+6
DRVDD + 0.3
AVDD1 + 0.3
AVDD2 + 0.3
AVDD1 + 0.3
AVDD1 + 0.3
AVDD1 + 0.3
V
V
V
V
V
V
V
V
V
V
V
V
V
–65
–40
+125
+85
300
°C
°C
°C
150
°C
The heat sink of the AD9444 package must be soldered to
ground.
Table 6.
Package Type
100-Lead TQFP/EP
θJA
19.8
θJB
8.3
θJC
2
Unit
°C/W
Typical θJA = 19.8°C/W (heat-sink soldered) for multilayer
board in still air.
Typical θJB = 8.3°C/W (heat-sink soldered) for multilayer board
in still air.
Typical θJC = 2°C/W (junction to exposed heat sink) represents
the thermal resistance through heat-sink path.
Airflow increases heat dissipation effectively reducing θJA. Also,
more metal directly in contact with the package leads, from
metal traces, through holes, ground, and power planes, reduces
the θJA. It is required that the exposed heat sink be soldered to
the ground plane.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
Rev. 0 | Page 8 of 40
AD9444
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Aperture Delay (tA)
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
Offset Error
The major carry transition should occur for an analog value
½ LSB below VIN+ = VIN−. Offset error is defined as the
deviation of the actual transition from that point.
Aperture Uncertainty (Jitter, tJ)
The sample-to-sample variation in aperture delay.
Clock Pulse Width and Duty Cycle
Pulse width high is the minimum amount of time that the
clock pulse should be left in the Logic 1 state to achieve rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed no
missing codes to 14-bit resolution indicates that all 16384 codes
must be present over all operating ranges.
Effective Number of Bits (ENOB)
The effective number of bits for a sine wave input at a given
input frequency can be calculated directly from its measured
SINAD using the following formula
ENOB =
(SINAD − 1.76 )
6.02
Gain Error
The first code transition should occur at an analog value ½ LSB
above negative full scale. The last transition should occur at an
analog value 1 ½ LSB below the positive full scale. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.
Integral Nonlinearity (INL)
The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1 ½ LSBs beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
Output Propagation Delay (tPD)
The delay between the clock rising edge and the time when all
bits are within valid logic levels.
Power-Supply Rejection Ratio
The change in full scale from the value with the supply at the
minimum limit to the value with the supply at its maximum limit.
Signal-to-Noise and Distortion (SINAD)
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc.
Signal-to-Noise Ratio (SNR)
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered) or dBFS (always related
back to converter full scale).
Temperature Drift
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
at TMIN or TMAX.
Total Harmonic Distortion (THD)
The ratio of the rms input signal amplitude to the rms value of
the sum of the first six harmonic components.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Rev. 0 | Page 9 of 40
AD9444
76 D11–
78 D12–
77 D11+
79 D12+
81 D13+ (MSB)
80 D13–
82 DRGND
83 DRVDD
84 OR–
86 AGND
85 OR+
87 AVDD1
88 AGND
89 AVDD1
91 AVDD1
90 AVDD1
92 AVDD1
93 AVDD1
94 AVDD1
96 AGND
95 AVDD1
97 AGND
99 AGND
98 AVDD1
100 DCS MODE
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AVDD1
1
75 DRVDD
DNC
2
74 DRGND
DNC
3
DNC
4
73 D10+
72 D10–
OUTPUT MODE
5
DFS
6
71 D9+
70 D9–
LVDSBIAS
7
69 D8+
AVDD1
8
AVDD1
9
68 D8–
67 DRGND
66 D7+
65 D7–
SENSE 10
VREF 11
AD9444
AGND 12
64 DCO+
TOP VIEW
(Not to Scale)
REFT 13
REFB 14
63 DCO–
62 DRVDD
AGND 15
61 DRGND
60 D6+
AVDD1 16
59 D6–
AVDD1 17
AVDD1 18
58 D5+
57 D5–
AVDD2 19
VIN+ 21
56 D4+
55 D4–
AGND 20
Rev. 0 | Page 10 of 40
D2– 49
D2+ 50
DRGND 48
D1– 45
D1+ 46
DRVDD 47
Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS Mode
05089-004
DNC = DO NOT CONNECT
AVDD1 42
(LSB) D0– 43
D0+ 44
AVDD2 40
AVDD1 41
CLK– 37
AVDD1 38
AVDD2 39
AVDD1 35
CLK+ 36
C1 33
AVDD1 34
51 D3–
AVDD2 31
AGND 32
AVDD1 25
AVDD2 30
53 DRGND
52 D3+
AVDD2 28
AVDD2 29
54 DRVDD
AVDD1 26
AVDD1 27
VIN– 22
AGND 23
AVDD1 24
AD9444
Table 7. Pin Function Descriptions—100-Lead TQFP/EP in LVDS Mode
Pin No.
1, 8 to 9,
16 to 18,
24 to 27,
34 to 35, 38,
41 to 42, 87,
89 to 95, 98
2 to 4
Mnemonic
AVDD1
Description
3.3 V (±5%) Analog Supply.
DNC
5
OUTPUT
MODE
6
DFS
7
LVDSBIAS
10
SENSE
11
VREF
12, 15, 20,
23, 32, 86,
88, 96 to 97,
99, Exposed
Heat Sink
13
AGND
Do Not Connect. These pins
should float.
CMOS Compatible Output Logic
Mode Control Pin. OUTPUT MODE
= 0 for CMOS mode, and OUTPUT
MODE = 1 (AVDD1) for LVDS
outputs.
Data Format Select Pin. CMOS
control pin that determines the
format of the output data. DFS =
high (AVDD1) for twos complement, DFS = low (ground) for
offset binary format.
Set Pin for LVDS Output Current.
Place 3.7 kΩ resistor terminated to
DRGND.
Reference Mode Selection.
Connect to AGND for internal 1 V
reference, and connect to AVDD2
for external reference.
1.0 V Reference I/O—Function
Dependent on SENSE. Decouple
to ground with 0.1 µF and 10 µF
capacitors.
Analog Ground. The exposed
heat sink on the bottom of the
package must be connected to
AGND.
14
REFB
19, 28 to 31,
39 to 40
21
22
33
AVDD2
VIN+
VIN−
C1
36
37
43
CLK+
CLK−
D0− (LSB)
REFT
Differential Reference Output.
Decoupled to ground with 0.1 µF
capacitor and to REFB (Pin 14) with
0.1 µF and 10 µF capacitors.
Differential Reference Output.
Decoupled to ground with a 0.1 µF
capacitor and to REFT (Pin 13) with
0.1 µF and 10 µF capacitors.
5.0 V Analog Supply (±5%).
Pin No.
44
45
46
47, 54, 62,
75, 83
48, 53, 61,
67, 74, 82
49
50
51
52
55
56
57
58
59
60
63
64
65
66
68
69
70
71
72
73
76
77
78
79
80
81
84
D2−
D2+
D3−
D3+
D4−
D4+
D5−
D5+
D6−
D6+
DCO−
DCO+
D7−
D7+
D8−
D8+
D9−
D9+
D10−
D10+
D11−
D11+
D12−
D12+
D13−
D13+ (MSB)
OR−
85
100
OR+
DCS MODE
Analog Input—True.
Analog Input—Complement.
Internal Bypass Node. Connect a
0.1 µF capacitor from this pin
to AGND.
Clock Input—True.
Clock Input—Complement.
D0 Complement Output Bit
(LVDS Levels).
Rev. 0 | Page 11 of 40
Mnemonic
D0+
D1−
D1+
DRVDD
DRGND
Description
D0 True Output Bit.
D1 Complement Output Bit.
D1 True Output Bit.
3.3 V Digital Output Supply
(3.0 V to 3.6 V).
Digital Ground.
D2 Complement Output Bit.
D2 True Output Bit.
D3 Complement Output Bit.
D3 True Output Bit.
D4 Complement Output Bit.
D4 True Output Bit.
D5 Complement Output Bit.
D5 True Output Bit.
D6 Complement Output Bit.
D6 True Output Bit.
Data Clock Output—Complement.
Data Clock Output—True.
D7 Complement Output Bit.
D7 True Output Bit.
D8 Complement Output Bit.
D8 True Output Bit.
D9 Complement Output Bit.
D9 True Output Bit.
D10 Complement Output Bit.
D10 True Output Bit.
D11 Complement Output Bit.
D11 True Output Bit.
D12 Complement Output Bit.
D12 True Output Bit.
D13 Complement Output.
D13 True Output Bit.
Out-of-Range Complement
Output Bit.
Out-of-Range True Output Bit.
Clock Duty Cycle Stabilizer (DCS)
Control Pin, CMOS-Compatible.
DCS = low (AGND) to enable DCS
(recommended). DCS = high
(AVDD1) to disable DCS.
76 D7
78 D9
77 D8
79 D10
81 D12
80 D11
82 DRGND
83 DRVDD
84 D13 (MSB)
86 AGND
85 OR
87 AVDD1
88 AGND
89 AVDD1
91 AVDD1
90 AVDD1
92 AVDD1
93 AVDD1
96 AGND
95 AVDD1
94 AVDD1
98 AVDD1
97 AGND
100 DCS MODE
99 AGND
AD9444
AVDD1
1
75 DRVDD
DNC
2
74 DRGND
DNC
3
DNC
4
73 D6
72 D5
OUTPUT MODE
5
DFS
6
71 D4
70 D3
DNC
7
69 D2
AVDD1
8
AVDD1
9
68 D1
67 DRGND
66 D0 (LSB)
65 DNC
SENSE 10
VREF 11
AD9444
AGND 12
64 DCO+
TOP VIEW
(Not to Scale)
REFT 13
REFB 14
63 DCO–
62 DRVDD
AGND 15
61 DRGND
60 DNC
AVDD1 16
DNC = DO NOT CONNECT
Figure 5. 100-Lead TQFP/EP Pin Configuration in CMOS Mode
Rev. 0 | Page 12 of 40
DNC 49
DNC 50
DRGND 48
DNC 45
DNC 46
DRVDD 47
DNC 43
DNC 44
AVDD1 42
51 DNC
AVDD2 40
AVDD1 41
AVDD1 25
AVDD1 38
AVDD2 39
53 DRGND
52 DNC
CLK+ 36
CLK– 37
54 DRVDD
AGND 23
AVDD1 24
C1 33
AVDD1 34
AVDD1 35
55 DNC
VIN– 22
AVDD2 31
AGND 32
56 DNC
VIN+ 21
AVDD2 30
AGND 20
AVDD2 28
AVDD2 29
58 DNC
57 DNC
AVDD1 26
AVDD1 27
AVDD2 19
05089-005
59 DNC
AVDD1 17
AVDD1 18
AD9444
Table 8. Pin Function Descriptions—100-Lead TQFP/EP in CMOS Mode
Pin No.
1, 8 to 9, 16 to 18,
24 to 27, 34 to 35,
38, 41 to 42, 87,
89 to 95, 98
2 to 4, 7,
43 to 46, 49 to 52,
55 to 60, 65
5
Mnemonic
AVDD1
Description
3.3 V (±5%) Analog Supply.
DNC
Do Not Connect. These
pins should float.
OUTPUT
MODE
10
SENSE
11
VREF
12, 15, 20, 23,
32, 86, 88, 96 to
97, 99, Exposed
Heat Sink
13
AGND
14
REFB
19, 28 to 31,
39 to 40
21
22
AVDD2
CMOS Compatible Output
Logic Mode Control Pin.
OUTPUT MODE = 0 for CMOS
mode, and OUTPUT MODE =
1 (AVDD1) for LVDS outputs.
Data Format Select Pin.
CMOS control pin that determines the format of the
output data. DFS = high
(AVDD1) for twos complement, DFS = low (ground) for
offset binary format.
Reference Mode Selection.
Connect to AGND for internal
1 V reference, and connect to
AVDD2 for external reference.
1.0 V Reference I/O—
Function Dependent on
SENSE. Decouple to ground
with 0.1 µF and 10 µF
capacitors.
Analog Ground. The exposed
heat sink on the bottom of
the package must be
connected to AGND.
Differential Reference Output. Decoupled to ground
with 0.1 µF capacitor and to
REFB (Pin 14) with 0.1 µF and
10 µF capacitors.
Differential Reference Output. Decoupled to ground
with a 0.1 µF capacitor and to
REFT (Pin 13) with 0.1 µF and
10 µF capacitors.
5.0 V Analog Supply (±5%).
VIN+
VIN−
Analog Input—True.
Analog Input—Complement.
6
DFS
REFT
Pin No.
33
Mnemonic
C1
36
37
47, 54, 62,
75, 83
48, 53, 61,
67, 74, 82
63
CLK+
CLK−
DRVDD
64
DCO+
66
D0 (LSB)
68
69
70
71
72
73
76
77
78
79
80
81
84
85
100
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13 (MSB)
OR
DCS MODE
Rev. 0 | Page 13 of 40
DRGND
DCO−
Description
Internal Bypass Node.
Connect a 0.1 µF capacitor
from this pin to AGND.
Clock Input—True.
Clock Input—Complement.
3.3 V Digital Output
Supply (2.5V to 3.6 V).
Digital Ground.
Data Clock Output—
Complement (CMOS Levels).
Data Clock Output—
True.
D0 Output Bit (LSB)
(CMOS Levels).
D1 Output Bit.
D2 Output Bit.
D3 Output Bit.
D4 Output Bit.
D5 Output Bit.
D6 Output Bit.
D7 Output Bit.
D8 Output Bit.
D9 Output Bit.
D10 Output Bit.
D11 Output Bit.
D12 Output Bit.
D13 Output Bit.
Out-of-Range Output.
Clock Duty Cycle Stabilizer
(DCS) Control Pin, CMOSCompatible. DCS = low
(AGND) to enable DCS
(recommended). DCS =
high (AVDD1) to disable DCS.
AD9444
EQUIVALENT CIRCUITS
AVDD2
VIN+
AVDD2
DRVDD
1kΩ
2.5pF
DX
3.5V
AVDD2
05089-009
SHA
X1
1kΩ
Figure 9. Equivalent CMOS Digital Output Circuit
05089-006
VIN–
2.5pF
VDD
Figure 6. Equivalent Analog Input Circuit
DRVDD
DRVDD
DCS MODE,
OUTPUT MODE,
DFS
30kΩ
K
LVDSBIAS
3.74kΩ
ILVDSOUT
05089-007
05089-010
1.2V
Figure 10. Equivalent Digital Input Circuit,
DFS, DCS MODE, OUTPUT MODE
Figure 7. Equivalent LVDS BIAS Circuit
AVDD2
DRVDD
V
DX–
DX+
V
V
12kΩ
150Ω
150Ω
CLK+
CLK–
10kΩ
10kΩ
05089-011
05089-008
V
12kΩ
Figure 8. Equivalent LVDS Digital Output Circuit
Figure 11. Equivalent Sample Clock Input Circuit
Rev. 0 | Page 14 of 40
AD9444
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, sample rate = 80 MSPS, LVDS mode, DCS enabled, TA = 25°C, 2 V p-p differential
input, AIN = −0.5 dBFS, internal trimmed reference (nominal VREF = 1.0 V), unless otherwise noted.
0
80MSPS
100.3MHz @ –0.5dBFS
SNR: 72.3dB
ENOB: 11.8BITS
SFDR: 96dBc
–20
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
–40
–60
–80
–100
0
5
10
15
20
25
30
35
40
FREQUENCY (MHz)
–120
05089-012
–120
0
5
10
15
20
25
30
35
40
FREQUENCY (MHz)
05089-015
AMPLITUDE (dBFS)
0
80MSPS
10.1MHz @ –0.5dBFS
SNR: 73.9dB
ENOB: 12.0BITS
SFDR: 97dBc
Figure 12. 64K Point Single-Tone FFT/80 MSPS/10.1 MHz
Figure 15. 64K Point Single-Tone FFT/80 MSPS/100 MHz
0
0
80MSPS
30.3MHz @ –0.5dBFS
SNR: 74.0dB
ENOB: 12.1BITS
SFDR: 95dBc
–20
AMPLITUDE (dBFS)
–40
–60
–80
–40
–60
–80
0
5
10
15
20
25
30
35
40
FREQUENCY (MHz)
–120
05089-013
–120
0
10
15
20
25
30
35
40
FREQUENCY (MHz)
Figure 13. 64K Point Single-Tone FFT/80 MSPS/30.3 MHz
Figure 16. 64K Point Single-Tone FFT/80 MSPS/125 MHz
0
0
80MSPS
70.3MHz @ –0.5dBFS
SNR: 73.3dB
ENOB: 11.9BITS
SFDR: 100dBc
80MSPS
151MHz @ –0.5dBFS
SNR: 71.1dB
ENOB: 11.5BITS
SFDR: 87dBc
–20
AMPLITUDE (dBFS)
–20
AMPLITUDE (dBFS)
5
05089-016
–100
–100
–40
–60
–80
–40
–60
–80
–100
–120
0
5
10
15
20
25
30
35
FREQUENCY (MHz)
40
05089-014
–100
–120
0
5
10
15
20
25
30
35
FREQUENCY (MHz)
Figure 17. 64K Point Single-Tone FFT/80 MSPS/151 MHz
Figure 14. 64K Point Single-Tone FFT/80 MSPS/70 MHz
Rev. 0 | Page 15 of 40
40
05089-017
AMPLITUDE (dBFS)
–20
80MSPS
125MHz @ –0.5dBFS
SNR: 71.2dB
ENOB: 11.6BITS
SFDR: 91dBc
AD9444
75
75
SNR dB @ –40°C
74
74
SNR dB @ –40°C
73
73
SNR dB @ +25°C
72
SNR dB @ +85°C
(dB)
(dB)
SNR dB @ +25°C
71
71
70
70
69
69
68
68
67
67
66
66
0
20
40
60
80
100 120 140 160
ANALOG INPUT FREQUENCY (MHz)
180
65
05089-018
65
200
SNR dB @ +85°C
0
20
40
60
80
100
120
140
160
180
05089-021
72
200
ANALOG INPUT FREQUENCY (MHz)
Figure 18. SNR vs. Analog Input Frequency, 80 MSPS/LVDS Mode
Figure 21. SNR vs. Analog Input Frequency, 80 MSPS/CMOS Mode
105
105
SFDR dBc @ +85°C
SFDR dBc @ +85°C
SFDR dBc @ +25°C
100
100
95
95
SFDR dBc @ +25°C
(dB)
(dB)
90
85
85
80
80
75
75
0
20
40
60
80
100 120 140 160
ANALOG INPUT FREQUENCY (MHz)
180
70
05089-019
70
200
THIRD –dBFS
0
20
40
60
80
100 120 140 160
ANALOG INPUT FREQUENCY (MHz)
180
200
Figure 22. SFDR vs. Analog Input Frequency, 80 MSPS/CMOS Mode
Figure 19. SFDR vs. Analog Input Frequency, 80 MSPS/LVDS Mode
120
SFDR dBc @ –40°C
05089-022
SFDR dBc @ –40°C
90
120
SECOND –dBFS
SECOND –dBFS
110
THIRD –dBFS
110
100
100
SFDR –dBFS
90
90
SECOND –dBc
80
80
SFDR –dBFS
(dB)
70
SFDR –dBFS
60
70
SECOND –dBc
60
50
50
40
40
30
30
20
20
THIRD –dBc
10
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
ANALOG INPUT AMPLITUDE (dBc)
0
10
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
ANALOG INPUT AMPLITUDE (dBc)
Figure 20. Single-Tone SFDR/Second/Third vs.
Analog Input Level, 80 MSPS, AIN = 30.3 MHz
Figure 23. Single-Tone SFDR/Second/Third vs.
Analog Input Level 80 MSPS, AIN = 70.30 MHz
Rev. 0 | Page 16 of 40
0
05089-023
SFDR –dBFS
05089-020
(dB)
THIRD –dBc
AD9444
0
0
SFDR: 102dBFS
–10
90dBFS REFERENCE LINE
–20
–20
AMPLITUDE (dBFS)
–30
–40
SFDR (dBc)
IMD (dBFS)
–40
–60
–50
–60
–70
–80
–80
–100
–100
WORST THIRD-ORDER IMD (dBc)
–90
SFDR (dBFS)
–110
5
10
15
20
25
30
35
40
FREQUENCY (MHz)
–120
–110 –100 –90
0
0
–10
90dBFS REFERENCE LINE
–20
–20
–30
–30
–50
–60
–70
–80
–40
SFDR (dBc)
–50
–60
–70
WORST THIRD-ORDER IMD (dBc)
–80
SFDR (dBFS)
–90
–100
–100
–110
–110
–120
–120
–110 –100 –90
5
10
15
20
25
30
35
40
FREQUENCY (MHz)
Figure 25. 32K Point Two-Tone FFT 80 MSPS/69.3 MHz/70.3 MHz
95
90
90
SFDR (dB)
95
85
75
75
50
60
70
80
SAMPLE RATE (MSPS)
90
100
110
05089-026
80
40
–60
–50
–40
–30
–20
–10
0
85
80
30
–70
Figure 28. Two-Tone SFDR vs. Analog Input Level, AIN = 69.3 MHz/70.3 MHz
100
20
–80
ANALOG INPUT LEVEL (dBFS)
100
70
WORST THIRD-ORDER IMD (dBFS)
Figure 26. SFDR vs. Sample Rate, VIN = 10.3 MHz @ −0.5 dBFS
70
10
20
30
40
50
60
70
80
SAMPLE RATE (MSPS)
90
100
110
Figure 29. SFDR vs. Sample Rate, VIN = 70.3 MHz @ −0.5 dBFS
Rev. 0 | Page 17 of 40
05089-029
0
05089-025
–90
05089-028
SFDR AND IMD3 (dB)
AMPLITUDE (dBFS)
–10
0
SFDR: –100dBFS
–40
SFDR (dB)
–20
Figure 27. Two-Tone SFDR vs. Analog Input Level, AIN = 9.8 MHz/10.8 MHz
Figure 24. 32K Point Two-Tone FFT 80 MSPS/9.8 MHz/10.8 MHz
–10
WORST THIRD-ORDER IMD (dBFS)
–80 –70 –60 –50 –40 –30
ANALOG INPUT LEVEL (dBFS)
05089-027
0
05089-024
–120
AD9444
0
12000
61.44MSPS
TOTAL INPUT SIGNAL
POWER: –30dBFS
–10
–20
10000
–30
AMPLITUDE (dBFS)
–40
8000
FREQUENCY
–50
–60
–70
–80
6000
4000
–90
–100
2000
–110
0
7.68
15.36
FREQUENCY (MHz)
23.04
30.72
0
05089-030
–130
8179
8180
8181
8182
8183
BIN
8184
8185
8186
8187
05089-033
–120
Figure 33. Ground Input Histogram
80 MSPS, VIN+ = VIN−, 32K Samples
Figure 30. 64K FFT, 61.44 MSPS, 4 @ WCDMA, IF = 46.08 MHz
250
0
NPR: 63.1dB
–10
230
–20
210
190
–40
AVDD1 (3.3V)
CURRENT (mA)
–50
–60
–70
–80
170
150
130
–90
110
–100
90
–110
AVDD2 (5.0V)
DRVDD (3.3V)
70
–130
0
5
10
15
20
25
FREQUENCY (MHz)
30
35
40
05089–031
–120
50
20
Figure 31. NPR, 80 MSPS/18 MHz Notch
30
40
50
60
70
80
90 100
SAMPLE RATE (MSPS)
110
120
130
05089-034
AMPLITUDE (dBFS)
–30
Figure 34. ISUPPLY vs. Sample Rate, AIN = 10.3 MHz @ −0.5 dBFS
100
105
SFDR (dBc)
100
SFDR - DCS ON (dBFS)
95
90
95
SFDR - DCS OFF (dBFS)
85
dB
(dB)
90
80
85
75
SNR (dB)
80
70
75 SNR - DCS ON (dB)
65
30
40
50
60
CLOCK DUTY CYCLE (%)
70
80
60
2.5
05089-032
70
20
2.7
2.9
3.1
3.3
3.5
3.7
VIN COMMON-MODE (V)
Figure 32. Single-Tone SNR/SFDR vs. Clock Duty Cycle,
FSAMPLE = 80 MSPS, 10.3 MHz @ −0.5 dBFS
Figure 35. Single-Tone SNR/SFDR vs.
VIN Common-Mode Voltage 80 MSPS/10.3 MHz
Rev. 0 | Page 18 of 40
3.9
05089-035
SNR - DCS OFF (dB)
AD9444
0.961
0.2
0.960
0.1
0
0.958
0.957
GAIN (%FS)
REFERENCE VOLTAGE (V)
0.959
0.956
0.955
0.954
–0.1
–0.2
–0.3
0.953
0
20
40
TEMPERATURE (°C)
60
80
–0.5
–40
–20
0.75
0.50
0.50
INL ERROR (LSB)
0.75
0.25
0
–0.25
–0.25
–0.75
–0.75
6144
8192
10240 12288 14336 16384
OUTPUT CODE
80
0
–0.50
4096
60
0.25
–0.50
05089-037
DNL ERROR (LSB)
1.00
2048
40
Figure 38. Gain vs. Temperature
1.00
0
20
TEMPERATURE (°C)
Figure 36. VREF vs. Temperature
–1.00
0
Figure 37. DNL Error vs. Output Code, 80 MSPS, AIN = 15 MHz
–1.00
0
2048
4096
6144
8192
10240 12288 14336 16384
OUTPUT CODE
Figure 39. INL Error vs. Output Code, 80 MSPS, AIN = 15 MHz
Rev. 0 | Page 19 of 40
05089-039
–20
05089-036
0.951
–40
05089-038
–0.4
0.952
AD9444
THEORY OF OPERATION
The AD9444 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated, high bandwidth,
track-and-hold circuit that samples the signal prior to quantization by the 14-bit pipeline ADC core. The device includes an
on-board reference and input logic that accepts TTL, CMOS, or
LVPECL levels. The digital output logic levels are user selectable
as standard 3 V CMOS or LVDS (ANSI-644 compatible) via the
OUTPUT MODE pin.
ANALOG INPUT AND REFERENCE OVERVIEW
A stable and accurate 0.5 V voltage reference is built into the
AD9444. The input range can be adjusted by varying the reference voltage applied to the AD9444, using either the internal
reference or an externally applied reference voltage. The input
span of the ADC tracks reference voltage changes linearly. The
various reference modes are described in the next few sections.
Internal Reference Trim
The internal reference voltage is trimmed during the production test to adjust the gain (analog input voltage range) of the
AD9444. Therefore, there is little advantage to the user supplying an external voltage reference to the AD9444. The gain trim
is performed with the AD9444’s input range set to 2 V p-p
nominal (SENSE connected to AGND). Because of this trim,
and because the 2 V p-p analog input range provides maximum
ac performance, there is little benefit to using analog input
ranges < 2 V p-p. Users are cautioned that the differential
nonlinearity of the ADC varies with the reference voltage.
Configurations that use < 2 V p-p may exhibit missing codes
and, therefore, degraded noise and distortion performance.
VIN+
VIN–
REFT
Internal Reference Connection
ADC
CORE
0.1µF
0.1µF
+
10µF
REFB
0.1µF
VREF
10µF
+
0.1µF
SELECT
LOGIC
SENSE
0.5V
AD9444
⎛ R2 ⎞
VREF = 0.5 × ⎜1 +
⎟
R1 ⎠
⎝
05089-043
A comparator within the AD9444 detects the potential at the
SENSE pin and configures the reference into four possible
states, which are summarized in Table 9. If SENSE is grounded,
the reference amplifier switch is connected to the internal resistor divider (see Figure 40), setting VREF to ~1 V. Connecting
the SENSE pin to VREF switches the reference amplifier output
to the SENSE pin, completing the loop and providing a ~0.5 V
reference output. If a resistor divider is connected, as shown in
Figure 41, the switch again sets to the SENSE pin. This puts the
reference amplifier in a noninverting mode with the VREF
output defined as
Figure 40. Internal Reference Configuration
VIN+
In all reference configurations, REFT and REFB drive the A/D
conversion core and establish its input span. The input range of
the ADC always equals twice the voltage at the reference pin for
either an internal or an external reference.
VIN–
REFT
ADC
CORE
0.1µF
0.1µF
+
10µF
REFB
0.1µF
VREF
+
10µF
0.1µF
R2
SELECT
LOGIC
SENSE
0.5V
AD9444
Figure 41. Programmable Reference Configuration
Rev. 0 | Page 20 of 40
05089-042
R1
AD9444
Table 9. Reference Configuration Summary
Selected Mode
External Reference
Internal Fixed Reference
Programmable Reference
SENSE Voltage
AVDD
VREF
0.2 V to VREF
Resulting VREF (V)
N/A
0.5
Internal Fixed Reference
AGND to 0.2 V
1.0
Resulting Differential Span (V p-p)
2 × External Reference
1.0
2 × VREF
R2 ⎞
⎛
0.5 × ⎜ 1 +
⎟ (See Figure 41)
R1 ⎠
⎝
2.0
External Reference Operation
Analog Inputs
As with most new high speed, high dynamic range ADCs, the
analog input to the AD9444 is differential. Differential inputs
improve on-chip performance as signals are processed through
attenuation and gain stages. Most of the improvement is a result
of differential analog stages having high rejection of even-order
harmonics. There are also benefits at the PCB level. First,
differential inputs have high common-mode rejection of stray
signals, such as ground and power noise. Second, they provide
good rejection of common-mode signals, such as local oscillator
feedthrough. The specified noise and distortion of the AD9444
cannot be realized with a single-ended analog input, so such
configurations are discouraged. Contact ADI for recommendations of other 14-bit ADCs that support single-ended analog
input configurations.
With the 1 V reference (nominal value, see the Internal Reference Trim section), the differential input range of the AD9444’s
analog input is nominally 2 V p-p or 1 V p-p on each input
(VIN+ or VIN−).
1Vp-p
3.5V
VIN–
DIGITAL OUT = ALL 1s
DIGITAL OUT = ALL 0s
05089-045
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 kΩ load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1 V.
VIN+
Figure 42. Differential Analog Input Range for VREF = 1 V
The AD9444 analog input voltage range is offset from ground
by 3.5 V. Each analog input connects through a 1 kΩ resistor to
the 3.5 V bias voltage and to the input of a differential buffer.
The internal bias network on the input properly biases the
buffer for maximum linearity and range (see the Equivalent
Circuits section). Therefore, the analog source driving the
AD9444 should be ac-coupled to the input pins. The recommended method for driving the analog input of the AD9444 is
to use an RF transformer to convert single-ended signals to
differential (see Figure 44). Series resistors between the output
of the transformer and the AD9444 analog inputs help isolate
the analog input source from switching transients caused by the
internal sample-and-hold circuit. The series resistors, along with
the 1 kΩ resisters connected to the internal 3.5 V bias, must be
considered in impedance matching the transformers input. For
example, if RT were set to 51 Ω and RS were set to 33 Ω, along
with a 1:1 impedance ratio transformer, the input would match
a 50 Ω source with a full-scale drive of 10.0 dBm. The 50 Ω
impedance matching can also be incorporated on the secondary
side of the transformer, as shown in the evaluation board schematic (see Figure 47 and Figure 59).
ANALOG
INPUT
SIGNAL RT
RS
ADT1–1WT
RS
0.1µF
AIN
AD9444
AIN
05089-046
The AD9444’s internal reference is trimmed to enhance the gain
accuracy of the ADC. An external reference may be more stable
over temperature, but the gain of the ADC is not likely to be
improved. Figure 36 shows the typical drift characteristics of the
internal reference in both 1 V and 0.5 V modes.
Figure 43. Transformer-Coupled Analog Input Circuit
Rev. 0 | Page 21 of 40
AD9444
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be
sensitive to the clock duty cycle. Commonly a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance characteristics. The AD9444 contains a clock duty cycle
stabilizer (DCS) that retimes the nonsampling edge, providing
an internal clock signal with a nominal 50% duty cycle. As
shown in Figure 32, noise and distortion performance are nearly
flat for a 30% to 70% duty cycle with the DCS enabled. The DCS
circuit locks to the rising edge of CLK+ and optimizes timing
internally. This allows for a wide range of input duty cycles at
the input without degrading performance. Jitter in the rising
edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 30 MHz
nominally. The loop has a time constant associated with it that
needs to be considered in applications where the clock rate can
change dynamically, which requires a wait time of 1.5 µs to 5 µs
after a dynamic clock frequency increase (or decrease) before
the DCS loop is relocked to the input signal. During the time
period the loop is not locked, the DCS loop is bypassed, and the
internal device timing is dependant on the duty cycle of the
input clock signal. In such an application, it may appropriate to
disable the duty cycle stabilizer. In all other applications,
enabling the DCS circuit is recommended to maximize ac
performance.
The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the duty cycle stabilizer, and logic high (AVDD1 = 3.3 V) disables the controller.
The AD9444 input sample clock signal must be a high quality,
extremely low phase noise source to prevent degradation of
performance. Maintaining 14-bit accuracy places a premium on
the encode clock phase noise. SNR performance can easily
degrade by 3 dB to 4 dB with 70 MHz analog input signals
when using a high jitter clock source. (See AN-501, Aperture
Uncertainty and ADC System Performance, for complete
details.) For optimum performance, the AD9444 must be
clocked differentially. The sample clock inputs are internally
biased to ~2.2 V, and the input signal is usually ac-coupled into
If a low jitter clock is available, another option is to ac couple a
differential ECL/PECL signal to the encode input pins, as shown
in Figure 46.
ADT1–1WT
CLOCK
SOURCE
CLK+
0.1µF
AD9444
CLK–
HSMS2812
DIODES
05089-047
Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer, and any noise, distortion, or timing jitter on
the clock is combined with the desired signal at the A/D output.
For that reason, considerable care was taken in the design of the
clock inputs of the AD9444, and the user is advised to give
careful thought to the clock source.
the CLK+ and CLK− pins via a transformer or capacitors.
Figure 44 shows one preferred method for clocking the AD9444.
The clock source (low jitter) is converted from single-ended-todifferential using an RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions
into the AD9444 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9444 and limits the noise
presented to the sample clock inputs.
Figure 44. Crystal Clock Oscillator, Differential Encode
VT
0.1µF
ENCODE
ECL/
PECL
0.1µF
AD9444
ENCODE
VT
05089-048
CLOCK INPUT CONSIDERATIONS
Figure 45. Differential ECL for Encode
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency (fINPUT) and rms amplitude due only to aperture jitter
(tJ) can be calculated using the following equation.
SNR = 20 log[2πfINPUT × tJ]
In the equation, the rms aperture jitter represents the root-mean
square of all jitter sources, which includes the clock input,
analog input signal, and ADC aperture jitter specification. IF
undersampling applications are particularly sensitive to jitter,
see Figure 46.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9444. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step.
Rev. 0 | Page 22 of 40
AD9444
75
tion resistor placed at the LVDS receiver inputs results in a
nominal 350 mV swing at the receiver. LVDS mode facilitates
interfacing with LVDS receivers in custom ASICs and FPGAs
that have LVDS capability for superior switching performance
in noisy environments. Single point-to-point net topologies are
recommended with a 100 Ω termination resistor as close to the
receiver as possible. It is recommended to keep the trace length
less than 1 inch to 2 inches and to keep differential output trace
lengths as equal as possible.
0.2ps
70
65
SNR (dBc)
0.5ps
60
1.0ps
1.5ps
55
2.0ps
2.5ps
50
3.0ps
CMOS Mode
40
1
10
100
INPUT FREQUENCY (MHz)
1000
05089-049
45
Figure 46. SNR vs. Input Frequency and Jitter
POWER CONSIDERATIONS
Care should be taken when selecting a power source. The use of
linear dc supplies is highly recommended. Switching supplies
tend to have radiated components that may be received by the
AD9444. Each of the power supply pins should be decoupled as
closely to the package as possible using 0.1 µF chip capacitors.
The AD9444 has separate digital and analog power supply
pins. The analog supplies are denoted AVDD1 (3.3 V) and
AVDD2 (5 V) and the digital supply pins are denoted DRVDD.
Although the AVDD1 and DRVDD supplies may be tied
together, best performance is achieved when the supplies are
separate. This is because the fast digital output swings can
couple switching current back into the analog supplies. Note
that both AVDD1 and AVDD2 must be held within 5% of the
specified voltage.
The DRVDD supply of the AD9444 is a dedicated supply for the
digital outputs, in either LVDS or CMOS output modes. When
in LVDS mode, the DRVDD should be set to 3.3 V. In CMOS
mode, the DRVDD supply may be connected from 2.5 V to
3.6 V to be compatible with the receiving logic.
DIGITAL OUTPUTS
In applications that can tolerate a slight degradation in dynamic
performance, the AD9444 output drivers can be configured to
interface with 2.5 V or 3.3 V logic families by matching DRVDD
to the digital supply of the interfaced logic. CMOS outputs are
available when OUTPUT MODE is CMOS logic low (or AGND
for convenience). In this mode, the output data bits are singleended CMOS, DX, as is the overrange output, OR. The output
clock is provided as a differential CMOS signal, DCO+/DCO−.
Lower supply voltages are recommended to avoid coupling
switching transients back to the sensitive analog sections of the
ADC. The capacitive load to the CMOS outputs should be
minimized, and each output should be connected to a single
gate through a series resistor (220 Ω) to minimize switching
transients caused by the capacitive loading.
TIMING
The AD9444 provides latched data outputs with a pipeline delay
of 12 clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of CLK+. Refer to Figure 2 and
Figure 3 for detailed timing diagrams.
OPERATIONAL MODE SELECTION
Data Format Select
The data format select (DFS) pin of the AD9444 determines
the coding format of the output data. This pin is 3.3 V CMOS
compatible, with logic high (or AVDD1, 3.3 V) selecting twos
complement, and DFS logic low (AGND) selecting offset binary
format. Table 10 summarizes the output coding.
LVDS Mode
Output Mode Select
The off-chip drivers on the chip can be configured to provide
LVDS-compatible output levels via Pin 5 (OUTPUT MODE).
LVDS outputs are available when OUTPUT MODE is CMOS
logic high (or AVDD1 for convenience) and a 3.74 kΩ RSET
resistor is placed at Pin 7 (LVDSBIAS) to ground. Dynamic
performance, including both SFDR and SNR, is maximized
when the AD9444 is used in LVDS mode, and designers are
encouraged to take advantage of this mode. The AD9444 outputs include complimentary LVDS outputs for each data bit
(DX+/DX−), the overrange output (OR+/OR−), and the output
data clock output (DCO+/DCO−). The RSET resistor current is
ratioed on-chip, setting the output current at each output equal
to a nominal 3.5 mA (11 × I RSET ). A 100 Ω differential termina-
The OUPUT MODE pin controls the logic compatibility,
as well as the pinout of the digital outputs. This pin is a CMOS
compatible input. With OUTPUT MODE = 0 (AGND), the
AD9444 outputs are CMOS-compatible and the pin assignment
for the device is defined in Table 8. With OUTPUT MODE = 1
(AVDD1, 3.3 V), the AD9444 outputs are LVDS-compatible and
the pin assignment for the device is defined in Table 7.
Duty Cycle Stabilizer
The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the DCS, and logic
high (AVDD1, 3.3 V) disables the controller.
Rev. 0 | Page 23 of 40
AD9444
Table 10. Digital Output Coding
Code
16383
8192
8191
0
VIN+ − VIN−
Input Span = 2 V p-p (V)
1.000
0
−0.000122
−1.00
VIN+ − VIN−
Input Span = 1 V p-p (V)
0.500
0
−0.000061
−0.5000
EVALUATION BOARD
Digital Output
Offset Binary (D9••••••D0)
11 1111 1111 1111
10 0000 0000 0000
01 1111 1111 1111
00 0000 0000 0000
Digital Output
Twos Complement (D9••••••D0)
01 1111 1111 1111
00 0000 0000 0000
11 1111 1111 1111
10 0000 0000 0000
Evaluation boards are offered to configure the AD9444 in
either CMOS or LVDS mode. Each represents a recommended
configuration for using the device over a wide range of sample
rates and analog input frequencies. These evaluation boards
provide all the support circuitry required to operate the ADC in
its various modes and configurations. Complete schematics and
layout plots follow and demonstrate the proper routing and
grounding techniques that should be applied at the system level.
Both the LVDS and CMOS versions of the evaluation board are
compatible with the high speed ADC FIFO evaluation kit (part
number HSC-ADC-EVALA-SC). The kit includes a high speed
data capture board that provides a hardware solution for capturing up to 32Ksamples of high speed ADC output data in a FIFO
memory chip (user upgradeable to 256K samples). Software is
provided to enable the user to download the captured data to a
PC via the USB port. This software also includes a behavioral
model of the AD9444 and many other high speed ADCs.
It is critical that signal sources with very low phase noise
(< 1 ps rms jitter) be used to realize the ultimate performance
of the converter. Proper filtering of the input signal, to remove
harmonics and lower the integrated noise at the input, is also
necessary to achieve the specified noise performance.
Behavioral modeling of the AD9444 is also available at
www.analog.com/ADIsimADC. The ADIsimADC™ software
supports virtual ADC evaluation using ADI proprietary
behavioral modeling technology. This allows rapid comparison
between the AD9444 and other high speed ADCs, with or
without hardware evaluation boards.
The evaluation boards are shipped with an ac to 6 V dc power
supply. The evaluation boards include low dropout regulators to
generate the various dc supplies required by the AD9444 and its
support circuitry. Separate power supplies are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers
(see Figure 47 to Figure 50 and Figure 59 to Figure 61).
The AD9444 LVDS evaluation board includes an on-board,
LVDS-to-CMOS translator, but the user may choose to remove
the translator and terminations to access the LVDS outputs
directly.
The CMOS evaluation board includes a buffer for the output
data and the DCO output clock of the AD9444.
Rev. 0 | Page 24 of 40
Rev. 0 | Page 25 of 40
Figure 47. LVDS Mode Evaluation Board Schematic
C13
20pF
GND
VCC
VCC
VCC
5V
GND
VCC
VCC
GND
GND
U1
PIN DEFINITIONS
LVDS/CMOS
AD9444
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
C9
0.1µF
C91
0.1µF
GND
R13
xx
C51
10µF
ANALOG
R6
36Ω
R4
36Ω
C2
0.1µF
GND
TOUTB
GND
R28
33Ω
C5 TINB
E15
0.1µF
C12
0.1µF
0.1µF
VCC
VCC
1kΩ
D2+
D2–
DRGND
DRVDD
D1+
D1–
D0+
(LSB) D0–
AVDD1
AVDD1
AVDD2
AVDD2
AVDD1
CLK–
CLK+
AVDD1
AVDD1
C1
AGND
AVDD2
AVDD2
AVDD2
AVDD2
AVDD1
AVDD1
L1
100Ω
4
3
TOUT
6
2
3.8kΩ
GND
R5
J4 xx
3.8kΩ
GND
C24
0.1µF
GND
GND
GND
GND
1
5
R2
T5
ADT1-1WT
+
10µF
C39
E25
E27
C3
0.1µF
NC
GND
E41
E24
E26
R1
3.8kΩ
R3
GND
EXTREF
GND
VCC
R20
XX
EXTREF
E20
GND
C86
R14
AVDD1
DNC
DNC
DNC
OUTPUT MODE
DFS
LVDSBIAS/DNC
AVDD1
AVDD1
SENSE
VREF
AGND
REFT
REFB
AGND
AVDD1
AVDD1
AVDD1
AVDD2
AGND
VIN+
VIN–
AGND
AVDD1
AVDD1
EPAD
GND
101
E2
C36
0.1µF
D11–
D11+
D12–
D12+
D13–
D13+ (MSB)
DRGND
DRVDD
OR–
OR+
AGND
AVDD1
AGND
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AGND
AGND
AVDD1
AGND
DCS MOD
GND
E1
D12_T/D10_YN
D13_C/D11_YN
D13_T/D12_YN
GND
DRVDD
DOR_C/D13_YN
DOR_T/DOR_YN
GND
VCC
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
GND
GND
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
E3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DRVDD
DRGND
D10+
D10–
D9+
D9–
D8+
D8–
DRGND
D7+
D7–
DCO+
DCO–
DRVDD
DRGND
D6+
D6–
D5+
D5–
D4+
D4–
DRVDD
DRGND
D3+
D3–
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
1kΩ
R15
1kΩ
D11_C/D7_YN
D11_T/D8_YN
D12_C/D9_YN
VCC
VCC
GND
GND
D6_TN
D6_CN
D5_TN
D5_CN
D4_TN
D4_CN
DRVDD
GND
D3_TN
D3_CN
D7_T/D0_YN
D7_CN
DRN
DRBN
DRVDD
GND
D9_C/D3_YN
D8_T/D2_YN
D8_C/D1_YN
GND
GND
D10_T/D6_YN
D10_C/D5_YN
D9_T/D4_YN
DRVDD
H2
MTHOLE6
GND
R27
XX
E40
E39
VCC
GND
E38
H3
MTHOLE6
U2
VCC
XTALINPUTB
XTALINPUT
XTALOUTB
XTALOUT
R12
1kΩ
R9
DRVDD
R19
XX
R37
XX
VXTAL
C26
0.1µF
VCC
ENCB
H4
MTHOLE6
GND
6
5
4
GND
2
VCC
OUTPUTB
OUTPUT
R38
XX
3
XTALINPUTB
GND R40
XX
GND
1
JN00158
VXTAL
C42
0.1µF
5V
1
E/D
2
3 NC
GND
~OUT
4
6
2
PRI SEC
3
P5
VDL
05089-050
VEE
1
NC 5
ENC
GND
FOR VF XTAL
R18
XX
7
GND
GND
50Ω
R8
FOR VECTRON XTAL
GND
8 XTALOUTB
R36
XX
1 XTALOUT
J1
ENCODE
T3
ADT1-1WT
CR2
OUT
GND
XTALINPUT
J5
GND
GND
VCC
VXTAL
C92
0.1µF
R39
XX
U6
ECLOSC
GND
C93
0.1µF
GND
14
VCC
C44
10µF
GND
R17
XX
GND
E52
+
ENCODE
8
7
6
5
4
3
2
1
VXTAL
E46
5V
GND
50Ω
R7
VXTAL
E47
VXTAL
OPTIONAL ENCODE CIRCUITS
AD9444
LVDS EVALUATION BOARD SCHEMATICS
H1
MTHOLE6
D2_TN
D2_CN
GND
DRVDD
D1_TN
D1_CN
D0_TN
D0_CN
VCC
VCC
VCC
ENCB
ENC
VCC
VCC
5V
GND C40
0.1µF
GND
VCC
VCC
5V
OPTIONAL
33Ω
R35
AD9444
POWER OPTIONS
ADP3338
PJ-102A
C33
10µF
GND
5V
VIN
3
+
C34
10µF
C4
10µF
C89
10µF
05089-051
GND
GND
GND
2
OUT1
OUT
IN
+
1
+
C6
10µF
GND
5V
4
C88
10µF
1
3
GND
+
1
GND
VIN
3
5V
DRVDD
DRVDD
OUT1
OUT
GND
U14
IN
+
GND
GND
GND
ADP3338
2
VCC
VCC
+
U3
1
3
2
C87
10µF
ADP3338
GND
2
3
C1
10µF
+
4
OUT1
OUT
IN
C57
10µF
3.3V
2
VIN
3
+
+
1
GND
4
GND
IN
2
VIN
OUT1
OUT
1
VDL
VDL
GND
4
VIN
P4
3.3V
GND
U15
3.3V
GND
U4
GND
ADP3338
Figure 48. LVDS Mode Evaluation Board Schematic (Continued)
VCC
+
C43
0.1µF
C64
10µF
C35
0.1µF
C32
0.1µF
C30
0.1µF
C28
0.1µF
C27
0.1µF
C48
0.1µF
C50
0.1µF
C60
0.1µF
C61
0.1µF
C46
0.1µF
C75
0.1µF
C14
XX
C17
XX
C16
XX
C15
XX
C31
XX
C37
XX
C38
XX
C29
XX
C19
XX
C18
XX
C90
XX
C70
XX
C45
XX
C49
XX
P19
GND
GND
VCC
C10
XX
C11
XX
GND
DRVDD
DRVDD
+
C65
10µF
C47
0.1µF
C23
0.1µF
C22
0.1µF
C21
0.1µF
C59
XX
GND
EXTREF
5V
5V
+
C56
10µF
C85
0.1µF
C53
0.1µF
C52
0.1µF
C71
XX
C58
0.1µF
C72
XX
C73
XX
+
C62
XX
GND
GND
Figure 49. LVDS Mode Evaluation Board Schematic (Continued)
Rev. 0 | Page 26 of 40
C55
10µF
05089-052
GND
GND
C69
XX
C20
0.1µF
AD9444
U7
SN75LVDS386
P6
C40MS
39
37
GND
DOR_C/D13_YN
D13_C/D11_YN
D12_C/D9_YN
D11_C/D7_YN
D10_C/D5_YN
D9_C/D3_YN
D8_C/D1_YN
D7_CN
DRBN
D6_CN
D5_CN
D4_CN
D3_CN
D2_CN
35
33
31
P39
P40
P37
P38
P35
P36
P33
P32
P29
P30
P27
P28
25 P25
23 P23
P26
21 P21
19 P19
P22
17 P17
15 P15
P18
13 P13
11 P11
P14
9 P9
7 P7
P10
29
27
D0_CN
5 P5
3 P3
GND
1 P1
D1_CN
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
GND
P34
P31
2
P24
P20
P16
P12
P8
P6
P4
P2
40
GND
38
36
34
GND
DOR_T/DOR_YN
32
D13_T/D12_YN
30
D12_T/D10_YN
28
D11_T/D8_YN
26
D10_T/D6_YN
24
D9_T/D4_YN
22
20
18
16
14
12
10
8
6
4
2
D8_T/D2_YN
D7_T/D0_YN
DRN
D6_TN
D5_TN
D4_TN
D3_TN
D2_TN
D1_TN
D0_TN
GND
P40
P39 39
GND
P38
P37 37
DRO
P36
P35 35
GND
P34
P33 33
D13O
P32
P31 31
D12O
P30
P29 29
D11O
P28
P27 27
D10O
P26
P25 25
D9O
P24
P23 23
D8O
P22
P21 21
D7O
P20
P19 19
D6O
P18
P17 17
D5O
P16
P15 15
D4O
P14
P13 13
D3O
P12
P11 11
D2O
P10
P9 9
D1O
P8
P7 7
D0O
P6
P5 5
ORO
P4
P3 3
P2
P1 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A1A
A1B
A2A
A2B
A3A
A3B
A4A
A4B
B1A
B1B
B2A
B2B
B3A
B3B
B4A
B4B
C1A
C1B
C2A
C2B
C3A
C3B
C4A
C4B
D1A
D1B
D2A
D2B
D3A
D3B
D4A
D4B
GND
VCC1
VCC2
GND1
ENA
A1Y
A2Y
A3Y
A4Y
ENB
B1Y
B2Y
B3Y
B4Y
GND2
VCC3
VCC4
GND3
C1Y
C2Y
C3Y
C4Y
ENC
D1Y
D2Y
D3Y
D4Y
END
GND4
VCC5
VCC6
GND5
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND
VDL
VDL
GND
VDL
RZ5
220
RSO16ISO
R1
1
R2
2
R3
3
R4
4
VDL
R5
5
R6
6
R7
7
R8
8
GND
VDL
VDL
GND
DRP
16
ORO
15
D13O
14
D12O
13
D11O
12
D10O
11
D9O
10
D8O
9
D7O
220
RSO16ISO
VDL
VDL
GND
VDL
VDL
GND
1
R1
16
D6O
2
R2
15
D5O
3
R3
14
D4O
4
R4
13
D3O
5
R5
12
D2O
6
R6
11
D1O
7
R7
10
D0O
8
R8
9
RZ4
74VCX86
3
1 1A
1Y
2 1B
4 2A
GND
00 XORN
VDL
E43
GND
E34
00
8
9 3A
11 R52
3Y
14 PWR
12 4A
GND
6
5 2B
10 3B
R53
E32
2Y
4Y
13 4B
7
GND
DRO
VDL
GND
U10
VDL
+
C76
10µF
C97
0.1µF
C82
0.1µF
C80
0.1µF
81
0.1µF
GND
05089-053
GND
DOR_T/DOR_YN
DOR_C/D13_YN
D13_T/D12_YN
D13_C/D11_YN
D12_T/D10_YN
D12_C/D9_YN
D11_T/D8_YN
D11_C/D7_YN
D10_T/D6_YN
D10_C/D5_YN
D9_T/D4_YN
D9_C/D3_YN
D8_T/D2_YN
D8_C/D1_YN
D7_T/D0_YN
D7_CN
DRN
DRBN
D6_TN
D6_CN
D5_TN
D5_CN
D4_TN
D4_CN
D3_TN
D3_CN
D2_TN
D2_CN
D1_TN
D1_CN
D0_TN
D0_CN
GND
P3
C40MS
Figure 50. LVDS Mode Evaluation Board Schematic (Continued)
Rev. 0 | Page 27 of 40
05089-057
05089-060
AD9444
Figure 54. LVDS Mode Evaluation Board Layout, Ground Plane 2
05089-061
05089-058
Figure 51. LVDS Mode Evaluation Board Layout, Primary Side
05089-059
05089-062
Figure 55. LVDS Mode Evaluation Board Layout, Power Plane 1
Figure 52. LVDS Mode Evaluation Board Layout, Secondary Side
Figure 56. LVDS Mode Evaluation Board Layout, Power Plane 2
Figure 53. LVDS Mode Evaluation Board Layout, Ground Plane 1
Rev. 0 | Page 28 of 40
05089-063
05089-064
AD9444
Figure 57. LVDS Mode Evaluation Board Layout, Primary Silkscreen
Figure 58. LVDS Mode Evaluation Board Layout, Secondary Silkscreen
Rev. 0 | Page 29 of 40
AD9444
LVDS MODE EVALUATION BOARD BILL OF MATERIALS (BOM)
Table 11.
Item
1
2
Qty.
1
16
3
38
4
5
6
1
1
17
7
8
9
10
11
12
13
14
2
1
1
1
1
2
1
4
15
16
2
3
17
18
19
20
21
22
23
24
25
2
2
1
3
1
1
1
1
4
REFDES
AD9444PCB
C1, C4, C6,
C33, C34,
C39, C44,
C55 to C57,
C64, C65,
C76, C87 to
C89
C2, C3, C5,
C9, C12, C20
to C24, C26
to C28, C30,
C32, C35,
C40, C42,
C43, C46 to
C48, C50,
C52, C53,
C58, C60,
C61, C75,
C80 to C82,
C85, C86,
C91 to C93,
C97
C51
CR2
E1 to E3, E24,
to E27, E32,
E34, E38,
E39, E40,
E41, E43,
E46, E47, E52
J1, J4
L1
P3
P4
R3
R4, R6
R8
R9, R12, R14,
R15
R28, R35
R39, R52,
R53
RZ4, RZ5
T3, T5
U1
U3, U4, U15
U14
U6
U7
U10
U6
Description
PCB, AD9444 LVDS Engineering Evaluation Board
Capacitors, Tantalum, SMT BCAPTAJC, 10 µF, 16 V, 10%
Manufacturer
PCSM
KEMET
MFG_PART_NO
AD9444LVDSCUSTREVC
T491C106K016AS
Capacitors, 0.1 µF 10 V Ceramic X5R 0402
Panasonic
ECJ-0EB1A104K
Capacitor, Ceramic 10 µF 6.3 V X5R 0805
Diode, Dual Schottky HSMS2812, SOT-23, 30 V, 20 mA
40-Pin Breakable Header
KEMET
Panasonic
3M
C0805C106K9PACTU
MA716-(TX)
2340-611TN
Connector, Gold, Male, Coaxial, SMA, Vertical
10 nH Inductor
Header, 40-Pin, Male, 40-Pin Right Angle
Power Jack
Resistor, 3.6 kΩ 1/16 W 1% 0402 SMD
Resistor, 36 Ω 1/16 W 5% 0402 SMD
Resistor, 49.9 Ω 1/16 W 1% 0402 SMD
Resistor, 1.00 kΩ 1/16 W 1% 0402 SMD
Johnston Comp.
Coilcraft
Samtec
Swithcraft
Panasonic
Panasonic
Panasonic
Panasonic
142-0701-201
0603CJ-10NXGBU
TSW-120-08-T-D-RA
RAPC722
ERJ-2GEJ362X
ERJ-2GEJ360X
ERJ-2RKF49R9X
ERJ-2RKF1001X
Resistor, 33 Ω 1/16 W 5% 0402 SMD
Resistor, 0 Ω 1/16 W 5% 0402 SMD
Panasonic
Panasonic
ERJ-2GEJ330X
ERJ-2GE0R00X
22 Ω Resistor Array, 16 Term
Transformer, ADT1-1WT, CD542, ADT1-1WT
14-Bit, 80 MSPS ADC
3.3 V Voltage Regulator
5 V Voltage Regulator
Clock Oscillator, 80 MHz
LVDS-to-CMOS Translator with 100 Term
2 Input XOR Gate
Pin Sockets, Closed End
CTS Corp.
Mini-Circuits
ADI
ADI
ADI
CTS Reeves
Texas Instruments
Fairchild
AMP
742163220JTR
ADT1-1WT
AD9444BSVZ-80
ADP3338-3.3 V
ADP3338-5.0 V
MX045-80
SN75LVDT386DGG
74VCX86M
5-330808-3
Rev. 0 | Page 30 of 40
AD9444
Item
26
Qty.
24
27
28
29
1
2
1
30
1
31
5
1
REFDES
C10, C11,
C13, to C19,
C29, C31,
C36 to C38,
C45, C49,
C59, C62,
C69, C70 to
C73, C901
J51
P5, P61
R1, R2, R5,
R7, R131
R17 to R20,
R27, R36 to
R38, R401
U21
Description
Capacitors, Select 10 V Ceramic X5R 0402
Manufacturer
Panasonic
MFG_PART_NO
Connector, Gold, Male, Coaxial, SMA, Vertical
Power Connectors
Resistors, Select 1/16 W 1% 0402 SMD
Johnston Comp.
Weiland
Panasonic
142-0701-201
Resistors, Select 1/16 W 1% 0402 SMD
Panasonic
XO Select
Vectron
Parts not placed.
Rev. 0 | Page 31 of 40
Rev. 0 | Page 32 of 40
Figure 59. CMOS Mode Evaluation Board Schematic
E15
TOUTB
GND
R6
36Ω
R4
36Ω
C9
0.1µF
C91
0.1µF
GND
R13
xx
C51
10µF
C13
20pF
GND
VCC
VCC
U1
PIN DEFINITIONS
LVDS/CMOS
AD9444
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
OPTIONAL
05089-054
PRI
CT
VCC
5V
GND
VCC
VCC
GND
GND
VCC
VCC
1kΩ
R15
DNC
DNC
DRGND
DRVDD
DNC
DNC
DNC
DNC
AVDD1
AVDD1
AVDD2
AVDD2
AVDD1
CLK–
CLK+
AVDD1
AVDD1
C1
AGND
AVDD2
AVDD2
AVDD2
AVDD2
AVDD1
AVDD1
GND
100Ω
4
3
C12
SEC
0.1µF
6
2
1
5
C78
0.1µF
L110NH C5 TINB
0.1µF
ANALOG
R5
xx
3.8kΩ
GND
R28
33Ω
J4
R2
3.8kΩ
NC
C39
+
10µF
GND
C2
0.1µF
GND
GND
EXTREF
GND
E25
E27
GND
T5
ADT1-1WT TOUT
R1
3.8kΩ
R3
GND
E26
R20
XX
E41
E24
VCC
C3
0.1µF
GND
GND
GND
EPAD
E2
101
D7
D8
D9
D10
D11
D12
DRGND
DRVDD
(MSB) D13
OR
AGND
DRVDD
AGND
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AGND
AGND
AVDD1
AGND
DCS MODE
EXTERNAL
REFERENCE
INPUT
E20
EXTREF
E1
H3
MTHOLE6
DRVDD
DRGND
D6
D5
D4
D3
D2
D1
DRGND
D0 (LSB)
DNC
DCO+
DCO–
DRVDD
DRGND
DNC
DNC
DNC
DNC
DNC
DNC
DRVDD
DRGND
DNC
DNC
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
H4
MTHOLE6
AVDD1
DNC
DNC
DNC
OUTPUT MODE
DFS
LVDSBIAS
AVDD1
AVDD1
SENSE
VREF
AGND
REFT
REFB
AGND
AVDD1
AVDD1
AVDD1
AVDD2
AGND
VIN+
VIN–
AGND
AVDD1
AVDD1
P5
DRVDD
GND
COUT
COUTB
DRVDD
GND
D7T/D0Y
D9C/D3Y
D8T/D2Y
D8C/D1Y
GND
GND
D10T/D6YN
D10C/D5YN
D9T/D4Y
DRVDD
5V
GND
E3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VCC
1kΩ
R21
GND
C36
0.1µF
VCC
VCC
E40
R12
1kΩ
D12T/D10YN
D13C/D11YN
D13T/D12YN
GND
DRVDD
DORC/D13Y
DORT/DORY
GND
VCC
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
GND
GND
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
GND
GND
GND
D11C/D7YN
D11T/D8YN
D12C/D9YN
U2
R27
XX
XTALINPUT
XTALOUTB
XTALOUT
E39
ENCB
H2
MTHOLE6
R19
XX
VXTAL
R37
XX
VCC
OUTPUTB
OUTPUT
E38
R9
1kΩ
GND
2
GND
VCC
C26
0.1µF
VCC
C42
0.1µF
3
XTALINPUTB
GND
XTALINPUTB
4
6
2
PRI SEC
3
NC 5
1
T3
ADT1-1WT
1
JN00158
GND R40
XX
R38
XX
GND
J1
GND
J5
GND
1
E/D
2
3 NC
GND
VXTAL
1 XTALOUT
GND
C96
0.1µF
H1
MTHOLE6
FOR VF XTAL
R18
XX
VEE
6
5
4
OUT
~OUT
VCC
FOR VECTRON XTAL
7
R36
XX
8 XTALOUTB
C92
0.1µF
50Ω
R8
GND
C93
0.1µF
R39
XX
VXTAL
C44
10µF
CR2
U6
ECLOSC
GND
+
GND
14
VCC
5V
ENC
GND
VXTAL
E52
ENCODE
GND
R17
XX
GND
E47
E46
GND
8
7
6
5
4
3
2
1
VXTAL
XTALINPUT
50Ω
R7
VXTAL
OPTIONAL ENCODE CIRCUITS
GND
AD9444
CMOS EVALUATION BOARD SCHEMATICS
GND
VDL
DRVDD
GND
DRVDD
VCC
VCC
VCC
ENCB
ENC
VCC
VCC
5V
GND C40
0.1µF
GND
VCC
VCC
5V
33Ω
R35
AD9444
ADP3338
U8
U15
3
1
VIN
VIN
1
GND
GND
VCC
C6
10µF
+
C33
10µF
GND
GND
5V
OUT1
IN
1
2
3
+
C4
10µF
Figure 60. CMOS Mode Evaluation Board Schematic (Continued)
Rev. 0 | Page 33 of 40
05089-055
C89
10µF
GND
+
GND
GND
OUT
C34
10µF
+
C88
10µF
3
2
VIN
3
GND
4
VIN
IN
2
5V
DRVDD
DRVDD
OUT1
GND
U14
OUT
3
GND
GND
GND
ADP3338
U3
1
2
C87
10µF
ADP3338
GND
2
+
+
3.3V
+
IN
C57
10µF
4
OUT1
OUT
C1
10µF
+
+
4
PJ-102A
5V
3
1
GND
IN
2
GND
GND
OUT1
OUT
3.3V
VCC
4
1
P4
VIN
VDL
GND
VDL
3.3V
GND
ADP3338
AD9444
40
RZ1
220
RSO16ISO
DORC/D13Y
D13T/D12Y
D13C/D11Y
D12T/D10Y
D12C/D9Y
D11T/D8Y
D11C/D7Y
R1
16
2
R2
15
3
R3
14
4
R4
13
5
R5
12
6
R6
11
7
R7
10
8
R8
9
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
XOR2IN
GND
VDL
GND
RZ2
220
RSO16ISO
D10T/D6Y
D10C/D5Y
D9T/D4Y
D9C/D3Y
D8T/D2Y
D8C/D1Y
D7T/D0Y
1
R1
16
2
R2
15
3
R3
14
4
R4
13
5
R5
12
6
R6
11
7
R7
10
8
R8
9
GND
VDL
GND
XOR2IN
38
R1
36
1
Q = OUTPUT
LE2 D = INPUT OE2
2Q8
2D8
2Q7
2D7
GND
GND
2Q6
2D6
2Q5
2D5
VCC
VCC
2Q4
2D4
2Q3
2D3
GND
GND
2Q2
2D2
2Q1
2D1
1Q8
1D8
1Q7
1D7
GND
GND
1Q6
1D6
1Q5
1D5
VCC
VCC
1Q4
1D4
1Q3
1D3
GND
GND
1D2
1Q2
1Q1
1D1
LE1
OE1
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
2
GND
3
4
GND
VDL
VDL
GND
GND
R4
R5
6
R6
8
GND
R3
5
7
GND
R2
R7
R8
16
15
ORM
D13M
14
D12M
13
D11M
12
D10M
11
10
9
34
32
30
28
26
D9M
24
D8M
22
D7M
20
RZ5
220
RSO16ISO
18
1
R1
16
16
2
R2
15
3
R3
14
D4M
4
R4
13
D3M
5
R5
12
6
R6
11
7
R7
10
8
R8
9
D6M
D5M
12
10
8
D2M
6
D1M
4
D0M
GND
RZ4
RZ4
14
2
P40
P39 39
GND
P38
P37 37
DRM
P36
P35 35
GND
P34
P33 33
D13M
P32
P31 31
D12M
P30
P29 29
D11M
P28
P27 27
D10M
P26
P25 25
D9M
P24
P23 23
D8M
P22
P21 21
D7M
P20
P19 19
D6M
P18
P17 17
D5M
P16
P15 15
D4M
P14
P13 13
D3M
P12
P11 11
D2M
P10
P9 9
D1M
P8
P7 7
D0M
P6
P5 5
ORM
P4
P3 3
P2
P1 1
GND
P3
C40MS
NOT PLACED
00
COUTB
R50
00
COUT
VDL
1 1A
E49
2 1B
E42
E45
GND
U4
74VCX86
XORZIN
R16
4 2A
GND
2Y
5 2B
9 3A
10 3B
VDL
E32
12 4A
GATE2
GND
3Y
00
R41
6
8
4Y
7
DRM
R14
GATE
00
11
14 PWR
13 4B
E31
00
3
1Y
GND
DRM
R42
VDL
GND
E30
U10
VDL
+
C66
10µF
C25
0.1µF
C41
0.1µF
C24
0.1µF
C68
0.1µF
C67
0.1µF
63
0.01µF
GND
Figure 61. CMOS Mode Evaluation Board Schematic (Continued)
Rev. 0 | Page 34 of 40
05089-056
DORT/DORY
1
U5
SN74LVCH16373A
220
RZ5
RSO16ISO
05089-065
05089-068
AD9444
05089-066
05089-069
Figure 65. CMOS Mode Evaluation Board Layout, Ground Plane 2
Figure 62. CMOS Mode Evaluation Board Layout, Primary Side
05089-067
05089-070
Figure 66. CMOS Mode Evaluation Board Layout, Power Plane 1
Figure 63. CMOS Mode Evaluation Board Layout, Secondary Side
Figure 67. CMOS Mode Evaluation Board Layout, Power Plane 2
Figure 64. CMOS Mode Evaluation Board Layout, Ground Plane 1
Rev. 0 | Page 35 of 40
05089-071
05089-072
AD9444
Figure 68. CMOS Mode Evaluation Board Layout, Primary Silkscreen
Figure 69. CMOS Mode Evaluation Board Layout, Secondary Silkscreen
Rev. 0 | Page 36 of 40
AD9444
CMOS MODE EVALUATION BOARD BILL OF MATERIALS (BOM)
Table 12.
Item
1
2
Qty.
1
16
REFDES
AD9444PCB
C1, C4, C6, C33, C34,
C39, C44, C55 to
C57, C64 to C66,
C87 to C89
Description
PCB, AD9444 LVDS Evaluation Board
Capacitors, Tantalum, SMT BCAPTAJC, 10 µF, 16 V, 10%
Manufacturer
PCSM
KEMET
MFG_PART_NO
AD9444LVDSCUSTREVC
T491C106K016AS
3
32
C2, C3, C5, C9, C12,
C20 to C23, C26 to
C28, C30, C32, C35,
C40, C42, C43, C46 to
C48, C50, C52, C53,
C58, C60, C61, C75,
C78, C85, C91, C92
Capacitors, 0.1 µF 10 V Ceramic X5R 0402
Panasonic
ECJ-0EB1A104K
4
5
C24, C25, C41, C67,
C68
Capacitors, 0.1 µF 16 V Ceramic X7R 0603
Panasonic
ECJ-1VB1C104K
5
6
7
1
1
20
C51
CR2
E1 to E3, E24 to E27,
E30 to E32, E38 to
E42, E45 to E47,
E49, E52
Capacitor, Ceramic 10 µF 6.3 V X5R 0805
Diode, Dual Schottky HSMS2812, SOT-23, 30 V, 20 mA
40-Pin Breakable Header
KEMET
Panasonic
3M
C0805C106K9PACTU
MA716-(TX)
2340-611TN
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2
1
1
1
1
2
1
4
2
2
1
4
2
1
4
1
1
4
J1, J4
L1
P3
P4
R3
R4, R6
R8
R9, R12, R15, R21
R14, R50
R28, R35
R39
RZ1 to RZ3, RZ6
T3, T5
U1
U3, U8, U15
U14
U5
U6
Connector, Gold, Male, Coaxial, SMA, Vertical
10 nH O402 Inductor
Header, 40-Pin, Male, 40-Pin Right Angle
Power Jack
Resistor, 3.6 kΩ 1/16 W 1% 0402 SMD
Resistors, 36 Ω 1/16 W 5% 0402 SMD
Resistor, 49.9 Ω 1/16 W 1% 0402 SMD
Resistors, 1.00 kΩ 1/16 W 1% 0402 SMD
Resistors, 0 Ω 1/10 W 5% 0603 SMD
Resistors, 33 Ω 1/16 W 5% 0402 SMD
Resistor, 0 Ω 1/16 W 5% 0402 SMD
220 Ω Resistor Array, 16 Term
Transformer, ADT1-1WT, CD542, ADT1-1WT
14-Bit, 80 MSPS ADC
3.3 V Voltage Regulator
5 V Voltage Regulator
16-Bit Flip Flop
Pin Sockets, Closed End
Johnston Comp.
Coilcraft
Samtec
Swithcraft
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
CTS Corp.
Mini-Circuits
ADI
ADI
ADI
Fairchild
AMP
142-0701-201
0402CS-10NX_B_
TSW-120-08-T-D-RA
RAPC722
ERJ-2GEJ362X
ERJ-2GEJ360X
ERJ-2RKF49R9X
ERJ-2RKF1001X
ERJ-3GEY0R00V
ERJ-2GEJ330X
ERJ-2GE0R00X
742163221JTR
ADT1-1WT
AD9444BSVZ-80
ADP3338-3.3 V
ADP3338-5.0 V
74LVTH162374
5-330808-3
Rev. 0 | Page 37 of 40
AD9444
Item
26
Qty.
26
27
28
1
15
29
30
31
32
3
1
1
2
1
REFDES
C10, C11, C13, C14 to
C19, C29, C31, C36 to
C37, C38, C45, C49,
C59, C62,C69, C70 to
C73, C90, C93, C961
J51
R1,R2,R5,R7, R13,
R17 to R20, R27,
R36 to R401
R16, R41, R421
C631
U41
P5, P61
Description
Capacitors, Select 10 V Ceramic X5R 0402
Manufacturer
Panasonic
MFG_PART_NO
Connector, Gold, Male, Coaxial, SMA, Vertical
Resistors, Select 1/16 W 1% 0402 SMD
Johnston Comp.
Panasonic
142-0701-201
Resistors, Select 1/16 W 5% 0603 SMD
Capacitor, Select 10 V Ceramic X5R 0603
XOR 74VCX86D
Power Connectors
Panasonic
Panasonic
Fairchild
Weiland
Parts not placed.
Rev. 0 | Page 38 of 40
74VCX86D
AD9444
OUTLINE DIMENSIONS
0.75
0.60
0.45
16.00 SQ
1.20
MAX
14.00 SQ
100
1
76
76
75
100
1
75
SEATING
PLANE
BOTTOM VIEW
(PINS UP)
TOP VIEW
(PINS DOWN)
CONDUCTIVE
HEAT SINK
51
25
26
0.20
0.09
51
50
25
50
1.05
1.00
0.95
7°
3.5°
0°
0.50 BSC
0.27
0.22
0.17
0.15
0.05
26
6.50
NOM
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MS-026AED-HD
NOTES
1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE
DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
3. THE EXPOSED HEAT SINK SOLDERED TO THE GROUND PLANE IS REQUIRED FOR THE 100-LEAD TQFP/EP.
Figure 70. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-100-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9444BSVZ-801
AD9444-CMOS/PCB
AD9444-LVDS/PCB
1
Temperature Range
–40°C to +85°C
Package Description
100-Lead TQFP_EP
CMOS Mode Evaluation Board
LVDS Mode Evaluation Board
Z = Pb-free part.
Rev. 0 | Page 39 of 40
Package Outline
SV-100-1
AD9444
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05089–0–10/04(0)
Rev. 0 | Page 40 of 40