Dual Channel, 12-Bit 105 MSPS IF Sampling
A/D Converter with Analog Input
Signal Conditioning
AD10200
a
FEATURES
Dual, 105 MSPS Minimum Sample Rate
Channel-Channel Isolation, >80 dB
AC-Coupled Signal Conditioning Included
Gain Flatness up to Nyquist: < 0.2 dB
Input VSWR 1.1:1 to Nyquist
80 dB Spurious-Free Dynamic Range
Two’s Complement Output Format
3.3 V or 5 V CMOS-Compatible Output Levels
0.850 W per Channel
Industrial and Military Grade
includes two wide-dynamic range ADCs. Each ADC has a
transformer coupled front-end optimized for Direct-IF sampling.
The AD10200 has on-chip track-and-hold circuitry, and utilizes
an innovative architecture to achieve 12-bit, 105 MSPS performance. The AD10200 uses innovative high-density circuit
design to achieve exceptional matching and performance while
still maintaining excellent isolation, and providing for significant
board area savings.
The AD10200 operates with 5.0 V supply for the analog-todigital conversion. Each channel is completely independent
allowing operation with independent encode and analog inputs.
The AD10200 is packaged in a 68-lead ceramic chip carrier
package. Manufacturing is done on Analog Devices, Inc. MIL38534 Qualified Manufacturers Line (QML) and components
are available up to Class-H (–55°C to +125°C).
APPLICATIONS
Radar IF Receivers
Phased Array Receivers
Communications Receivers
Secure Communications
GPS Antijamming Receivers
Multichannel, Multimode Receivers
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 105 MSPS.
PRODUCT DESCRIPTION
The AD10200 is a full channel ADC solution with on-module
signal conditioning for improved dynamic performance and
fully matched channel-to-channel performance. The module
2. Input signal conditioning with full power bandwidth to
250 MHz.
3. Fully tested/characterized performance at 121 MHz AIN.
4. Optimized for IF sampling.
FUNCTIONAL BLOCK DIAGRAM
AINA2
AINB2
7
63
D00A 34
(LSB)
50 D00B
D01A 33
49 D01B
(LSB)
T1A
T1B
D02A 32
48 D02B
D03A 31
50⍀
47 D03B
50⍀
46 D04B
D04A 30
T/H
D05A 29
T/H
AD10200
45 D05B
D06A 28
42 D06B
D07A 25
ADC
D08A 24
12
41 D07B
ADC
12
12
40 D08B
12
39 D09B
D09A 23
D10A 22
OUTPUT RESISTORS
38 D10B
OUTPUT RESISTORS
37 D11B
D11A 21
(MSB)
(MSB)
TIMING
18
REF
17
ENCODEA ENCODEA
REF
TIMING
3
56
53
54
REF_A_OUT
REF_B_OUT
ENCODEB
ENCODEB
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD10200–SPECIFICATIONS1 (V
DD =
Parameter
Temp
3.3 V, VCC = 5.0 V; ENCODE = 105 MSPS, unless otherwise noted)
Test
Level
MIL
Subgroup
Min
RESOLUTION
Full
Full
Full
Full
Full
IV
IV
I
I
I
ANALOG INPUT
Input Voltage Range
Input Impedance
Input VSWR3
Analog Input Bandwidth, High
Analog Input Bandwidth, Low
25°C
25°C
Full
Full
Full
V
V
IV
IV
IV
ANALOG REFERENCE
Output Voltage
Load Current
Tempco
Full
25°C
Full
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Duty Cycle
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Output Valid Time (tV)4
Output Propagation Delay (PD)4
Output Rise Time (tR)
Output Fall Time (tF)
DIGITAL INPUTS
Encode Input Common Mode
Differential Input (Enc, Enc)
Logic “1” Voltage
Logic “0” Voltage
Input Resistance
Input Capacitance
POWER SUPPLY5
Power Dissipation6
Power Supply Rejection Ratio
I (DVDD) Current
I (AVCC) Current
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)7
(Without Harmonics)
fIN = 10 MHz
fIN = 41 MHz
fIN = 71 MHz
fIN = 121 MHz
Max
12
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
Gain Error2
Output Offset
DIGITAL OUTPUTS
Logic “1” Voltage4
Logic “0” Voltage4
Output Coding
Typ
12
12
1, 2, 3
1, 2, 3
1, 2, 3
–0.99
–3
–9
–12
12
12
12
200
1
I
V
V
1, 2, 3
2.4
Full
Full
Full
25°C
25°C
Full
Full
25°C
25°C
I
IV
IV
V
V
IV
IV
V
V
4, 5, 6
12
12
105
Full
Full
Full
Full
Full
25°C
± 0.5
± 0.75
Guaranteed
±1
2.048
50
1.1:1
250
2.5
5
50
45
50
1.0
0.25
5.3
5.5
3.5
3.3
12
12
12
12
3.0
4.5
IV
IV
IV
IV
IV
V
12
12
12
12
12
1.2
0.4
2.0
1.6
3
5
4.5
Full
Full
VI
VI
1, 2, 3
1, 2, 3
3.1
Full
Full
Full
Full
I
IV
I
I
1, 2, 3
12
1, 2, 3
1, 2, 3
1800
± 0.5
25
340
25°C
Full
25°C
Full
25°C
Full
25°C
Full
V
V
I
II
I
II
I
II
4
5, 6
4
5, 6
4
5, 6
67
66
66.5
65
66.4
64
65
64
–2–
Bits
+0.99
+3
LSB
LSB
+9
+12
% FS
LSB
1.25:1
V p-p
Ω
Ratio
MHz
MHz
2.6
10
55
8.0
2.0
5.0
0.8
8
3.3
0
0.2
Two’s Complement
64
62
62.5
61.5
61
61
Unit
2200
±5
40
410
V
mA
ppm/°C
MSPS
MSPS
%
ns
ps rms
ns
ns
ns
ns
V
V
V
V
kΩ
pF
V
V
mW
mV/V
mA
mA
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
REV. A
AD10200
Parameter
DYNAMIC PERFORMANCE
(Continued)
Signal-to-Noise Ratio (SINAD)8
(With Harmonics)
fIN = 10 MHz
fIN = 41 MHz
fIN = 71 MHz
fIN = 121 MHz
Spurious Free Dynamic Range9
fIN = 10 MHz
fIN = 41 MHz
fIN = 71 MHz
fIN = 121 MHz
Two-Tone Intermodulation
Distortion10 (IMD)
fIN = 10 MHz; fIN = 12 MHz
fIN = 71 MHz; fIN = 72 MHz
fIN = 121 MHz; fIN = 122 MHz
Channel-to-Channel Isolation11
fIN = 121 MHz
Temp
Test
Level
MIL
Subgroup
25°C
Full
25°C
Full
25°C
Full
25°C
Full
V
V
I
II
I
II
I
II
25°C
Full
25°C
Full
25°C
Full
25°C
Full
V
V
I
II
I
II
I
II
25°C
Full
25°C
Full
25°C
Full
V
V
V
V
I
II
4
5, 6
Full
IV
12
4
5, 6
4
5, 6
4
5, 6
4
5, 6
4
5, 6
4
5, 6
Min
Typ
63
60.5
61
57
56
53
66
63
65.5
63
63.5
60
58.5
55
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
81
70
81
65
58
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
55.5
53
86
81
70
65
62
57
dBc
dBc
dBc
dBc
dBc
dBc
80
85
dB
73
67.5
67
60
61
55.5
74
Max
Unit
NOTES
1
All ac specifications tested by driving ENCODE and ENCODE differentially.
2
Gain Error measured at 2.5 MHz.
3
Input VSWR guaranteed 10 MHz to 200 MHz.
4
tV and tPD are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is
not to exceed an ac load of 10 pF or a dc current of ± 40 mA.
5
Supply voltages should remain stable within ± 5% for normal operation.
6
Power dissipation measured with encode at rated speed and 0 dBm analog input.
7
Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonic removed). Encode = 105 MSPS. SNR
is reported in dBFS, related back to converter full scale.
8
Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 105 MSPS. SINAD
is reported in dBFS, related back to converter full scale.
9
Analog Input signal equal –1 dBFS; SFDR is ratio of converter full scale to worst spur.
10
Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. f1 = x MHz
± 100 kHz, f2 = x MHz ± 100 kHz.
11
Channel-to-Channel isolation tested with A Channel/50 Ω terminated (AINA2) grounded and a full-scale signal applied to B Channel (A INB2).
Specifications subject to change without notice.
REV. A
–3–
AD10200
ABSOLUTE MAXIMUM RATINGS 1, 2
Table I. Output Coding (VREF = 2.5 V) (Two’s Complement)
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . 5 V p-p(18 dBm)
Digital Inputs . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . . 150°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
2
Typical thermal impedances for “Z” package:
θJC = 2.22°C/W; θJA = 24.3°C/W.
Code
AIN (V)
Digital Output
+2047
•
•
0
–1
•
•
–2048
+1.024
•
•
0
–0.00049
•
•
–1.024
0111 1111 1111
•
•
0000 0000 0000
1111 1111 1111
•
•
1000 0000 0000
EXPLANATION OF TEST LEVELS
Test Level
I.
II.
100% production tested.
100% production tested at 25°C and sample tested at
specific temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD10200BZ
5962-9961002HXA
5962-9961001HXA
AD10200/PCB
–40°C to +85°C (Case)
–40°C to +85°C (Case)
–55°C to +125°C (Case)
68-Lead Ceramic Leaded Chip Carrier
68-Lead Ceramic Leaded Chip Carrier
68-Lead Ceramic Leaded Chip Carrier
Evaluation Board with AD10200BZ
Z-68B
Z-68B
Z-68B
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD10200 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. A
AD10200
6
AGNDA 10
AGNDA 11
DNC 12
AGNDB
NC
DNC
1 68 67 66 65 64 63 62 61
AINB2
2
3
DNC
4
AVCC
AGNDB
5
AGNDB
SHIELD
7
AGNDA
8
AGNDA
DNC
AINA2
NC
9
DNC
VREF_A_OUT
AGNDA
PIN CONFIGURATION
PIN 1
IDENTIFIER
60
AGNDB
AGNDB
58 DNC
59
AGNDA 13
AVCC 14
DNC 15
57
DNC
REF_B_OUT
55 AGNDB
56
AGNDA 16
ENCODEA 17
ENCODEA 18
54
ENCODEB
ENCODEB
52 AGNDB
51 DV
CC
AD10200
53
TOP VIEW
(Not to Scale)
AGNDA 19
DVCC 20
(MSB) D11A 21
50
D0B (LSB)
49
D1B
48 D2B
47 D3B
D10A 22
D9A 23
D8A 24
D7A 25
DGNDA 26
46
D4B
D5B
44 DGNDB
45
NC = NO CONNECT
DGNDB
D7B
D6B
D8B
D9B
AGNDA
AGNDB
(MSB) D11B
D10B
D1A
(LSB) D0A
D2A
DGNDA
D6A
D5A
D4A
D3A
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
2, 5, 9–11, 13, 16, 19, 35
SHIELD
AGNDA
3
6, 62
7
4, 8, 12, 15, 57, 58, 64, 67
14, 66
17
18
20
21–25, 28–34
VREF_A_OUT
NC
AINA2
DNC
AVCC
ENCODEA
ENCODEA
DVCC
D11A–D7A,
D6A–D0A
DGNDA
AGNDB
Internal Ground Shield between Channels
A Channel Analog Ground. A and B grounds should be connected as close to
the device as possible.
A Channel Internal Voltage Reference
No Connection
Analog Input for A Side ADC
Do Not Connect
Analog Positive Supply Voltage (Nominally 5.0 V)
Complement of Encode
Data conversion initiated on the rising edge of ENCODE input.
Digital Positive Supply Voltage (Nominally 3.3 V)
Digital Outputs for ADC A. D0 (LSB)
26, 27
36, 52, 55, 59–61, 65, 68
37–42, 45–50
43, 44
51
53
54
56
63
REV. A
D11B–D6B,
D5B–D0B
DGNDB
DVCC
ENCODEB
ENCODEB
VREF_B_OUT
AINB2
A Channel Digital Ground
B Channel Analog Ground. A and B grounds should be connected as close to
the device as possible.
Digital Outputs for ADC B. D0 (LSB)
B Channel Digital Ground
Digital Positive Supply Voltage (Nominally 3.3 V)
Data conversion initiated on rising edge of ENCODE input.
Complement of Encode
B Channel Internal Voltage Reference
Analog Input for B Side ADC
–5–
AD10200
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
Overvoltage Recovery Time
The amount of time required for the converter to recover to
0.02% accuracy after an analog input signal of the specified
percentage of full scale is reduced to midscale.
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Power Supply Rejection Ratio
Aperture Delay
The ratio of a change in output offset voltage to a change in
power supply voltage.
The delay between the 50% point on the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Signal-to-Noise-and-Distortion (SINAD)
The deviation of any code from an ideal 1 LSB step.
The ratio of the rms signal amplitude (set a 1 dB below full scale)
to the rms value of the sum of all other spectral components,
excluding the first five harmonics and dc. [May be reported in
dBc (i.e., degrades as signal levels is lowered) or in dBFS (always
related back to converter full scale)].
Encode Pulsewidth/Duty Cycle
Signal-to-Noise Ratio (without Harmonics)
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic “1” state to achieve
rated performance; pulsewidth low is the minimum time
ENCODE pulse should be left in low state. At a given clock
rate, these specs define an acceptable Encode duty cycle.
The ratio of the rms signal amplitude (set a I dB below full
scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. [May be
reported in dBc (i.e., degrades as signal levels is lowered) or in
dBFS (always related back to converter full scale).]
Harmonic Distortion
Spurious-Free Dynamic Range
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component may or may not be a harmonic. [May be reported in dBc
(i.e., degrades as signal levels is lowered) or in dBFS (always
related back to converter full scale).]
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Transient Response
The time required for the converter to achieve 0.02% accuracy when a one-half full-scale step function is applied to the
analog input.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more that 3 dB below the guaranteed limit.
Two-Tone Intermodulation Distortion Rejection
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
The ratio of the rms value of either input tone to the rms value of
the worst third order intermodulation product; reported in dBc.
Output Propagation Delay
Voltage Standing-Wave Ratio (VSWR)
The delay between the 50% point of the rising edge of ENCODE
command and the time when all output data bits are within
valid logic levels.
The ratio of the amplitude of the elective field at a voltage maximum to that at an adjacent voltage minimum.
–6–
REV. A
Typical Performance Characteristics–AD10200
0
0
ENCODE = 105 MSPS
AIN = 10MHz (–1dBFS)
SNR = 66.84dBFS
SFDR = 82.28dBc
ⴚ10
ⴚ20
ⴚ20
ⴚ30
ⴚ40
ⴚ40
ⴚ50
ⴚ50
ⴚ60
dB
dB
ⴚ30
ⴚ70
ⴚ80
ⴚ60
ⴚ70
ⴚ80
ⴚ90
ⴚ90
ⴚ100
ⴚ100
ⴚ110
ⴚ110
ⴚ120
ⴚ120
ⴚ130
ENCODE = 105 MSPS
AIN = 41MHz (–1dBFS)
SNR = 66.06dBFS
SFDR = 80.59dBc
ⴚ10
0
5
10
15
20
25
30
35
FREQUENCY – MHz
40
45
ⴚ130
50
0
TPC 1. Single Tone @ 10 MHz
ⴚ20
ⴚ30
ⴚ40
ⴚ40
ⴚ50
ⴚ50
ⴚ60
ⴚ70
ⴚ80
40
45
50
ⴚ60
ⴚ70
ⴚ80
ⴚ90
ⴚ90
ⴚ100
ⴚ100
ⴚ110
ⴚ110
ⴚ120
ⴚ120
0
5
10
15
20
25
30
35
FREQUENCY – MHz
40
45
ⴚ130
50
0
TPC 2. Single Tone @ 71 MHz
5
10
15
20
25
30
35
FREQUENCY – MHz
40
45
50
TPC 5. Single Tone @ 121 MHz
0
0
ENCODE = 105 MSPS
AIN = 121MHz (–6dBFS)
SNR = 66.9dBFS
SFDR = 65.57dBc
ⴚ10
ⴚ20
ⴚ30
ENCODE = 105 MSPS
AIN = 201MHz (–10dBFS)
SNR = 66.84dBFS
SFDR = 64.57dBc
ⴚ10
ⴚ20
ⴚ30
ⴚ40
ⴚ40
ⴚ50
ⴚ50
ⴚ60
dB
dB
20
25
30
35
FREQUENCY – MHz
ENCODE = 105 MSPS
AIN = 121MHz (–1dBFS)
SNR = 64.92dBFS
SFDR = 64.73dBc
ⴚ10
dB
dB
ⴚ30
ⴚ70
ⴚ60
ⴚ70
ⴚ80
ⴚ80
ⴚ90
ⴚ90
ⴚ100
ⴚ100
ⴚ110
ⴚ110
ⴚ120
ⴚ120
0
5
10
15
20
25
30
35
FREQUENCY – MHz
40
45
ⴚ130
50
0
5
10
15
20
25
30
35
FREQUENCY – MHz
40
TPC 6. Single Tone @ 201 MHz
TPC 3. Single Tone @ 121 MHz
REV. A
15
0
ENCODE = 105 MSPS
AIN = 71MHz (–1dBFS)
SNR = 66.04dBFS
SFDR = 79.71dBc
ⴚ20
ⴚ130
10
TPC 4. Single Tone @ 41 MHz
0
ⴚ10
ⴚ130
5
–7–
45
50
AD10200
0
0
ENCODE = 105 MSPS
AIN = 37MHz & 38MHz (–10dBFS)
SFDR = 79.84dBc
ⴚ10
ⴚ20
ⴚ20
ⴚ30
ⴚ40
ⴚ40
ⴚ50
ⴚ50
ⴚ60
dBc
dBc
ⴚ30
ⴚ70
ⴚ80
ⴚ60
ⴚ70
ⴚ80
ⴚ90
ⴚ90
ⴚ100
ⴚ100
ⴚ110
ⴚ110
ⴚ120
ⴚ120
ⴚ130
ENCODE = 105 MSPS
AIN = 71MHz & 72MHz (–7dBFS)
SFDR = 74.8dBc
ⴚ10
0
5
10
15
20
25
30
35
FREQUENCY – MHz
40
45
ⴚ130
50
0
5
10
15
20
25
30
35
FREQUENCY – MHz
40
45
50
TPC 10. Two-Tone @ 71 MHz/72 MHz
TPC 7. Two-Tone @ 37 MHz/38 MHz
3.0
0
ENCODE = 105 MSPS
AIN = 120MHz & 121MHz (–7dBFS)
SFDR = 63.8dBc
ⴚ10
ⴚ20
ENCODE = 105 MSPS
DNL MAX = 0.486 Codes
DNL MIN = 0.431 Codes
2.5
ⴚ30
2.0
ⴚ40
1.5
ⴚ60
LSB
dBc
ⴚ50
ⴚ70
1.0
ⴚ80
0.5
ⴚ90
0.0
ⴚ100
ⴚ110
ⴚ0.5
ⴚ120
ⴚ130
0
5
10
15
20
25
30
35
FREQUENCY – MHz
40
45
ⴚ1.0
50
0
1024
1536
2048
2560
3072
3584
4096
TPC 11. Differential Nonlinearity
TPC 8. Two-Tone @ 120 MHz/121 MHz
3
512
0
ENCODE = 105 MSPS
INL MAX = 0.874 Codes
INL MIN = 0.895 Codes
ⴚ1
2
ENCODE = 105 MSPS
3dB = 261MHz
ⴚ2
ⴚ3
1
dBFS
LSB
ⴚ4
0
ⴚ5
ⴚ6
ⴚ1
ⴚ7
ⴚ8
ⴚ2
ⴚ9
ⴚ3
0
512
1024
1536
2048
2560
3072
3584
ⴚ10
3.0
4096
32.7 62.4 92.1 121.8 151.5 181.2 210.9 240.6 270.3 300.0
MHz
TPC 12. Gain Flatness
TPC 9. Integral Nonlinearity
–8–
REV. A
AD10200
11
10MHz = 1.0149
10 50MHz = 1.085
100MHz = 1.130
150MHz = 1.092
9
8
7
6
5
4
3
10MHz = 50.22 + j.173
50MHz = 48.79 – j4.2
100MHz = 46.95 – j5.9
150MHz = 48.55 – j4.66
2
1
3.0 32.7
TPC 13. Input Impedance S11
SAMPLE N–1
62.4
92.1 121.8 151.5 181.2 210.9 240.6 270.3 300.0
MHz
TPC 14. Voltage Standing Wave Ratio (VSWR)
SAMPLE N
SAMPLE N+10
SAMPLE N+11
AIN
SAMPLE N+1
SAMPLE N+9
1/f S
ENCODE
ENCODE
t PD
DATA N⬇11
D11⬇D0
DATA N⬇10
N⬇9
N⬇2
DATA N⬇1
tV
DATA N
DATA N + 1
Figure 1. Timing Diagram
VCC
VCC
VCC
17k⍀
17k⍀
Q1
NPN
ENCODE
ENCODE
100⍀
100⍀
8k⍀
8k⍀
VREF OUTPUT
Figure 2. Equivalent Encode Input Circuit
Figure 4. Equivalent Voltage Reference Output Circuit
VCC
VCC
5k⍀
5k⍀
AIN
100⍀
50⍀
DIGITAL
OUTPUT
7k⍀
7k⍀
Figure 3. Equivalent Digital Output Circuit
REV. A
Figure 5. Equivalent Analog Input Circuit
–9–
AD10200
APPLICATION NOTES
Theory of Operation
The AD10200 is a high-dynamic range dual 12-bit, 105 MHz
subrange pipeline converter that uses switched capacitor
architecture. The analog input section uses AINA2/AINB2 at
2.048 V p-p with an input impedance of 50 Ω. The analog input
includes an ac-coupled wide-band 1:1 transformer, which provides
high-dynamic range and SNR while maintaining VSWR and
gain flatness. The ADC includes a high-bandwidth linear track/
hold that gives excellent spurious performance up to and beyond
the Nyquist rate. The high-bandwidth track/hold has a low jitter
of 0.25 ps rms, leading to excellent SNR and SFDR performance.
AC-coupled differential PECL/ECL encode inputs are recommended for optimum performance.
USING THE AD10200
ENCODE Input
Any high speed A/D converter is extremely sensitive to the quality
of the sampling clock provided by the user. A track/hold circuit
is essentially a mixer, and any noise, distortion, or timing jitter
on the clock will be combined with the desired signal at the A/D
output. For that reason, considerable care has been taken in the
design of the ENCODE input of the AD10200, and the user is
advised to give commensurate thought to the clock source. The
ENCODE input are fully TTL/CMOS compatible. For optimum performance, the AD10200 must be clocked differentially.
Note that the ENCODE inputs cannot be driven directly from
PECL level signals (VIHD is 3.5 V max). PECL level signals can
easily be accommodated by ac coupling as shown in Figure 6.
Good performance is obtained using an MC10EL16 in the
circuit to drive the encode inputs.
0.1␮F
510⍀
Figure 6. AC Coupling to ENCODE Inputs
The voltage level definitions for driving ENCODE and ENCODE
in differential mode are shown in Figure 7.
ENCODE
Voltage Reference
A stable and accurate 2.5 V voltage reference is designed into
the AD10200 (VREFOUT). An external voltage reference is
not required.
Timing
The AD10200 provides latched data outputs, with 10 pipeline
delays. Data outputs are available one propagation delay (tPD)
after the rising edge of the encode command (see Figure 1). The
length of the output data lines and loads placed on them should
be minimized to reduce transients within the AD10200; these
transients can detract from the converter's dynamic performance.
2. The minimization of the impedance associated with ground
and power paths.
ENCODE Inputs
500 mV min,
750 mV nom
5.0 V max
0 V min
1.25 V min, 1.6 V nom
VIHD
VICM
Special care was taken in the design of the analog input section
of the AD10200 to prevent damage and corruption of data when
the input is overdriven.
1. The minimization of the loop area encompassed by a signal
and its return path.
ENCODE Voltage Level Definition
ENCODE
The analog input is a single ended ac-coupled high performance
1:1 transformer with an input impedance of 50 Ω to 105 MHz.
The nominal full scale input is 2.048 V p-p.
Proper grounding is essential in any high speed, high resolution
system. Multilayer printed circuit boards (PCBs) are recommended to provide optimal grounding and power schemes. The
use of ground and power planes offers distinct advantages:
GND
High Differential Input Voltage (VIHD)
Low Differential Input Voltage (VILD)
Common-Mode Input (VICN)
Analog Input
GROUNDING AND DECOUPLING
Analog and Digital Grounding
0.1␮F
Differential Signal Amplitude (VID)
The digital outputs are TTL/CMOS-compatible and a separate
output power supply pin supports interfacing with 3.3 V logic.
AD10200
ENCODE
510⍀
Digital Outputs
The minimum guaranteed conversion rate of the AD10200 is
10 MSPS. At internal clock rates below 10 MSPS, dynamic
performance may degrade. Therefore, input clock rates below
10 MHz should be avoided.
ENCODE
PECL
GATE
Often, the cleanest clock source is a crystal oscillator producing
a pure sine wave. In this configuration, or with any roughly
symmetrical clock input, the input can be ac-coupled and biased
to a reference voltage that also provides the ENCODE. This
ensures that the reference voltage is centered on the encode signal.
VID
VILD
VIHS
ENCODE
3. The inherent distributed capacitor formed by the power
plane, PCB insulation and ground plane.
These characteristics result in both a reduction of electromagnetic
interference (EMI) and an overall improvement in performance.
It is important to design a layout that prevents noise from coupling to the input signal. Digital signals should not be run in
parallel with input signal traces and should be routed away from
the input circuitry. The PCB should have a ground plane covering
all unused portions of the component side of the board to provide a low impedance path and manage the power and ground
currents. The ground plane should be removed from the area
near the input pins to reduce stray capacitance.
0.1␮F
VILS
Figure 7. Differential Input Levels
–10–
REV. A
AD10200
LAYOUT INFORMATION
EVALUATION BOARD
The schematic of the evaluation board (Figure 8) represents
a typical implementation of the AD10200. The pinout of the
AD10200 is very straightforward and facilitates ease of use and
the implementation of high frequency/high resolution design
practices. It is recommended that high quality ceramic chip
capacitors be used to decouple each supply pin to ground directly
at the device. All capacitors can be standard high quality ceramic
chip capacitors.
The AD10200 evaluation board (Figure 9) is designed to
provide optimal performance for evaluation of the AD10200
analog-to-digital converter. The board encompasses everything
needed to ensure the highest level of performance for evaluating
the AD10200. The board requires an analog input signal, encode
clock and power supply inputs. The clock is buffered on-board
to provide clocks for the latches. The digital outputs and out
clocks are available at the standard 40-pin connectors J1 and J2.
Care should be taken when placing the digital output runs.
Because the digital outputs have such a high-slew rate, the
capacitive loading on the digital outputs should be minimized.
Circuit traces for the digital outputs should be kept short and
connect directly to the receiving gate. Internal circuitry buffers
the outputs of the ADC through a resistor network to eliminate
the need to externally isolate the device from the receiving gate.
Power to the analog supply pins is connected via banana jacks.
The analog supply powers the associated components and the
analog section of the AD10200. The digital outputs of the
AD10200 are powered via banana jacks with 3.3 V. Contact the
factory if additional layout or applications assistance is required.
Figure 8. Evaluation Board Mechanical Layout
REV. A
–11–
C29 ⴙ
10␮F
E26
C30 ⴙ
10␮F
ⴙ3.3VDB
E25
ⴙ3.3VDA
DGNDA
C10
0.1␮F
U1
DUT_3.3VDA
AGNDA
C34
0.1␮F
ⴙ5VAA_
25
26
23
24
22
19
20
21
16
17
18
15
13
14
11
12
10
DGNDB
U8
C16
0.1␮F
47⍀
ⴞ20%
@100MHz
L2
47⍀
ⴞ20%
@100MHz
DGNDA
U1
C12
0.1␮F
L1
DUT_3.3VDB
DUT_3.3VDA
D7A
DGNDA
D10A
D9A
D8A
ⴙ3.3VDA
D11A (MSBA)
AGNDA
AGNDA
ENCAB
ENCA
ⴙ5VAA
SCLK_A
AGNDA
SDOUT_A
AGNDA
AGNDA
NC = NO CONNECT
D7A
DGNDA
D10A
D9A
D8A
D11A
AGNDA
NC
AGNDA
ENCAB
ENCA
NC
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
DGNDA
D6A
D5A
AGNDA
C37
DNS
0.1␮F
C33
AGNDA
U1
AD10200
E5
ⴙ
ⴙ
L3
47⍀
ⴞ20%
@100MHz
L4
47⍀
ⴞ20%
@100MHz
AGNDB
C4
10␮F
AGNDA
C3
10␮F
ⴙ5AB
E6
ⴙ5AA
D2A
D1A
J4
SMA
AINA1
7
6
AINA2
AGNDA
(NC)
AGNDA
SDIN_A
9
5
AGNDA
VFU_A
AGNDA
LID
AGNDA
AGNDA
AGNDB
D11B
D10B
J3
SMA
DNS
D4B
D5B
DGNDB
D1B
D2B
D3B
ENCB
AGNDB
ⴙ3.3VDB
D0B (LSB)
SDOUT_B
REF_B
AGNDB
ENCBB
AGNDB
AGNDB
VFU_B
45
44
47
46
49
48
51
50
52
54
53
56
55
58
57
59
60
AGNDB
J6
SMA
DNS
AGNDA
J7
SMA
ⴙ5AB_
U1
C21
0.1␮F
AGNDB
AGNDB
ⴙ5AA_
U1
C20
0.1␮F
AGNDA
D9B
5
4
3
2
D4A
D3A
E49
D8B
REF_A
AGNDA
27
DGNDA
28
D6A
29
D5A
30
D4A
31
D3A
32
D2A
33
D1A
34 D0A (LSBA)
D0A
ⴙ5VAB_
67
66
AGNDB
(NC)
1
68
SHIELD
AGNDB
AGNDA
(NC)
65
64
63
SCLK_B
ⴙ5VAB
62
AGNDB
SDIN_B
AINB2
61
AGNDB
DGNDB
43
AINB1
35
AGNDA
36
AGNDB
37
D11B (MSBB)
38
D10B
39
D9B
40
D8B
41
D7B
42
D6B
D7B
D6B
–12–
DGNDB
D4B
D5B
DGNDB
D1B
D2B
D3B
D0B
ENCB
AGNDB
AGNDB
ENCBB
NC
DGNDB
C18
0.1␮F
U17
DUT_3.3VDB
AGNDB AGNDB
AGNDB
AGNDB
0.1␮F
C35
E50
C36
DNS
LATCHB
DGNDB
0⍀
R50
0⍀
R54
LATCHA
DGNDA
0⍀
R48
0⍀
R51
R8
50⍀
0⍀
R49
0⍀
R53
R7
50⍀
0⍀
R47
0⍀
R52
DGNDB
DUT_3.3VDB
(LSB) D0A
D1A
DGNDB
D2A
D3A
D4A
D5A
DGNDB
D6A
D7A
DUT_3.3VDB
D8A
D9A
DGNDB
D10A
D11A
DGNDA
DUT_3.3VDA
(LSB) D0A
D1A
DGNDA
D2A
D3A
D4A
D5A
DGNDA
D6A
D7A
DUT_3.3VDA
D8A
D9A
DGNDA
D10A
D11A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OE1
O0
O1
GND
O2
O3
VCC
O4
O5
GND
O6
O7
O8
O9
GND
O10
O11
VCC
O12
O13
GND
OE1
O0
O1
GND
O2
O3
VCC
O4
O5
GND
O6
O7
O8
O9
GND
O10
O11
VCC
O12
O13
74LCX16374
LE1
I0
I1
GND
I2
I3
VCC
I4
I5
GND
I6
I7
I8
I9
GND
I10
I11
VCC
I12
I13
GND
O14
O15
OE2
U17
GND
I14
I15
LE2
74LCX16374
LE1
I0
I1
GND
I2
I3
VCC
I4
I5
GND
I6
I7
I8
I9
GND
I10
I11
VCC
I12
I13
O14
O15
OE2
U16
GND
I14
I15
LE2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
100⍀
R18
B11B (MSB)
R16
B9B
100⍀
R40
B8B
100⍀
DUT_3.3VDB
R44
B7B
100⍀
R45
B6B
100⍀
DGNDB
R46
B5B
100⍀
R15
B4B
100⍀
R14
B3B
100⍀
R13
B2B
100⍀
DGNDB
R24
B1B (LSB)
100⍀
R23
B0B
100⍀
DUT_3.3VDB
R22
F3B
DNS
R21
F2B
DNS
DGNDB
R20
F1B
DNS
R19
F0B
DNS
DGNDB
R17
B10B
100⍀
DGNDB
DGNDB
R18
B11A (MSB)
100⍀
R17
B10A
100⍀
DGNDA
R16
B9A
100⍀
R40
B8A
100⍀
DUT_3.3VDA
R44
B7A
100⍀
R45
B6A
100⍀
DGNDA
R46
B5A
100⍀
R15
B4A
100⍀
R14
B3A
100⍀
R13
B2A
100⍀
DGNDA
R24
B1A (LSB)
100⍀
R23
B0A
100⍀
DUT_3.3VDA
R22
F3A
DNS
R21
F2A
DNS
DGNDA
R20
F1A
DNS
R19
F0A
DNS
DGNDA
DGNDA
BUFLATB
DGNDB
C14 ⴙ
10␮F
ⴙ3.3VDB
BUFLATA
DGNDA
C15 ⴙ
10␮F
ⴙ3.3VDA
R71
B3A
B2A
B1A
B4A
R72
B3B
B2B
B1B
B4B
DGNDB
F0B
F3B
F2B
F1B
(LSB) B0B
50⍀
B6B
B5B
B8B
B7B
B9B
(MSB) B11B
B10B
DGNDA
F0A
F3A
F2A
F1A
(LSB) B0A
50⍀
B6A
B5A
B8A
B7A
B9A
(MSB) B11A
B10A
36
35
20
19
16
17
18
14
15
10
11
12
13
DGNDB
21
22
25
24
23
27
26
31
30
29
28
34
33
32
36
35
7
8
9
38
37
39
40
5
6
H40DM
J2
DGNDA
21
22
3
4
2
1
20
19
25
24
23
27
26
14
15
16
17
18
31
30
29
28
10
11
12
13
34
33
32
37
5
6
7
8
9
39
38
40
4
H40DM
J1
2
3
1
AD10200
Figure 9a. Evaluation Board
REV. A
AD10200
U14
5
NR
1
3
ERR OUT
ADP3330
2
IN
SD
SD
6
4
C1
0.1␮F
J5
ENCODE
SMA
AGNDA
J12
SMA
R1
50⍀
AGNDA
U2
NC
VCC
D
Q
DB
QB
VBB
VEE
MC10EL16
1
2
3
4
C2
0.1␮F
AGNDA
8
7
6
5
DGNDA
ENCAB
ENCAB
R43
100⍀
R58
33k⍀
AGNDA
R56
33k⍀
C6
0.1␮F
1
2
3
4
AGNDA
8
7
6
5
+3.3VA
DGNDA
2
AGNDB
5
NR
1
ERR OUT
ADP3330
IN
SD
SD
6
4
C22
0.1␮F
J10
ENCODE
SMA
R60
50⍀
J11
SMA
AGNDB
8
7
6
5
R39
33k⍀
E19
BUFLATA
R64
100⍀
DGNDA
8
7
6
5
R3
100⍀
+3.3VDB
DGNDB
1
2
3
4
R66
100⍀
MC10EL16
C28
0.1␮F
AGNDB
2
U9
VCC
NC
Q
D
QB
DB
VEE
VBB
C24
0.1␮F
ENCBB
ENCB
R38
33k⍀
C25
0.1␮F
1
2
3
4
U10
D0
VCC
D0B
Q0
D1B
Q1
D1
VEE
C26
0.1␮F
8
7
6
5
+3.3VB
MC100EPT23
DGNDB
DGNDB
DGNDB
NC = NO CONNECT
BANANA JACKS FOR GNDS AND PWRS
E3
E4
AGNDB
AGNDA
E33
DGNDB
DGNDB
E34
DGNDA
E42
E44
E48
E41
E43
E47
E67
E70
E72
E73
E76
E81
E68
E69
E71
E74
E75
E82
E66
DGNDB
DGNDA
E65
DGNDA
DGNDA
AGNDA
E29
E36
E38
E40
E30
E35
E37
E39
E79
E84
E80
E83
E45
E46
DGNDB
AGNDB
STAND OFFS ON THE BOARD
SO1 SO4
SO2 SO5
SO3 SO6
Figure 9b. Evaluation Board
REV. A
LATCHA
E23
R63
100⍀
+3.3VB
AGNDB
R61
50⍀
AGNDB
+3.3VA
DGNDA
AGNDB
C27
0.47␮F
U11
VCC
NC
Q
D
QB
DB
VEE
VBB
MC10EL16
C23
0.1␮F
DGNDB
D0
VCC
D0B
Q0
D1B
Q1
D1
VEE
MC100EPT23
C5
0.1␮F
8
7
6
5
NC = NO CONNECT
1
2
3
4
AGNDB
U4
DGNDA
U15
+5VAB_
DGNDA
1
2
3
4
R4
100⍀
MC10EL16
3
C8
0.1␮F
R3
100⍀
DGNDA
U3
NC
VCC
D
Q
DB
QB
VBB
VEE
C7
0.1␮F
+3.3VA
AGNDA
R41
50⍀
R42
100⍀
AGNDA
C13
0.47␮F
1
+5VAA_
–13–
LATCHB
E24
E22
BUFLATB
AD10200
BILL OF MATERIALS LIST FOR AD10200 EVAL BOARD
Qty.
Component Name
Ref Des
2
1
2
4
4
74LCX16373MTD
AD10200BZ
ADP3330
BRES0805
BRES0805
8
BRES0805
23
CAP2
4
CAP2
U16, U17
U1
U14, U15
R38, R39, R56, R58
R1, R41, R60,
R61
R3, R4, R42, R43,
R63, R64, R65, R66
C1, C2, C5, C6,
C7, C8, C9, C10,
C12, C16, C17, C18,
C20, C21, C22, C23,
C24, C25, C26, C28,
C33, C34, C35
C13, C27, C38, C39
2
4
4
10
2
6
N49DM
IND2
MC10EL16
BJACK
MC100ELT23
POLCAP2
8
RES2
4
24
RES4
RES2
1
1
2
2
4
4
SMA
SMA
SMA
SMA
Stand-Off
Screws
1
PCB
J1, J2
L1, L2, L3, L4
U2, U3 U9, U11
BJ1 – BJ10
U4, U10
C3, C4, C14, C15,
C29, C30
R47, R48, R49,
R50, R51, R52,
R53, R54
R7, R8, R71, R72
R9, R10, R11, R12,
R13, R14, R15, R16,
R17, R18, R23, R24,
R25, R26, R27, R28,
R29, R30, R35, R36,
R40, R44, R45, R46
J4
J7
J11, J12
J5, J10
S01–S04
Value
Description
M/S P/Ns
33 kΩ
50 Ω
SM 3.3 V Regulator
SM 0805 Resistor
SM 0805 Resistor
74LCX16374MTD (Fairchild)
AD10200BZ
ADP3330ART-3.3-RL7 (Analog)
ERJ6GEYJ333V (Panasonic)
ERJ6GEYJ510V (Panasonic)
100 Ω
SM 0805 Resistor
ERJ6GEYJ101V (Panasonic)
0.1 µF
SM 0805 Capacitor
GRM40X7R104K025BL
(MENA)
0.47 µF
SM 1206 Capacitor
47 Ω
2×20×100 Male Connector
Inductor
10 µF
SM 1812 Polar Capacitor
0Ω
SM 0805 Resistor
VJ1206U474MFXMB
(VITRAMON)
TSW-120-08G-D (Samtec)
2743019447 (Fair Ride)
MC1016EP16D (Motorola)
108-0740-001 (Johnson Comp.)
SY100ELT23L (Micrel-Synergy)
T491C106M016A57280
(KEMET)
ERJ-6GEY0R00V (Panasonic)
50 Ω
SM 0805 Resistor
ERJ-6GEYJ510V (Panasonic)
AINA2
AINB2
ENCODE
ENCODE
Stand-Off
Screws (Stand-Off)
142-0701-201 (Johnson Comp.)
142-0701-201 (Johnson Comp.)
142-0701-201 (Johnson Comp.)
142-0701-201 (Johnson Comp.)
313-2477-016 (Johnson Comp.)
MPMS 0040005PH (Building
Fasteners)
GS03363 Rev. A
POWER JACK
AD10200 Eval Board
–14–
REV. A
–15–
C3
GND TIES
C29
REV. A
Figure 10b. Bottom Assembly
R71
R41
R58
C2
C6
U4
C9
R7
R1
C1
R3
U2
R4
C13
U3
R56
U14
R43
R42
C8
C7
C34
C37
C15
E48
U16
R48
R47
R51
R52
C20
C10
GND TIE
GND TIE
C33
GND TIE
GND TIE
GND TIE
GND TIE
E40
C24
C36
C35
U15
R64
R65
R53
C21
C18
C28
C25
U17
R54
C17
R8 R49
R50
R63
U9
R38
C27
U11
C22
R60
R66
R39
C23
U10
R61
GND TIES
R72
C30
C4
C14
Figure 10a. Bottom View
AD10200
AD10200
Figure 10c. Ground 1
AGNDB
DGNDB
AGNDA
DGNDA
Figure 10d. Ground 2
–16–
REV. A
–17–
C3
GND TIES
C29
REV. A
Figure 10f. Top View
Figure 10e. Bottom Silk
R71
R41
R58
C2
C6
U4
C9
R7
R1
C1
R3
U2
R4
C13
U3
R56
U14
R43
R42
C8
C7
C34
C37
C15
E48
U16
R47
R48
R51
R52
C20
C10
GND TIE
GND TIE
C33
GND TIE
GND TIE
GND TIE
GND TIE
E40
C24
C36
C35
U15
R64
R65
R53
C21
C18
C28
C25
U17
R54
C17
R8 R49
R50
R63
U9
R38
C27
U11
C22
R60
R66
R39
C23
U10
R61
GND TIES
R72
C30
C4
C14
AD10200
AD10200
E5
E3
E33
E37
E29
L4
E35
E63
ENCBBAR
ENCB
L2
E1
GND TIES
E2
BJ1
EXTRA
E36
U6
E80
E79
E46
E45
C39
E58
E62
E59
J10
J11
E60
E61
C26
E83
E84
E55
E22
BUFLATB
E24
LATCHB
E50
AINB1
REF_B
U1
AINB2
J6
ANALOG
DEVICES
COPYRIGHT
E12
2/10 00
GND TIE
AD10200 EVALUATION BOARD
GS03363 (A)
E7
BEL
J7
E11
GND TIE
E39
E77
GND TIE
E49
E47
GND TIE
PIN 1
E78
REF_A
J3
E8
J2
3.3VDB
DGNDB
E30
E27
E26
C16
E38
AGNDB
R1
R1 1
R3 0
R2 0
R2 9
R2 8
R2 7
R1 6
R9 2
R2
R3 5
R3 6
R3 5
4
R3
R3 3
R3 2
1
+5VAB
J4
AINA1
8
R1 7
R1 6
R1 0
R4 4
R4 5
R4 6
R4 5
R1 4
R1 3
R1 4
R2
AINA2
J12
E81
E65
E66
E9
E10
E41
L3
BJ2
EXTRA
E28
+5VAA
E57
E56
E54
E42
E51
C38
U5
GND TIES
E64
LATCHA
E52 E53
9
R1
J5
E23
C5
E82
1
R2 0
R2
ENCABAR
3
R2 2
R2
BUFLATA
E19
ENCA
J1
AGNDA
E6
E43
E44
E68
E67
E74
E73
E71
E72
E69
E70
E75
E76
L1
3.3VDA
DGNDA
C12
E34
E4
E25
Figure 10g. Top Assembly
E3
E5
E29
U6
C39
E79
E58
E62
E59
J10
J11
E46
E60
E61
E45
C26
E83
E84
E55
E22
BUFLATB
E24
LATCHB
R1
R1 1
0
E80
E36
R3
R2 0
R2 9
R2 8
R2 7
R1 6
R9 2
R2
R3 5
R3 6
R3 5
R3 4
3
R3
R3 2
1
ENCBBAR
ENCB
L2
E1
E35
GND TIES
E2
L4
E63
3.3VDB
DGNDB
BJ1
EXTRA
E50
AINB1
REF_B
U1
AINB2
J6
ANALOG
DEVICES
COPYRIGHT
E12
2/10 00
GND TIE
AD10200 EVALUATION BOARD
GS03363 (A)
E7
BEL
J7
E11
GND TIE
E39
E77
GND TIE
E49
E47
GND TIE
PIN 1
E78
REF_A
J3
E8
J2
C16
E38
AGNDB
E30
E27
E26
E33
E37
+5VAB
J4
AINA1
8
R1 7
R1 6
R1 0
R4 4
R4
5
R4 6
R4 5
R1 4
R1 3
R1 4
R2
AINA2
L3
BJ2
EXTRA
E28
+5VAA
AGNDA
E6
E82
E81
E65
E66
E9
E10
E41
E42
E23
BUFLATA
LATCHA
E57
E52 E53
E56
E54
E51
C38
U5
GND TIES
E64
C5
J12
1
R2 0
R2 9
R1
ENCABAR
J5
3
R2 2
R2
E19
ENCA
J1
E43
E44
E68
E67
E74
E73
E71
E72
E69
E70
E75
E76
L1
3.3VDA
DGNDA
C12
E34
E4
E25
Figure 10h. Top Silk
–18–
REV. A
AD10200
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
68-Lead Ceramic Leaded Chip Carrier
(Z-68B)
0.010 (0.25)
0.008 (0.20)
0.007 (0.18)
0.290 (7.37)
MAX
0.960 (24.38)
0.950 (24.13) SQ
0.940 (23.88)
61
9
10
60
PIN 1
DETAIL A
1.070
(27.18)
MIN
0.800
(20.32)
BSC
1.190 (30.23)
1.180 (29.97) SQ
1.170 (29.72)
TOP VIEW
(PINS DOWN)
TOE DOWN
ANGLE
0–8 DEGREES
26
44
27
0.060 (1.52)
0.050 (1.27)
0.040 (1.02)
43
DETAIL A
0.230 (5.84)
MAX
0.055 (1.40)
0.050 (1.27)
0.045 (1.14)
0.021 (0.533)
0.017 (0.432)
0.014 (0.357)
Revision History
Location
Page
Data Sheet changed from REV. 0 to REV. A.
Edit to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edit to Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Edit to ENCODE Inputs section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Edit to Figure 9a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
REV. A
–19–
–20–
PRINTED IN U.S.A.
C01634–0-8/01(A)