Dual Bipolar/JFET, Audio
Operational Amplifier
OP275
FEATURES
Excellent Sonic Characteristics
Low Noise: 6 nV/Hz
Low Distortion: 0.0006%
High Slew Rate: 22 V/s
Wide Bandwidth: 9 MHz
Low Supply Current: 5 mA
Low Offset Voltage: 1 mV
Low Offset Current: 2 nA
Unity Gain Stable
SOIC-8 Package
PDIP-8 Package
PIN CONNECTIONS
8-Lead Narrow-Body SOIC
(S Suffix)
OUT A 1
8
V+
–IN A 2
7
OUT B
6
–IN B
+IN A 3
V– 4
OP275
5
+IN B
8-Lead PDIP
(P Suffix)
OUT A
1
–IN A
+IN A
V–
OP275
8
V+
2
7
OUT B
3
6
–IN B
4
5
+IN B
APPLICATIONS
High Performance Audio
Active Filters
Fast Amplifiers
Integrators
GENERAL DESCRIPTION
The OP275 is the first amplifier to feature the Butler Amplifier
front end. This new front end design combines both bipolar
and JFET transistors to attain amplifiers with the accuracy and
low noise performance of bipolar transistors, and the speed and
sound quality of JFETs. Total Harmonic Distortion plus Noise
equals that of previous audio amplifiers, but at much lower
supply currents.
A very low l/f corner of below 6 Hz maintains a flat noise density
response. Whether noise is measured at either 30 Hz or 1 kHz,
it is only 6 nVHz. The JFET portion of the input stage gives
the OP275 its high slew rates to keep distortion low, even when
large output swings are required, and the 22 V/µs slew rate of the
OP275 is the fastest of any standard audio amplifier. Best of all,
this low noise and high speed are accomplished using less than
5 mA of supply current, lower than any standard audio amplifier.
Improved dc performance is also provided with bias and offset
currents greatly reduced over purely bipolar designs. Input offset
voltage is guaranteed at 1 mV and is typically less than 200 µV.
This allows the OP275 to be used in many dc-coupled or summing applications without the need for special selections or the
added noise of additional offset adjustment circuitry.
The output is capable of driving 600  loads to 10 V rms while
maintaining low distortion. THD + Noise at 3 V rms is a low
0.0006%.
The OP275 is specified over the extended industrial (–40°C to
+85°C) temperature range. OP275s are available in both plastic DIP and SOIC-8 packages. SOIC-8 packages are available
in 2500-piece reels. Many audio amplifiers are not offered
in SOIC-8 surface-mount packages for a variety of reasons;
however, the OP275 was designed so that it would offer full
performance in surface-mount packaging.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks
and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com
Tel: 781/329-4700
Fax: 781/326-8703
© 2004 Analog Devices, Inc. All rights reserved.
OP275–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 15.0 V, T = 25C, unless otherwise noted.)
S
Parameter
Symbol
AUDIO PERFORMANCE
THD + Noise
Voltage Noise Density
en
Current Noise Density
Headroom
in
INPUT CHARACTERISTICS
Offset Voltage
VOS
Input Bias Current
IB
Input Offset Current
IOS
Input Voltage Range
Common-Mode Rejection Ratio
VCM
CMRR
Large Signal Voltage Gain
AVO
Offset Voltage Drift
VOS/T
A
Conditions
Min
VIN = 3 V rms,
RL = 2 k, f = 1 kHz
f = 30 Hz
f = 1 kHz
f = 1 kHz
THD + Noise  0.01%,
RL = 2 k, VS = ±18 V
–40°C  TA  +85°C
VCM = 0 V
VCM = 0 V, –40°C  TA  +85°C
VCM = 0 V
VCM = 0 V, –40°C  TA  +85°C
VCM = ±10.5 V,
–40°C  TA  +85°C
RL = 2 k
RL = 2 k, –40°C  TA  +85°C
RL = 600 
–10.5
Typ
%
nVHz
nVHz
pAHz
>12.9
dBu
100
100
2
2
80
250
175
106
RL = 2 k
RL = 2 k, –40°C  TA  +85°C
RL = 600 , VS = ±18 V
–13.5
–13
±13.9
±13.9
+14, –16
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
VS = ±4.5 V to ±18 V
VS = ±4.5 V to ±18 V,
–40°C  TA  +85°C
VS = ±4.5 V to ±18 V, VO = 0 V,
RL = , –40°C  TA  +85°C
VS = ±22 V, VO = 0 V, RL = ,
–40°C  TA  +85°C
85
111
RL = 2 k
15
Supply Voltage Range
VS
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Gain Bandwidth Product
Phase Margin
Overshoot Factor
SR
BWP
GBP
Øm
VIN = 100 mV, AV = +1,
RL = 600 , CL = 100 pF
1
1.25
350
400
50
100
+10.5
mV
mV
nA
nA
nA
nA
V
dB
V/mV
V/mV
V/mV
µV/°C
200
2
VO
ISY
Unit
0.006
7
6
1.5
OUTPUT CHARACTERISTICS
Output Voltage Swing
Supply Current
Max
+13.5
+13
V
V
V
dB
80
dB
4
±4.5
22
5
mA
5.5
±22
mA
V
9
62
V/µs
kHz
MHz
Degrees
10
%
Specifications subject to change without notice.
–2–
REV. C
OP275
ABSOLUTE MAXIMUM RATINGS1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22 V
Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22 V
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . ±7.5 V
Output Short-Circuit Duration to GND3 . . . . . . . . . . Indefinite
Storage Temperature Range
P, S Packages . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP275G . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
P, S Packages . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . . .300°C
Package Type
JA4
JC
Unit
8-Lead Plastic DIP (P)
8-Lead SOIC (S)
103
158
43
43
°C/W
°C/W
NOTES
1
Absolute maximum ratings apply to packaged parts, unless otherwise noted.
2
For supply voltages greater than ±22 V, the absolute maximum input voltage is equal
to the supply voltage.
3
Shorts to either supply may destroy the device. See data sheet for full details.
4
JA is specified for the worst-case conditions, i.e., JA is specified for device in socket
for PDIP packages; JA is specified for device soldered in circuit board for SOIC
packages.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
OP275GP
OP275GS
OP275GS-REEL
OP275GS-REEL7
OP275GSZ*
OP275GSZ-REEL*
OP275GSZ-REEL7*
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead PDIP
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
N-8
R-8
R-8
R-8
R-8
R-8
R-8
*Z = Pb-free part.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate
on the human body and test equipment and can discharge without detection. Although the OP275 features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
REV. C
–3–
OP275–Typical Performance Characteristics
25
1500
5
0
–5
–10
–VOM
–15
1000
500
+GAIN
RL = 600
5
10
15
20
SUPPLY VOLTAGE – V
25
135
20
90
MARKER 15 309.058Hz
PHASE (A/R) 90.606Deg
45
0
0
–10
–45
–20
–90
10k
100k
1M
PHASE – Degrees
30
CLOSED-LOOP GAIN – dB
40
40
10
80
60
40
20
1M
TPC 7. Common-Mode
Rejection vs. Frequency
–180
10M
100k
20
VS = 15V
TA = 25C
AVCL = +100
10M
VS = 15V
TA = 25C
50
AVCL = +10
10
0
1M
TPC 3. Closed-Loop Gain and
Phase, AV = +1
AVCL = +1
AVCL = +1
40
AVCL = +10
30
AVCL = +100
20
–10
10
10k
100k
1M
10M
FREQUENCY – Hz
0
100
100M
80
GAIN
+PSRR
80
VS = 15V
TA = 25C
–PSRR
40
20
0
10
1M
10M
100
100
60
10k
100k
FREQUENCY – Hz
1k
TPC 6. Closed-Loop Output
Impedance vs. Frequency
OPEN-LOOP GAIN – dB
POWER SUPPLY REJECTION – dB
VS = 15V
TA = 25C
10k
100k
FREQUENCY – Hz
–40
FREQUENCY – Hz
120
1k
–135
TPC 5. Closed-Loop Gain vs.
Frequency
120
0
100
–90
–30
30
–30
1k
TPC 4. Open-Loop Gain,
Phase vs. Frequency
100
–20
10k
100
–20
10M
0
–45
60
FREQUENCY – Hz
COMMON-MODE REJECTION – dB
75
50
VS = 15V
TA = 25C
50
0
25
50
TEMPERATURE – C
45
TPC 2. Open-Loop Gain vs.
Temperature
MARKER 15 309.059Hz
MAG (A/H)
60.115dB
60
–25
90
10
–10
IMPEDANCE – 
0
135
20
0
–GAIN
RL = 600
250
0
–50
TPC 1. Output Voltage Swing
vs. Supply Voltage
GAIN – dB
–GAIN
RL = 2k
750
180
VS = 15V
TA = 25C
30
+GAIN
RL = 2k
–20
–25
40
100
1k
10k
100k
FREQUENCY – Hz
1M
TPC 8. Power Supply Rejection vs.
Frequency
–4–
60
40
PHASE
VS = 15V
RL = 2k
TA = 25C
0
45
Ø m = 58
90
20
135
0
180
–20
225
–40
270
–60
1k
10k
100k
1M
10M
FREQUENCY – Hz
PHASE – Degrees
+VOM
10
VS = 15V
VO = 15V
PHASE – Degrees
1250
OPEN-LOOP GAIN – V/mV
OUTPUT VOLTAGE SWING – V
15
GAIN – dB
TA = 25C
RL = 2k
20
100M
TPC 9. Open-Loop Gain,
Phase vs. Frequency
REV. C
OP275
100
16
AVCL = +1
NEGATIVE EDGE
90
60
Øm
9
55
GBW
8
50
80
OVERSHOOT – %
10
70
60
–25
0
25
50
TEMPERATURE – C
50
40
30
VS = 15V
RL = 2k
VIN = 100mV p-p
20
0
40
100
75
TPC 10. Gain Bandwidth Product,
Phase Margin vs. Temperature
200
300
400
100
LOAD CAPACITANCE – pF
10
TA = 25C
VS = 15V
AVCL = +1
RL = 2k
4.5
TA = +85C
TA = +25C
4.0
TA = –40C
3.5
5
0
1k
10k
100k
1M
FREQUENCY – Hz
3.0
10M
TPC 13. Maximum Output
Swing vs. Frequency
10
15
20
SUPPLY VOLTAGE – V
200
150
100
50
–25
0
25
50
TEMPERATURE – C
75
100
TPC 16. Input Bias Current vs.
Temperature
8
+VOM
6
4
TA = 25C
VS = 15V
2
1k
LOAD RESISTANCE – 
10k
VS = 15V
110
100
90
SINK
80
70
60
50
40
SOURCE
30
20
–50
25
–25
0
25
50
TEMPERATURE – C
75
100
TPC 15. Short-Circuit Current
vs. Temperature
500
VS = 15V
TA = 25C
4
VS = 15V
–40 C to +85 C
400
BASED ON 920 OP AMPS
3
300
UNITS
CURRENT NOISE DENSITY – pA/ Hz
250
REV. C
5
5
300
0
–50
0
TPC 14. Supply Current vs.
Supply Voltage
VS = ±15V
10
TPC 12. Maximum Output
Voltage vs. Load Resistance
ABSOLUTE OUTPUT CURRENT – mA
15
–VOM
120
25
20
12
0
100
500
5.0
SUPPLY CURRENT – mA
MAXIMUM OUTPUT SWING – V
0
14
TPC 11. Small Signal Overshoot vs.
Load Capacitance
30
INPUT BIAS CURRENT – nA
AVCL = +1
POSITIVE EDGE
10
7
–50
MAXIMUM OUTPUT SWING – V
65
PHASE MARGIN – Degrees
GAIN BANDWIDTH PRODUCT – MHz
11
2
1
200
100
10
100
1k
FREQUENCY – Hz
TPC 17. Current Noise Density
vs. Frequency
–5–
100k
0
0
1
2
3
4
5
6 7
TCVOS – V/C
8
9
TPC 18. TCVOS Distribution
10
OP275
10
200
160
VS = 15V
TA = 25C
50
45
6
+0.1%
+0.01%
STEP SIZE – V
4
120
UNITS
TA = 25C
VS = 15V
8
80
2
0
–2
–4
40
–0.01%
–0.1%
–6
40
SLEW RATE – V/s
BASED ON 920 OP AMPS
35
–SR
30
+SR
25
–8
0
–500–400–300–200–100 0 100 200 300 400 500
INPUT OFFSET VOLTAGE – V
–10
TPC 19. Input Offset (VOS)
Distribution
0
100
200
300
400
CAPACITIVE LOAD – pF
500
TPC 21. Slew Rate vs. Capacitive
Load
50
VS = 15V
RL = 2k
35
30
45
TA = 25C
SLEW RATE – V/s
SLEW RATE – V/s
20
100 200 300 400 500 600 700 800 900
SETTLING TIME – ns
TPC 20. Step Size vs. Settling
Time
40
25
20
15
10
VS = 15V
RL = 2k
–SR
100
90
40
35
30
+SR
10
0%
25
5
0
0
0
0.2
0.4
0.6
0.8
1.0
20
–50
5V
–25
DIFFERENTIAL INPUT VOLTAGE – V
TPC 22. Slew Rate vs. Differential
Input Voltage
0
25
50
TEMPERATURE –  C
75
100
TPC 23. Slew Rate vs. Temperature
TPC 24. Negative Slew Rate
RL = 2 k , VS = ±15 V, AV = +1
CH A: 80.0 V FS
MKR: 6.23 nV/ Hz
100
90
200ns
10.0 V/DIV
100
90
10
10
0%
0%
5V
200ns
TPC 25. Positive Slew Rate
RL = 2 k , VS = ±15 V, AV = +1
50mV
100ns
TPC 26. Small Signal Response
RL = 2 k , VS = ±5 V, AV = +1
–6–
0 Hz
MKR:
1 000 Hz
2.5 kHz
BW: 15.0 MHz
TPC 27. Voltage Noise Density
vs. Frequency VS = ±15 V
REV. C
OP275
APPLICATIONS
Circuit Protection
THD + NOISE – %
0.010
OP275 has been designed with inherent short-circuit protection
to ground. An internal 30  resistor, in series with the output,
limits the output current at room temperature to ISC+ = 40 mA
and ISC– = –90 mA, typically, with ±15 V supplies.
However, shorts to either supply may destroy the device when
excessive voltages or currents are applied. If it is possible for a
user to short an output to a supply for safe operation, the output
current of the OP275 should be design-limited to ±30 mA, as
shown in Figure 1.
VS = 18V
RL = 600
0.001
0.0001
0.5
1
10
OUTPUT SWING – V rms
Figure 4. Headroom, THD + Noise vs. Output
Amplitude (V rms); RLOAD = 600  , VSUP = ±18 V
Total Harmonic Distortion
Total Harmonic Distortion + Noise (THD + N) of the OP275 is
well below 0.001% with any load down to 600 . However, this is
dependent upon the peak output swing. In Figure 2, the THD +
Noise with 3 V rms output is below 0.001%. In Figure 3, THD +
Noise is below 0.001% for the 10 k and 2 k loads but increases
to above 0.1% for the 600  load condition. This is a result of the
output swing capability of the OP275. Notice the results in Figure 4,
showing THD versus VIN (V rms). This figure shows that the THD
+ Noise remains very low until the output reaches 9.5 V rms. This
performance is similar to competitive products.
The output of the OP275 is designed to maintain low harmonic
distortion while driving 600  loads. However, driving 600 
loads with very high output swings results in higher distortion if
clipping occurs. A common example of this is in attempting to
drive 10 V rms into any load with ±15 V supplies. Clipping will
occur and distortion will be very high. To attain low harmonic
distortion with large output swings, supply voltages may be
increased. Figure 5 shows the performance of the OP275 driving
600  loads with supply voltages varying from ±18 V to ±20 V.
Notice that with ±18 V supplies the distortion is fairly high, while
with ±20 V supplies it is a very low 0.0007%.
RFB
0.0001
FEEDBACK
RX
332 
–
A1
+
VOUT
0.001
THD – %
A1 = 1/2 OP275
Figure 1. Recommended Output Short-Circuit Protection
RL = 600
VOUT = 10V rms @ 1kHz
0.01
0.010
THD + NOISE – %
RL = 600, 2k, 10k
VS = 15V
VIN = 3V rms
AV = +1
0.1
0
17
18
19
20
SUPPLY VOLTAGE – V
21
22
0.001
0.0005
Figure 5. THD + Noise vs. Supply Voltage
20
100
1k
10k
FREQUENCY – Hz
20k
Noise
The voltage noise density of the OP275 is below 7 nV/Hz from
30 Hz. This enables low noise designs to have good performance
throughout the full audio range. Figure 6 shows a typical OP275
with a 1/f corner at 2.24 Hz.
Figure 2. THD + Noise vs. Frequency vs. RLOAD
THD + NOISE – %
1
600
0.1
CH A: 80.0V FS
MKR: 45.6V/ Hz
AV = +1
VS = 18V
VIN = 10V rms
80kHz FILTER
0.010
10.0V/DIV
2k
0.001
10k
0.0001
20
100
1k
FREQUENCY – Hz
10k
20k
Figure 3. THD + Noise vs. RLOAD; VIN =10 V rms
0Hz
MKR:
2.24Hz
10Hz
BW: 0.145Hz
Figure 6. 1/f Noise Corner, VS = ±15 V, AV = 1000
REV. C
–7–
OP275
Noise Testing
prevent phase reversal; however, they will not prevent this effect
from occurring in noninverting applications. For these applications,
the fix is a simple one and is illustrated in Figure 9. A 3.92 k
resistor in series with the noninverting input of the OP275 cures
the problem.
For audio applications, the noise density is usually the most
important noise parameter. For characterization, the OP275 is
tested using an Audio Precision, System One. The input signal
to the Audio Precision must be amplified enough to measure it
accurately. For the OP275, the noise is gained by approximately
1020 using the circuit shown in Figure 7. Any readings on the
Audio Precision must then be divided by the gain. In implementing this test fixture, good supply bypassing is essential.
RFB*
–
VOUT
+
VIN
RL
RS
3.92k
100
909
*RFB
2k
IS OPTIONAL
A
OP37
OP275
Overload or Overdrive Recovery
OUTPUT
B
909
100
100
Figure 9. Output Voltage Phase Reversal Fix
OP37
909
Overload or overdrive recovery time of an operational amplifier
is the time required for the output voltage to recover to a rated
output voltage from a saturated condition. This recovery time
is important in applications where the amplifier must recover
quickly after a large abnormal transient event. The circuit shown
in Figure 10 was used to evaluate the OP275’s overload recovery
time. The OP275 takes approximately 1.2 ms to recover to VOUT =
+10 V and approximately 1.5 µs to recover to VOUT = –10 V.
4.42k
490
Figure 7. Noise Test Fixture
Input Overcurrent Protection
The maximum input differential voltage that can be applied
to the OP275 is determined by a pair of internal Zener diodes
connected across its inputs. They limit the maximum differential
input voltage to ±7.5 V. This is to prevent emitter-base junction
breakdown from occurring in the input stage of the OP275 when
very large differential voltages are applied. However, to preserve
the OP275’s low input noise voltage, internal resistances in series
with the inputs were not used to limit the current in the clamp
diodes. In small signal applications, this is not an issue; however,
in applications where large differential voltages can be inadvertently applied to the device, large transient currents can flow
through these diodes. Although these diodes have been designed
to carry a current of ±5 mA, external resistors as shown in Figure 8
should be used in the event that the OP275’s differential voltage
were to exceed ±7.5 V.
1.4k
1.4k
2
R2
10k
2
3
VIN
4V p-p
@100Hz
–
A1
1
VOUT
+
RS
909k
RL
2.43k
A1 = 1/2 OP275
Figure 10. Overload Recovery Time Test Circuit
Measuring Settling Time
The design of OP275 combines a high slew rate and a wide gain
bandwidth product to produce a fast settling (tS < 1 µs) amplifier
for 8- and 12-bit applications. The test circuit designed to measure the settling time of the OP275 is shown in Figure 11. This
test method has advantages over false-sum node techniques in
that the actual output of the amplifier is measured, instead of an
error voltage at the sum node. Common-mode settling effects are
exercised in this circuit in addition to the slew rate and bandwidth effects measured by the false-sum node method. Of course,
a reasonably flat-top pulse is required as the stimulus.
–
OP275
3
R1
1k
6
+
Figure 8. Input Overcurrent Protection
The output waveform of the OP275 under test is clamped by
Schottky diodes and buffered by the JFET source follower.
The signal is amplified by a factor of 10 by the OP260 and
then Schottky-clamped at the output to prevent overloading the
oscilloscope’s input amplifier. The OP41 is configured as a fast
integrator, which provides overall dc offset nulling.
Output Voltage Phase Reversal
Since the OP275’s input stage combines bipolar transistors for
low noise and p-channel JFETs for high speed performance, the
output voltage of the OP275 may exhibit phase reversal if either
of its inputs exceeds its negative common-mode input voltage.
This might occur in very severe industrial applications where
a sensor or system fault might apply very large voltages on the
inputs of the OP275. Even though the input voltage range of the
OP275 is ±10.5 V, an input voltage of approximately –13.5 V will
cause output voltage phase reversal. In inverting amplifier configurations, the OP275’s internal 7.5 V input clamping diodes will
High Speed Operation
As with most high speed amplifiers, care should be taken with
supply decoupling, lead dress, and component placement.
Recommended circuit configurations for inverting and noninverting applications are shown in Figures 12 and 13.
–8–
REV. C
OP275
16V–20V
–
+
+15V
0.1F
1k
2N4416
+
–
V–
D1
D2
0.1F
1/2 OP260AJ
1F
RF
2k
10k
–
–
–
IC2
10k
16V–20V
RG
222
2N2222A
5V
1N4148
OUTPUT
(TO SCOPE)
D4
+
V+
D3
DUT
+
1k
RL
+
750
15k
SCHOTTKY DIODES D1–D4 ARE
HEWLETT-PACKARD HP5082-2835
IC1 IS 1/2 OP260AJ
IC2 IS PMI OP41EJ
–15V
Figure 11. OP275’s Settling Time Test Fixture
CFB
+15V
10F
+
0.1F
RFB
–
2
3
VIN
8
–
1/2
1
OP275
+
4 0.1F
RS
VOUT
RL
Figure 14. Compensating the Feedback Pole
Attention to Source Impedances Minimizes Distortion
Since the OP275 is a very low distortion amplifier, careful attention should be given to source impedances seen by both inputs.
As with many FET-type amplifiers, the p-channel JFETs in the
OP275’s input stage exhibit a gate-to-source capacitance that varies with the applied input voltage. In an inverting configuration,
the inverting input is held at a virtual ground and, as such, does
not vary with input voltage. Thus, since the gate-to-source voltage
is constant, there is no distortion due to input capacitance modulation. In noninverting applications, however, the gate-to-source
voltage is not constant. The resulting capacitance modulation
can cause distortion above 1 kHz if the input impedance is
greater than 2 k and unbalanced.
Figure 12. Unity Gain Follower
+15V
10F
+
0.1F
10pF
4.99k
4.99k
3
8
–
VOUT
2k
–15V
2
CIN
+
10F
+
VIN
CS
1/2
OP275
+
4
1
VOUT
2k
RG
RF
2.49k
0.1F
10F
+
–
VIN
Figure 13. Unity Gain Inverter
VOUT
+
* RS = RG//RF IF RG//RF > 2k
FOR MINIMUM DISTORTION
In inverting and noninverting applications, the feedback resistance forms a pole with the source resistance and capacitance
(RS and CS) and the OP275’s input capacitance (CIN), as shown
in Figure 14. With RS and RF in the kilohm range, this pole
can create excess phase shift and even oscillation. A small
capacitor, CFB, in parallel and RFB eliminates this problem.
By setting RS (CS + CIN) = RFBCFB, the effect of the feedback
pole is completely removed.
REV. C
OP275
RS*
–15V
Figure 15. Balanced Input Impedance to Minimize
Distortion in Noninverting Amplifier Circuits
Figure 15 shows some guidelines for maximizing the distortion
performance of the OP275 in noninverting applications. The best
way to prevent unwanted distortion is to ensure that the parallel
combination of the feedback and gain setting resistors (RF and
RG) is less than 2 k. Keeping the values of these resistors small
has the added benefits of reducing the thermal noise of the circuit
–9–
OP275
and dc offset errors. If the parallel combination of RF and RG is
larger than 2 k, then an additional resistor, RS, should be used
in series with the noninverting input. The value of RS is determined by the parallel combination of RF and RG to maintain the
low distortion performance of the OP275.
Driving Capacitive Loads
The OP275 was designed to drive both resistive loads to 600 
and capacitive loads of over 1000 pF and maintain stability. While
there is a degradation in bandwidth when driving capacitive loads,
the designer need not worry about device stability. The graph in
Figure 16 shows the 0 dB bandwidth of the OP275 with capacitive loads from 10 pF to 1000 pF.
10
9
8
6
5
4
3
2
1
A 3-Pole, 40 kHz Low-Pass Filter
The closely matched and uniform ac characteristics of the OP275
make it ideal for use in GIC (Generalized Impedance Converter)
and FDNR (Frequency-Dependent Negative Resistor) filter
applications. The circuit in Figure 18 illustrates a linear-phase,
3-pole, 40 kHz low-pass filter using an OP275 as an inductance
simulator (gyrator). The circuit uses one OP275 (A2 and A3) for
the FDNR and one OP275 (A1 and A4) as an input buffer and
bias current source for A3. Amplifier A4 is configured in a gain
of 2 to set the pass band magnitude response to 0 dB. The benefits of this filter topology over classical approaches are that the
op amp used in the FDNR is not in the signal path and that the
filter’s performance is relatively insensitive to component variations. Also, the configuration is such that large signal levels can
be handled without overloading any of the filter’s internal nodes.
As shown in Figure 19, the OP275’s symmetric slew rate and low
distortion produce a clean, well behaved transient response.
0
800
R1
95.3k
1000
Figure 16. Bandwidth vs. CLOAD
VIN
High Speed, Low Noise Differential Line Driver
The circuit in Figure 17 is a unique line driver widely used in
industrial applications. With ±18 V supplies, the line driver can
deliver a differential signal of 30 V p-p into a 2.5 k load. The
high slew rate and wide bandwidth of the OP275 combine to
yield a full power bandwidth of 130 kHz while the low noise
front end produces a referred-to-input noise voltage spectral
density of 10 nV/Hz.
–
A2
3
+
R1
2k
2
A1
1
R2
787
1
–
A2
+
2
3
R3
1.82k
5
6
R6
4.12k
A3
C4
2200pF
7
5
R7
100k
R9
1k
6
A4
7
VOUT
R8
1k
C3
2200pF
A1, A4 = 1/2 OP275
A2, A3 = 1/2 OP275
R9
50
VO1
R5
1.82k
R11
1k
R4
2k
R7
2k
Figure 18. A 3-Pole, 40 kHz Low-Pass Filter
VO2 – VO1 = VIN
1
P1
10k
R2
2k
R5
2k R6
2k
6
A1 = 1/2 OP275
C1
2200pF
R4
1.87k
–
3
+
VIN
1
C2
2200pF
R3
2k
2
2 –
A1
3
+
–
400
600
CLOAD – pF
+
200
–
0
+
BANDWIDTH – MHz
7
The design is a transformerless, balanced transmission system
where output common-mode rejection of noise is of paramount
importance. Like the transformer based design, either output can
be shorted to ground for unbalanced line driver applications
without changing the circuit gain of 1. Other circuit gains can be
set according to the equation in the diagram. This allows the
design to be easily set to noninverting, inverting, or differential
operation.
–
A3
5
+
A2, A3 = 1/2 OP275
100
90
7
R8
2k
R10
50
R12
1k
VOUT
10V p-p
10kHz
VO2
10
R3
GAIN = R1
SET R2, R4, R5 = R1 AND R6, R7, R8 = R3
0%
Figure 17. High Speed, Low Noise Differential Line Driver
SCALE: VERTICAL–2V/ DIV
HORIZONTAL–10s/ DIV
Figure 19. Low-Pass Filter Transient Response
–10–
REV. C
OP275
OP275 SPICE Model
*
* Node assignments
*
noninverting input
*
inverting input
*
positive supply
*
negative supply
*
output
**
.SUBCKT OP275 1
2
99
50
34
*
* INPUT STAGE & POLE AT 100 MHz
*
R3
5
51
2.188
R4
6
51
2.188
CIN
1
2
3.7E-12
CM1
1
98
7.5E-12
CM2
2
98
7.5E-12
C2
5
6
364E-12
I1
97 4
100E-3
IOS
1
2
1E-9
EOS
9
3
POLY(1) 26
28
0.5E-3 1
Q1
5
2
7
QX
Q2
6
9
8
QX
R5
7
4
1.672
R6
8
4
1.672
D1
2
36
DZ
D2
1
36
DZ
EN
3
1
10
0
1
GN1
0
2
13
0
1E-3
GN2
0
1
16
0
1E-3
*
EREF 98 0
28
0
1
EP
97 0
99
0
1
EM
51 0
50
0
1
*
* VOLTAGE NOISE SOURCE
*
DN1
35 10
DEN
DN2
10 11
DEN
VN1
35 0
DC
2
VN2
0
11
DC
2
*
* CURRENT NOISE SOURCE
*
DN3
12 13
DIN
DN4
13 14
DIN
VN3
12 0
DC
2
VN4
0
14
DC
2
*
* CURRENT NOISE SOURCE
*
DN5
15 16
DIN
DN6
16 17
DIN
VN5
15 0
DC
2
VN6
0
17
DC
2
*
* GAIN STAGE & DOMINANT POLE AT 32 Hz
*
R7
18 98
1.09E6
C3
18 98
4.55E-9
G1
98 18
5
6
4.57E-1
V2
97 19
1.35
V3
20 51
1.35
D3
18 19
DX
D4
20 18
DX
REV. C
* POLE/ZERO PAIR AT 1.5 MHz/2.7 MHz
*
R8
21 98
1E-3
R9
21 22
1.25E-3
C4
22 98
47.2E-12
G2
98 21
18
28
1E-3
*
* POLE AT 100 MHz
*
R10 23 98 1
C5
23 98
1.59E-9
G3
98 23
21
28
1
*
* POLE AT 100 MHz
*
R11 24 98 1
C6
24 98
1.59E-9
G4
98 24
23
28
1
*
* COMMON-MODE GAIN NETWORK WITH ZERO AT
1 kHz
*
R12 25 26 1E6
C7 25 26 1.5915E-12
R13 26 98 1
E2
25 98
POLY(2) 1 98
2 98
0 2.50
2.50
*
* POLE AT 100 MHz
*
R14 27 98 1
C8
27 98
1.59E-9
G5
98 27
24
28
1
*
* OUTPUT STAGE
*
R15
28 99
100E3
R16
28 50
100E3
C9
28 50
1E-6
ISY
99 50
1.85E-3
R17
29 99
100
R18
29 50
100
L2
29 34
1E-9
G6
32 50
27
29
10E-3
G7
33 50
29
27
10E-3
G8
29 99
99
27
10E-3
G9
50 29
27
50
10E-3
V4
30 29
1.3
V5
29 31
3.8
F1
29 0
V4
1
F2
0
29
V5
1
D5
27 30
DX
D6
31 27
DX
D7
99 32
DX
D8
99 33
DX
D9
50 32
DY
D10
50 33
DY
*
* MODELS USED
*
.MODEL QX
PNP(BF=5E5)
.MODEL DX
D(IS=1E-12)
.MODEL DY
D(IS=1E-15 BV=50)
.MODEL DZ
D(IS=1E-15 BV=7.0)
.MODEL DEN
D(IS=1E-12 RS=4.35K KF=1.95E-15
AF=1)
.MODEL DIN
D(IS=1E-12 RS=268 KF=1.08E-15 AF=1)
.ENDS
–11–
OP275
OUTLINE DIMENSIONS
8-Lead Standard Small Outline Package [SOIC]
(S Suffix)
(R-8)
Dimensions shown in millimeters and (inches)
4.00 (0.1574)
3.80 (0.1497)
8
5
1
4
6.20 (0.2440)
5.80 (0.2284)
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
SEATING
0.10
PLANE
C00298–0–2/04(C)
5.00 (0.1968)
4.80 (0.1890)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
 45
0.25 (0.0099)
8
0.25 (0.0098) 0 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8-Lead Plastic Dual-in-Line Package [PDIP]
(P Suffix)
(N-8)
Dimensions shown in inches and (millimeters)
0.375 (9.53)
0.365 (9.27)
0.355 (9.02)
8
5
1
4
0.295 (7.49)
0.285 (7.24)
0.275 (6.98)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.180
(4.57)
MAX
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.015
(0.38)
MIN
SEATING
PLANE
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
COMPLIANT TO JEDEC STANDARDS MO-095AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Revision History
Location
Page
2/04—Data Sheet changed from REV. B to REV. C.
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1/03—Data Sheet changed from REV. A to REV. B.
Deleted WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
–12–
REV. C