Precision JFET, High Speed,
Dual Operational Amplifier
OP249
Data Sheet
PIN CONFIGURATIONS
Slew rate: 22 V/µs typical
Settling time (0.01%): 1.2 µs maximum
Offset voltage: 200 µV typical
Open-loop gain: 1000 V/mV minimum
Total harmonic distortion: 0.002% typical
OUT A
1
–IN A
2
+IN A
3
V–
4
OP249
A
B
8
V+
7
OUT B
6
–IN B
5
+IN B
00296-001
FEATURES
Figure 1. 8-Lead CERDIP (Q-8) and
8-Lead PDIP (N-8)
Output amplifier for fast DACs
Signal processing
Instrumentation amplifiers
Fast sample-and-holds
Active filters
Low distortion audio amplifiers
Input buffer for ADCs
Servo controllers
+IN A
1
8
–IN A
V–
2
A
7
OUT A
+IN B
3
OP249
6
V+
–IN B
4
B
5
OUT B
00296-002
APPLICATIONS
Figure 2. 8-Lead SOIC (R-8)
GENERAL DESCRIPTION
The OP249 is a high speed, precision dual JFET op amp, similar
to the popular single op amp. The OP249 outperforms available
dual amplifiers by providing superior speed with excellent dc
performance. Ultrahigh open-loop gain (1 kV/mV minimum),
low offset voltage, and superb gain linearity makes the OP249
the industry’s first true precision, dual high speed amplifier.
Symmetrical slew rate, even when driving large load, such as,
600 Ω or 200 pF of capacitance and ultralow distortion, make
the OP249 ideal for professional audio applications, active filters,
high speed integrators, servo systems, and buffer amplifiers.
With a slew rate of 22 V/µs typical and a fast settling time of less
than 1.2 µs maximum to 0.01%, the OP249 is an ideal choice for
high speed bipolar DAC and ADC applications. The excellent
dc performance of the OP249 allows the full accuracy of high
resolution CMOS DACs to be realized.
0.01
TA = 25°C
VS = ±15V
VO = 10V p-p
RL = 10kΩ
AV = 1
10mV
500ns
Figure 3. Fast Settling (0.01%)
Rev. I
0.001
20
100
90
100
1k
10
0%
5V
1µs
00296-005
10
0%
00296-003
100
90
00296-004
870ns
10k 20k
Figure 4. Low Distortion, AV = 1, RL = 10 kΩ
Figure 5. Excellent Output Drive, RL = 600 Ω
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©1989–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
OP249
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Applications ....................................................................................... 1
Applications Information .............................................................. 13
Pin Configurations ........................................................................... 1
Open-Loop Gain Linearity ....................................................... 14
General Description ......................................................................... 1
Offset Voltage Adjustment ........................................................ 14
Revision History ............................................................................... 2
Settling Time ............................................................................... 14
Specifications..................................................................................... 3
DAC Output Amplifier .............................................................. 15
Electrical Characteristics ............................................................. 3
Discussion on Driving ADCs ................................................... 16
Absolute Maximum Ratings ............................................................ 6
Outline Dimensions ....................................................................... 17
ESD Caution .................................................................................. 6
Ordering Guide .......................................................................... 18
REVISION HISTORY
10/15—Rev. H to Rev. I
Changes to Features Section............................................................ 1
Changes to Ordering Guide ............................................................ 8
Deleted Table 7 .................................................................................. 8
11/13—Rev. G to Rev. H
Changes to Figure 39 and Figure 41............................................. 13
4/10—Rev. F to Rev. G
Changes to Features Section and General Description Section . 1
Changes to Offset Voltage Parameter, Table 1 .............................. 3
Deleted Long Term Offset Voltage Parameter and
Note 1, Table 1 ................................................................................... 3
Changes to Offset Voltage Parameter, Offset Voltage
Temperature Coefficient Parameter, and Note 1, Table 3 ........... 5
Delete OP249F Columns, Table 3................................................... 5
Changes to Offset Voltage Parameter and Offset Voltage
Temperature Coefficient Parameter, Table 4................................. 5
Inserted OP249F Columns, Table 4 ............................................... 5
Changes to Discussion on Driving ADCs Section ..................... 16
Deleted Figure 52 and Figure 53................................................... 17
9/01—Rev. D to Rev. E
Edits to Features and Pin Connections ..........................................1
Edits to Electrical Characteristics .............................................. 2, 3
Edits to Absolute Maximum Ratings, Package Type, and
Ordering Guide..................................................................................4
Deleted Wafer Test Limits and Dice Characteristics Section ......5
Edits to Typical Performance Characteristics ................................8
Edits to Macro-Model Figure........................................................ 15
Edits to Outline Dimensions......................................................... 17
5/07—Rev. E to Rev. F
Updated Format .................................................................. Universal
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Table 3 and Table 4 ....................................................... 5
Changes to Table 5 ............................................................................ 6
Changes to Figure 31 ...................................................................... 11
Changes to Figure 37 and Figure 38............................................. 12
Deleted OP249 SPICE Macro-Model Section ............................ 14
Deleted Figure 18; Renumbered Sequentially............................. 14
Deleted Table I ................................................................................ 15
Changes to Discussion on Driving ADCs Section ..................... 17
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 19
Rev. I | Page 2 of 18
Data Sheet
OP249
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VS = ±15 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Offset Voltage
Offset Stability
Input Bias Current
Input Offset Current
Input Voltage Range1
Symbol
VOS
Conditions
VCM = 0 V
Min
IB
IOS
IVR
VCM = 0 V, TA = 25°C
VCM = 0 V, TA = 25°C
OP249A
Typ
0.2
1.5
30
6
12.5
Max
0.75
75
25
±11
Common-Mode Rejection
Power-Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing
CMR
PSRR
AVO
VO
VCM = ±11 V
VS = ± 4.5 V to ±18 V
VO = ±10 V, RL = 2 kΩ
RL = 2 kΩ
80
1000
ISC
80
31.6
500
±20
Supply Current
Slew Rate
Gain Bandwidth Product2
Settling Time
Phase Margin
Differential Input Impedance
Open-Loop Output Resistance
Voltage Noise
Voltage Noise Density
ISY
SR
GBW
tS
ΘM
ZIN
RO
en p-p
en
Current Noise Density
Voltage Supply Range
in
VS
1
2
3
No load, VO = 0 V
RL = 2 kΩ, CL = 50 pF
18
3.5
10 V step 0.01%3
0 dB gain
0.1 Hz to 10 Hz
fO = 10 Hz
fO = 100 Hz
fO = 1 kHz
fO = 10 kHz
fO = 1 kHz
±4.5
Guaranteed by CMR test.
Guaranteed by design.
Settling time is sample tested.
Rev. I | Page 3 of 18
Max
0.9
75
25
–12.5
90
12
1200
12.5
50
±12.0
−12.5
36
Output shorted to
ground
OP249F
Typ
0.2
1.5
30
6
12.5
±11
−12.5
90
12
1400
12.5
±12.0
Short-Circuit Current Limit
Min
–12.5
36
±50
−33
5.6
22
4.7
0.9
55
1012||6
35
2
75
26
17
16
0.003
±15
±20
7.0
18
3.5
1.2
±18
±4.5
±50
–33
5.6
22
4.7
0.9
55
1012||6
35
2
75
26
17
16
0.003
±15
7.0
1.2
±18
Unit
mV
µV/month
pA
pA
V
V
V
dB
µV/V
V/mV
V
V
V
mA
mA
mA
mA
V/µs
MHz
µs
Degrees
Ω||pF
Ω
µV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
V
OP249
Data Sheet
VS = ±15 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
Offset Voltage
Input Bias Current
Input Offset Current
Input Voltage Range1
Symbol
VOS
IB
IOS
IVR
Conditions
VCM = 0 V
VCM = 0 V, TA = 25°C
VCM = 0 V TA = 25°C
Min
OP249G
Typ
0.4
40
10
12.5
Max
2.0
75
25
−12.0
90
12
1100
12.5
50
±11
Common-Mode Rejection
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing
CMR
PSRR
AVO
VO
VCM = ±11 V
VS = ±4.5 V to ±18 V
VO = ±10 V; RL = 2 kΩ
RL = 2 kΩ
76
500
±12.0
Short-Circuit Current Limit
ISC
−12.5
36
Output shorted to ground
±20
Supply Current
Slew Rate
Gain Bandwidth Product2
Settling Time
Phase Margin
Differential Input Impedance
Open-Loop Output Resistance
Voltage Noise
Voltage Noise Density
ISY
SR
GBW
tS
ΘM
ZIN
RO
en p-p
en
Current Noise Density
Voltage Supply Range
in
VS
1
2
No load; VO = 0 V
RL = 2 kΩ, CL = 50 pF
18
10 V step 0.01%
0 dB gain
0.1 Hz to 10 Hz
fO = 10 Hz
fO = 100 Hz
fO = 1 kHz
fO = 10 kHz
fO = 1 kHz
±4.5
Guaranteed by CMR test.
Guaranteed by design.
Rev. I | Page 4 of 18
±50
−33
5.6
22
4.7
0.9
55
1012||6
35
2
75
26
17
16
0.003
±15
7.0
1.2
±18
Unit
mV
pA
pA
V
V
V
dB
µV/V
V/mV
V
V
V
mA
mA
mA
mA
V/µs
MHz
µs
Degree
Ω||pF
Ω
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
V
Data Sheet
OP249
VS = ±15 V, −55°C ≤ TA ≤ +125°C for A grade, unless otherwise noted.
Table 3.
Parameter
Offset Voltage
Symbol
VOS
Conditions
VCM = 0 V
Offset Voltage Temperature Coefficient
Input Bias Current1
Input Offset Current1
Input Voltage Range2
TCVOS
IB
IOS
IVR
VCM = 0 V
Min
OP249A
Typ
Max
0.12
1.0
1
4
0.04
12.5
10
20
4
±11
Common-Mode Rejection
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing
CMR
PSRR
AVO
VO
VCM = ±11 V
VS = ±4.5 V to ±18 V
RL = 2 kΩ; VO = ±10 V
RL = 2 kΩ
76
500
−12.5
110
5
1400
12.5
50
±12
Supply Current
1
2
ISY
−12.5
5.6
No load, VO = 0 V
7.0
Unit
mV
μV/°C
nA
nA
V
V
V
dB
μV/V
V/mV
V
V
V
mA
TA = 125°C.
Guaranteed by CMR test.
VS = ±15 V, −40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 4.
Parameter
Offset Voltage
Offset Voltage Temperature Coefficient
Input Bias Current1
Input Offset Current1
Input Voltage Range2
Symbol
VOS
TCVOS
IB
IOS
IVR
Conditions
VCM = 0 V
VCM = 0 V
Min
OP249F
Typ
0.5
2.2
0.3
0.02
12.5
Max
1.1
12
4.0
1.2
±11
Common-Mode Rejection
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing
CMR
PSRR
AVO
VO
VCM = ±11 V
VS = ±4.5 V to ±18 V
RL = 2 kΩ; VO = ±10 V
RL = 2 kΩ
80
250
1
2
ISY
No load, VO = 0 V
TA = 85°C.
Guaranteed by CMR test.
Rev. I | Page 5 of 18
OP249G
Typ
1.0
6
0.5
0.04
12.5
Max
3.6
25
4.5
1.5
−12.5
95
10
1200
12.5
100
±11
−12.5
90
7
1200
12.5
76
100
250
±12
Supply Current
Min
±12.0
−12.5
5.6
7.0
−12.5
5.6
7.0
Unit
mV
μV/°C
nA
nA
V
V
V
dB
μV/V
V/mV
V
V
V
mA
OP249
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Supply Voltage
Input Voltage2
Differential Input Voltage2
Output Short-Circuit Duration
Storage Temperature Range
Operating Temperature Range
OP249A (Q)
OP249F (Q)
OP249G (N, R)
Junction Temperature Range
OP249A (Q), OP249F (Q)
OP249G (N, R)
Lead Temperature (Soldering, 60 sec)
1
1
2
Rating
±18 V
±18 V
36 V
Indefinite
−65°C to +175°C
−55°C to +125°C
−40°C to +85°C
−40°C to +85°C
−65°C to +175°C
−65°C to +150°C
300°C
Absolute maximum ratings apply to packaged parts, unless otherwise noted.
For supply voltages less than ±18 V, the absolute maximum input voltage is
equal to the supply voltage.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 6. Thermal Resistance
Package Type
8-Lead CERDIP (Q)
8-Lead PDIP (N)
8-Lead SOIC (R)
1
θJA1
134
96
150
θJC
12
37
41
Unit
°C/W
°C/W
°C/W
θJA is specified for worst-case mounting conditions, that is, θJA is specified for
device in socket for CERDIP and PDIP packages; θJA is specified for device
soldered to printed circuit board for SOIC package.
ESD CAUTION
Rev. I | Page 6 of 18
Data Sheet
OP249
TYPICAL PERFORMANCE CHARACTERISTICS
120
120
45
40
90
PHASE
Θm = 55
20
135
0
180
10k
100k
1M
225
100M
10M
FREQUENCY (Hz)
+PSRR
60
–PSRR
40
20
0
10
00296-006
–20
1k
80
Θm
6
GBW
4
–50
–25
0
25
50
75
100
2
125
TEMPERATURE (°C)
24
–SR
22
+SR
20
18
16
–75
00296-007
45
–75
–25
0
25
50
75
100
125
Figure 10. Slew Rate vs. Temperature
28
140
TA = 25°C
VS = ±15V
TA = 25°C
VS = ±15V
RL = 2kΩ
26
SLEW RATE (V/µs)
100
80
60
24
22
20
40
0
100
1k
10k
100k
1M
00296-011
18
20
00296-008
COMMON-MODE REJECTION (dB)
–50
TEMPERATURE (°C)
Figure 7. Phase Margin, Gain Bandwidth Product vs. Temperature
120
1M
100k
VS = ±15V
RL = 2kΩ
CL = 50pF
26
SLEW RATE (V/µs)
PHASE MARGIN (°C)
GAIN BANDWIDTH PRODUCT (MHz)
8
50
10k
28
10
55
1k
Figure 9. Power Supply Rejection vs. Frequency
VS = ±15V
60
100
FREQUENCY (Hz)
Figure 6. Open-Loop Gain, Phase vs. Frequency
65
00296-009
GAIN
60
PHASE (°C)
0
100
00296-010
80
POWER SUPPLY REJECTION (dB)
100
OPEN-LOOP GAIN (dB)
TA = 25°C
VS = ±15V
TA = 25°C
VS = ±15V
RL = 2kΩ
16
0
10M
0.2
0.4
0.6
0.8
DIFFERENTIAL INPUT VOLTAGE (V)
FREQUENCY (Hz)
Figure 11. Slew Rate vs. Differential Input Voltage
Figure 8. Common-Mode Rejection vs. Frequency
Rev. I | Page 7 of 18
1.0
OP249
Data Sheet
35
0.01
TA = 25°C
VS = ±15V
VO = 10V p-p
RL = 10kΩ
AV = 1
TA = 25°C
VS = ±15V
SLEW RATE (V/µs)
30
25
NEGATIVE
20
POSITIVE
15
5
0
200
100
400
300
0.001
20
500
00296-015
00296-012
10
100
1k
10k
20k
CAPACITIVE LOAD (pF)
Figure 12. Slew Rate vs. Capacitive Load
Figure 15. Distortion vs. Frequency
10
0.01
TA = 25°C
VS = ±15V
AVCL = 1
8
TA = 25°C
VS = ±15V
VO = 10V p-p
RL = 2kΩ
AV = 1
OUTPUT STEP SIZE (V)
6
0.1%
4
0.01%
2
0
–2
0.01%
–4
0.1%
–8
–10
0
200
400
600
800
0.001
20
1000
00296-016
00296-013
–6
100
1k
10k
20k
10k
20k
SETTLING TIME (ns)
Figure 13. Step Size vs. Settling Time
Figure 16. Distortion vs. Frequency
100
0.01
TA = 25°C
VS = ±15V
VO = 10V p-p
RL = 600Ω
AV = 1
80
60
40
20
0
0
100
1k
10k
0.001
20
FREQUENCY (Hz)
00296-017
00296-014
VOLTAGE NOISE DENSITY (nV/ Hz)
TA = 25°C
VS = ±15V
100
1k
Figure 17. Distortion vs. Frequency
Figure 14. Voltage Noise Density vs. Frequency
Rev. I | Page 8 of 18
Data Sheet
OP249
500mV
0.1
1s
TA = 25°C
VS = ±15V
VO = 10V p-p
RL = 10kΩ
AV = 1
+1µV
00296-018
0.01
20
00296-021
–1µV
100
1k
10k
BANDWIDTH (0.1Hz TO 10Hz)
TA = 25°C, VS = ±15V
20k
Figure 21. Low Frequency Noise
Figure 18. Distortion vs. Frequency
60
TA = 25°C
VS = ±15V
0.1
TA = 25°C
VS = ±15V
VO = 10V p-p
RL = 2kΩ
AV = 10
CLOSED-LOOP GAIN (dB)
50
40
AVCL = 100
30
20
10
0
AVCL = 10
AVCL = 5
AVCL = 1
0.01
20
100
1k
10k
–20
1k
00296-022
00296-019
–10
10k
20k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 19. Distortion vs. Frequency
Figure 22. Closed-Loop Gain vs. Frequency
50
TA = 25°C
VS = ±15V
0.1
TA = 25°C
VS = ±15V
VO = 10V p-p
RL = 600kΩ
AV = 10
IMPEDANCE (Ω)
40
30
AVCL = 1
20
AVCL = 10
10
0.01
20
100
1k
10k
0
100
20k
1k
10k
00296-023
00296-020
AVCL = 100
100k
1M
FREQUENCY (Hz)
Figure 20. Distortion vs. Frequency
Figure 23. Closed-Loop Output Impedance vs. Frequency
Rev. I | Page 9 of 18
10M
OP249
Data Sheet
30
20
OUTPUT VOLTAGE SWING (V)
25
OUTPUT VOLTAGE (V p-p)
TA = 25°C
RL = 2kΩ
15
20
15
AD8512
10
OP249
10
5
0
–5
–10
5
1M
00296-027
0
1k
–15
00296-024
AD712
–20
10M
0
±5
FREQUENCY (Hz)
Figure 24. Output Voltage vs. Frequency
±20
6.0
VS = ±15V
RL = 2kΩ
VIN = 100mV p-p
VS = ±15V
NO LOAD
60
SUPPLY CURRENT (mA)
70
AVCL = 1
NEGATIVE EDGE
50
AVCL = 1
POSITIVE EDGE
40
30
10
00296-025
20
AVCL = 5
0
0
100
200
300
400
5.8
5.6
5.4
5.2
–75
500
00296-028
80
–50
–25
0
LOAD CAPACITANCE (pF)
50
75
100
125
Figure 28. Supply Current vs. Temperature
16
14
25
TEMPERATURE (°C)
Figure 25. Small Overshoot vs. Load Capacitance
6.0
TA = 25°C
VS = ±15V
5.8
12
SUPPLY CURRENT (mA)
+VOHM = |–VOHM|
10
8
6
4
TA = +25°C
5.6
TA = +125°C
5.4
TA = –55°C
5.2
0
100
00296-026
2
1k
00296-029
MAXIMUM OUTPUT SWING (V)
±15
Figure 27. Output Voltage Swing vs. Supply Voltage
90
OVERSHOOT (%)
±10
SUPPLY VOLTAGE (V)
5.0
10k
0
LOAD RESISTANCE (Ω)
5
10
15
SUPPLY VOLTAGE (V)
Figure 29. Supply Current vs. Supply Voltage
Figure 26. Maximum Output Voltage Swing vs. Load Resistance
Rev. I | Page 10 of 18
20
Data Sheet
OP249
180
10k
TA = 25°C
VS = ±15V
415 × OP249
(830 OP AMPS)
INPUT BIAS CURRENT (pA)
140
VS = ±15V
VCM = 0V
UNITS
120
100
80
60
00296-030
40
20
0
–1000 –800 –600 –400 –200
0
200
400
600
800
1k
100
10
1
–75
1000
00296-033
160
–50
–25
VOS (µV)
Figure 30. VOS Distribution (N-8)
50
75
100
125
104
TA = 25°C
VS = ±15V
VS = ±15V
–40°C TO +85°C
(830 OP AMPS)
270
240
103
BIAS CURRENT (pA)
210
180
150
120
90
102
101
00296-031
60
30
0
0
2
4
6
8
10
12
14
16
18
20
22
100
–15
24
00296-034
UNITS
25
Figure 33. Input Bias Current vs. Temperature
300
–10
TCVOS (µV/°C)
–5
5
0
10
15
COMMON-MODE VOLTAGE (V)
Figure 31. TCVOS Distribution (N-8)
Figure 34. Bias Current vs. Common-Mode Voltage
50
50
TA = 25°C
VS = ±15V
VS = ±15V
40
INPUT BIAS CURRENT (pA)
40
30
20
10
30
20
0
0
1
2
3
4
00296-035
10
00296-032
OFFSET VOLTAGE (µV)
0
TEMPERATURE (°C)
0
5
0
TIME AFTER POWER APPLIED (Minutes)
2
4
6
8
TIME AFTER POWER APPLIED (Minutes)
Figure 32. Offset Voltage Warm-Up Drift
Figure 35. Bias Current Warm-Up Drift
Rev. I | Page 11 of 18
10
OP249
Data Sheet
80
80
40
20
0
–75
–50
–25
0
25
50
75
100
VS = ±15V
8000
RL = 10kΩ
6000
RL = 2kΩ
4000
2000
00296-037
OPEN-LOOP GAIN (V/mV)
10000
0
25
50
40
20
–50
–25
0
25
50
75
100
125
Figure 38. Short-Circuit Output Current vs. Junction Temperature
12000
–25
SINK
TEMPERATURE (°C)
Figure 36. Input Offset Current vs. Temperature
–50
60
0
–75
125
TEMPERATURE (°C)
0
–75
VS = ±15V
SOURCE
00296-038
SHORT-CIRCUIT OUTPUT CURRENT (mA)
60
00296-036
INPUT OFFSET CURRENT (pA)
TA = 25°C
VCM = 0V
75
100
125
TEMPERATURE (°C)
Figure 37. Open-Loop Gain vs. Temperature
Rev. I | Page 12 of 18
Data Sheet
OP249
APPLICATIONS INFORMATION
V+
+IN
100
90
VOUT
–IN
10
0%
5V
1µs
A) OP249
00296-039
100
90
V–
Figure 39. Simplified Schematic (1/2 OP249)
2
1/2
OP249
+3V
5V
1
3
5kΩ
Figure 41. Large-Signal Transient Response,
AV = 1, VIN = 20 V p-p, ZL = 2 kΩ//200 pF, VS = ±15 V
The OP249 was carefully designed to provide symmetrically
matched slew characteristics in both the negative and positive
directions, even when driving a large output load.
+18V
8
1/2
OP249
+3V
5
7
4
–18V
5kΩ
00296-040
6
1µs
B) LT1057
00296-041
10
0%
Figure 40. Burn-In Circuit
The OP249 represents a reliable JFET amplifier design,
featuring an excellent combination of dc precision and high
speed. A rugged output stage provides the ability to drive a
600 Ω load and still maintain a clean ac response. The OP249
features a large signal response that is more linear and symmetric
than previously available JFET input amplifiers. Figure 41
compares the large signal response of the OP249 to other
industry-standard dual JFET amplifiers.
Typically, the slewing performance of the JFET amplifier is
specified as a number of V/µs. There is no discussion on the
quality, that is, linearity and symmetry of the slewing response.
The slewing limitation of the amplifier determines the maximum
frequency at which a sinusoidal output can be obtained without
significant distortion. However, it is important to note that the
nonsymmetric slewing typical of previously available JFET
amplifiers adds a higher series of harmonic energy content to
the resulting response—and an additional dc output component.
Examples of potential problems of nonsymmetric slewing behavior
can be in audio amplifier applications, where a natural low distortion sound quality is desired and in servo or signal processing
systems where a net dc offset cannot be tolerated. The linear
and symmetric slewing feature of the OP249 makes it an ideal
choice for applications that exceed the full power bandwidth
range of the amplifier.
Rev. I | Page 13 of 18
OP249
Data Sheet
R4
R3
VIN
1/2
R5
50kΩ
VOUT
OP249
R1
200kΩ
R2
31Ω
VOS ADJUST RANGE = ±V
R2
R1
00296-044
+V
100
90
–V
Figure 44. Offset Adjustment for Inverting Amplifier Configuration
+V
10
R5
1µs
50mV
R3
50kΩ
R1
200kΩ
1/2
R2
33Ω
Figure 42. Small-Signal Transient Response,
AV = 1, ZL = 2 kΩ||100 pF, No Compensation, VS = ±15 V
R4
VOUT
OP249
–V
As with most JFET input amplifiers, the output of the OP249
can undergo phase inversion if either input exceeds the specified
input voltage range. Phase inversion does not damage the
amplifier, nor does it cause an internal latch-up condition.
Supply decoupling should be used to overcome inductance and
resistance associated with supply lines to the amplifier. A 0.1 µF
and a 10 µF capacitor should be placed between each supply pin
and ground.
OPEN-LOOP GAIN LINEARITY
The OP249 has both an extremely high open-loop gain of
1 kV/mV minimum and constant gain linearity, which enhances its
dc precision and provides superb accuracy in high closed-loop
gain applications. Figure 43 illustrates the typical open-loop
gain linearity—high gain accuracy is assured, even when
driving a 600 Ω load.
OFFSET VOLTAGE ADJUSTMENT
The inherent low offset voltage of the OP249 makes offset
adjustments unnecessary in most applications. However, where
a lower offset error is required, balancing can be performed
with simple external circuitry, as shown in Figure 44 and Figure 45.
VOS ADJUST RANGE = ±V
VIN
GAIN =
VOUT
VIN
=1+
R2
R1
R5
R4 + R2
00296-045
00296-042
0%
R5
IF R2 << R4
=1+
R4
Figure 45. Offset Adjustment for Noninverting Amplifier Configuration
In Figure 44, the offset adjustment is made by supplying a small
voltage at the noninverting input of the amplifier. Resistors R1
and R2 attenuate the potentiometer voltage, providing a ±2.5 mV
(with VS = ±15 V) adjustment range, referred to the input.
Figure 45 shows the offset adjustment for the noninverting
amplifier configuration, also providing a ±2.5 mV adjustment
range. As shown in the equations in Figure 45, if R4 is not much
greater than R2, a resulting closed-loop gain error must be
accounted for.
SETTLING TIME
The settling time is the time between when the input signal begins
to change and when the output permanently enters a prescribed
error band. The error bands on the output are 5 mV and 0.5 mV,
respectively, for 0.1% and 0.01% accuracy.
Figure 46 shows the settling time of the OP249, which is typically
870 ns. Moreover, problems in settling response, such as thermal
tails and long-term ringing, are nonexistent.
VERTICAL 50µV/DIV
INPUT VARIATION
870ns
100
90
00296-043
10
10mV
HORIZONTAL 5V/DIV
OUTPUT CHARGE
Figure 43. Open-Loop Gain Linearity; Variation in Open-Loop Gain Results in
Errors in High Closed-Loop Gain Circuits; RL = 600 Ω, VS = ±15 V
Rev. I | Page 14 of 18
500ns
Figure 46. Settling Characteristics of the OP249 to 0.01%
00296-046
0%
Data Sheet
OP249
DAC OUTPUT AMPLIFIER
Because the DAC output capacitance appears at the inputs of
the op amp, it is essential that the amplifier be adequately
compensated. Compensation increases the phase margin and
ensures an optimal overall settling response. The required lead
compensation is achieved with Capacitor C in Figure 48.
Unity-gain stability, a low offset voltage of 300 µV typical, and a
fast settling time of 870 ns to 0.01%, makes the OP249 an ideal
amplifier for fast DACs.
For CMOS DAC applications, the low offset voltage of the OP249
results in excellent linearity performance. CMOS DACs, such as
the PM7545, typically have a code-dependent output resistance
variation between 11 kΩ and 33 kΩ. The change in output
resistance, in conjunction with the 11 kΩ feedback resistor, results
in a noise gain change, which causes variations in the offset
error, increasing linearity errors. The OP249 features low offset
voltage error, minimizing this effect and maintaining 12-bit
linearity performance over the full-scale range of the converter.
VDD
75Ω
0.1µF
18
REFERENCE
OR VIN
500Ω
19
C
33pF
20
VDD
RFB
OUT1 1
VREF
2
+15V
0.1µF
8
1/2
PM7545
AGND 2
3
4
VOUT
1
OP249
0.1µF
DB11 TO DB0 DGND
3
00296-047
–15V
12
DATA INPUT
Figure 47. Fast Settling and Low Offset Error of the OP249 Enhances CMOS DAC Performance—Unipolar Operation
R4
20kΩ
1%
REFERENCE
OR VIN
500Ω
18
20
VDD
RFB
19 VREF
R5
10kΩ
1%
75Ω
0.1µF
C
+15V
33pF
0.1µF
OUT1 1
2
AGND 2
3
1/2
PM7545
R3
10kΩ
1%
8
OP249
DB11 TO DB0 DGND
1
5
1/2
OP249
6
4
3
12
–15V
DATA INPUT
7
VOUT
0.1µF
00296-048
VDD
Figure 48. Fast Settling and Low Offset Error of the OP249 Enhances CMOS DAC Performance—Bipolar Operation
Rev. I | Page 15 of 18
OP249
Data Sheet
A
B
4µs
4µs
100
90
100
90
10
0%
500mV
1µs
500mV
C = 5pF
RESPONSE IS GROSSLY UNDERDAMPED,
AND EXHIBITS RINGING
1µs
00296-049
10
0%
C = 15pF
FAST RISE TIME CHARACTERISTICS, BUT AT EXPENSE
OF SLIGHT PEAKING IN RESPONSE
Figure 49. Effect of Altering Compensation from Circuit in Figure 47—PM7545 CMOS DAC with 1/2 OP249, Unipolar Operation;
Critically Damped Response Is Obtained with C ≈ 33 pF
Figure 49 illustrates the effect of altering the compensation on
the output response of the circuit in Figure 47. Compensation is
required to address the combined effect of the output capacitance
of the DAC, the input capacitance of the op amp, and any stray
capacitance. Slight adjustments to the compensation capacitor may
be required to optimize settling response for any given application.
+15V
1/2
OP249
2
4
7A13 PLUG-IN
1
0.1µF
*
7A13 PLUG-IN
–15V
1kΩ
300pF
(t S DAC ) + (t S AMP )
ΔIOUT =
+15V
2
|VREF |
1kΩ
1.5kΩ
2N3904
1N4148
+15V
DISCUSSION ON DRIVING ADCs
2N2907
1.8kΩ
10µF
0.01µF
0.47µF
220Ω
0.1µF
*
VREF
00296-050
Settling characteristics of op amps also include the ability of the
amplifier to recover, that is, settle, from a transient current output
load condition. An example of this includes an op amp driving
the input from a SAR-type ADC. Although the comparison
point of the converter is usually diode clamped, the input swing
of plus-and-minus a diode drop still gives rise to a significant
modulation of input current. If the closed-loop output impedance
is low enough and bandwidth of the amplifier is sufficiently
large, the output settles before the converter makes a comparison
decision, which prevents linearity errors or missing codes.
1kΩ
+
The actual overall settling time is affected by the noise gain of
the amplifier, the applied compensation, and the equivalent
input capacitance at the input of the amplifier.
TTL INPUT
*DECOUPLE CLOSE TOGETHER ON GROUND
PLANE WITH SHORT LEAD LENGTHS.
Figure 50. Transient Output Impedance Test Fixture
As seen in Figure 51, the OP249 has an extremely fast recovery
of 247 ns (to 0.01%) for a 1 mA load transient. The performance
makes it an ideal amplifier for data acquisition systems.
Figure 50 shows a settling measurement circuit for evaluating
recovery from an output current transient. An output disturbing
current generator provides the transient change in output load
current of 1 mA.
247.4ns
100
90
10
0%
2mV
2V
100ns
Figure 51. Transient Recovery Time of the OP249 from
a 1 mA Load Transient to 0.01%
Rev. I | Page 16 of 18
00296-051
t S TOTAL =
8
3
The settling time of the combination of the current output DAC
and the op amp can be approximated by
2
0.1µF
Data Sheet
OP249
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
5
1
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
070606-A
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 52. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
1
5
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 53. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. I | Page 17 of 18
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
OP249
Data Sheet
0.005 (0.13)
MIN
8
0.055 (1.40)
MAX
5
0.310 (7.87)
0.220 (5.59)
1
4
0.100 (2.54) BSC
0.320 (8.13)
0.290 (7.37)
0.405 (10.29) MAX
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
SEATING
PLANE
15°
0°
0.015 (0.38)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 54. 8-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-8)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1
OP249AZ
OP249FZ
OP249GPZ
OP249GSZ
OP249GSZ-REEL
OP249GSZ-REEL7
1
Temperature Range
−55°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead CERDIP
8-Lead CERDIP
8-Lead PDIP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
The OP249GPZ, OP249GSZ, OP249GSZ-REEL, and OP249GSZ-REEL7 are RoHS compliant parts.
©1989–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00296-0-10/15(I)
Rev. I | Page 18 of 18
Package Option
Q-8
Q-8
N-8
R-8
R-8
R-8