FEATURES
PIN CONNECTIONS
Outstanding gain linearity
Ultrahigh gain, 5000 V/mV min
Low VOS over temperature, 55 μV max
TCVOS, 0.3 μV/°C max
High PSRR, 3 μV/V max
Low power consumption, 60 mW max
Available in die form
OP77
VOS TRIM 1
8
VOS TRIM
–IN 2
7
V+
+IN 3
6
OUT
5
NC
V– 4
TOP VIEW
(Not to Scale)
00320-001
Data Sheet
Next Generation OP07 Ultralow
Offset Voltage Operational Amplifier
OP77
NC = NO CONNECT
Figure 1. 8-Pin Hermetic
CERDIP_Q-8 (Z Suffix)
VOS TRIM
VOS TRIM
–IN
OP77
7
2
6
3
+IN
V+
8
1
OUT
5
4
NC
TOP VIEW
(Not to Scale)
NC = NO CONNECT
00320-002
4V– (CASE)
Figure 2. TO-99
(J Suffix)
GENERAL DESCRIPTION
The OP77 has outstanding gain of 10,000,000 or more that is
maintained over the full 10 V output range. This gain-linearity
eliminates incorrectable system nonlinearities common in
previous monolithic op amps and provides superior performance
in high closed-loop gain applications. Low initial VOS drift and
rapid stabilization time, combined with only 50 mW of power
consumption, are significant improvements over previous
designs. These characteristics, plus the TCVOS of 0.3 μV/°C
maximum and the low VOS of 25 μV maximum, eliminates
Rev. G
the need for VOS adjustment and increases system accuracy over
temperature.
A PSRR of 3 μV/V (110 dB) and CMRR of 1.0 μV/V maximum
virtually eliminate errors caused by power supply drifts and
common-mode signals. This combination of outstanding
characteristics makes the OP77 ideally suited for high resolution
instrumentation and other tight error budget systems.
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Technical Support
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OP77
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Thermal Resistance .......................................................................6 Pin Connections ............................................................................... 1 ESD Caution...................................................................................6 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................7 Revision History ............................................................................... 2 Test Circuits ..................................................................................... 10 Specifications..................................................................................... 3 Applications..................................................................................... 11 Electrical Specifications ............................................................... 3 Precision Current Sinks ............................................................. 12 Wafer Test Limits .......................................................................... 4 Outline Dimensions ....................................................................... 15 Typical Electrical Characteristics ............................................... 5 Ordering Guide .......................................................................... 16
Absolute Maximum Ratings............................................................ 6 REVISION HISTORY
10/15—Rev. F to Rev. G
Changes to Features Section and General Description Section..... 1
Changes to Note 1, Ordering Guide.................................................. 16
3/15—Rev. E to Rev. F
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 16
4/10—Rev. D to Rev. E
Removed Figure 33 and Two Subsequent Paragraphs ............... 12
6/09—Rev. C to Rev. D
Changes to Figure 1 and Figure 2 ................................................... 1
Changes to Table 1 ............................................................................ 3
Removed Endnote 1 and Endnote 2 in Table 3 ............................ 4
Changes to Figure 16 ........................................................................ 9
Changes to Figure 31 and Figure 32 ............................................. 12
Changes to Figure 38 ...................................................................... 14
Moved Figure 39 ............................................................................. 14
10/02—Rev. B to Rev. C
Edits to Specifications ...................................................................... 2
Figure 2 Caption Changed ............................................................ 10
Figure 3 Caption Changed ............................................................ 10
Edits to Figure 10 ............................................................................ 11
Updated Outline Dimensions ....................................................... 15
2/02—Rev. A to Rev. B
Remove 8-Lead SO PIN Connection Diagrams ........................... 1
Changes to Absolute Maximum Rating......................................... 2
Remove OP77B column from Specifications ................................ 2
Remove OP77B column from Electrical Characteristics ........ 3, 5
Remove OP77G column from Wafer Test Limits......................... 6
Remove OP77G column from Typical Electrical Characteristics .... 6
Rev. G | Page 2 of 16
Data Sheet
OP77
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
@ VS = ±15 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
INPUT OFFSET VOLTAGE
LONG-TERM STABILITY1
INPUT OFFSET CURRENT
INPUT BIAS CURRENT
INPUT NOISE VOLTAGE2
INPUT NOISE VOLTAGE DENSITY
Symbol
VOS
VOS/time
IOS
IB
enp-p
en
INPUT NOISE CURRENT2
INPUT NOISE CURRENT DENSITY
inp-p
in
INPUT RESISTANCE
Differential Mode3
Common Mode
INPUT VOLTAGE RANGE
COMMON-MODE REJECTION RATIO
POWER SUPPLY REJECTION RATIO
LARGE-SIGNAL VOLTAGE GAIN
RIN
RINCM
IVR
CMRR
PSRR
AVO
OUTPUT VOLTAGE SWING
VO
SLEW RATE2
CLOSED-LOOP BANDWIDTH2
OPEN-LOOP OUTPUT RESISTANCE
POWER CONSUMPTION
SR
BW
RO
Pd
OFFSET ADJUSTMENT RANGE
Conditions
Min
−0.2
0.1 Hz to 10 Hz
fO = 10 Hz
fO = 100 Hz2
fO = 1000 Hz
0.1 Hz to 10 Hz
fO = 10 Hz
fO = 100 Hz2
fO = 1000 Hz
26
±13
VCM = ±13 V
VS = ±3 V to ±18 V
RL ≥ 2 kΩ
VO = ±10 V
RL ≥ 10 kΩ
RL ≥ 2 kΩ
RL ≥ 1 kΩ
RL ≥ 2 kΩ
AVCL + 1
VS = ±15 V, no load
VS = ±3 V, no load
Rp = 20 kn
1
5000
±13.5
±12.5
±12.0
0.1
0.4
OP77E
Typ
10
0.3
0.3
+1.2
0.35
10.3
10.0
9.6
14
0.32
0.14
0.12
45
200
±14
0.1
0.7
12,000
±14.0
±13.0
±12.5
0.3
0.6
60
50
3.5
±3
Max
25
1.5
+2.0
0.6
18.0
13.0
11.0
30
0.80
0.23
0.17
Min
−0.2
18.5
±13
1.0
3.0
2000
±13.5
±12.5
±12.0
0.1
0.4
60
4.5
OP77F
Typ
20
0.4
0.3
+1.2
0.38
10.5
10.2
9.8
15
0.35
0.15
0.13
45
200
±14
0.1
0.7
6000
±14.0
±13.0
±12.5
0.3
0.6
60
50
3.5
±3
Max
60
2.8
+2.8
0.65
20.0
13.5
11.5
35
0.90
0.27
0.18
1.6
3.0
Unit
μV
μV/Mo
nA
nA
μVp-p
nV/√Hz
pAp-p
pA√Hz
MΩ
GΩ
V
μV/V
μV/V
V/mV
V
60
4.5
V/μs
MHz
Ω
mW
mV
Long-term input offset voltage stability refers to the averaged trend line of VOS vs. time over extended periods after the first 30 days of operation. Excluding the initial
hour of operation, changes in VOS during the first 30 operating days are typically 2.5 μV.
2
Sample tested.
3
Guaranteed by design.
Rev. G | Page 3 of 16
OP77
Data Sheet
@ VS = ±15 V, −25°C ≤ TA ≤ +85°C for OP77FJ and OP77E/OP77F, unless otherwise noted.
Table 2.
Parameter
INPUT OFFSET VOLTAGE
AVERAGE INPUT OFFSET VOLTAGE DRIFT1
INPUT OFFSET CURRENT
AVERAGE INPUT OFFSET CURRENT DRIFT2
INPUT BIAS CURRENT
AVERAGE INPUT BIAS CURRENT DRIFT2
INPUT VOLTAGE RANGE
COMMON-MODE REJECTION RATIO
POWER SUPPLY REJECTION RATIO
LARGE-SIGNAL VOLTAGE GAIN
Symbol
VOS
TCVOS
IOS
TCIOS
IB
TCIB
IVR
CMRR
PSRR
AVO
OUTPUT VOLTAGE SWING
POWER CONSUMPTION
VO
Pd
1
2
Conditions
VCM = ±13 V
VS = ±3 V to ±18 V
RL ≥ 2 kΩ
VO = ±10 V
RL ≥ 2 kΩ
VS = ±15 V, no load
OP77E
Typ
10
0.1
0.5
1.5
−0.2
+2.4
8
±13.0 ±13.5
0.1
1.0
2000
6000
Min
±12
±13.0
60
Max
45
0.3
2.2
4.0
+4.0
40
1.0
3.0
OP77F
Typ
20
0.2
0.5
1.5
−0.2
+2.4
15
±13.0 ±13.5
0.1
1.0
1000
4000
Min
±12
75
±13.0
60
Max
100
0.6
4.5
85
+6.0
60
3.0
5.0
75
Unit
µV
µV/°C
nA
pA/°C
nA
pA/°C
V
pV/V
µV/V
V/mV
V
mW
OP77E: TCVOS is 100% tested on J and Z packages.
Guaranteed by end-point limits.
WAFER TEST LIMITS
@ VS = ±15 V, TA = 25°C, for OP77NBC devices, unless otherwise noted.
Table 3.
Parameter
INPUT OFFSET VOLTAGE
INPUT OFFSET CURRENT
INPUT BIAS CURRENT
INPUT RESISTANCE
Differential Mode
INPUT VOLTAGE RANGE
COMMON-MODE REJECTION RATIO
POWER SUPPLY REJECTION RATIO
OUTPUT VOLTAGE SWING
Symbol
VOS
IOS
IB
LARGE-SIGNAL VOLTAGE GAIN
AVO
DIFFERENTIAL INPUT VOLTAGE
POWER CONSUMPTION
Pd
RIN
IVR
CMRR
PSRR
VO
Conditions
VCM = ±13 V
VS = ±3 V to ±18 V
RL = 10 kΩ
RL = 2 kΩ
RL = 1 kΩ
RL = 2 kΩ
VO = ±10 V
VO = 0 V
Rev. G | Page 4 of 16
OP77NBC Limit
40
2.0
±2
Unit
µV max
nA max
nA max
26
±13
1
3
±13.5
±12.5
±12.0
2000
MΩ min
V min
µV/V max
µV/V max
V min
±30
60
V max
mW max
V/mV min
Data Sheet
OP77
TYPICAL ELECTRICAL CHARACTERISTICS
@ VS = ±15 V, TA = 25°C, unless otherwise noted.
Table 4.
Parameter
AVERAGE INPUT OFFSET VOLTAGE DRIFT
NULLED INPUT OFFSET VOLTAGE DRIFT
AVERAGE INPUT OFFSET CURRENT DRIFT
SLEW RATE
BANDWIDTH
Symbol
TCVOS
TCVOSn
TCIOS
SR
BW
Conditions
RS = 50 Ω
RS = 50 Ω, RP = 20 kΩ
RL ≥ 2 kΩ
AVCL + 1
Rev. G | Page 5 of 16
OP77NBC Limit
0.1
0.1
0.5
0.3
0.6
Unit
µV/°C
µV/°C
pA/°C
V/µs
MHz
OP77
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Supply Voltage
Differential Input Voltage
Input Voltage2
Output Short-Circuit Duration
Storage Temperature Range
Operating Temperature Range
Junction Temperature (TJ)
Lead Temperature (Soldering, 60 sec)
1
Rating
±22 V
±30 V
±22 V
Indefinite
−65°C to +150°C
−25°C to +85°C
−65°C to +150°C
300°C
Absolute Maximum Ratings apply to both dice and packaged parts, unless
otherwise noted.
2
For supply voltages less than ±22 V, the absolute maximum input voltage is
equal to the supply voltage.
1
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Table 6.
Package Type
8-Pin TO-99 H-08 (J Suffix)
8-Lead Hermetic CERDIP Q-8 (Z Suffix)
1
θJA1
150
148
θJC
18
16
Unit
°C/W
°C/W
θJA is specified for worst-case mounting conditions, i.e., θJA is specified for a
device in socket for the TO-99 and CERDIP packages.
ESD CAUTION
Rev. G | Page 6 of 16
Data Sheet
OP77
TYPICAL PERFORMANCE CHARACTERISTICS
30
VS = ±15V
TA = 25°C
RL = 10kΩ
CHANGE IN OFFSET VOLTAGE (µV)
INPUT VOLTAGE (µV)
(NULLED TO 0µV @ VOUT = 0V)
2
1
0
–1
J, Z PACKAGES
+0.3µV/°C
20
S.D.
10
MEAN
0
–10
–20
–5
0
OUTPUT VOLTAGE (V)
5
10
–30
–55
00320-004
–2
–10
Figure 3. Gain Linearity (Input Voltage vs. Output Voltage)
–15
5
25
45
65
TEMPERATURE (°C)
85
105
125
Figure 6. Untrimmed Offset Voltage vs. Temperature
25
4
20
15
10
5
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
125
2
1
0
–1
–2
–3
–4
00320-005
0
–55
VS = ±15V
TA = 25°C
3
0
0.5
1.0
1.5
2.0
2.5
3.0
TIME AFTER POWER SUPPLY TURN-ON (Minutes)
Figure 4. Open-Loop Gain vs. Temperature
3.5
00320-008
CHANGE IN INPUT OFFSET VOLTAGE (µV)
VS = ±15V
OPEN-LOOP GAIN (V/µV)
–35
00320-007
–0.3µV/°C
Figure 7. Warm-Up Drift
16
30
TA = 25°C
RL = 2kΩ
VS = ±15V
ABSOLUTE CHANGE IN INPUT
OFFSET VOLTAGE (µV)
12
8
4
DEVICE IMMERSED IN
70°C OIL BATH (20 UNITS)
20
15
MAXIMUM
10
AVERAGE
5
0
±5
±10
±15
POWER SUPPLY VOLTAGE (V)
±20
0
–10
Figure 5. Open-Loop Gain vs. Power Supply Voltage
0
10
20
30
40
TIME (Seconds)
50
60
Figure 8. Offset Voltage Change Due to Thermal Shock
Rev. G | Page 7 of 16
70
00320-009
MIMIMUM
0
00320-006
OPEN-LOOP GAIN (V/µV)
25
OP77
Data Sheet
130
100
VS = ±15V
TA = 25°C
TA = 25°C
120
110
60
PSRR (dB)
40
100
90
20
80
0
70
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
60
0.1
00320-010
–20
10
1
Figure 9. Closed-Loop Response for Various Gain Configurations
160
10k
4
0
120
45
100
80
90
60
40
135
INPUT BIAS CURRENT (nA)
VS = ±15V
PHASE (Degrees)
OPEN-LOOP GAIN (dB)
1k
Figure 12. PSRR vs. Frequency
VS = ±15V
TA = 25°C
140
10
100
FREQUENCY (Hz)
00320-013
CLOSED-LOOP GAIN (dB)
80
3
2
1
0.1
1
10
100
1k
FREQUENCY (Hz)
10k
100k
180
1M
0
–75
00320-011
0
0.01
Figure 10. Open-Loop Gain/Phase Response
–50
–25
25
50
0
TEMPERATURE (°C)
75
100
125
00320-014
20
Figure 13. Input Bias Current vs. Temperature
2.0
150
TA = 25°C
VS = ±15V
INPUT OFFSET CURRENT (nA)
140
120
110
100
1.5
1.0
0.5
80
1
10
100
1k
FREQUENCY (Hz)
10k
100k
0
–75
Figure 11. CMRR vs. Frequency
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
Figure 14. Input Offset Current vs. Temperature
Rev. G | Page 8 of 16
125
00320-015
90
00320-012
CMMR (dB)
130
Data Sheet
OP77
10
100
POWER CONSUMPTION (mW)
TA = 25°C
1
1k
10k
100k
FREQUENCY (Hz)
10
1
0
Figure 15. Input Wideband Noise vs. Bandwidth (0.1 Hz to Frequency
Indicated)
20
RS1 = RS2 = 200kΩ
THERMAL NOISE OF SOURCE
VS = ±15V
TA = 25°C
VIN = ±10mV
RESISTORS
INCLUDED
POSITIVE SWING
15
EXCLUDED
100
RS = 0
10
40
Figure 18. Power Consumption vs. Power Supply
MAXIMUM OUTPUT (V)
INPUT NOISE VOLTAGE (nV/ Hz)
1k
10
20
30
TOTAL SUPPLY VOLTAGE V+ TO V– (V)
00320-019
0.1
100
00320-016
RMS NOISE (mV)
VS = ±15V
TA = 25°C
NEGATIVE SWING
10
5
10
100
1k
FREQUENCY (Hz)
0
100
40
32
OUTPUT SHORT-CIRCUIT CURRENT (mA)
VS = ±15V
TA = 25°C
28
24
20
16
12
8
4
10k
100k
FREQUENCY (Hz)
1M
VS = ±15V
TA = 25°C
35
30
25
20
15
00320-018
PEAK-TO-PEAK AMPLITUDE (V)
10k
Figure 19. Maximum Output Voltage vs. Load Resistance
Figure 16. Total Input Noise Voltage vs. Frequency
0
1k
1k
LOAD RESISTANCE TO GROUND (Ω)
0
1
2
3
TIME FROM OUTPUT BEING SHORTENED (Minutes)
Figure 20. Output Short-Circuit Current vs. Time
Figure 17. Maximum Output Swing vs. Frequency
Rev. G | Page 9 of 16
4
00320-021
1
00320-017
1
00320-020
VS = ±15V
TA = 25°C
OP77
Data Sheet
TEST CIRCUITS
200kΩ
TYPICAL PRECISION
OP AMP
50Ω
10kΩ
VO
VO
VOS =
4000
VIN = ±10V
00320-022
OP77
3.3kΩ
6
V–
INPUT REFERRED NOISE =
VO
25,000
Figure 22. Typical Low-Frequency Noise Test Circuit
20kΩ
VY
8
7 6
OP77
3
+
V+
Actual open-loop voltage gain can vary greatly at various output
voltages. All automated testers use endpoint testing and therefore
only show the average gain. This causes errors in high closedloop gain circuits. Because this is difficult for manufacturers to
test, users should make their own evaluations. This simple test
circuit makes it easy. An ideal op amp would show a horizontal
scope trace.
1
2
INPUT
+10V
Figure 25. Open-Loop Gain Linearity
OUTPUT
4.7µF
(≈10Hz FILTER)
4
–
0V
00320-026
7
OP77
00320-023
3
RL
–10V
NOTES
1. GAIN NOT CONSISTANT. CAUSES NONLINEAR ERRORS.
2. AVO SPEC IS ONLY PART OF THE SOLUTION.
3. CHECK SPECIFICATION TABLE 1 AND TABLE 2 FOR PERFORMANCE.
V+
100Ω
VX
VX
AVO 650V/mV
RL = 2kΩ
2.5MΩ
2
VY
1MΩ
10Ω
Figure 21. Typical Offset Voltage Test Circuit
100Ω
100kΩ
OUTPUT
00320-024
4
V–
Figure 23. Optional Offset Nulling Circuit
–10V
0V
+10V
VX
00320-027
100kΩ
+18V
+
10µF
10Ω
2
7
3
10kΩ
*
+
This is the output gain linearity trace for the new OP77. The
output trace is virtually horizontal at all points, assuring
extremely high gain accuracy. The average open-loop gain is
truly impressive—approximately 10,000,000.
0.1µF
OP77
10kΩ
Figure 26. Output Gain Linearity Trace
6
4
10Ω
0.1µF
10µF
–18V
NOTES
*1 PER BOARD
00320-025
*
Figure 24. Burn-In Circuit
Rev. G | Page 10 of 16
Data Sheet
OP77
APPLICATIONS
R3
1kΩ
R2
1MΩ
0.1µF
2
3
R1
100kΩ
3
7
OP77E
6
OP77
R2
100kΩ
4
0.1µF
R3
1kΩ
2
6
R5
10Ω
R4
990Ω
Figure 29. Basic Current Source
00320-028
R4
1MΩ
–15V
R3
+15V
Figure 27. Precision High-Gain Differential Amplifier
The high gain, gain linearity, CMRR, and low TCVOS of the
OP77 make it possible to obtain performance not previously
available in single-stage, very high-gain amplifier applications.
VIN
R1
R2
2
3
2N2222
OP77
6
2N2907
R5
For best CMR, R1 must equal R3 . In this example, with a
R2
R4
IOUT = VIN
Type
Common-Mode Voltage
Gain Linearity, Worst Case
TCVOS
TCIOS
GIVEN R3 = R4 + R5, R1 = R2
These current sources can supply both positive and negative
current into a grounded load.
Amount
0.01%/V
0.02%
0.003%/°C
0.008%/°C
Note that
R4
R5
+ 1
2
R


ZO =
R5 + R 4 R3
RF
10µF
R2
R1
+15V
And that for ZO to be infinite
0.1µF
3
7
OP77
6
4
0.1µF
100Ω
OUTPUT
CLOAD
–15V
00320-029
2
IOUT < 100mA
( R1R3– R5)
Figure 30. 100 mA Current Source
Table 7. Maximum Errors
RS
–15V
R4
10 mV differential signal, the maximum errors are as listed in
Table 7.
INPUT
IOUT < 15mA
00320-031
R1
1kΩ
VIN
00320-030
+15V
Figure 28. Isolating Large Capacitive Loads
This circuit reduces maximum slew rate but allows driving
capacitive loads of any size without instability. Because the boon
resistor is inside the feedback loop, its effect on output
impedance is reduced to insignificance by the high open-loop
gain of the OP77.
Rev. G | Page 11 of 16
R5 + R 4
R2
must = R3
R1
OP77
Data Sheet
PRECISION CURRENT SINKS
R1
V+
OP77
RL
200Ω
IRF520
R1
1Ω
1W
IO
RL
00320-032
V–
Figure 32. Positive Current Source
The simple high-current sinks, shown Figure 31 and Figure 32,
require the load to float between the power supply and the sink.
Figure 31. Positive Current Sink
In these circuits, the high gain, high CMRR, and low TCVOS of
the OP77 ensure high accuracy.
The high gain and low TCVOS ensure accurate operation with
inputs from microvolts to volts. In Figure 33, the signal always
appears as a common-mode signal to the op amps. The
OP77EZ CMRR of 1 µV/V ensures errors of less than 2 ppm.
1kΩ
1kΩ
+15V
+15V
0.1µF
C1
30pF
0.1µF
2
3
VIN
D1
1N4148
7
2
D2
3
6
OP77E
7
OP77E
VOUT
0 < VOUT < 10V
4
0.1µF
2N4393
4
0.1µF
6
R3
2kΩ
00320-035
OP77
VIN
R1
VIN > 0V
IO =
–15V
–15V
Figure 33. Precision Absolute Value Amplifier
15V
+
2
2
2
10µF
REF-01
VO
4
REF-01
REF-01
6
VO
4
6
VO
6
4
100Ω
OP77
VOUT
100Ω
100Ω
0.1µF
Figure 34. Low Noise Precision Reference
Rev. G | Page 12 of 16
00320-036
VIN
IRF520
VIN
VIN
IO =
R1
VIN > 0V
FULL SCALE OF 1V.
IO = 1A/V
00320-033
IO
200Ω
Data Sheet
OP77
In Figure 35, CH must be of polystyrene, Teflon*, or
polyethylene to minimize dielectric absorption and leakage.
The droop rate is determined by the size of CH and the bias
current of the AD820.
Figure 34 relies upon low TCVOS of the OP77 and noise
combined with very high CMRR to provide precision buffering
of the averaged REF-01 voltage outputs.
*Teflon is a registered trademark of the Dupont Company
1kΩ
+15V
+15V
1N4148
0.1µF
VIN
1kΩ 3
7
OP77
2
6
2N930
4
0.1µF
1kΩ 3
7
AD820
6
VOUT
4
0.1µF
CH
RESET
–15V
–15V
Figure 35. Precision Positive Peak Detector
Rev. G | Page 13 of 16
00320-037
2
0.1µF
OP77
Data Sheet
+15V
CC
0.1µF
RF
100kΩ
0.1µF
VIN
VO
RS
1kΩ
2
R1
2kΩ
3
7
OP77
6
D1
1N4148
TRIM
4
0.1µF
–15V
6
Ra
5
50kΩ
REF-02
VOUT
1.5kΩ
3
TEMP
GND
4
00320-038
VTH
2
VIN
Rc
Rb1
VOUT
OP77
0.1µF
Rbp
00320-039
+15V
–15V
Figure 36. Precision Threshold Detector/Amplifier
Figure 37. Precision Temperature Sensor
When VIN < VTH, amplifier output swings negative, reversing the
biasing diode D1. VO = VTH if RL= ∞ when VIN > VTH, the loop
closes,
Table 8. Resistor Values
TCVOUT Slope (S)
Temperature Range

R 
VO = VTH + (VIN − VTH )1 + F 
RS 

Output Voltage
Range
Zero-Scale
Ra (±1% Resistor)
Rb1 (±1% Resistor)
Rbp (Potentiometer)
Rc (±1% Resistor)
CC is selected to smooth the response of the loop.
10 mV/°C
−55°C to
+125°C
−0.55 V to
+1.25 V
0 V @ 0°C
9.09 kΩ
1.5 kΩ
200 Ω
5.11 kΩ
100 mV/°C
−55°C to
+125°C
−5.5 V to
+12.5V
0 V @ 0°C
15 kΩ
1.82 kΩ
500 Ω
84.5 kΩ
10 mV/°F
−67°F to
+257°C
−0.67 V to
+2.57V
0 V @ 0°F
7.5 kΩ
1.21 kΩ
200 Ω
8.25 kΩ
7
V+
(OPTIONAL
NULL)
R2B1
1
R1B
R1A
8
R7
C1
Q19
Q10
Q9
Q3 Q6
Q5
NONINVERTING 3
INPUT
INVERTING
INPUT
2
Q11 Q12
Q8
Q7
Q27
R3
Q26
Q1
R4
Q21
Q22
Q23
Q24
Q2
C3
Q17
C2
6
R10
Q16
R5
Q20
Q15
Q25
Q18
Q14
Q13
4
V–
1R2A AND
R9
OUTPUT
Q4
R2B ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY.
Figure 38. Simplified Schematic
Rev. G | Page 14 of 16
R6
R8
00320-003
R2A1
Data Sheet
OP77
OUTLINE DIMENSIONS
0.005 (0.13)
MIN
8
0.055 (1.40)
MAX
5
0.310 (7.87)
0.220 (5.59)
1
4
0.100 (2.54) BSC
0.320 (8.13)
0.290 (7.37)
0.405 (10.29) MAX
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
SEATING
PLANE
0.015 (0.38)
0.008 (0.20)
15°
0°
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 39. 8-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-8)
Dimensions shown in inches and (millimeters)
REFERENCE PLANE
0.50 (12.70)
MIN
0.185 (4.70)
0.165 (4.19)
0.100 (2.54)
BSC
0.250 (6.35) MIN
0.050 (1.27) MAX
0.160 (4.06)
0.140 (3.56)
5
0.370 (9.40)
0.335 (8.51)
0.021 (0.53)
0.016 (0.40)
6
4
0.200 (5.08)
BSC
0.335 (8.51)
0.305 (7.75)
7
3
2
SIDE VIEW
0.040 (1.02) MAX
8
1
0.100 (2.54)
BSC
0.019 (0.48)
0.016 (0.41)
0.045 (1.14)
0.027 (0.69)
0.034 (0.86)
0.028 (0.71)
BOTTOM VIEW
45° BSC
0.040 (1.02)
0.010 (0.25)
COMPLIANT TO JEDEC STANDARDS MO-002-AK
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 40. 8-Pin Metal Header [TO-99]
(H-08)
Dimensions shown in inches and (millimeters)
Rev. G | Page 15 of 16
01-15-2015-B
BASE & SEATING PLANE
OP77
Data Sheet
ORDERING GUIDE
Model1
OP77FJZ
OP77EZ
OP77FZ
OP77NBC
1
Temperature Range
−25°C to +85°C
−25°C to +85°C
−25°C to +85°C
Package Description
8-Pin Metal Header [TO-99]
8-Lead Ceramic Dual In-Line Package [CERDIP]
8-Lead Ceramic Dual In-Line Package [CERDIP]
Die
The OP77FJZ is a RoHS compliant part.
©2002–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00320-0-10/15(G)
Rev. G | Page 16 of 16
Package Option
H-08 (J Suffix)
Q-8 (Z Suffix)
Q-8 (Z Suffix)