Low Distortion, High Speed
Rail-to-Rail Input/Output Amplifiers
AD8027/AD8028
Data Sheet
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GENERAL DESCRIPTION
The AD8027/AD80281 are high speed amplifiers with rail-to-rail
input and output that operate on low supply voltages and are
optimized for high performance and a wide dynamic signal range.
The AD8027/AD8028 have low noise (4.3 nV/√Hz, 1.6 pA/√Hz)
and low distortion (120 dBc at 1 MHz). In applications that use a
fraction of or use the entire input dynamic range and require
low distortion, the AD8027/AD8028 are ideal choices.
Many rail-to-rail input amplifiers have an input stage that switches
from one differential pair to another as the input signal crosses
a threshold voltage, which causes distortion. The AD8027/AD8028
have a unique feature that allows the user to select the input
crossover threshold voltage through the DISABLE/SELECT pin
(DISABLE/SELECT x in the 10-lead MSOP, hereafter referred
to as DISABLE/SELECT throughout this data sheet). This feature
controls the voltage at which the complementary transistor
input pairs switch. The AD8027/AD8028 also have intrinsically
low crossover distortion.
1
Protected by U.S. patent numbers 6,486,737B1; 6,518,842B1.
Rev. D
AD8027
8
DISABLE/SELECT
–IN 2
7
+VS
+IN 3
6
VOUT
–VS 4
5
DNC
DNC = DO NOT CONNECT. DO NOT
CONNECT TO THIS PIN.
Figure 1. 8-Lead SOIC, AD8027
See the Pin Configurations and Function Descriptions section
for additional pin configurations and information about the pin
functions.
With their wide supply voltage range (2.7 V to 12 V) and wide
bandwidth (190 MHz), the AD8027/AD8028 amplifiers are
designed to work in a variety of applications where speed and
performance are needed on low supply voltages. The high performance of the AD8027/AD8028 is achieved with a quiescent
current of only 6.5 mA (typical) per amplifier. The AD8027/
AD8028 have a shutdown mode that is controlled via
the DISABLE/SELECT pin.
The AD8027/AD8028 are available in 8-lead SOIC, 6-lead SOT-23,
and 10-lead MSOP packages. The AD8028WARMZ-R7 is an
automotive grade version, qualified for automotive applications.
See the Automotive Products section for more details. The
AD8027/AD8028 family is designed to work over the extended
temperature range of −40°C to +125°C.
–20
G = +1
FREQUENCY = 100kHz
RL = 1kΩ
–40
–60
VS = +5V
VS = +3V
VS = ±5V
–80
–100
–120
–140
0
1
2
3
4
5
6
7
OUTPUT VOLTAGE (V p-p)
8
9
10
03327-063
APPLICATIONS
DNC 1
SFDR (dB)
High speed
190 MHz, −3 dB bandwidth (G = +1)
100 V/µs slew rate
Low distortion
120 dBc at 1 MHz SFDR
80 dBc at 5 MHz SFDR
Selectable input crossover threshold
Low noise
4.3 nV/√Hz
1.6 pA/√Hz
Low offset voltage: 900 µV maximum
Low power: 6.5 mA per amplifier supply current
Power-down mode
No phase reversal: VIN > |VS| + 200 mV
Wide supply range: 2.7 V to 12 V
Small packaging: 8-lead SOIC, 6-lead SOT-23, 10-lead MSOP
Qualified for automotive applications (AD8028WARMZ-R7 only)
03327-101
FEATURES
Figure 2. SFDR vs. Output Voltage
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AD8027/AD8028
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Crossover Selection .................................................................... 20
Applications ....................................................................................... 1
Output Stage................................................................................ 21
General Description ......................................................................... 1
DC Errors .................................................................................... 21
Pin Connection Diagram ................................................................ 1
Wideband Operation ..................................................................... 22
Revision History ............................................................................... 2
Circuit Considerations .............................................................. 22
Specifications..................................................................................... 3
Applications Information .............................................................. 24
Absolute Maximum Ratings ............................................................ 7
Using the DISABLE/SELECT Pin ............................................ 24
Maximum Power Dissipation ..................................................... 7
Driving a 16-Bit ADC ................................................................ 24
ESD Caution .................................................................................. 7
Band-Pass Filter .......................................................................... 25
Pin Configuration and Function Descriptions ............................. 8
Design Tools and Technical Support ....................................... 25
Typical Performance Characteristics ........................................... 10
Outline Dimensions ....................................................................... 26
Test Circuit ...................................................................................... 19
Ordering Guide .......................................................................... 27
Theory of Operation ...................................................................... 20
Automotive Products ................................................................. 27
Input Stage ................................................................................... 20
REVISION HISTORY
7/15—Rev. C to Rev. D
Changed SELECT to DISABLE/SELECT, NC to DNC, VS+ to
+VS, and VS− to −VS ....................................................... Throughout
Changes to Features Section, Figure 1, and General Description
Section ................................................................................................ 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Table 3 ............................................................................ 5
Added Pin Configurations and Function Descriptions Section 8
Added Figure 4, Figure 5, Table 5, and Table 6; Renumbered
Sequentially ....................................................................................... 8
Added Figure 6, Figure 7, Table 7, and Table 8............................. 9
Changes to Figure 10 Caption and Figure 13 Caption .............. 10
Changes to Figure 16 Caption and Figure 19 Caption .............. 11
Changes to Figure 20 Caption and Figure 21 ............................. 12
Changes to Figure 26 Caption....................................................... 13
Changes to Figure 36 and Figure 37............................................. 14
Changes to Figure 42 ...................................................................... 15
Changes to Figure 50 Caption....................................................... 17
Added Test Circuit Section and Figure 59 .................................. 19
Changes to Theory of Operation Section .................................... 20
Changes to Crossover Selection Section and Figure 61 ............ 21
Changes to Wideband Operation Section, Figure 62, Figure 63,
and Figure 64 ................................................................................... 22
Changes to PCB Layout Section ................................................... 23
Changes to Using the DISABLE/SELECT Pin Section and
Table 6 .............................................................................................. 24
Changes to Figure 67 and Design Tools and Technical Support
Section .............................................................................................. 25
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 27
Added Automotive Products Section .......................................... 27
3/05—Rev. B to Rev. C
Updated Format .................................................................. Universal
Change to Figure 1 ............................................................................1
10/03—Rev. A to Rev. B
Changes to Figure 1 ...........................................................................1
8/03—Rev. 0 to Rev. A
Addition of AD8028 ........................................................... Universal
Changes to General Description .....................................................1
Changes to Figure 1, Figure 3, Figure 4, Figure 8, Figure 13,
Figure 15, Figure 17.......................................................... 1, 6, 7, 8, 9
Changes to Figure 58, Figure 60 ............................................. 18, 20
Changes to Specifications .................................................................3
Updated Outline Dimensions ....................................................... 22
Updated Ordering Guide .............................................................. 23
3/03—Revision 0: Initial Version
Rev. D | Page 2 of 27
Data Sheet
AD8027/AD8028
SPECIFICATIONS
VS = ±5 V at TA = 25°C, RL = 1 kΩ to midsupply, G = +1, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Spurious-Free Dynamic Range
(SFDR)
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
Crosstalk, Output to Output
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current1
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Impedance
Input Capacitance
Input Common-Mode Voltage
Range
Common-Mode Rejection Ratio
DISABLE/SELECT PIN
Selection Input Voltage
Crossover Low
Crossover High2
Disable Input Voltage
Disable Switching Speed
Enable Switching Speed
Test Conditions/Comments
Min
Typ
G = +1, VOUT = 0.2 V p-p
AD8028W only: TMIN to TMAX
G = +1, VOUT = 2 V p-p
AD8028W only: TMIN to TMAX
G = +2, VOUT = 0.2 V p-p
G = +1, VOUT = 2 V step
G = −1, VOUT = 2 V step
G = +2, VOUT = 2 V step
138
138
20
20
190
Max
Unit
16
90
100
35
MHz
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
fC = 1 MHz, VOUT = 2 V p-p, RF = 24.9 Ω
120
dBc
fC = 5 MHz, VOUT = 2 V p-p, RF = 24.9 Ω
f = 100 kHz
f = 100 kHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
G = +1, RL = 100 Ω, VOUT = 2 V p-p, VS = ±5 V at 1 MHz
80
4.3
1.6
0.1
0.2
−93
dBc
nV/√Hz
pA/√Hz
%
Degrees
dB
DISABLE/SELECT = tristate or open, PNP active
AD8028W only: TMIN to TMAX
DISABLE/SELECT = high, NPN active
AD8028W only: TMIN to TMAX
TMIN to TMAX
VCM = 0 V, NPN active
TMIN to TMAX
AD8028W only: TMIN to TMAX
VCM = 0 V, PNP active
TMIN to TMAX
AD8028W only: TMIN to TMAX
AD8028W only: TMIN to TMAX
VOUT = ±2.5 V, AD8028W only: TMIN to TMAX
200
240
1.50
4
4
−8
−8
100
VCM = ±2.5 V
AD8028W only: TMIN to TMAX
90
88
TMIN to TMAX
Tristate < ±20 µA, TMIN to TMAX
TMIN to TMAX
50% of input to <10% of final VOUT
−3.0
Rev. D | Page 3 of 27
32
±0.1
110
800
850
900
900
6
6
−11
−11
±0.9
µV
µV
µV
µV
µV/°C
µA
µA
µA
µA
µA
µA
µA
dB
6
2
−5.2 to +5.2
MΩ
pF
V
110
dB
dB
−3.9 to −3.7
−4.6
980
45
V
V
V
ns
ns
AD8027/AD8028
Parameter
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
(Rising/Falling Edge)
Output Voltage Swing
Short-Circuit Output
Off Isolation
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Quiescent Current (Disabled)
Power Supply Rejection Ratio
1
2
Data Sheet
Test Conditions/Comments
Min
Typ
VIN = +6 V to −6 V, G = −1
AD8028W only: TMIN to TMAX
Sinking and sourcing
VIN = 0.2 V p-p, f = 1 MHz, DISABLE/SELECT = low
30% overshoot
−4.9 to +4.9
ns
−4.94 to +4.94
120
−49
20
V
mA
dB
pF
6.5
370
90
Unit
40/45
2.7
AD8028W only: TMIN to TMAX
DISABLE/SELECT = low
AD8028W only: TMIN to TMAX
VS ± 1 V, AD8028W only: TMIN to TMAX
Max
12
8.5
9.5
500
500
110
V
mA
mA
µA
µA
dB
No sign or a plus sign indicates current into the pin; a minus sign indicates current out of the pin.
It is recommended to float the DISABLE/SELECT pin for crossover high mode.
VS = 5 V at TA = 25°C, RL = 1 kΩ to midsupply, G = +1, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Spurious-Free Dynamic Range (SFDR)
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
Crosstalk, Output to Output
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current1
Input Offset Current
Open-Loop Gain
Test Conditions/Comments
Min
Typ
Max Unit
G = +1, VOUT = 0.2 V p-p
AD8028W only: TMIN to TMAX
G = +1, VOUT = 2 V p-p
AD8028W only: TMIN to TMAX
G = +2, VOUT = 0.2 V p-p
G = +1, VOUT = 2 V step
G = −1, VOUT = 2 V step
G = +2, VOUT = 2 V step
131
131
18
18
185
12
85
100
40
MHz
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
fC = 1 MHz, VOUT = 2 V p-p, RF = 24.9 Ω
fC = 5 MHz, VOUT = 2 V p-p, RF = 24.9 Ω
f = 100 kHz
f = 100 kHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
G = +1, RL = 100 Ω, VOUT = 2 V p-p,
VS = ±5 V at 1 MHz
90
64
4.3
1.6
0.1
0.2
−92
dBc
dBc
nV/√Hz
pA/√Hz
%
Degrees
dB
DISABLE/SELECT = tristate or open, PNP active
AD8028W only: TMIN to TMAX
DISABLE/SELECT = high NPN active
AD8028W only: TMIN to TMAX
TMIN to TMAX
VCM = 2.5 V, NPN active
TMIN to TMAX
AD8028W only: TMIN to TMAX
VCM = 2.5 V, PNP active
TMIN to TMAX
AD8028W only: TMIN to TMAX
AD8028W only: TMIN to TMAX
VOUT = 1 V to 4 V, AD8028W only: TMIN to TMAX
200
Rev. D | Page 4 of 27
28
240
2
4
4
−8
−8
96
±0.1
105
800
850
900
900
µV
µV
µV
µV
µV/°C
6
µA
µA
6
µA
−11 µA
µA
−11 µA
±0.9 µA
dB
Data Sheet
Parameter
INPUT CHARACTERISTICS
Input Impedance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
DISABLE/SELECT PIN
Selection Input Voltage
Crossover Low
Crossover High2
Disable Input Voltage
Disable Switching Speed
Enable Switching Speed
OUTPUT CHARACTERISTICS
Overdrive Recovery Time
(Rising/Falling Edge)
Output Voltage Swing
Off Isolation
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Quiescent Current (Disabled)
Power Supply Rejection Ratio
1
2
AD8027/AD8028
Test Conditions/Comments
Min
VCM = 0 V to 2.5 V
AD8028W only: TMIN to TMAX
90
84
TMIN to TMAX
Tristate < ±20 µA, TMIN to TMAX
TMIN to TMAX
50% of input to <10% of final VOUT
2.0
6
2
−0.2 to +5.2
105
MΩ
pF
V
dB
dB
1100
50
V
V
V
ns
ns
50/50
ns
0.04 to 4.96
−49
105
20
V
dB
mA
pF
0.4
0.08 to 4.92
2.7
6
AD8028W only: TMIN to TMAX
DISABLE/SELECT = low
AD8028W only: TMIN to TMAX
VS ± 1 V, AD8028W only: TMIN to TMAX
Max Unit
1.1 to 1.3
VIN = −6 V to +1 V, G = −1
AD8028W only: TMIN to TMAX
VIN = 0.2 V p-p, f = 1 MHz, DISABLE/SELECT = low
Sinking and sourcing
30% overshoot
Typ
320
90
105
Test Conditions/Comments
Min
Typ
G = +1, VOUT = 0.2 V p-p
AD8028W only: TMIN to TMAX
G = +1, VOUT = 2 V p-p
AD8028W only: TMIN to TMAX
G = +2, VOUT = 0.2 V p-p
G = +1, VOUT = 2 V step
G = −1, VOUT = 2 V step
G = +2, VOUT = 2 V step
125
125
19
19
180
12
8.5
9
450
450
V
mA
mA
µA
µA
dB
Max
Unit
No sign or a plus sign indicates current into the pin; a minus sign indicates current out of the pin.
It is recommended to float the DISABLE/SELECT pin for crossover high mode.
VS = 3 V at TA = 25°C, RL = 1 kΩ to midsupply, G = +1, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Spurious-Free Dynamic Range (SFDR)
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
Crosstalk, Output to Output
fC = 1 MHz, VOUT = 2 V p-p, RF = 24.9 Ω
fC = 5 MHz, VOUT = 2 V p-p, RF = 24.9 Ω
f = 100 kHz
f = 100 kHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
G = +1, RL = 100 Ω, VOUT = 2 V p-p, VS = 3 V at
1 MHz
Rev. D | Page 5 of 27
10
73
100
48
MHz
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
85
64
4.3
1.6
0.15
0.20
−89
dBc
dBc
nV/√Hz
pA/√Hz
%
Degrees
dB
29
AD8027/AD8028
Parameter
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current1
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Impedance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
DISABLE/SELECT PIN
Selection Input Voltage
Crossover Low
Crossover High2
Disable Input Voltage
Disable Switching Speed
Enable Switching Speed
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
(Rising/Falling Edge)
Output Voltage Swing
Short-Circuit Current
Off Isolation
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Quiescent Current (Disabled)
Power Supply Rejection Ratio
1
2
Data Sheet
Test Conditions/Comments
DISABLE/SELECT = tristate or open, PNP active
AD8028W only: TMIN to TMAX
DISABLE/SELECT = high NPN active
AD8028W only: TMIN to TMAX
TMIN to TMAX
VCM = 1.5 V, NPN active
TMIN to TMAX
AD8028W only: TMIN to TMAX
VCM = 1.5 V, PNP active
TMIN to TMAX
AD8028W only: TMIN to TMAX
AD8028W only: TMIN to TMAX
VOUT = 1 V to 2 V, AD8028W only: TMIN to TMAX
RL = 1 kΩ
VCM = 0 V to 1.5 V
AD8028W only: TMIN to TMAX
TMIN to TMAX
Tristate < ±20 µA, TMIN to TMAX
TMIN to TMAX
50% of input to <10% of final VOUT
Min
Max
Unit
200
800
850
900
900
µV
µV
µV
µV
µV/°C
µA
µA
µA
µA
µA
µA
µA
dB
240
2
4
4
−8
−8
90
88
78
±0.1
100
Rev. D | Page 6 of 27
−11
±0.9
MΩ
pF
V
dB
dB
1150
50
V
V
V
ns
ns
55/55
ns
0.03 to 4.97
72
−49
20
V
mA
dB
pF
1.1 to 1.3
0.4
0.07 to 4.93
6.0
No sign or a plus sign indicates current into the pin; a minus sign indicates current out of the pin.
It is recommended to float the DISABLE/SELECT pin for crossover high mode.
6
−11
6
2
−0.2 to +3.2
100
2.7
AD8028W only: TMIN to TMAX
DISABLE/SELECT = low
AD8028W only: TMIN to TMAX
VS ± 1 V, AD8028W only: TMIN to TMAX
6
2.0
VIN = −4 V to +1 V, G = −1
AD8028W only: TMIN to TMAX
Sinking and sourcing
VIN = 0.2 V p-p, f = 1 MHz, DISABLE/SELECT = low
30% overshoot
Typ
300
88
100
12
8.0
9
420
420
V
mA
mA
µA
µA
dB
Data Sheet
AD8027/AD8028
ABSOLUTE MAXIMUM RATINGS
Rating
12.6 V
See Figure 3
±VS ± 0.5 V
±1.8 V
−65°C to +125°C
−40°C to +125°C
300°C
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8027/AD8028
package is limited by the associated rise in junction temperature
(TJ) on the die. The plastic encapsulating the die locally reaches
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8027/AD8028.
Exceeding a junction temperature of 175°C for an extended
period of time can result in changes in the silicon devices,
potentially causing failure.
The still air thermal properties of the package and PCB (θJA),
ambient temperature (TA), and the total power dissipated in the
package (PD) determine the junction temperature of the die.
The junction temperature can be calculated as
TJ = TA + (PD × θJA)
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL) is referenced to
midsupply, the total drive power is VS/2 × IOUT, some of which is
dissipated in the package and some in the load (VOUT × IOUT).
The difference between the total drive power and the load
power is the drive power dissipated in the package.
If the rms signal levels are indeterminate, consider the worst
case, when VOUT = VS/4 for RL to midsupply.
PD = (VS × I S ) +
RL
In single-supply operation with RL referenced to –VS, worst case
is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. Also,
more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes reduces
the θJA. Care must be taken to minimize parasitic capacitances
at the input leads of high speed op amps, as described in the
PCB Layout section.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC
(125°C/W), 6-lead SOT-23 (170°C/W), and 10-lead MSOP
(130°C/W) packages on a JEDEC standard 4-layer board.
Output Short Circuit
Shorting the output to ground or drawing excessive current
from the AD8027/AD8028 can cause catastrophic failure.
2.0
1.5
8-LEAD SOIC
1.0
10-LEAD MSOP
0.5
6-LEAD SOT-23
0
–55
–35
–15
5
25
45
65
85
AMBIENT TEMPERATURE (°C)
105
125
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
PD = Quiescent Power + (Total Drive Power − Load Power)
V V
PD = (VS × I S ) +  S × OUT
RL
 2
(VS /4 )2
 VOUT 2
–

RL

Rev. D | Page 7 of 27
03327-002
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature Range (Soldering 10 sec)
Junction Temperature
It is recommended that rms output voltages be considered. If RL
is referenced to –VS, as in single-supply operation, the total
drive power is VS × IOUT.
MAXIMUM POWER DISSIPATION (W)
Table 4.
AD8027/AD8028
Data Sheet
DNC 1
AD8027
8
DISABLE/SELECT
–IN 2
7
+VS
+IN 3
6
VOUT
–VS 4
5
DNC
DNC = DO NOT CONNECT. DO NOT
CONNECT TO THIS PIN.
03327-001
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. 8-Lead SOIC, AD8027 Pin Configuration
Table 5. 8-Lead SOIC, AD8027 Pin Function Descriptions
Mnemonic
DNC
Description
Do Not Connect. Do not connect to these pins.
2
3
4
6
7
8
−IN
+IN
−VS
VOUT
+VS
DISABLE/SELECT
Negative Input.
Positive Input.
Negative Supply.
Output Voltage.
Positive Supply
Power-Down/Select. The power-down function places the device into low power
consumption mode. The select function of this pin shifts the crossover point (where the
NPN/PNP input differential pairs transition from one to the other) closer to either the positive
supply rail or the negative supply rail.
VOUT 1
–VS 2
+IN 3
+
–
AD8027
6
+VS
5
DISABLE/SELECT
4
–IN
03327-102
Pin No.
1, 5
Figure 5. 6-Lead SOT-23, AD8027 Pin Configuration
Table 6. 6-Lead SOT-23, AD8027 Pin Function Descriptions
Pin No.
1
2
3
4
5
Mnemonic
VOUT
−VS
+IN
−IN
DISABLE/SELECT
6
+VS
Description
Output Voltage.
Negative Supply.
Positive Input.
Negative Input.
Power-Down/Select. The power-down function places the device into low power
consumption mode. The select function of this pin shifts the crossover point (where the
NPN/PNP input differential pairs transition from one to the other) closer to either the positive
supply rail or the negative supply rail.
Positive Supply.
Rev. D | Page 8 of 27
AD8027/AD8028
VOUTA 1
–IN A 2
–
+IN A 3
+
AD8028
–VS 4
8
+VS
7
VOUTB
–
6
–IN B
+
5
+IN B
03327-103
Data Sheet
Figure 6. 8-Lead SOIC, AD8028 Pin Configuration
Table 7. 8-Lead SOIC, AD8028 Pin Function Descriptions
Mnemonic
VOUTA
−IN A
+IN A
−VS
+IN B
−IN B
VOUTB
+VS
Description
Output Voltage, Channel A.
Negative Input, Channel A.
Positive Input, Channel A.
Negative Supply.
Positive Input, Channel B.
Negative Input, Channel B.
Output Voltage, Channel B.
Positive Supply.
VOUTA 1
10 +VS
–IN A 2
–
+IN A 3
+
–VS 4
DISABLE/SELECT A 5
AD8028
9
VOUTB
–
8
–IN B
+
7
+IN B
6
DISABLE/SELECT B
03327-104
Pin No.
1
2
3
4
5
6
7
8
Figure 7. 10-Lead MSOP, AD8028 Pin Configuration
Table 8. 10-Lead MSOP, AD8028 Pin Function Descriptions
Pin No.
1
2
3
4
5
Mnemonic
VOUTA
−IN A
+IN A
−VS
DISABLE/SELECT A
6
DISABLE/SELECT B
7
8
9
10
+IN B
−IN B
VOUTB
+VS
Description
Output Voltage, Channel A.
Negative Input, Channel A.
Positive Input, Channel A.
Negative Supply.
Power-Down/Select, Channel A. The power-down function places the device into low power
consumption mode. The select function of this pin shifts the crossover point (where the
NPN/PNP input differential pairs transition from one to the other) closer to either the positive
supply rail or the negative supply rail.
Power-Down/Select, Channel B. The power-down function places the device into low power
consumption mode. The select function of this pin shifts the crossover point (where the
NPN/PNP input differential pairs transition from one to the other) closer to either the positive
supply rail or the negative supply rail.
Positive Input, Channel B.
Negative Input, Channel B.
Output Voltage, Channel B.
Positive Supply.
Rev. D | Page 9 of 27
AD8027/AD8028
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
Default conditions: VS = 5 V at TA = 25°C, RL = 1 kΩ, unless otherwise noted.
8
G = +2
7 VOUT = 200mV p-p
6
5
CLOSED-LOOP GAIN (dB)
0
–1
–2
G = +2
–4
AD8028
G = +1
–5
G = +10
–6
–7
G = –1
2
1
–1
–3
1
10
FREQUENCY (MHz)
100
1000
G = +1
1 VOUT = 200mV p-p
–4
0.1
CLOSED-LOOP GAIN (dB)
0
–1
VS = 5V
–4
–5
–6
–7
10
FREQUENCY (MHz)
100
–3
–4
–5
–6
–7
VS = +5V
–9
1000
Figure 9. AD8027 Small Signal Frequency Response for Various Supplies
VS = ±5V
1
10
FREQUENCY (MHz)
100
1000
Figure 12. AD8028 Small Signal Frequency Response for Various Supplies
2
8
G = +2
7 VOUT = 2V p-p
G = +1
1 VOUT = 2V p-p
0
6
CLOSED-LOOP GAIN (dB)
VS = 5V
–1
–2
–3
VS = +3V
–4
–5
–6
–7
–8
5
VS = 5V
4
3
VS = +5V
2
1
0
VS = +3V
–1
–2
VS = +5V
1
10
FREQUENCY (MHz)
–3
100
1000
–4
0.1
03327-005
–9
–10
0.1
–2
–10
0.1
03327-004
1
1000
VS = +3V
–8
VS = +5V
–9
–10
0.1
100
G = +1
1 VOUT = 200mV p-p
0
–8
10
FREQUENCY (MHz)
2
–1
–3
1
Figure 11. Small Signal Frequency Response for Various Supplies
VS = +3V
–2
VS = 5V
0
–2
2
CLOSED- LOOP GAIN (dB)
3
–9
Figure 8. Small Signal Frequency Response for Various Gains
CLOSED-LOOP GAIN (dB)
4
–8
–10
0.1
VS = +5V
03327-007
–3
VS = +3V
03327-006
AD8027
G = +1
VOUT = 200mV p-p
03327-003
NORMALIZED CLOSED-LOOP GAIN (dB)
1
Figure 10. Large Signal Frequency Response for Various Supplies, G = +1
1
10
FREQUENCY (MHz)
100
1000
03327-008
2
Figure 13. Large Signal Frequency Response for Various Supplies, G = +2
Rev. D | Page 10 of 27
Data Sheet
AD8027/AD8028
4
3
G = +1
3 VOUT = 200mV p-p
2
CLOSED-LOOP GAIN (dB)
CL = 5pF
0
–1
–2
–3
CL = 0pF
–4
–5
–6
–3
CL = 0pF
–4
–5
–6
–7
100
1000
8
6
5
5
CLOSED-LOOP GAIN (dB)
6
VOUT = 2V p-p
1
0
–1
–2
1
10
FREQUENCY (MHz)
100
1000
Figure 15. Frequency Response for Various Output Amplitudes
4
3
1
0
–1
–4
0.1
1
0
0
CLOSED-LOOP GAIN (dB)
2
–1
–2
–40°C
+125°C
–4
–5
+25°C
–6
G = +1
VOUT = 200mV p-p
10
FREQUENCY (MHz)
100
1000
1
10
FREQUENCY (MHz)
100
1000
Figure 16. AD8027 Small Signal Frequency Response vs. Frequency for
Various Temperatures
–1
–2
–3
+125°C
–4
–5
–40°C
–6
–7 G = +1
VOUT = 200mV p-p
–8
0.1
1
03327-011
1
VOUT = 2.0V p-p
RL = 1k
Figure 18. Small Signal Frequency Response for Various RLOAD Values
1
–8
0.1
VOUT = 2.0V p-p
RL = 150
2
2
–3
VOUT = 0.2V p-p
RL = 1k
–3
03327-010
–4
0.1
VOUT = 0.2V p-p
RL = 150
–2
VOUT = 4V p-p
–3
1000
03327-013
2
G = +2
7
3
100
Figure 17. AD8028 Small Signal Frequency Response for Various CLOAD Values
VOUT = 200mV p-p
4
10
FREQUENCY (MHz)
+25°C
10
FREQUENCY (MHz)
100
1000
03327-014
G = +2
1
03327-012
10
FREQUENCY (MHz)
7
CLOSED-LOOP GAIN (dB)
–2
–10
0.1
03327-009
1
Figure 14. AD8027 Small Signal Frequency Response for Various CLOAD Values
CLOSED-LOOP GAIN (dB)
–1
–9
–8
0.1
–7
CL = 5pF
–8
–7
8
CL = 20pF
0
1
CLOSED-LOOP GAIN (dB)
G = +1
2 VOUT = 200mV p-p
1
CL = 20pF
Figure 19. AD8028 Small Signal Frequency Response vs. Frequency for
Various Temperatures
Rev. D | Page 11 of 27
AD8027/AD8028
2
VOLTAGE NOISE (nV/ Hz)
VICM = +VS – 0.2V
DISABLE/SELECT = HIGH
1
0
VICM = –VS + 0.2V
DISABLE/SELECT = TRI
–1
–2
–3
–4
VICM = 0V
DISABLE/SELECT = HIGH OR TRI
–5
100
10
10
VOLTAGE
CURRENT
–7 G = +1
VOUT = 200mV p-p
–8
0.1
1
VICM = –VS + 0.3V
DISABLE/SELECT = TRI
10
FREQUENCY (MHz)
100
1000
1
10
03327-015
–6
100
1k
10k
100k
1M
10M
100M
1
1G
03327-018
CLOSED-LOOP GAIN (dB)
100
VICM = +VS – 0.3V
DISABLE/SELECT = HIGH
3
CURRENT NOISE (pA/ Hz)
4
Data Sheet
FREQUENCY (Hz)
Figure 23. Voltage and Current Noise vs. Frequency
Figure 20. Small Signal Frequency Response vs. Frequency for Various Input
Common-Mode Voltages
–10
6.9
G = +2
6.8 RL = 150
–20
–30
6.7
CLOSED-LOOP GAIN (dB)
–40
–60
–70
–80
B TO A
–90
A TO B
–100
–110
–120
6.5
6.4
6.3
6.2
0.1
1
10
FREQUENCY (MHz)
100
1000
5.9
0.1
Figure 21. AD8028 Crosstalk, Output to Output (see Figure 59)
110
G = +1
VOUT = 2V p-p
RL = 1k
–40
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
50
55
40
35
30
20
PHASE (Degrees)
75
60
DISTORTION (dB)
95
PHASE
70
–60
VS = +3V
–80
–100
15
10
–120
–5
0
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
–25
1G
03327-017
OPEN-LOOP GAIN (dB)
80
1000
–20
115
90
100
10
FREQUENCY (MHz)
Figure 24. 0.1 dB Flatness Frequency Response
135
GAIN
1
03327-019
0.01
03327-016
–140
0.001
–10
10
VOUT = 2V p-p
6.1
6.0
–130
100
VOUT = 200mV p-p
6.6
Figure 22. Open-Loop Gain and Phase vs. Frequency
–140
0.1
VS = +5V
VS = 5V
1
FREQUENCY (MHz)
10
20
Figure 25. Harmonic Distortion vs. Frequency and Supply Voltage
Rev. D | Page 12 of 27
03327-020
CROSSTALK (dB)
–50
Data Sheet
AD8027/AD8028
–20
–45
–55
–40
DISABLE/SELECT = TRI
DISABLE/SELECT = HIGH
–60
VS = +5V
VS = +3V
DISTORTION (dB)
DISTORTION (dB)
–65
VS = 5V
–80
–100
–75
–85
–95
–105
–120
0
1
2
3
4
5
6
7
OUTPUT VOLTAGE (V p-p)
8
9
10
03327-021
Figure 26. Harmonic Distortion vs. Output Voltage
–125
0.5
–50
–50
–60
–60
VS = +5V
1.5
2.0
2.5
3.0
3.5
INPUT COMMON-MODE VOLTAGE (V)
4.0
4.5
G = +1 (RF = 24.9)
VOUT = 1.0V p-p AT 100kHz
VS = +3V
VS = +5V
–70
VS = +3V
–80
DISTORTION (dB)
–90
–100
–110
–120
–80
–90
–100
–110
–120
–140
0.5
–130
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
1.0
1.5
2.0
2.5
3.0
3.5
INPUT COMMON-MODE VOLTAGE (V)
4.0
4.5
–140
0.5
03327-022
–130
1.5
2.0
2.5
3.0
3.5
INPUT COMMON-MODE VOLTAGE (V)
–20
–20
VS = +5
VOUT = 2.0V p-p
SECOND HARMONIC: SOLID LINE
–40 THIRD HARMONIC: DASHED LINE
RL = 1k
DISTORTION (dB)
–60
–80
1.0
4.0
4.5
Figure 30. Harmonic Distortion vs. Input Common-Mode Voltage,
DISABLE/SELECT = Trisate or Open
Figure 27. Harmonic Distortion vs. Input Common-Mode Voltage,
DISABLE/SELECT = High
G = +1 (RF = 24.9)
VOUT = 2.0V p-p
SECOND HARMONIC: SOLID LINE
–40 THIRD HARMONIC: DASHED LINE
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
03327-025
DISTORTION (dB)
1.0
Figure 29. Harmonic Distortion vs. Input Common-Mode Voltage, VS = 5 V
–70
RL = 150
–100
–60
G = +2
G = +10
G = +1
–80
–100
–120
–120
–140
0.1
1
FREQUENCY (MHz)
10
20
03327-023
DISTORTION (dB)
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
–140
0.1
1
FREQUENCY (MHz)
10
Figure 31. Harmonic Distortion vs. Frequency and Gain
Figure 28. Harmonic Distortion vs. Frequency and Load
Rev. D | Page 13 of 27
20
03327-026
–140
–115
03327-024
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
AD8027/AD8028
0.10
0.10
0.05
0.05
0
0
–0.05
–0.05
–0.10
–0.10
50mV/DIV
20ns/DIV
–0.20
G = +1
VS = ±2.5V
50mV/DIV
4.0
G = –1
3.5
RL = 1kΩ
3.0 V = ±2.5V
S
2.5
2.0
1.5
INVERTED
1.0
INPUT
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
500mV/DIV
–4.0
VOUT = 2V p-p
1.0
0
100ns/DIV
03327-028
–1.0
500mV/DIV
Figure 33. Large Signal Transient Response, G = +1
2.5
G = +2
2.0 VS = ±2.5V
1.5
4.0
G = +1
3.5 R = 1kΩ
L
3.0 VS = ±2.5V
2.5
2.0
1.5
INPUT
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
500mV/DIV
–4.0
VOUT = 4V p-p
VOUT = 2V p-p
0.5
0
–0.5
–1.0
50mV/DIV
20ns/DIV
03327-029
–1.5
–2.5
50ns/DIV
Figure 36. Overdrive Recovery, G = −1
1.0
–2.0
20ns/DIV
Figure 35. Small Signal Transient Response with Capacitive Load
VOUT = 4V p-p
–2.0
CL = 5pF
–0.20
Figure 32. Small Signal Transient Response
2.0
CL = 20pF
–0.15
03327-027
–0.15
G = +1
VS = ±2.5V
03327-030
0.15
03327-031
0.15
0.20
G = +1
VS = ± 2.5V
Figure 37. Overdrive Recovery, G = +1
Figure 34. Large Signal Transient Response, G = +2
Rev. D | Page 14 of 27
50ns/DIV
03327-032
0.20
Data Sheet
Data Sheet
AD8027/AD8028
–10
–8
DISABLE/SELECT = TRI
–6
VIN (200mV/DIV)
+0.1%
VOUT – 2VIN (2mV/DIV)
–0.1%
–4
–2
VS = +5V
0
VS = 5V
2
4
VS = +3V
6
DISABLE/SELECT = HIGH
8
10
03327-033
5s/DIV
0
1
2
3
4
5
6
7
8
INPUT COMMON-MODE VOLTAGE (V)
9
10
03327-036
INPUT BIAS CURRENT (A)
G = +2
Figure 41. Input Bias Current vs. Input Common-Mode Voltage
Figure 38. Long-Term Settling Time
250
DISABLE/SELECT = TRI
200
+0.1%
–0.1%
0
–800
3.0
2.5
–40
–7.5
VS = +5V
–8.0
DISABLE/SELECT = TRI
–25
–10
5
20
35
50
65
TEMPERATURE (°C)
80
95
110
200
400
600
800
–8.5
125
340
320
300
INPUT OFFSET VOLTAGE (V)
VS = +3V
0
360
280
260
240
DISABLE/SELECT = TRI
VS = 5V
VS = +3V
220
DISABLE/SELECT = HIGH
200
180
VS = +5V
160
140
120
100
80
03327-035
DISABLE/SELECT = HIGH
INPUT BIAS CURRENT [DISABLE/SELECT = TRI] (µA)
INPUT BIAS CURRENT [DISABLE/SELECT = HIGH] (µA)
–7.0
3.5 VS = ±5V
–200
Figure 42. Input Offset Voltage Distribution
–6.5
4.0
–400
INPUT OFFSET VOLTAGE (µV)
Figure 39. 0.1% Short-Term Settling Time
4.5
–600
03327-037
20ns/DIV
100
50
03327-034
VOUT – 2VIN (0.1%/DIV)
DISABLE/SELECT = HIGH
150
Figure 40. Input Bias Current vs. Temperature
60
–40
–25
–10
5
20
35
50
65
TEMPERATURE (°C)
80
95
110
Figure 43. Input Offset Voltage vs. Temperature
Rev. D | Page 15 of 27
125
03327-038
VOUT (400mV/DIV)
FREQUENCY
VIN (200mV/DIV)
AD8027/AD8028
Data Sheet
120
290
VS = 5V
100
DISABLE/SELECT = HIGH
250
80
230
CMRR (dB)
210
40
DISABLE/SELECT = TRI
190
60
20
170
–4
–3
–2
–1
0
1
2
3
INPUT COMMON-MODE VOLTAGE (V)
4
5
0
1k
03327-039
150
–5
Figure 44. Input Offset Voltage vs. Input Common-Mode Voltage, VS = ±5 V
290
10k
100k
1M
FREQUENCY (Hz)
10M
100M
03327-042
INPUT OFFSET VOLTAGE (V)
270
Figure 47. Common-Mode Rejection Ratio (CMRR) vs. Frequency
0
VS = +5V
–10
270
–30
–40
230
PSSR (dB)
INPUT OFFSET VOLTAGE (V)
–20
DISABLE/SELECT = HIGH
250
210
DISABLE/SELECT = TRI
190
–PSRR
–50
+PSRR
–60
–70
–80
–90
170
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
INPUT COMMON-MODE VOLTAGE (V)
4.5
5.0
–110
100
03327-040
150
Figure 45. Input Offset Voltage vs. Input Common-Mode Voltage, VS = 5 V
10k
100k
1M
FREQUENCY (Hz)
10M
100M
1G
Figure 48. Power Supply Rejection Ratio (PSRR) vs. Frequency
–20
270
VS = +3V
VIN = 0.2V p-p
G = +1
–30 DISABLE/SELECT = LOW
DISABLE/SELECT = HIGH
250
OFF ISOLATION (dB)
–40
230
210
190
DISABLE/SELECT = TRI
170
–60
–70
–80
0
0.50
1.00
1.50
2.00
2.50
INPUT COMMON-MODE VOLTAGE (V)
3.00
Figure 46. Input Offset Voltage vs. Input Common-Mode Voltage, VS = 3 V
Rev. D | Page 16 of 27
–100
10k
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 49. Off Isolation vs. Frequency
1G
03327-044
150
–50
–90
03327-041
INPUT OFFSET VOLTAGE (V)
1k
03327-043
–100
Data Sheet
AD8027/AD8028
130
LOAD RESISTANCE TIED
TO MIDSUPPLY
150
120
100
VS = +3V
0
VS = +5V VS = 5V
–50
VOH – VS+
–100
5V
110
OPEN-LOOP GAIN (dB)
VOL – VS–
50
+5V
100
+3V
90
80
–200
100
1000
LOAD RESISTANCE ()
10000
60
0
10
Figure 50. Output Saturation Voltage vs. Load Resistance
20
30
ILOAD (mA)
40
50
60
03327-048
70
–150
03327-045
OUTPUT SATURATION VOLTAGE (mV)
200
Figure 53. Open-Loop Gain vs. Load Current
100
1M
DISABLE/SELECT = LOW
0.1
G = +2
G = +1
0.01
0.001
1k
10k
100k
1M
10M
FREQUENCY (Hz)
100M
1G
10k
1k
100
10
100k
Figure 51. Output Enabled—Impedance vs. Frequency
80
VS = +5V
RL = 1kΩ TIED TO MIDSUPPLY
VS = +5V
DISABLE/SELECT CURRENT (A)
60
40
VOL – –VS
35
+VS – VOH
30
25
–40
–25
–10
5
20
35
50
65
TEMPERATURE (°C)
80
95
110
10M
FREQUENCY (Hz)
100M
1G
Figure 54. Output Disabled—Impedance vs. Frequency
125
03327-047
OUTPUT SATURATION VOLTAGE (mV)
45
1M
03327-049
G = +5
Figure 52. Output Saturation Voltage vs. Temperature
+125°C
VS = +10V
AT +25°C
40
+25°C
20
–40°C
0
–20
–40
–60
–80
0
0.5
1.0
1.5
2.0
DISABLE/SELECT VOLTAGE (V)
2.5
Figure 55. DISABLE/SELECT Current vs.
DISABLE/SELECT Voltage and Temperature
Rev. D | Page 17 of 27
3.0
03327-050
1
OUTPUT IMPEDANCE ()
100k
03327-046
OUTPUT IMPEDANCE ()
10
AD8027/AD8028
Data Sheet
1.5
9.0
DISABLE/SELECT PIN
(–2.0V TO –0.5V)
8.5
1.0
8.0
SUPPLY CURRENT (mA)
0.5
0
–0.5
G = –1
VS = 2.5V
VIN = –1.0V
0
50
100
150
TIME (ns)
200
250
VS = +3V
6.0
5.5
4.0
–40
DISABLE/SELECT PIN (–2.0V TO –0.5V)
1.0
OUTPUT
0.5
0
–0.5
2
3
4
5
6
7
8
9
10
03327-052
G = –1
VS = 2.5V
VIN = –1.0V
–1.5
0.5 1
–25
–10
5
20
35
50
65
TEMPERATURE (°C)
80
95
110
125
Figure 58. Quiescent Supply Current vs. Temperature and Supply Voltage
1.5
OUTPUT VOLTAGE (V)
VS = +5V
6.5
4.5
Figure 56. Enable Turn On Timing
–1.0
VS = 5V
7.0
03327-053
–1.5
7.5
5.0
–1.0
03327-051
OUTPUT VOLTAGE (V)
OUTPUT
Figure 57. Disable Turn-Off Timing
Rev. D | Page 18 of 27
Data Sheet
AD8027/AD8028
TEST CIRCUIT
V1
VI
+
R2
50Ω
U1
+
1/2
AD8028
1/2
AD8028
–
U2
R3
1kΩ
VOUT
–
CROSSTALK = 20log (VOUT/VIN)
03327-116
R1
50Ω
Figure 59. Crosstalk Test Circuit (see Figure 21)
Rev. D | Page 19 of 27
AD8027/AD8028
Data Sheet
THEORY OF OPERATION
The NPN input pair can then operate at 200 mV above the
positive rail. Both input pairs are protected from differential
input signals above 1.4 V by four diodes across the input (see
Figure 60). In the event of differential input signals that exceed
1.4 V, the diodes conduct and excessive current flows through
them. Include a series input resistor to limit the input current to
10 mA.
The AD8027/AD8028 are rail-to-rail input/output amplifiers
designed in the Analog Devices, Inc., extra fast complementary
bipolar (XFCB) process. The XFCB process enables the
AD8027/AD8028 to run on 2.7 V to 12 V supplies with 190 MHz
of bandwidth and a 100 V/μs slew rate. The AD8027/AD8028
have 4.3 nV/√Hz of wideband noise with 17 nV/√Hz noise at
10 Hz. This noise performance, with an offset of less than
900 μV maximum and drift performance of 1.50 μV/°C typical,
makes the AD8027/AD8028 ideal for high speed, precision
applications. Additionally, the input stage operates 200 mV
beyond the supply rails and shows no phase reversal. The
amplifiers feature overvoltage protection on the input stage.
When the inputs exceed the supply rails by 0.7 V, ESD protection
diodes turn on, drawing excessive current through the differential input pins. Include a series input resistor to limit the input
current to less than 10 mA.
CROSSOVER SELECTION
The AD8027/AD8028 have a crossover selection feature that
allows the user to choose the crossover point between the
PNP/NPN differential pairs. Although the crossover region is
small, avoid operating in this region because it can introduce
offset and distortion to the output signal. To help avoid operating in the crossover region, the AD8027/AD8028 allow the user
to select from two preset crossover locations (voltage levels)
using the DISABLE/SELECT pin. The crossover region is about
200 mV and is defined by the voltage level at the base of Q5 in
Figure 60. Internally, two separate voltage sources are created
approximately 1.2 V from either rail. One rail or the other is
connected to Q5, based on the voltage applied to the DISABLE/
SELECT pin. This allows either dominant PNP pair operation,
when the DISABLE/SELECT pin is left open, or dominant NPN
pair operation, when the DISABLE/SELECT pin is pulled high.
INPUT STAGE
The rail-to-rail input performance is achieved by operating
complementary input pairs. The common-mode level of the
differential input signal determines which pair is on. As shown
in Figure 60, a tail current (ITAIL) is generated that sources the
PNP differential input structure consisting of Q1 and Q2. A
reference voltage is generated internally that is connected to the
base of Q5. This voltage is continually compared against the
common-mode input voltage. When the common-mode level
exceeds the internal reference voltage, Q5 diverts the tail
current (ITAIL) from the PNP input pair to a current mirror that
sources the NPN input pair consisting of Q3 and Q4.
The DISABLE/SELECT pin also provides the traditional powerdown function when it is pulled low. This pin allows the designer
to achieve the best precision and ac performance for high-side
and low-side signal applications. See Figure 54 through Figure 57
for DISABLE/SELECT pin characteristics.
VCC
+
ITAIL
1.2V
–
VOUTP
ICMFB
Q5
Q3
Q1
Q2
Q4
VN
VP
VSEL
VEE
LOGIC
VOUTN
VCC
ICMFB
+
1.2V
03327-054
–
VEE
Figure 60. Simplified Input Stage
Rev. D | Page 20 of 27
Data Sheet
AD8027/AD8028
The size of the discontinuity is defined as
(
DC ERRORS
The AD8027/AD8028 use two complementary input stages to
achieve rail-to-rail input performance, as described in the Input
Stage section. To use the dc performance over the entire commonmode range, the input bias current and input offset voltage of
each pair must be considered.
Because the input pairs are complementary, the input bias current reverses polarity when going through the crossover region
shown in Figure 41. The offset between pairs is described by
(
 R + RF
VOS , NPN , OUT = VOS , NPN  G
 RG
)
 R +R
VOS, PNP − VOS, NPN = I B, PNP − I B, NPN ×  RS  G F

  RG


 − RF 




where:
IB, PNP is the input bias current of either input when the PNP
input pair is active.
IB, NPN is the input bias current of either input pair when the
NPN pair is active.
If RS is sized so that it equals RF when multiplied by the gain
factor, this effect is eliminated. It is strongly recommended to
balance the impedances in this manner when traveling through
the crossover region to minimize the dc error and distortion. As
an example, assuming that the PNP input pair has an input bias
current of 6 µA and the NPN input pair has an input bias
current of −2 µA, a 200 µV shift in offset occurs when traveling
through the crossover region with RF equal to 0 Ω and RS equal
to 25 Ω.
In addition to the input bias current shift between pairs, each
input pair has an input bias current offset that contributes to the
total offset in the following manner:
Referring to Figure 61, the output offset voltage of each pair is
calculated by
 R + RF
VOS , PNP , OUT = VOS , PNP  G
 RG




Using the crossover select feature of the AD8027/AD8028 helps
to avoid this region. In the event that the region cannot be
avoided, the quantity (VOS, PNP − VOS, NPN) is trimmed to
minimize this effect.
OUTPUT STAGE
The AD8027/AD8028 use a common emitter output structure
to achieve rail-to-rail output capability. The output stage is
designed to drive 50 mA of linear output current, 40 mA within
200 mV of the rail, and 2.5 mA within 35 mV of the rail.
Loading of the output stage, including any possible feedback
network, lowers the open-loop gain of the amplifier. Refer to
Figure 53 for the loading behavior. Capacitive load can degrade
the phase margin of the amplifier. The AD8027/AD8028 can
drive up to 20 pF, G = +1, as shown in Figure 14. Include a
small (25 Ω to 50 Ω) series resistor, RSNUB, if the capacitive load
is to exceed 20 pF for a gain of 1. Increasing the closed-loop
gain increases the amount of capacitive load that can be driven
before a series resistor must be included.
)
 R + RF
VDIS = VOS,PNP − VOS,NPN ×  G
 RG




 R + RF
FVOS = I B + RS  G
 RG
RF
RG
+
VOS
+VS
–
IB –





 − I B − RF


VIN
–
+
RS
–
AD8027/
AD8028
+
where the difference of the two input stages is the discontinuity
experienced when going through the crossover region.
Rev. D | Page 21 of 27
IB+
VOUT
+
–
DISABLE/SELECT
–VS
Figure 61. Op Amp DC Error Sources
03327-055
In the event that the crossover region cannot be avoided, specific attention is given to the input stage to ensure constant
transconductance and minimal offset in all regions of operation.
The regions are PNP input pair running, NPN input pair
running, and both running at the same time (in the 200 mV
crossover region). Maintaining constant transconductance in
all regions ensures the best wideband distortion performance
when going between these regions. With this technique, the
AD8027/AD8028 can typically achieve 85 dBc SFDR for a
2 V p-p, 1 MHz, and G = +1 signal on ±1.5 V supplies. Another
requirement needed to achieve this level of distortion is that the
offset of each pair must be laser trimmed, even for low frequency
signals.
AD8027/AD8028
Data Sheet
WIDEBAND OPERATION
CF
Voltage feedback amplifiers can use a wide range of resistor
values to set their gain. Proper design of the feedback network
of the application requires consideration of the following issues:



+VS
Poles formed by the amplifier input capacitances with the
resistances seen at the amplifier input terminals
Effects of mismatched source impedances
Resistor value impact on the voltage noise of the
application
Amplifier loading effects
With a wide bandwidth of 190 MHz, the AD8027/AD8028 have
numerous applications and configurations. The AD8027/AD8028
device shown in Figure 62 is configured as a noninverting amplifier. Table 9 provides an easy selection table of gain, resistor
values, bandwidth, and noise performance, and Figure 63 shows
the inverting configuration.
+VS
C1
0.1F
C2
10F
RG
–
DISABLE/SELECT
C4
0.1F
–VS
Figure 63. Wideband Inverting Gain Configuration
CIRCUIT CONSIDERATIONS
Balanced Input Impedances
Balanced input impedances can help to improve distortion
performance. When the amplifier transitions from PNP pair
to NPN pair operation, a change in both the magnitude and
direction of the input bias current occurs. When multiplied by
imbalanced input impedances, a change in offset can result. The
key to minimizing this distortion is to keep the input impedances
balanced on both inputs. Figure 64 shows the effect of the
imbalance and degradation in SFDR performance for a 50 Ω
source impedance, with and without a 50 Ω balanced feedback
path.
G = +1
VOUT = 2V p-p
–30 RL = 1k
VS = +3V
VOUT
C3
10F
–40
–VS
SFDR (dB)
–50
C4
0.1F
R1 = RF||RG
R1
C5
VOUT
C3
10F
+
DISABLE/SELECT
+
AD8027/
AD8028
–20
AD8027/
AD8028
03327-056
R1
VIN
–
R1 = RF||RG
The AD8027/AD8028 have an input capacitance of 2 pF. This
input capacitance forms a pole with the amplifier feedback
network, destabilizing the loop. For this reason, it is generally
desirable to keep the source resistances below 500 Ω, unless
some capacitance is included in the feedback network. Likewise,
keeping the source resistances low also takes advantage of the
AD8027/AD8028 low input voltage noise of 4.3 nV/√Hz.
RF
C2
10F
RG
VIN
C1
0.1F
03327-057

RF
–60
RF = 0
–70
Figure 62. Wideband Noninverting Gain Configuration
RF = 24.9
–80
–90
1
FREQUENCY (MHz)
10
20
03327-058
RF = 49.9
–100
0.1
Figure 64. SFDR vs. Frequency and Various RF
Table 9. Component Values, Bandwidth, and Noise Performance (VS = ±2.5 V)
Noise Gain
(Noninverting)
1
2
10
RSOURCE (Ω)
50
50
50
RF (Ω)
0
499
499
RG (Ω)
Not applicable
499
54.9
−3 dB Small Signal BW (MHz)
190
95
13
Rev. D | Page 22 of 27
Output Noise with Resistors (nV/√Hz)
4.4
10
45
Data Sheet
AD8027/AD8028
PCB Layout
As with all high speed op amps, achieving optimum performance from the AD8027/AD8028 requires careful attention to
PCB layout. Particular care must be exercised to minimize lead
lengths of the bypass capacitors. Excess lead inductance can
influence the frequency response and even cause high frequency oscillations. The use of a multilayer board with an
internal ground plane can reduce ground noise and enable a
tighter layout.
The length of the high frequency bypass capacitor pads and
traces is critical. A parasitic inductance in the bypass grounding
works against the low impedance created by the bypass capacitor.
Because load currents flow from supplies as well as ground,
place the load at the same physical location as the bypass capacitor
ground. For large values of capacitors, which are intended to be
effective at lower frequencies, the current return path length is
less critical.
Power Supply Bypassing
To achieve the shortest possible lead length at the inverting
input, position the feedback resistor, RF, beneath the board so
that it spans the distance from the output, to the inverting
input. Situate the return node of the resistor, RG, as closely as
possible to the return node of the negative supply bypass
capacitor.
Power supply pins are actually inputs, and care must be taken to
provide a clean, low noise, dc voltage source to these inputs.
The bypass capacitors have two functions.
On multilayer boards, clear all layers underneath the op amp of
metal to avoid creating parasitic capacitive elements. This is
especially true at the summing junction (the negative input).
Extra capacitance at the summing junction can cause increased
peaking in the frequency response and lower phase margin.
•
Grounding
To minimize parasitic inductances and ground loops in high
speed, densely populated boards, a ground plane layer is critical.
Understanding where the current flows in a circuit is critical in
the implementation of high speed circuit design. The length of
the current path is directly proportional to the magnitude of the
parasitic inductances and, therefore, the high frequency impedance of the path. Fast current changes in an inductive ground
return can create unwanted noise and ringing.
•
Provide a low impedance path for unwanted frequencies
from the supply inputs to ground, thereby reducing the
effect of noise on the supply lines.
Provide sufficient localized charge storage, for fast
switching conditions and minimizing the voltage drop at
the supply pins and the output of the amplifier. This is
usually accomplished with larger electrolytic capacitors.
Decoupling methods are designed to minimize the bypassing
impedance at all frequencies. This can be accomplished with a
combination of capacitors in parallel to ground.
Use high quality ceramic chip capacitors and always keep them
as close as possible to the amplifier package. A parallel combination of a 0.01 µF ceramic and a 10 µF electrolytic covers a wide
range of rejection for unwanted noise. The 10 µF capacitor is
less critical for high frequency bypassing, and, in most cases,
one per supply line is sufficient.
Rev. D | Page 23 of 27
AD8027/AD8028
Data Sheet
APPLICATIONS INFORMATION
USING THE DISABLE/SELECT PIN
The disable time of the AD8027/AD8028 amplifiers is load
dependent. Table 11 lists typical enable/disable times. See
Figure 56 and Figure 57 for the actual switching measurements.
The AD8027/AD8028 unique DISABLE/SELECT pin has two
functions:
•
Table 11. DISABLE/SELECT Switching Speeds
The power-down function places the AD8027/AD8028
into low power consumption mode. In power-down mode,
the amplifiers draw 500 µA maximum of supply current.
The second function, as described in the Crossover
Selection section, shifts the crossover point (where the
NPN/PNP input differential pairs transition from one to
the other) closer to either the positive supply rail or the
negative supply rail. This selectable crossover point allows
the user to minimize distortion based on the input signal
and environment. The default state is −1.2 V from the
positive power supply, with the DISABLE/SELECT pin left
floating or in tristate mode. In tristate mode, it is important
that current to the pin is limited to ±20 μA maximum.
Time
tON
tOFF
Supply Voltages (RL = 1 kΩ)
+5 V
+3 V
50 ns
50 ns
1100 ns
1150 ns
DRIVING A 16-BIT ADC
With the adjustable crossover distortion selection point and low
noise, the AD8028 is an ideal amplifier for driving or buffering
input signals into high resolution ADCs such as the AD7677, a
16-bit, 1 LSB INL, 1 MSPS differential ADC. Figure 65 shows
the typical schematic for driving the ADC. The AD8028 driving
the AD7677 offers performance close to nonrail-to-rail amplifiers
and avoids the need for an additional supply other than the
single 5 V supply already used by the ADC.
Table 10 lists the voltage levels and modes of operation for
the DISABLE/SELECT pin over the full temperature range.
In this application, the DISABLE/SELECT pins are biased to
avoid the crossover region of the AD8028 for low distortion
operation.
Table 10. DISABLE/SELECT Pin Mode Control
Mode
Disable
Crossover Referenced −1.2 V
to Positive Supply
Crossover Referenced +1.2 V
to Negative Supply
±5 V
45 ns
980 ns
DISABLE/SELECT Pin Voltage (V)
−VS to –VS + 0.4
−VS + 1.1 to –VS +1.3
Table 12 lists summary test data for the schematic shown in
Figure 65.
Table 12. ADC Driver Performance, fC = 100 kHz,
VOUT = 4.7 V p-p
−VS + 2.0 to +VS
Parameter
Second Harmonic Distortion
Third Harmonic Distortion
Total Harmonic Distortion
SFDR
When the input stage transitions from one input differential
pair to the other, there is virtually no noticeable change in the
output waveform.
+5V
0.1µF
–
15Ω
AD8028
ANALOG INPUT +
4MHz LPF +5V
2.7nF
+
INPUT RANGE
(0.15V TO 2.65V)
DISABLE/SELECT
(OPEN)
+5V
AD7677
16 BITS
0.1µF
–
15Ω
AD8028
ANALOG INPUT –
+
2.7nF
4MHz LPF
DISABLE/SELECT
(OPEN)
Figure 65. Unity-Gain Differential Drive
Rev. D | Page 24 of 27
03327-059
•
Measurement
−105 dB
−102 dB
−102 dB
105 dBc
Data Sheet
AD8027/AD8028
As shown in Figure 66, the AD8028 and AD7677 combination
offers excellent integral nonlinearity (INL).
1.0
The test data shown in Figure 68 indicates that this design
yields a filter response with a center frequency of fO = 1 MHz,
and a bandwidth of 450 kHz.
CH1 S21 LOG
INL (LSB)
0.5
5dB/REF 6.342dB
1:6.3348dB 1.00 000MHz
1
0
0
16384
32768
CODE
49152
65536
0.1
Figure 66. Integral Nonlinearity
BAND-PASS FILTER
In Figure 67, the AD8027/AD8028 device is configured as a
1 MHz band-pass filter. The target specifications are fO = 1 MHz
and a −3 dB pass band of 500 kHz. To start the design, select fO,
Q, C1, and R4. Then use the following equations to calculate the
remaining variables:
DESIGN TOOLS AND TECHNICAL SUPPORT
Analog Devices is committed to simplifying the design process
by providing technical support and online design tools. Analog
Devices offers technical support via evaluation boards, sample
ICs, interactive evaluation tools, data sheets, SPICE models,
application notes, and phone and email support available at
www.analog.com.
f O (MHz)
Band Pass (MHz)
k = 2πfOC1
C2 = 0.5C1
R1 = 2/k, R2 = 2/(3k), R3 = 4/k
H = 1/3(6.5 − 1/Q)
R5 = R4/(H − 1)
R2
105Ω
+5V
C1
1000pF
C3
0.1µF
+
C2
500pF
R3
634Ω
AD8027/
AD8028
VOUT
DISABLE/
SELECT
–
C4
–5V 0.1µF
R5
523Ω
R4
523Ω
03327-061
VIN
R1
316Ω
10
Figure 68. Band-Pass Filter Response
In communication systems, active filters are used extensively in
signal processing. The AD8027/AD8028 are excellent choices
for active filter applications. In realizing this filter, it is important that the amplifier have a large signal bandwidth of at least
10× the center frequency, fO. Otherwise, a phase shift can occur
in the amplifier, causing instability and oscillations.
Q
1
FREQUENCY – MHz
03327-062
–1.0
03327-060
–0.5
Figure 67. Band-Pass Filter Schematic
Rev. D | Page 25 of 27
AD8027/AD8028
Data Sheet
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
5
1
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
Figure 69. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
3.00
2.90
2.80
1.70
1.60
1.50
6
5
4
1
2
3
3.00
2.80
2.60
PIN 1
INDICATOR
0.95 BSC
1.90
BSC
1.45 MAX
0.95 MIN
0.15 MAX
0.05 MIN
0.50 MAX
0.30 MIN
0.20 MAX
0.08 MIN
SEATING
PLANE
10°
4°
0°
0.60
BSC
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 70. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
Rev. D | Page 26 of 27
0.55
0.45
0.35
12-16-2008-A
1.30
1.15
0.90
Data Sheet
AD8027/AD8028
3.10
3.00
2.90
10
3.10
3.00
2.90
5.15
4.90
4.65
6
1
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
6°
0°
0.23
0.13
0.70
0.55
0.40
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
0.15
0.05
COPLANARITY
0.10
Figure 71. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
AD8027ARZ
AD8027ARZ-REEL
AD8027ARZ-REEL7
AD8027ARTZ-R2
AD8027ARTZ-REEL7
AD8028ARZ
AD8028ARZ-REEL
AD8028ARZ-REEL7
AD8028ARMZ
AD8028ARMZ-REEL7
AD8028WARMZ-R7
AD8027ART-EBZ
AD8028AR-EBZ
1
2
3
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
6-Lead SOT-23
6-Lead SOT-23
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
Evaluation Board
Evaluation Board
Package Option
R-8
R-8
R-8
RJ-6
RJ-6
R-8
R-8
R-8
RM-10
RM-10
RM-10
Ordering Quantity
1
2500
1000
250
3000
1
2500
1000
1
1000
1000
Branding3
H4B#
H4B#
H5B#
H5B#
Y5R#
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
# denotes lead-free, may be top or bottom marked.
AUTOMOTIVE PRODUCTS
The AD8028W model is available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for this model.
©2003–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03327-0-7/15(D)
Rev. D | Page 27 of 27