Engineering 43
Chp 14-1
Op Amp Circuits
Bruce Mayer, PE
Licensed Electrical & Mechanical Engineer
BMayer@ChabotCollege.edu
Engineering-43: Engineering Circuit Analysis
1
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Ckts W/ Operational Amplifiers

OpAmp Utility
1. OpAmps Are Very
Useful Electronic
Components
2. We Have Already
Developed The
Tools To Analyze Practical OpAmp Circuits
3. The Linear Models for OpAmps
Include Dependent Sources
– A PRACTICAL Application of Dependent Srcs
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Real Op Amps
LM324 DIP
 Physical Size
Progression of
OpAmps Over
the Years
LMC6294
MAX4240
Maxim (Sunnyvale, CA) Max4241 OpAmp
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Apex PA03
HiPwr OpAmp
 Notice OutPut Rating
• 30A @75 V
 PwrOut → 30A•75V
→ 2.25 kW!
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
OpAmp Symbol & Model
 The Circuit Symbol
Is a Version of the
Amplifier TRIANGLE
 The Linear Model
• Typical Values
Ri : 105   1012 
OUTPUT RESISTANCE
RO : 1  50
A : 105  107
BW : 1 MHz
INPUT RESISTANCE
GAIN
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
OpAmp InPut Terminolgy
 The Average of
the two Input
Voltages is called
the Common-Mode
v1  v2
Signal
viCM 
2
 The Difference between vid  v1  v2
the Inputs is called the
and
Differential-Signal, vid
vo  AO  vid
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx

vo

OpAmp Power Connections
 BiPolar Power
Supplies
 UniPolar Supply
 For Signal I/O Analysis the Supplies
Need NOT be shown explicitly
• But they MUST physically be there to actually
Power the Operational Amplifier
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
OpAmp Circuit Model
LOAD
OP-AMP
DRIVING CIRCUIT
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
vi→vo Transfer Characteristics
Linear
Region
vo/vi =
Const
Saturation
 The OUTPUT Voltage Level can NOT exceed the
SUPPLY the Level
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Unity Gain Buffer (FeedBack)
FeedBack
Loop
Op-Amp BUFFER GAIN
LM324
0.99999
LMC6492
0.9998
MAX4240
0.99995
KVL :  V  R I  R I  A V  0
s
i
O
O in
 Controlling Variable = Vin  Ri I
KVL : - Vout  RO I  AOVin  0
 Solve For Buffer Gain (I = Vin/Ri)
Vout
1

recall AO    Thus The Amplification
Ri
Vout
Vs 1 
A



1
O
RO  AO Ri
VS
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
UGB Algebra
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
The Ideal OpAmp
 The IDEAL
Characteristics
•
•
•
•
Ro = 0
Ri = 
A =  (open loop gain)
BW = 
 The Consequences
of Ideality
Ro  0  vo  Av  v 
Ri    i  i  0
i
i
@V3 : V3  VS1  12[V ]
A    v  v
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Summing Point Constraint
 The MOST important
aspects of Ideality:
• Ri = ∞ → i+ = i− = 0
– The OpAmp INput looks
like an OPEN Circuit
• A = ∞ → v+ = v−
– The OpAmp Input looks
like a SHORT Circuit
 This simultaneous
OPEN & SHORT
Characteristic is
called the →
Engineering-43: Engineering Circuit Analysis
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Looks Like
an OPEN
to Current
Looks Like
a SHORT
to Voltage
 SUMMING POINT
CONSTRAINT
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Analyzing Ideal OpAmp Ckts
1. Verify the presence of NEGATIVE
FeedBack
2. Assume the Summing Point Constraint
Applies in this fashion:
•
i+ = i−= 0 (based on Ri = ∞)
•
v+ − v− = 0 (based on AO = ∞)
3. Use KVL, KCL, Ohm’s Law, and other
linear ckt analysis techniques to
determine quantities of interest
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Voltage Follower
 The Voltage Follower
vO  v S
v  v s
v  v
• Also Called Unity Gain
Buffer (UGB) from Before
vO  v
 Usefulness of UGB
Connection w/o Buffer
vO  vS  iRs
 The SOURCE
Supplies The Power
Engineering-43: Engineering Circuit Analysis
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Buffered Connection
vO  vS
 The Source Supplies
NO Power (the
OpAmp does it)
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Inverting
OpAmp Ckt
 Determine Voltage Gain,
G = Vout/Vin
 Start with Ao
v  0
i  0
v  0
Ao    v  v
 v  0
 Now From Input R
Ri    i  i  0
 Apply KCL at v−
Vs  0 Vout  0

0
R1
R2
Engineering-43: Engineering Circuit Analysis
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 Finally The Gain
Vout
R2
G

Vs
R1
 Next: Examine Ckt w/o
Ideality Assumption
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Replace OpAmp w/ Linear Model
 Consider Again the
Inverting OpAmp
Circuit
1. Identify the Op
Amp Nodes
v
vo
v
 Draw the
Linear Model
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Drawing the OpAmp Linear Model
2. Redraw the circuit
cutting out the
Op Amp
v
3. Draw components
of linear OpAmp
(on the circuit of
step-2)
v
vo
vo
Ri
v
v
RO


Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
A(v  v )
Drawing the OpAmp Linear Model
4. UNTANGLE as
Needed
v
R2
R2
v
ve  v  v
 The BEFORE
& AFTER
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
NonIdeal Inverting Amp
 Replace the OpAmp with
the LINEAR Model
b - d
b - a
• Label Nodes for Tracking
 Draw The Linear
Equivalent For Op-amp
 Note the External
Component Branches
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
NonIdeal Inverting Amp cont.
 On The LINEAR Model
Connect The External
Components
 ReDraw Ckt for
Increased Clarity
R2
 Now Must Sweat the
Details
ve  v  v
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
NonIdeal Inverting Amp cont.
 Node Analysis
• Note GND Node
 Controlling Variable In
Terms Of Node Voltages
ve  v1
Engineering-43: Engineering Circuit Analysis
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2
ve  v  v
 The 2 Eqns in Matrix Form
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Inverting Amp – Invert Matrix
 Use Matrix Inversion to Solve 2 Eqns in 2 Unknowns
• Very Useful for 3 Eqn/Unknwn Systems as well
– e.g., http://www.wikipedia.org/wiki/Matrix_inversion
 The Matrix Determinant 
 Solve for vo
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Inverting Amp – Invert Matrix cont
 Then the System Gain
 Typical Practical Values for the Resistances
• R1 = 1 kΩ
R2 = 5 kΩ
 Then the Real-World Gain
vO
 4.9996994
vS
 Recall The Ideal Case for A→; Then The Eqn at top
vO
 5 1
 5 1
 lim A

 5.0000
vS
1  K  A R2 Ro  1    
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Compare Ideal vs. NonIdeal
v  0
i  0
v  0
 Ideal Assumptions
Ri    i  i  0
A    v  v  0
Engineering-43: Engineering Circuit Analysis
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 Gain for Real Case
• Replace Op-amp By Linear
Model, Solve The Resulting
Circuit With Dep. Sources
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Compare Ideal vs. NonIdeal cont.

i  0

 Ideal Case at Inverting
Terminal
The Ideal Opamp Assumption
Provides an
Excellent
Real-World
Approximation.
Unless Forced to
do Otherwise We
Will Always Use
the IDEAL Model
 Gain for NonIdeal Case
0  vS 0  vO
vO
R2

0

R1
R2
vS
R1
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Example  Differential Amp
 KCL At Inverting Term
 KCL at NONinverting
Terminal
 Assume Ideal OpAmp

 R 
R
R  R 
i  0  vO  1  2 v  2 v1  2  1  1 v  v1 
R1
R1   R2 
 R1 

 By The KCLs
A simple
Voltage
Divider
i  0  v 
Engineering-43: Engineering Circuit Analysis
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R4
R4
v2  v 
v2
R3  R4
R3  R4
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Example  Differential Amp cont
 Then in The Ideal Case
 Now Set External R’s
• R4 = R2
• R3 = R1
 Subbing the R’s
Into the vo Eqn
R2
vO 
(v2  v1 )
R1
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Ex. Precision Diff V-Gain Ckt
 Find vo
 Assume Ideal OpAmps
• Which Voltages are Set?
v1
i  0
v1  v1 , v2  v2
• What Voltages Are Also
Known Due To Infinite
Gain Assumption?
v2
v2
• Now Use The Infinite
Resistance Assumption
 CAUTION: There could be
currents flowing INto or
OUTof the OpAmps
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Ex. Precision Diff V-Gain Ckt cont
 The Ckt Reduces To Fig. at Right
 KCL at v1
v1
 KCL at v2
va
v2
 Eliminate va Using The above Eqns
and Solve for vo in terms of v1 & v2
• Note the increased Gain over Diff Amp
OpAmp
Current
Engineering-43: Engineering Circuit Analysis
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R2 R1  1  R2 R1  2R2 RG 
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
NONinverting Amp - Ideal
v0
R2
i  0
v  vi
R1
 Ideal Assumptions
• Infinite Gain
v  v
• Infinite Ri with v+ = v1
v  v1  v  v1
Engineering-43: Engineering Circuit Analysis
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 Since i− = 0 Arrive at
“Inverse Voltage Divider”
R1
R1  R2
vi 
v0  v0 
vi
R1  R2
R1
R2
OR : v0  1 
vi
R1
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Example  Find Io for Ideal OpAmp
v  12V
v  12V
Ri    i  0
 Ideal Assumptions
A    v  v  12V
Ri    i  i  0
Engineering-43: Engineering Circuit Analysis
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 KCL at v−
12  Vo 12

 0  Vo  84V
12k
2k
Vo
 IO 
 8.4mA
10k
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Example: TransResistance Ckt
 The trans-resistance
Amp circuit below
performs Current to
Voltage Conversion
• Find vo/iS
0V
iS
0V
Engineering-43: Engineering Circuit Analysis
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 Use the Summing
Point Constraint
• → v− = 0V
• Now by KCL at v−
Node with i− = 0
– Notice that iS flows
thru the 1Ω resistor
– Thus by Ohm’s Law
vO  0 V  1   iS
or
vO iS  1  1 volt amp
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Key to OpAmp Ckt Analysis  IOA
 Remember that the “Nose” of the
OpAmp “Triangle” can SOURCE or
SINK “Infinite” amounts of Current
IOA = ± ∞
|IOA,max| = Isat
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Example: TransResistance Ckt
 Notice
that the
OpAmp
Absorbs
ALL of the
Source
Current
 The (Ideal) OpAmp will Source or Sink
Current Out-Of or In-To its “nose” to
maintain the V-Constraint: v+ = v−
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Example: TransConductance Ckt
 The transonductance
Amp circuit below
performs Voltage to
Current Conversion
• Find io/v1

V  0
0
RL
iO
Engineering-43: Engineering Circuit Analysis
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• → v− = v+
• → i− = i+ = 0
 Thus v− = v1
0
v1
 Use the Summing
Point Constraint
v1  0 v1

Then
RI
RI
by KCL
or
& Ohm iO v1  1 RI  GI
iO 
• Notice the Output is
Insensitive to Load
Resistance
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Example: Summing Amp Circuit
if 
iA 
iB 
 Label Important
Quantities
 By Virtual Short
(v+=v−) Across
OpAmp Inputs
Engineering-43: Engineering Circuit Analysis
37
vf
0V
iL 
0V
 Also by Summing
Point Contstraint
(i+ = i− =0) KCL at vf
node
i f  i A  iB
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Example: Summing Amp Circuit
if 
iA 
iB 
 Use Ohm for iA & iB
iA 
iB 
vA  v f
RA
vB  v f
RB
vA  0 vA


RA
RA
vB  0 vB


RB
RB
Engineering-43: Engineering Circuit Analysis
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vf
0V
iL 
0V
 Also by Ohm Thru Rf
vo  v f  R f  i f
Recall i f  i A  iB
So vo  v f  R f  i A  iB 
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Example: Summing Amp Circuit
if 
iA 
iB 
 Recall
i & iB v
vA A
B
iA 
RA
iB 
 Sub for iA & iB
RB
 v A vB 

vo  v f  R f  

 RA RB 
Engineering-43: Engineering Circuit Analysis
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vf
0V
iL 
0V
 But by Virtual Short
vf=0; Thus after
ReArranging
vo  
Rf
RA
vA 
Rf
RB
vB
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Example: Summing Amp Circuit
if 
iA 
iB 
 Input Resistances:
RinA 
v A  v A   v A
v A

i A v A  v A  RA  v A RA
RinA 
RinA 
0V
iL 
0V
 Similarly for RinB
RinB 
v A
v A RA  v A RA  v A RA
vB  vB   vB
vB

iB vB  vB  RB  vB RB
RinB 
v A
1

 RA
0  v A RA 1 RA
vB
vB RB  vB RB  vB RB
RinB 
vB
1

 RB
0  vB RB 1 RB
Engineering-43: Engineering Circuit Analysis
40
vf
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Example: Summing Amp Circuit
 For the OUTput
Resistance as seen
by the LOAD, put
the Circuit in a
“Black Box”
 Thévenizing the
Black Box
iL 

vL

iL 
 Recall vo
vo  
Engineering-43: Engineering Circuit Analysis
41
Rf
RA
vA 
Rf
RB
vB
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Example: Summing Amp Circuit
 Thus Have
iL 

Rf
RA
vA 
Rf
RB
vB

vL

 But the Previous
analysis vo does
NOT depend on RL
at ALL
 If vL = vo in all cases
then have R
vL  vo  vL 
 From the LOAD
Perspective Expect
RL
vL 
vo
RL  Ro
Engineering-43: Engineering Circuit Analysis
42
L
RL
vo
RL
 vL 
vo  Ro  0
RL  0
• Since vo is Not
affected by RL,
then Ro =Bruce
0 Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Example: Summing Summary
if 
iA 
vf
iB 
vo  
Rf
RA
vA 
Engineering-43: Engineering Circuit Analysis
43
0V
Rf
RB
iL 
0V
RinA  RA
vB
RinB  RB
Ro  0
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Example: I & V Inputs
 Set Voltages
R
i  0
v



v
vO
iS
+
-
vS
 Required

• Find the expression for vo.
• Indicate where and how
Ideal OpAmp assumptions
Are Used
Engineering-43: Engineering Circuit Analysis
44
v  vS
 Infinite Gain Assumption
Fixes v− v  vS
 Use Infinite Input
Resistance Assumption
 Apply KCL to Inverting
Input
 Then Solving
vo  v 
iS 
0
R
vo  vS  Ri S
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Example – Find G and Vo
v  VS
VS 
VO
v _  VS
i  0
VS
R2
R1
 Ideal Assumptions
A    v  v  VS
Ri    i  i  0
 Yields Inverse Divider
Engineering-43: Engineering Circuit Analysis
45
 Solving
VO 
VO
G
 101
VS
100k  1k
VS
1k
VS  1mV  VO  0.101V
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Example  OpAmp Based I-Mtr
 Desired Transfer Characteristic = 10V/mA → Find R2
NON-INVERTING AMPLIFIER
R
G 1 2
R1
VI  RI I
 R 
VO  GVI  1  2  RI I
 R1 
 R 
 R 
VO 10V

 10k  1  2  RI  10  1  2   R2  9k
I 1mA
 R1 
 R1 
Engineering-43: Engineering Circuit Analysis
46
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Offset & Saturation
 A NonInverting Amp
• But How to Handle This???
 Start w/ KCL at v−
• Assume Ideality
• Then at Node Between the
1k & 4k Resistors
v  v1
i  0
v  v1
A    v  v  v1
 Then the Output
Engineering-43: Engineering Circuit Analysis
47
 Notes on Output Eqn
• Slope = 1+(R2/R1) as Before
• Intercept =
−(0.5V)x(4kΩ/1kΩ)
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Example – Offset & Saturation
 Note how “Offset” Source Generates a
NON-Zero Output When v1 = 0
 The Transfer Characteristic for This Circuit
“Saturates” at
“Rail” Potential
IN LINEAR RANGE
−2V Offset
Engineering-43: Engineering Circuit Analysis
48
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
WhiteBoard Work
 Let’s Work a Unity
Gain Buffer Problem
• Vs = 60mV
• Rs = 29.4 kΩ
• RL = 600 Ω
 Find Load Power
WITH and withOUT
OpAmp UGB
Engineering-43: Engineering Circuit Analysis
49
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
All Done for Today
What’s
an
OpAmp?
Engineering-43: Engineering Circuit Analysis
50
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Engineering 43
Appendix
Bruce Mayer, PE
Registered Electrical & Mechanical Engineer
BMayer@ChabotCollege.edu
Engineering-43: Engineering Circuit Analysis
51
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Engineering-43: Engineering Circuit Analysis
52
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
29.4
29.4 k
Engineering-43: Engineering Circuit Analysis
53
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
 Unity Gain Buffer
Source-Driven
Circuit
• Vs = 60mV
• Rs = 29.4 kΩ
• RL = 600 Ω
Engineering-43: Engineering Circuit Analysis
54
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Key to OpAmp Ckt Analysis  IOA
 Remember that the “Nose” of the
OpAmp “Triangle” can SOURCE or
SINK “Infinite” amounts of Current
IOA = ± ∞
Engineering-43: Engineering Circuit Analysis
55
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Unity Gain Buffer
Op-Amp BUFFER GAIN
LM324
0.99999
LMC6492
0.9998
MAX4240
0.99995
 Controlling Variable = Vin  Ri I
KVL :  Vs  Ri I  RO I  AOVin  0
KVL : - Vout  RO I  AOVin  0
 Solve For Buffer Gain by KVL
Vout
1
 Thus The Amplification

recall AO  
V
Ri
Vs 1 
AO    out  1
RO  AO Ri
VS
Engineering-43: Engineering Circuit Analysis
56
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Comparator
 Ideal Comparator and Transfer Characteristic
 “Zero-Cross” Detector → Heart of Solid State Relay Cnrtl
Engineering-43: Engineering Circuit Analysis
57
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Find G & Rin for NonIdeal Case
 The OpAmp Model
v

Ri

v
RO
vO
A( v   v  )
 Add Input Source-V
 Determine Equivalent
Circuit Using Linear
Model For Op-Amp
Engineering-43: Engineering Circuit Analysis
58
v1


v

Ri

v
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
RO
vO
A( v   v  )
Example
R
 Required

• Draw The Linear

Equivalent Circuit
• Write The Loop Equations
vO
iS
vo
v


RO
Ri
+
-
1. Locate Nodes
2. Place the nodes in
linear circuit model
v
Engineering-43: Engineering Circuit Analysis
59
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
v
Example cont
3. Add Remaining
Components to Complete
Linear Model
R
i2
i1
iS
+
-
• Two Loops
• One Current Source
• Mesh-2
Ri (i2  iS )  ( R  RO )i2  A(v  v_ )  0
RO
Ri
 Examine Circuit
 Use Meshes
• Mesh-1 i1  is
vo
v
 DONE
• But Could Sub for (v+-v-)
and solve for i2
• Controlling Variable
v  v_  Ri (i2  iS )
Engineering-43: Engineering Circuit Analysis
60
A(v + - v -)
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Find G & Rin for NonIdeal Case
 Add The External
Components
 The Equivalent Circuit for
Mesh Analysis
R2
v1


v

Ri
v
RO

R1
vO
A( v   v  )
 Now Re-draw Circuit To
Enhance Clarity

vO

• Be Faithful to the NODES
• There Are Only Two Loops
Engineering-43: Engineering Circuit Analysis
61
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Find G & Rin for NonIdeal Case
R2
 Now The Mesh Eqns
• Mesh-1
• Mesh-2
 The Controlling Variable
in Terms of Loop
Currents
v1


2
v
1


Ri
R1
v
RO
A( v   v  )
 Eliminating vi
vO   R2i2  R1 (i1  i2 )
 Continue Analysis on
Next Slide
Engineering-43: Engineering Circuit Analysis
62
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
vO
G & Rin for NonIdeal Case cont
 The Math Model From
Mesh Analysis

vO
vO   R2i2  R1 (i2  i1 )

 The Input-R and Gain
vO
v1
Rin 
G
i1
v1
 Then the Model in
Matrix Form →
Engineering-43: Engineering Circuit Analysis
63
 R1
( R1  R2 )
  i1  v1 
 AR  R ( R  R  R ) i    0 
1
1
2
O  2 
 
 i
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
G & Rin for NonIdeal Case cont
 The Matrix-Inversion Soln
1
 R1
 v1 
 i1  ( R1  R2 )
i    AR  R ( R  R  R )  0 
1
1
2
O   
 2  i
 Invert Matrix as Before
• Find Determinant, 
• Adjoint Matrix
  ( R1  R2  RO )( R1  R2 )  R1 ( ARi  R1 )
R1 
( R  R2  RO )
Adj   1

  ( ARi  R1 ) ( R1  R2 )
 Then the Solution
R1  v1 
 i1  1 ( R1  R2  RO )
i      ( AR  R ) ( R  R )  0 
 2

i
1
1
2  
Engineering-43: Engineering Circuit Analysis
64
 Solving for Mesh Currents
R1  R2  RO
i1 
v1

i2 
 ( ARi  R1 )
 Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
G & Rin for NonIdeal Case cont
 The (Long) Expression for The input Resistance
 By Mesh Currents
vO  R1i1  ( R1  R2 )i2

R1 ( R1  R2  RO )
( R  R2 )( ARi  R1 )
v1  1
v1


 This Looks Ugly
• How Can we Simplify?

vO
– Recall
 A→
 Ri → 
Engineering-43: Engineering Circuit Analysis
65

Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
G & Rin for NonIdeal Case cont
 Use A→ in Expression for 
  Lim A ( R1  R2  RO )( R1  R2 )  R1 ( ARi  R1 )  ARi R1
 Now Since For Op-Amps Ri→ Also, then vo
R1 ( R1  R2  RO )
( R1  R2 )( ARi  R1 )
vO 
v1 
v1


( R1  R2 )( ARi  R1 )
( R1  R2 )( ARi )
vO  0 
v1 
v1


( R  R2 )( ARi )
( R  R2 )
vO  1
v1  1
v1
ARi R1
R1
vO
R1  R2
 Finally then G:
G

v1
R1

 And The Expression for Rin: Rin  
Engineering-43: Engineering Circuit Analysis
66
Infinite Input
Resistance
is GOOD
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx