Engineering 43
FETs-2
(Field Effect Transistors)
Bruce Mayer, PE
Registered Electrical & Mechanical Engineer
BMayer@ChabotCollege.edu
Engineering-43: Engineering Circuit Analysis
1
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Learning Goals
 Understand the Basic Physics of
MOSFET Operation
 Describe the Regions of Operation of a
MOSFET
 Use the Graphical LOAD-LINE method
to analyze the operation of basic
MOSFET Amplifiers
 Determine the Bias-Point (Q-Point) for
MOSFET circuits
Engineering-43: Engineering Circuit Analysis
2
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Load Line: Common Source Amp
 Shown below is
typical “CommonSource” Amplifier
circuit
 THE DC sources,
VDD & VGG bias the
MOSFET for Amp
operation
 That is, the two DC
sources set The
Operating, or Q, Pt
 Now apply KVL to
left loop
 vin t   vGS  VGG  0
or vGS  vin t   VGG
Engineering-43: Engineering Circuit Analysis
3
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Load Line: Common Source Amp
 Using the values
given the Schematic
vGS  1V sin 1000  2 t   4V
 Now KVL on Right
Loop
 VDD  RD iD  vDS  0
or VDD  RD iD  vDS
 Rearranging
1
VDD
iD  
vDS 
RD
RD
Engineering-43: Engineering Circuit Analysis
4
 Of form: y = mx + b
 Using given values
1
20 V
iD  
vDS 
or
1 k
1 k
iD   1 mSvDS  20 mA
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Load Line: Common Source Amp
 Thus the LoadLine
Equation
1
20 V
iD  
vDS 
1 k
1 k
 Plot this on the FET
vi Curve to
determine the
Operating Point
 Since this is a LINE
need only 2-points
• Intercepts are easy
Engineering-43: Engineering Circuit Analysis
5
 Making a T-Table
vDS
iD
0
20 mA
20V
0
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Draw LoadLine on FET vi Curve
VGG = VGS
sets Q-Pt
Engineering-43: Engineering Circuit Analysis
6
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Max and Min Opp-Points
 The common source
Amp is designed to
Operate in the
SATURATION
Region. Recall the
vGS Eqn
vGS  1V sin 2000t   4V
 By sin behavior
Pt - A
 1V  4V  3V Pt - B
vGS ,max  1V  4V  5V
vGS ,min
Engineering-43: Engineering Circuit Analysis
7
 Reading the vi-LL graph
find (vDS,iD) co-ords
• (vDSmin,iD) = (4V,16mA)
– vGS = 5V
• (vDSmax,iD) = (16V,4mA)
– vGS = 3V
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Voltage Swing
 The common source
Amp is must stay in
Saturation. For this
nFET that means
max & min vGS
values of 5V & Vto
give the 1V
amplitude of the sin
 From Last Slide We
calculated
corresponding
Engineering-43: Engineering Circuit Analysis
8
Xmax/min values for vDS
• vDS,min = 4V (vGS = 5)
• vDS,max = 16V (vGS = 3)
 Note that the output
direction is Opposite
the Input direct
 The ckt produces a
SATURATED output
Voltage Swing of
4V−16V = −12V
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Input and OutPut Compared
Gate Excitation
 Note that OUTput
peaks occur at
INput Valleys →
Inversion
 The ratio of the
V-swings
AS 
vDS Response
Engineering-43: Engineering Circuit Analysis
9
 12 V
 6
2V
 This is NOT the
Gain  𝐴𝑣 =
𝑣𝑜𝑢𝑡 𝑣𝑖𝑛
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
LoadLine Gain
 Notice
• vGS: 4→3
– VDS: 11→16 (∆ = 5)
• vGS: 4→5
– VDS: 11→4 (∆ = 7)
Input
 Unequal ∆’s due to the
NONlinear nature of
MOSFETS; they are
“Square-Law” devices
• The iD lines in SAT are
NOT evenly Spaced
Output
Engineering-43: Engineering Circuit Analysis
10
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
LoadLine Gain
 Since the FET is NOT
linear, 𝑣𝑂𝑈𝑇 is NOT
directly proportional
to 𝑣𝐼𝑁 , so we can NOT
Define a true Gain
Input
 “Small Signal” methods
WILL allow us to define
a true grain for the AC
part of the voltage input
• Requires Calculus
– To “Linearize” ckt
Output
Engineering-43: Engineering Circuit Analysis
11
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Common-Source Amp Analysis
 To analyze The Common-Source
Amplifier we will do the following:
1. Perform DC analysis to find the bias, or
Q, point; i.e., find the DC drain current
and check that the transistor is in the
saturation region)
2. Find circuit small-signal AC model
(based on the bias point obtained)
3. Perform AC (small signal) analysis
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Saturation Slippery-Slope
 Must also take care that the small-signal
input does NOT push the FET Out of
Saturation at ANY Time.
 The vin-Amplitude and Bias-Pt Selection
could
• Drive the FET out of SAT
and into TRIODE Operation
• Drive the FET into CutOff
(vGS < Vto)
Engineering-43: Engineering Circuit Analysis
13
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
One-Supply Bias Circuit
 Usually only ONE
supply voltage is
available. In this
case set VG with a
voltage
divider
 Use
Thévenin
At Gate
Engineering-43: Engineering Circuit Analysis
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 Using Thévenin
Analysis at VG to
relative to GND
VG  gnd  Vth  VGG
VGG
R1

VDD
R1  R 2
Rth  RG  R1 ||R 2
R1  R 2
RG 
R1  R 2
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Bias-Pt Analysis by Thévenin
)
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Digression: RG by Src DeAct
16
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Alternative
Engineering-43: Engineering Circuit Analysis
One-Supply Bias Circuit
 Replacing
the left
side of
the ckt
with its
Thévenin
equivalent
 Then the
KVL Eqn for the
Gate Loop
0  VG  RG 0 v GS  R S i D
Engineering-43: Engineering Circuit Analysis
17
 The is NO V-Drop
across RG as iG = 0
 Thus VG  R S i D v GS
 Recall the CS amp
is designed to
i D operate in
Saturation which
produces iD at this
level
i D  K vGS Vto 
2
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
One-Supply Bias Circuit
 If the Circuit has
been properly
Biased the FET is in
SATURATION
 In Saturation iD is
INdependent of vDS
and equals, at the
operating , or Q,
point
i DQ  K v GSQ Vto 
2
Engineering-43: Engineering Circuit Analysis
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 Recall the
KVL eqn
on the
GATE
Loop (now
Assumed at the “Q”
VG v GSQ
point):
i DQ 
RS
 Sub into SAT eqn
V Gv GSQ
RS
i D
 K v GSQ Vto 
2
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
One-Supply Bias Circuit
 Solve for vGSQ: V Gv GSQ
 K v GSQ Vto
RS




 Or: V Gv GSQ  RS K v GSQ Vto
 Introduce new Constant: U  RS K
 Yields quadratic Eqn in vGSQ:
2
GSQ
Uv
2


 1  2UVto vGSQ  UV  VG  0
2
to
 Now Solve by MATLAB’s MuPAD
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
2
vGSQ by MuPAD
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
One-Supply Bias Circuit
 Discarding the Negative Root find
2UVto  1 
4U VG  Vto   1
v GSQ 
2U
 Then Find iDQ by subbing vGSQ from
above into the gate KVL Eqn:
i DQ 
Engineering-43: Engineering Circuit Analysis
21
VG v GSQ
RS
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
One-Supply Bias Circuit
 Solving the last two
eqns yields iDQ and
vGSQ
• Beware that the
parabolic iD eqn will
produce an
extraneous root
– Discard the
SMALLER root as
SAT requires:
vGS−Vto ≥ 0
vGS Vto   i D K
Engineering-43: Engineering Circuit Analysis
22
 The KVL
eqn on ckt
Right-Side
0  VDD 
iD
R D i D v DS
RS iD
 ReArranging
v DS  VDD  R D  R S i D
 Then with iDQ from
before (MuPAD)
v DSQ  VDD  R D  R S i DQ
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Small Signal FET Model
 At the Operating
Point the quantities
are DC, and should
be Noted in Upper
case letters:
Q - Pt  VDSQ , I DQ 
 If a small-amplitude
ac signal is injected
into the circuit the
instantaneous
quantity Eqns:
Engineering-43: Engineering Circuit Analysis
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iD t   I DQ  id t 
vGS t   VGSQ  vgs t 
 Where id and vgs are
the small signal
quantities
 A conceptual Diagram
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Small Signal FET Model
 Recall iD in SAT
2
i D  K vGS Vto 
 From last slide
iD t   I DQ  id t 
 Using this reln and
expanding the IDQ+id
eqn yields


id  2 K V GSQVto  vgs  g m v gs
vGS t   VGSQ  vgs t 
 Subbing for iD & vGS  Where gm is called
2
the “small signal
I DQid  K V GSQvgs  Vto 
transconduce” for an
 Now the Q-Pt is also
nMOSFET
in Saturation so,
2
 Again for IGFET
I DQ K V GSQVto 
ig 0
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Small Signal FET Model
 These eqns describe the linear small
signal operation in the Saturation region
id  g m v gs
and
ig  0
 A graphical representation of the model
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
gm(Q)
 Usually a greater
value of gm is better
than a smaller one
 gm is a function of
the Device “K”
Parameter and the
Q-Pt values
 Recall
g m  2 K V GSQVto 
 Also recall at Q-Pt
Engineering-43: Engineering Circuit Analysis
26
I DQ K V GSQVto 
2
 Or: V GSQVto   I DQ K
 Thus g m  2 K I DQ K
 Simplifying: g m  2 KI DQ
 Recall from our
MOSFET Construction
Discussion
 W  KP
K  
L 2
• “KP” is single
quantity Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
gm(Q)
 Using g m  2 KI DQ
 And
W
K 
L
 KP

 2
 Find
 W  KP
gm  2  
I DQ
L 2
 Simplifying
W
g m  2 KP 
 I DQ
L
Engineering-43: Engineering Circuit Analysis
27
 Thus to increase the
transconductance of
a KP-fixed MOSFET
• Increase IDQ
– Remember, Vswing
must be entirely in the
SATURATION region
• Increase the W/L
ratio
– But this makes the
transistor BIGGER;
usually NOT desired
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Refined Small Signal Model
 The previous model
assumed
CONSTANT iD in
Saturation
 Real MOSFETs
exhibit
an
upward
Slope
in SAT:
Engineering-43: Engineering Circuit Analysis
28
 Recall that a SLOPE
on a vi Curve is
effectively
• A Conductance;
G or g
• An inverse
Resistance 1/R or 1/r
 On a MOSFET this
slope is called the
“Drain Resistance, rd
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Refined Small Signal Model
 The KCL Equation for the model
that accounts for the
id  g m v gs
upward iD Slope in SAT
 The Graphical Representation
vds

rd

vds

Engineering-43: Engineering Circuit Analysis
29
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
gm & rd by Calculus
 Start with Refined
Model Equation
id  g m v gs  vds rd
 ReCall
ΔI
Δi
G
& g
V
v
• G & g in Siemens
(amps per volt)
 Now let the ∆’s
approach ZERO to
make derivatives
Engineering-43: Engineering Circuit Analysis
30
 Specifically find the
slope of model eqn
when vds = 0
id  g m vgs  0 rd
 Thus di
d
 gm
g m:
dvgs
v 0
ds
 Note that the FET
operates at the Q-Pt
vDS  VDSQ  vds  VDSQ  0
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
gm & rd by Calculus
 Again use dy y

approx:
dx x
 In the this case vds =
0 implies vDS = VDSQ
so can approximate:
ΔiD
gm 
vGS v V
DS
DSQ
 This Eqn is an
approximation of a
derivation amongst
iD, vGS and vDS
Engineering-43: Engineering Circuit Analysis
31
 Again letting
iD
the ∆’s go g m 
vGS
to zero
 Recall
ΔV
Δv
R
& r
I
i
 Now in the smallsignal eqn let vgs = 0
id  g m  0  vds rd
or id  vds rd vgs 0
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Q  Pt
gm & rd by Calculus
 Solving
vds
this Eqn rd 
id
for rd
v gs  0
 In this Case
vGS  VGSQ  v gs  VGSQ  0
 Again use dy y

approx:
dx x
 Thus similar to
before
ΔvDS
rd 
iD v V
GS
Engineering-43: Engineering Circuit Analysis
32
 Thus we can write a
partial derivative for rd
vDS
rd 
 1 iD vDS Q  Pt
iD Q  Pt
 Or, as stated in the
Text Book
1
iD

rd vDS
 gd
Q  Pt
GSQ
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Example 12.3: Find gm & rd
Q-Pt →
(VDSQ, IDQ)
=
(10 V, 7.4 mA)
Also
VGSQ = 3.5 V
Engineering-43: Engineering Circuit Analysis
33
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Example 12.3: Find gm & rd
 Recall approx.
ΔiD
gm 
vGS
vDS VDSQ
 In This Example
VDSQ = 10 V
Δi D
gm 
vGS v 10V
DS
 Make a t-Table
when vDS = 10V
• See vi Graph
Engineering-43: Engineering Circuit Analysis
34
vGS
iD
4V 10.7mA
3V 4.7mA
 Thus
• ∆vGS = (4 − 3) V = 1V
• ∆iD = (10.7 − 4.7) mA
= 6mA
 Then gm:
6 mA
gm 
 6 mSiemens
1V
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Example 12.3: Find gm & rd
 Recall approx.
ΔvDS
rd 
iD
vGS VGSQ
 In This Example
VGSQ = 3.5 V
ΔvDS
rd 
iD v 3.5V
GS
 Make a t-Table
when vGS = 3.5V
• See vi Graph
Engineering-43: Engineering Circuit Analysis
35
vDS
iD
4V 6.7mA
14V 8mA
 Thus
• ∆vDS = (14 − 4) V = 10V
• ∆iD = (8 − 6.7) mA =
1.3mA
 Then rd:
10 V
rd 
 7.69 k
1.3 mA
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Example 12.3: Find gm & rd
Q-Pt →
(VDSQ, IDQ)
=
(10 V, 7.4 mA)
ΔiD
Also
VGSQ = 3.5 V
ΔvDS
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
All Done for Today
Large Scale
Resistance
Challenge
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
All Done for Today
3 & 4
Connection
nFET
Engineering-43: Engineering Circuit Analysis
38
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
Engineering 43
Appendix
Bruce Mayer, PE
Registered Electrical & Mechanical Engineer
BMayer@ChabotCollege.edu
Engineering-43: Engineering Circuit Analysis
39
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx
DC Srcs  SHORTS in Small-Signal
 In the small-signal equivalent circuit DC
voltage-sources are represented by
SHORT CIRUITS; since their voltage is
CONSTANT, the exhibit ZERO
INCREMENTAL, or SIGNAL, voltage
 Alternative Statement: Since a DC
Voltage source has an ac component of
current, but NO ac VOLTAGE, the DC
Voltage Source is equivalent to a
SHORT circuit for ac signals
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx