Engineering 43
Diodes-1
Bruce Mayer, PE
Registered Electrical & Mechanical Engineer
BMayer@ChabotCollege.edu
Engineering-43: Engineering Circuit Analysis
1
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Learning Goals
 Understand the Basic Physics of
Semiconductor PN Junctions which
form most Diode Devices
 Sketch the VI Characteristics of Typical
PN Junction Diodes
 Use the Graphical LOAD-LINE method
to determine the “Operating Point” of
NonLinear (includes Diodes) Circuits
with Resistive Loads
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Learning Goals
 Analyze diode-containing VoltageRegulation Circuits
 Use various math models for Diode
operation to solve for Diode-containing
Circuit Voltages and/or Currents
IDEAL and
 Learn The difference
PieceWise-Linear
Models
between LARGE-signal
and SMALL-Signal
Circuit Models
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Diodes are ONE-Way Devices

Diodes exhibit a form of
RECTIFICATION
•
i.e., They allows current to Flow in the
FORWARD direction, But NOT in the
REVERSE direction
– Think of a diode as a“Check-Valve”
for Electrical Current”
– The Voltage Drop Across a
Diode is Called its “Bias” Voltage


FORWARD Bias → Flow ALLOWED
REVERSE Bias → NO Flow Allowed
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Basic Concepts
 Diodes are
extremely Important
Devices as they
perform the
RECTIFICATION
operation
 Rectification means
that current can
(usually) Flow in
ONE direction, and
NOT the Other
Engineering-43: Engineering Circuit Analysis
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 The Circuit Symbol
• Notation: vD & iD
represent the
INSTANTANEOUS
diode voltage &
current
 Notice
• Anode → + terminal
• Cathode → − terminal
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Diodes are Highly NONlinear
 Note
•
•
•
•
Fairly SHARP CORNERS
FLAT Region
Changes in CONCAVITY
Three Distinct
OPERATING REGIONS
Typical RectifyingDiode V-I Curve
Rectification
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Diode Physics  Materials
• Silicon (Si) and Germanium (Ge) are the two most common
single elements that are used to make Diodes. A
compound that is commonly used is Gallium Arsenide
(GaAs), especially in the case of LEDs because of it’s large
bandgap.
• Silicon and Germanium are both group 4 elements,
meaning they have 4 valence electrons. Their structure
allows them to grow in a shape called the diamond lattice.
• Gallium is a group 3 element while Arsenide is a group 5
element. When put together as a compound, GaAs creates
a zincblend lattice structure.
• In both the diamond lattice and zincblend lattice, each atom
shares its valence electrons with its four closest neighbors.
This sharing of electrons is what ultimately allows diodes to
be build. When dopants from groups 3 or 5 (in most cases)
are added to Si, Ge or GaAs it changes the properties of
the material so we are able to make the P- and N-type
materials that become the diode.
Engineering-43: Engineering Circuit Analysis
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Si
+4
Si
+4
Si
+4
Si
+4
Si
+4
Si
+4
Si
+4
Si
+4
Si
+4
The diagram above shows the 2D
structure of the Si crystal. The
White lines represent the
electronic bonds made when the
valence electrons are shared.
Each Si atom shares one electron
with each of its four closest
neighbors so that its valence band
will have a full 8 electrons.
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
N-Type (Negative) Material
+4
+4
+4
+4
+5
+4
+4
+4
+4
When extra valence electrons are
introduced into a material such as silicon
an n-type material is produced. The extra
valence electrons are introduced by
putting impurities or dopants into the
silicon. The dopants used to create an
n-type material are Group V elements.
The most commonly used dopants from
Group V are arsenic, antimony and
phosphorus. The 2D diagram to the left
shows the extra electron that will be
present when a Group V dopant is
introduced to a material such as silicon.
This extra electron is very mobile.
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
P-Type (Positive) Material
+4
+4
+4
+4
+3
+4
+4
+4
+4
p-type material is produced when the
dopant that is introduced is from Group III.
Group III elements have only 3 valence
electrons and therefore there is an electron
missing. This creates a hole (h+), or a
positive charge that can move around in
the material. Commonly used Group III
dopants are aluminum, boron, and gallium.
The 2D diagram to the left shows the hole
that will be present when a Group III dopant
is introduced to a material such as silicon.
This hole is quite mobile in the same way
the extra electron is mobile in a n-type
material.
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
P-N Junction (Diode) Physics
 P & N Type Semi
Matls Brought
Together to form
a METALLURICAL
(seamless) Junction
 The HUGE
MisMatch in Carrier
Concentrations
Results in e− & h+
Cross DIFFUSION
Engineering-43: Engineering Circuit Analysis
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 Carrier Diffusion
• e− Diffuse in to the
P-Type Material
• h+ Diffuse in to the
N-Type Material
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
P-N Junction Physics cont.
 In a p-n JCN Carrier
Cross-Diffusion is
SELF-LIMITING
E-Field
• The e−/h+ Diffusion
leaves Behind fixed
IONIZED Atom
Cores of the
OPPOSITE Charge
• The Ion Cores set up
an ELECTRIC FIELD
that COUNTERS the
Diffusion Gradient
Engineering-43: Engineering Circuit Analysis
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 For Si the Field-Filled
Depletion Region
• E-Field  1 MV/m
• Depl Reg Width,
xd = 1-10 µm
• E-fld•dx  0.6-0.7 V
– “built-in” Potential
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
P-N Junction Rectifier
 A Rectifier is a
“Check Valve” for
Current flow
• Current Allowed in
ONE Direction but
NOT the other
E-Field
 Side Issue →
“Bias” Voltage
• A “Bias” Voltage is
just Another name
for EXTERNALLY
APPLIED Voltage
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
P-N Junction Rectifier cont
 p-n junction
Rectification
• A small “Forward
Bias” Voltage results
in Large currents
• Any level of
“Reverse” Bias
results in almost NO
current flow
 Class Q:
• For Fwd Bias, Which
End is +; P or N???
Engineering-43: Engineering Circuit Analysis
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E-Field
 A: the P end
• The Applied Voltage
REDUCES the
internal E-Field; This
“Biases” The
Junction in Favor of
DIFFUSION
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
P-N Junction Rectifier cont.2
• Internal Field
ENHANCED
 p-n junction 
No Applied Voltage
– Carriers Pulled AWAY
from Jcn; xd grows
Xd
 Forward Bias
• Diffusion & E-Field in
Balance, No Current
Flows
 Reverse Biased
Engineering-43: Engineering Circuit Analysis
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• Internal Field
REDUCED
– Carriers PUSHED and
Diffuse to the Jcn
where they are
“injected” into the other
side; xd Contracts
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Properties of Rectifying Junctions
Reverse
Forward
 IN914 PN Diode
• IF = 75 000 µA
• IR = 0.025-50 µA
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
The BIASED P-N Junction
 “Bias” Simply refers to whether the PN
Junction will allow current to flow or not
• Forward Bias: Vapplied > 0 (Anode Positive)
– In forward bias the depletion region shrinks slightly in
width. With this shrinking the energy required for
charge carriers to cross the depletion region decreases
exponentially. Therefore, as the applied voltage
increases, current starts to flow across the junction.
The barrier potential of the diode is the voltage at
which appreciable current starts to flow through the
diode. The barrier potential varies for different
materials.
Bruce Mayer, PE
 The Barrier Potential for Silicon is 0.6-0.7 volts
Engineering-43: Engineering Circuit Analysis
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BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
The BIASED P-N Junction
 “Bias” Simply refers whether the PN Junction
will allow current to flow or not
• Reverse Bias: Vapplied < 0 (Anode Negative)
– Under reverse bias the depletion region widens. This
causes the electric field produced by the ions to cancel
out the applied reverse bias voltage. A small leakage
current, Is (saturation current) flows under reverse bias
conditions. This saturation current is made up of
electron-hole pairs being PRODUCED in the
depletion region. Saturation current is sometimes
referred to as the scale current because of it’s
relationship to junction temperature
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Small-Signal Diode
iD
IS
(mA)
• vD ≡ Bias Voltage
• iD ≡ Current through
Diode. iD is
• Negative for
Reverse Bias
• Positive for Forward
Bias
Knee
VBR
~V
vD
• IS ≡ Saturation
Current
• VBR ≡ Breakdown
Voltage
• V ≡ Barrier, or
Knee, Potential
Voltage
(nA)
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
A
Rectifying
Diode
Data
Sheet
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
1N914
Data
Sheet
Page-1
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
1N914
Data
Sheet
Page-2
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Anode is P-Side
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Diode Macro Behavior
 The Knee Voltage,
𝑉𝜙 , is typically
about 0.6-0.7 V
 In the REVERSE
Bias Range, the
current, IS, is on the
order of nA to µA,
depending on the
SIZE of the diode
 Temperature
Sensitivity
dV
2 mV

dT
K
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Diode Model  Shockley Eqn
 The TransConductance (vD,iD) curve on
the previous slide is
  v  
characterized by the iD  I s e nV   1


SHOCKELY equation:


D
T
• Where
– Is ≡ Reverse Bias SATURATION Current
– n ≡ emission coefficient (sometimes called the
“diode quality factor”)
– VT ≡ Thermal Voltage: VT
 kT q
 k ≡ Boltzmann’s constant (1.38x10−23 J/K)
 q ≡ Charge on an electron (1.6x10−19 Coul)
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Diode Model  Shockley Eqn
 Note the Shockely Eqn does NOT
predict Reverse-Bias BreakDown
 Also when vD is Large and Negative
  v D  
nV
iD  I s e T   1  iD  I s e  10  1  I s  0  1   I s






• But we saw from the vi curves that Is is
NOT constant
• Also reverse Bias Currents are
often much larger than Is
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Diode Model  Shockley Eqn
 when vD is Large and Positive
e
 vD

 nVT



 1  e
 vD

 nVT



1  e
 vD

 nVT



 iD  I s e
 vD

 nVT



• At 300k VT ≈ 26 mV
• if vD = 0.2V (200 mV),  200mV 
 1.526mv 
e
 168.7
and n ≈ 1.5 Then
 Thus the simplified Eqn is quite
accurate in the FORWARD-Bias Region
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Diode Model  Shockley Eqn
 Finally If we know iD & IS then we can
 iD 
solve the Shockely
vD  nVT ln   1
Equation for vD
 Is 
• Note that this eqn is NOT defined for
Negative Diode currents and thus
applies only to the
Forward Bias Region
vD by Schockely Eqn
450
400
350
vD (mV)
 For n = 1.5,
Is = 25 µA
300
250
>> iD = linspace(0,1000,500); % in mA
>> vD = n*VT*log(iD/Is +1);
>> plot(iD,vD)
>> plot(iD,vD, 'LineWidth', 3), grid,
xlabel('iD (mA)'), ylabel('vD (mV)'),
title('vD by Schockely Eqn')
200
150
100
50
0
Engineering-43: Engineering Circuit Analysis
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0
100
200
300
400
500
600
700
800
900
iD (mA)Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
1000
Example: Exercise 10.2
 Consider a diode
under Fwd-Bias so
 vD 
that this Eqn


 nVT 
applies: iD  I s e
 In this case
• VT = 26 mV
• n=1
 Find ∆vD so that the
current iD 2
Doubles: i  2
 By Fwd Bias eqn
 v D  v D

 nVT



iD 2 I s e

2
 vD 
iD1


nV
I s e T 
 Cancelling Is and
dividing the
exponential
e
 v D  v D v D


nVT
 nVT



e
 v D

 nVT
D1
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx



2
Example: Exercise 10.2
 Taking the ln of both
sides of the last eqn
  v D  
 nVT  

ln e
 ln 2




 Thus
v D
 ln 2
nVT
 Then
v D  ln 2nVT
Engineering-43: Engineering Circuit Analysis
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 Recalling Values for
n & VT
v D  ln 2  1  26mV
 18.02 mV
 Next, Find ∆vD so
that the current
increases 10X
 In the above eqn
replace 2 with 10
v D  ln 10  1  26mV
 59.9 mV
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
ZENER Diodes
 “Zeners” exploit the
reverse-bias BreakDown to effect
Voltage Regulation
 A typical vi curve
 Vz is specified
explicitly
 The Rev-Bias BrkDwn portion of the vi
curve is designed to
be as VERTICAL as
possible
 Ckt Designers use
Zeners to Regulate
(or pin) a voltage
point at certain level
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Zener Diode Voltage Regulation
 A Typical Zener Ckt

V “Pinned at Vref

Engineering-43: Engineering Circuit Analysis
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A Zener diode is used in this
circuit to regulate the voltage of
the current supply provided by
V+ to the desired Vref voltage
required by this IC circuit. The
small size and low cost of the
Zener (compared to other
techniques, such as a linear
regulator or reference chip)
make it ideal in this type of
application.
Note that This solution would
NOT work in an application with
a very high V+ (forcing the
Zener device to dissipate more
than a few watts).
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Source-Resistor vs Diode LoadLine
 When We analyzed
 The NONlinear
LINEAR DC Circuits,
problem can be
we arrived at Linearsolved
Algebra Equations
NUMERICALLY
(e.g. MATLAB fzero)
• i.e.; n-Eqns in
n-Unknowns
 But the Diode vi
curve is highly nonLinear, so the
previous methods
do NOT apply
Engineering-43: Engineering Circuit Analysis
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 OR it can be solved
GRAPHICALLY
using so-called
Load-Line Analysis
• IF the powering ckt is
LINEAR
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Digression: LINEAR Devices
 V-Source:VS  0  i  VS
 I-Source: I S  0  v  I S
 0 x  b
 0 x  b
 Resistor: iR  GvR or vR  RiR
 m x  0
 Capacitor: iC  C  dvC dt   0  mx   0
 Inductor: vL  L  diL dt   0  mx   0
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Source-Resistor-Diode LoadLine
 The simplest
LoadLine analysis is
a SERIES Circuit
with
 vR

• A Power Source
(usually Voltage)
• A controlling element
(in this case a diode)
• A Resistive Load
 A pictorial
Representation
Engineering-43: Engineering Circuit Analysis
34
 By ohm VSS  vR  vD
& KVL
 RiD  vD
 We need to find iD
and vD
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Source-Resistor-Diode LoadLine
 From the KCL eqn
Notice for the
Resistor
 vR

VSS  Ri D  vD
• If iD=0, then vD = VSS
• If vD=0, then
iD = VSS/R
Engineering-43: Engineering Circuit Analysis
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 Plotting these two
(vD,iD)points on a
vD-iD curve produces
a STRAIGHT-line
that describes the
Resistor Behavior
 The Diode Curve
can plotted on top
of the Resistor curve
• The Crossing Pt is
the solution, or
OperatingBrucePoint
Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Constructing the LoadLine
 Recall the the KCL Eqn: VSS  Ri D  vD
 Taking iD as the dependent Variable
VSS
1
iD   v D 
R
R
of form
y  mx  b
 The above Eqn is a straight line
 Need only Two Points to construct the
circuit operating line
vD
iD
Pt
(load line) so make
B
0 Vss/R
a “T-Table”
A
Vss
0
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
LoadLine graphic Conceptually
(Also Called Quiescent, or Q, Point)
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Vsrc + Resistor + Diode Math
VSS
1
 Recall
iD   v D 
R
R
Eqn for iD:
 v 




 Also the
 nV 

iD  I s e
 1
Shockley Eqn:


D
T


 vD 




 Equating
vD V SS
 nVT 

 
 Is e
 1
the iD’s:
R
R




 The Equation is TRANSCENDTAL in vD
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Vsrc + Resistor + Diode Math
 For use in MATLAB fzero  Collect all
terms on one side of Eqn:
 vD 




vD V SS
 nVT 

 
 Is e
 1  0
R
R




 Note that the Eqn has been “ZeroED”
 If we know R, n, VT, and VSS (vD is the
unknown) then we can create an
anonymous function for input into fzero
Engineering-43: Engineering Circuit Analysis
39
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Load Line Example
 Consider Ckt
8.3 Ω
1.5 V
• IS = 2x10−14 amps
• n = 1.5
 Plot Load-Line and
Diode Curve on
Same Graph yields
the operating point
LoadLine Analysis
200
180
140
120
iD (mA)
 For the Diode Use
the Shockely Eqn in
Fwd Bias with
160
100
80
60
40
20
0
0
0.5
1
vD (volts)
Engineering-43: Engineering Circuit Analysis
40
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
1.5
LoadLine Example  Q-pt
LoadLine Analysis
200
180
160
140
iD (mA)
120
100
80
60
≈4340
20
0
0
Engineering-43: Engineering Circuit Analysis
41
0.5
1
vD (volts)
≈1.15
1.5
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Check Answer by MATLAB
 MATLAB Code
 MATLAB Results
% Bruce Mayer, PE
% ENGR43 * 07Jan12
% LoadLine_Example_120107.m
%
Is = 2E-14 % Amps
n = 1.5
vD = linspace(0,1.2,500); % 0-1.2V
iD = Is*(exp(vD/(n*VT)-1)); % in Amps
R = 8.3; % ohms
Vss = 1.5 % Volts
vR = [0, 1.5] % Resistor Voltage Pts
iR = [Vss/R, 0] % Resistor Current Pts
%
% plot in mA
plot(vD, 1000*iD, vR, 1000*iR, 'LineWidth',3),
grid,...
xlabel('vD (volts)'), ylabel('iD (mA)'),
title('LoadLine Analysis')
%
% Solve Numerically as check
% fcn to Zero
Zfcn = @(x) -x/R+Vss/R - Is*(exp(x/(n*VT)-1))
vDQ = fzero(Zfcn,1.1)
iDQma = 1000*(-vDQ/R+Vss/R)
vDQ =
1.1461
iDQma =
42.6349
 Thus the Graphical
Estimate is quite
good for the Q
Point.
Engineering-43: Engineering Circuit Analysis
42
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Zener V-Reg Load Line Analysis
 A regulating Circuit
 Solving for iD again
yields the LoadLine
VSS
1
iD   v D 
R
R
• Note that the Zener
LoadLine has a
NEGATIVE y-intercept
 The LoadLine T-table
 By KVL
vD  Ri D  VSS  0
Engineering-43: Engineering Circuit Analysis
43
Pt
vD
iD
B
0
−Vss/R
A
−Vss
0
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Example 10.3  Zener Reg
• R = 1 kΩ
• Could find Zener
Diode vi curve from
the Data Sheet
 Analyze this Ckt for
OutPut is the
Diode Voltage
• VSS,lo = 15V
• VSS,hi = 20V
Engineering-43: Engineering Circuit Analysis
44
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Example 10.3  Zener Reg
Pt
vD
iD
Blo
0
−15 mA
Alo −15 V
Bhi
0
Ahi −20V
0
−20 mA
0
Engineering-43: Engineering Circuit Analysis
45
VSS
1
iD   v D 
R
R
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Check Sensitivity of Zener LL
 Find
dvD
vD  10   10.5V


 15   20V
dVSS VSS
dvD 0.5 V

 10%
dVSS
5 V
 Thus, for example, a
4V change in the
Input, VSS, results in
only a 0.4V change
in the OutPut, vo
Engineering-43: Engineering Circuit Analysis
46
 Most REAL Zeners have
much STEEPER DownSlope than that shown in
the Book, so they have
much BETTER output
Sensitivity
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Complicated Circuit LL Analysis
 Any LINEAR Circuit, no matter how
complicated allows Diode LoadLine
Analysis to determine the Q-Point
 Recall that ANY linear ckt can be
“Thévenized” into a V-src and Series
resistance or impedance
 Thus to use the LL on this type of Ckt,
simply disconnect the Diode, Thévenize
the LINEAR ckt-fragment and then
reconnect the Diode
Engineering-43: Engineering Circuit Analysis
47
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Complicated Circuit LL Analysis
 The Thévenization
process concept
 Put into y = mx+b
form to produce the
LoadLine (iD is
dependent variable)
 1
iD   
 RT
 Then by Ohm & KVL
(ClockWise current)
as before
RT iD  vD  VSS  0
Engineering-43: Engineering Circuit Analysis
48

VSS
vD 
RT

 Now can apply the
normal LoadLine
Methods
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Example: Thévenization
 Given Ckt
 Now Detach the
NONlinear element
(the Diode) and
Thévenize
 Find Q-point Given
Zener vi Curve
←VT
 First Redraw
←RT
Engineering-43: Engineering Circuit Analysis
49
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Example: Thévenization
 For VT have simple
Voltage-Divider
6
VT  24V 
 20V
6  1.2
 Since have INDEP
Src find RT by
Source DeActivation
←VT
←RT
 Now ReAttach Diode
for LoadLine Ckt
• Setting 24V Src = 0
6kΩ 1.2kΩ
RT 
 1kΩ
6  1.2kΩ
Engineering-43: Engineering Circuit Analysis
50

vD

iD
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Example: Thévenization
 Then KVL on the
Thévenized Ckt
VSS
1
iD   v D 
R
R

1
20V
iD  
vD 
1kΩ
1kΩ
 Then the T-Table
Pt
vD
iD
B
0
−20 mA
A
− 20 V
 The Q-Point is then
the Intersection of
the Line and Curve
• See next slide
0
Engineering-43: Engineering Circuit Analysis
51
 Next Draw this
LoadLine on the
Same Graph as the
Zener vi Curve
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Example: Thévenization
 Thus the Operating, or Q,
Point for the Thevenized
Ckt
• vD = −10 V
• iD = −10 mA
Engineering-43: Engineering Circuit Analysis
52
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Example: Thévenization
 Also Find the
ORIGINAL Source
Current
 Note that vL =
−vD = +10V
IS 

10V

Engineering-43: Engineering Circuit Analysis
53
 Using KCL and Ohm
Find

24  10 V
IS 
 11.67 mA
1.2 kΩ
 Then the Source
Power
PS  VS I S  24V 11.67 mA
PS  280 mW
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
All Done for Today
William
Bradford
Shockley
 Born February 13, 1910 • London, England
 Died August 12, 1989 (aged 79) • Stanford, CA
Engineering-43: Engineering Circuit Analysis
54
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Engineering 43
Appendix
Diode vi Curves
Bruce Mayer, PE
Registered Electrical & Mechanical Engineer
BMayer@ChabotCollege.edu
Engineering-43: Engineering Circuit Analysis
55
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Fig 10.8 Diode characteristic
for Exercise 10.3
Engineering-43: Engineering Circuit Analysis
56
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Figure P10.20
for HW
Reference
Engineering-43: Engineering Circuit Analysis
57
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx
Vsrc + Resistor + Diode Math
 For use in MATLAB fzero  Multiply
Both sides by R/vD:
 vD 






R
 vD V SS

nVT 

 I s e
 1 
 
R

  vD
 R


 Yields
V SS
1
vD
Engineering-43: Engineering Circuit Analysis
58
 vD 

RI s  nVT  
e

 1
vD 



Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-10a_Diode-1_Physics_LoadLine.pptx