Engineering 43
Series/Parallel,
Dividers,
Nodes & Meshes
Bruce Mayer, PE
Licensed Electrical & Mechanical Engineer
BMayer@ChabotCollege.edu
Engineering-43: Engineering Circuit Analysis
1
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
OutLine
 Equivalent Resistance:
• SERIES Connection by KVL & Ohm
• PARALLEL Connection by KCL & Ohm





Combining Resistors
VOLTAGE Divider by KVL & Ohm
CURRENT Divider by KCL & Ohm
Multi ↔ V-Sources by KVL & Ohm
Multi || I-Sources by KCL & Ohm
Engineering-43: Engineering Circuit Analysis
2
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
OutLine
 Rat’s Nest UNTANGLING
• Be FAITHFUL to the
NODES
 NODE Analysis for Vk by
KCL & Ohm
• Always define a GND (V=0)
Node; picked by the Engr
 LOOP Analysis for Ik by
KVL & Ohm
Engineering-43: Engineering Circuit Analysis
3
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
GamePlan HiPoints
 Combine Resistors
• Series
• Parallel
 Electrical “Dividers”
• Voltage
• Current
 Source Addition
• V in Series
• I in Parallel
 UnTangling
 NODE-Voltage
analysis
• by CURRENT Law
 LOOP-Current
analysis
• By VOLTAGE Law
 Linear Alegbra
• MATLAB
 GND Node
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
ReCall KVL and KCL
 Kirchoff’s VOLTAGE
Law → ∑V-Drops
around ANY Closed
Loop = 0
•
𝑉𝐷𝑟𝑜𝑝
𝐶𝐿
𝐼𝑖𝑛 +
𝐼𝑜𝑢𝑡
Engineering-43: Engineering Circuit Analysis
5

𝑛𝑑

1
24V
+
-
3
2
18V

2A

=0
−24V + 6V +18V = 0
 Kirchoff’s
CURRENT Law →
For ANY Node
∑Iin = ∑Iout
•
2 A  6V 
=0
I  2 A
a
2A
I
b
I cb  4 A
I ab  3A
c
3A
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Series Parallel
 Up To Now We Have Studied Circuits That
Can Be Analyzed With One Application Of
KVL Or KCL
 We will see That In Some Situations It Is
Advantageous To Combine Resistors To
Simplify The Analysis Of A Circuit
 Now We Examine Some More Complex
Circuits Where We Can Simplify The Analysis
Using Techniques:
• Combining Resistors
• Ohm’s Law
Engineering-43: Engineering Circuit Analysis
6
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Resistor Equivalents
 Series
• Resistors Are In Series If They
Carry Exactly The Same Current
RS  R1  R2  R3    RN
 Parallel
• Resistors Are In Parallel If
They have Exactly the
Same Potential Across Them
1
1
1
1
1
 


RP R1 R2 R3
RN
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Conductance Equivalents
 ReCall: G = 1/R
RS  R1  R2  R3    RN
 For SERIES

Connection
1
1
1
1
1
GS

G1

G2

G3

GN
GS = 1.479 S
1
1
1
1
1






 For PARALLEL RP R1 R2 R3
RN
Connection

GP = 15 S
Engineering-43: Engineering Circuit Analysis
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GP  G1  G2  G3    GN
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Combine
Resistors;
UnTangle
Example:
Find RAB
3k
SERIES
6k||3k = 2k
(10K,2K)SERIES
6k || 12k  4k
(4K,2K)SERIES
6k || 6k  3k
5k
4k || 12k  3k
Engineering-43: Engineering Circuit Analysis
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(3K,9K)SERIES
12k
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
More Examples
 Step-1: Series
Reduction
 Step-2: Parallel
Reduction
18k || 9k  6k
9k
9 kΩ
6k  6k  10k
 22 k
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Example w/o ReDrawing
12k || 12k  6k
12k
6k || (4k  2k )
3k || 6k  2k




Step-1: 4k↔8k = 12k
Step-2: 12k 12k = 6k
Step-3: 3k 6k = 2k
Step-4: 6k (4k↔2k) = 3k = RAB
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Series-Parallel Resistor Circuits
 Combing Components Can Reduce The
Complexity Of A Circuit And Render It
Suitable For Analysis Using The Basic
Tools Developed So Far
• Combining Resistors In SERIES Eliminates
One NODE From The Circuit
• Combining Resistors In PARALLEL
Eliminates One LOOP From The Circuit
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
S-P Circuit Analysis Strategy
 Reduce Complexity Until The Circuit
Becomes Simple Enough To Analyze
 Use Data From Simplified Circuit To
Compute Desired Variable(s) In Original
Circuit
• Hence Must Keep Track Of Any
Relationship Between Variables
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Example – Ladder Network
 Find All I’s & V’s in Ladder Network
• 1st: S-P Reduction
4k || 12k
12k
• 2nd: S-P Reduction
6k
– Also by Ohm’s Law
Va
I2 
6k
Vb  3k  I 3
Engineering-43: Engineering Circuit Analysis
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I3
6k || 6k
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Ladder Network cont.
• Final Reduction; Find Calculation Starting
Points
12V
I1 
 1.0mA
9k  3k
Va  3k 1.0mA  3V
• Now “Back Substitute” Using KVL, KCL,
and Ohm’s Law
– e.g.; From Before and Using Ohm & KCL
Va
3V
 I 2  6k  6k  0.5mA I1  I 2  I 3  I 3  0.5mA
Vb  3k  I 3  Vb  1.5V 
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx

The Voltage Divider
 Ohm’s Law
vR1  R1it 
KVL ON
THIS
LOOP
vR2  R2i t 
 Ohm’s Law in KVL
vt   R1it   R2it 
vt   R1  R2  it 
vt 
 Find 𝑖 𝑡 by  i t  
R1  R2
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Voltage Divider cont.
 Now Sub 𝑖 𝑡 Into Ohm’s
Law to Arrive at The
Voltage Divider Eqns
KVL ON
THIS
LOOP
 vt  
 vt  
vR1  R1 i t   R1 
 and vR2  R2 i t   R2 

R

R
R

R
2
2
 1
 1
 Quick Chk → In Turn, Set R1, R2 to 0
 vt  
 vt  
R1  0  vR1  0

0
and
v

R
R2
2

  vt 
 0  R2 
 0  R2 
 vt  
 vt  


R2  0  vR1  R1 

v
t
and
v

0
R2


0
 R1  0 
 R1  0 
Engineering-43: Engineering Circuit Analysis
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

Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
V-Divider Summary
 Governing Equations
R1
vR1 
v(t )
R1  R2
vR2 
R2
v(t )
R1  R2
• The Larger the R, The Larger the V-drop
 Example
• Gain/Volume Control
– R1 is a Variable
Resistor Called a
Potentiometer, or
“Pot” for Short
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Volume Control Example
• Case-I → R1 = 90 kΩ
 R2 
V2  
 v(t )
 R1  R2 
30k


V2  
9V  2.25V

 90k  30k 
9V
• Case-II → R1 = 20 kΩ
30kΩ
 R2 
V2  
 v(t )
 R1  R2 
30k


V2  
9V  5.4V

 20k  30k 
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Practical Example  Power Line
 Using Voltage Divider
Vload


183.5 Ω
 
 400 kV


183.5

16.5
Ω


 367 kV
Also
Pload  I 2 Rload 
Pload  2 kA   183.5    734 MW
2
 Power Dissipated by the Line is a LOSS
Pline-LOSS  Psrc  Pload  I 2 Rline 
Pline  2 kA   16.5    66 MW
2
Engineering-43: Engineering Circuit Analysis
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8.25% of Pwr Generated is
Lost to Line Resistance!
* How to Reduce Losses?
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Equivalent Circuit
 The Equivalent Circuit Concept Can
Simplify The Analysis Of Circuits
• For Example, Consider A Simple
Voltage Divider
– As Far As The
Current Is
Concerned Both
Circuits Are
Equivalent
i
vS
R1
i
vS
+
-
R2
i
+
-
vS
R1  R2
 The One On The Right Has Only One Resistor
SERIES Resistors →
Engineering-43: Engineering Circuit Analysis
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R1
R2

R1  R2
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
R1  R2
Schematic vs. Physical
 Sometimes, For Practical Construction
Reasons, Components That Are Electrically
Connected May Be Physically Quite Apart
• Each Resistor Pair Below Has the SAME
Node-to-Node Series-Equivalent Circuit
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
CONNECTOR SIDE
ILLUSTRATING THE DIFFERENCE
BETWEEN PHYSICAL LAYOUT AND
ELECTRICAL CONNECTIONS
PHYSICAL NODE
PHYSICAL NODE
PHYSICAL NODE
SECTION OF 14.4 KB VOICE/DATA MODEM
CORRESPONDING POINTS
COMPONENT SIDE
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Generalization  Multiple v-Sources
– Voltage Rises Are
SUBTRACTED From Drops

v5
R1
i(t)
R2

 v4 
 Apply KVL
vR1  v2  v3  vR 2  v4  v5  v1  0
Engineering-43: Engineering Circuit Analysis
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
v3

+ -
• We Select The Reference
Direction To Move Along
The Path
+
-
+
-
1
+ +
-
 Voltage Sources In Series

Can Be Algebraically
v
Added To Form An

Equivalent Source
 v2 
 v R1 
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx

vR2

Multiple v-Source Equivalent
 Collect All SOURCES On One Side
v1  v2  v3  v4  v5   vR1  vR 2
v   v
eq
R1
 vR 2
R1
 The Equivalent Circuit:
• V-source in Series
veq
R2
+
-
ADD directly
Engineering-43: Engineering Circuit Analysis
25
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Generalization  Mult. Resistors
 Apply KVL (rise = Σdrops)
 Now by Ohm’s Law
KVL
 And Define RS
 Then Voltage Division For Multiple Resistors
vRik  Rk i t   vR
k
• [Rk/RS] is the Divider RATIO
Engineering-43: Engineering Circuit Analysis
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 Rk 
    vt 
 RS 
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Example
 Find: I, Vbd, P30kΩ

 Apply KVL & Ohm
APPLY KVL
TO THIS
bd LOOP
V
 Solving for I

 Now VbdNo by RED loop: Vbd  12  20 [k ] I  0
Vbd  12  20 [k ]  0.1  12  2
So by KVL  Vbd  10V
 Finally, The 30 kΩ Resistor Power Dissipation
P  I 2 R  (104 A) 2 (30 103 )  30 104 W  300W
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Examples
 Find: I, Vbd
APPLY KVL
TO THIS LOOP
• Use KVL and Ohm’s Law
 6  80kI  12  40kI  0  80  40 k  I  6  12 V  I  0.05mA
Vbd  40k I    12V   0  Vbd  12V  40k  0.05mA  12  2 V  10V
 Find VS by V-Divider
• The V20k Divider Eqn

20
3V  VS
25  15  20
3V
• Solving for VS
Engineering-43: Engineering Circuit Analysis
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
25  15  20
VS 
3  9V
20
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
When In Doubt → ReDraw
 From The Last Diagram
It Was Not Immediately
Obvious That This Was
a V-Divider Situation
• UnTangle/Redraw at Right
20
Vad 
VS  3V
20  15  25
or
20  15  25
20  15  25
VS 
Vad 
3V  9V
20
20
• When Untangling be FAITHFUL to Nodes
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Single Node-Pair (SNP) Circuits
OF SINGLE
 EXAMPLE
SNP Example
 SNP Circuits Are
Characterized By
ALL the Elements
Having The SAME
VOLTAGE Across
Them → They Are
In PARALLEL
NODE-PAI

V


This Element is INACTIVE
V • The InActive Element

Engineering-43: Engineering Circuit Analysis
30
Has NO Potential Across
it → SHORT Circuited
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
UnTangling Reminder
 Nodes Can Take STRANGE Shapes
NODE →
A region of
Constant
Electrical
Potential
Low
Distortion
Power
Amplifier
Engineering-43: Engineering Circuit Analysis
31
e.g.; a group
of
connected
WIRES is
ONE Node
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
LOW VOLTAGE POWER SUPPLY FOR CRT - PARTIAL VIEW
SOME PHYSICAL NODES
Engineering-43: Engineering Circuit Analysis
32
COMPONENT SIDE
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
CONNECTION SIDE
The Current Divider
 Basic Circuit
APPLY KCL
 The Current i(t)
Enters The Top
Node then Splits, or
DIVIDES, into the
the Currents
i1(t) and i2(t)
Engineering-43: Engineering Circuit Analysis
33
 Apply KCL at Top
Node
 Use Ohm’s Law to
Replace Currents
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
The Current Divider cont.
 Basic Circuit
1
it  
vt 
Rp
Rp
vt  
 By KCL & Ohm
R1 R2
i t 
R1  R2
 The Current Division
𝑖2 𝑡 = 𝑣𝑅𝑡
1
=𝑅 𝑣 𝑡
2
2
𝑖1 𝑡 = 𝑣𝑅𝑡
1
=𝑅 𝑣 𝑡
1
1
𝑖1 𝑡 = 𝑅1
𝑅1 𝑅2
𝑖 𝑡
1 𝑅1 +𝑅2
𝑅2
𝑖
𝑡
=
1
𝑅1 +𝑅2 𝑖
 Define PARALLEL
𝑡
𝑖2 𝑡 = 𝑅1
𝑖2 𝑡 =
𝑅1 𝑅2
𝑖 𝑡
𝑅
+𝑅
2 1
2
𝑅1
𝑖 𝑡
𝑅1 +𝑅2
Resistance
Engineering-43: Engineering Circuit Analysis
34
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Current Divider Example
 For This Ckt Find:
I1, I2, Vo
 When in doubt…
REDRAW the circuit
to Better Visualize
the Connections
 By I-Divider
Vo  I 2  80kΩ
 24V
2-Legged
Divider is
more
Evident
Engineering-43: Engineering Circuit Analysis
35
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Real World Example
 Car Stereo and Circuit Model
215mA
 Use I-Divider to Find
Current thru the 4Ω
Speakers
215mA
 Thus the Speaker
Power
 Power Per Speaker
by Joule
Engineering-43: Engineering Circuit Analysis
36
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Current & Power Example
KCL
 For This Ckt Find:
• I 1, I 2,
• P40k  Power
ABSORBED by
40 kΩ Resistor
 By I-Divider
120
16mA
I1 
120  40
 12mA
 Find I2 by I-Divider
OR KCL
• Choose KCL
Engineering-43: Engineering Circuit Analysis
37
I 2  I1  16mA  I 2  12  16 mA
 I 2  4mA
 The 40k Power by I2∙R
P40k  12mA 40k 
2
 milli   k   milli
P40k  5760mW  5.76W
2
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Generalization: Multi 𝒊-Sources
 Given Single Node-Pair Ckt w/ Multiple Srcs
KCL
 KCL on Top Node:
 Combine Src Terms
(be sure exclude R
Terms) To Form The
Equivalent Source
Engineering-43: Engineering Circuit Analysis
38
 The Equivalent Ckt
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Generalization: Multi 𝒊- Sources
 By Analysis and Electrical Physics of
KCL 
i1  i3  i4  i6  iO
=
 Thus CURRENT Sources in PARALLEL
ADD directly
• Compare to VOLTAGE Sources in SERIES
which also ADD Directly
Engineering-43: Engineering Circuit Analysis
39
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
𝒊-Source Example
 For This Ckt Find
Vo, and the
Power Supplied
by the I-Srcs 10mA
6k 
3k 
15mA

VO

 Combine Srcs to
 Vo by Ohm’s Law
Yield Equivalent Ckt V  R I  2k  5mA   10V
o
p Src


Use
PASSIVE
SIGN
R
V
Convention for Power
p

5mA
Rp 
6k * 3k
 2 k
6k  3k
Engineering-43: Engineering Circuit Analysis
40
O
P10m  10V 10mA   100mW
P15m  10V  15mA 
 150mW
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Generalization: Multi Resistors
 Given Single Node-Pair Ckt w/ Multiple R’s
vt   R p io t  

iK t   vt  RK 
iK t  
Rp
RK
io t 
 KCL on Top Node:
 The Equivalent
Resistance & v(t)
N
1
1

R p K 1 RK
vt   io t   R p
Engineering-43: Engineering Circuit Analysis
41
Ohm’s Law at
Each Resistor
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
KCL
Multi-R Example
 For This Ckt Find
i1, and the
Power Supplied
by the I-Source 8mA
 Find Rp
1
1
1
1



R p 4kΩ 20kΩ 5kΩ
5 1 4
1


20kΩ
2kΩ
 R p  2kΩ
Engineering-43: Engineering Circuit Analysis
42
i1
4k
20k
5k
 Recall the General
Current Divider Eqn
vt   R p io t  

iK t   vt  RK 
iK t  
Rp
RK
io t 
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Multi-R Example cont.
 Find i1, by Divider
• Take Care with
Passive Sign Conv
2kΩ
8mA   4mA
i1 
4kΩ
 Find v for SingleNode-Pair by Ohm
v  isrc R p
 8mA 2kΩ   16V
 Find Psrc by v•i
Engineering-43: Engineering Circuit Analysis
43
i1
4k
20k
5k
8mA
Psrc  visrc

v

  16V 8mA   128mW
• Note: this time For
Passive Sign
Convention CURRENT
Direction assigned
as POSITIVE
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Multi-R: Alternative Approach
 Start by
Combining R’s
NOT associated
8mA
with i1
 The Ckt After the
R-Combination
i1
4k
4k
8mA
Engineering-43: Engineering Circuit Analysis
44
20k||5k
i1
4k
20k
5k
 Now Have 1:1 Current
Divider so
4kΩ
i1 
isrc
4kΩ  4kΩ
1
i1  isrc  4mA
2
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Example: Multi-R, Multi-Isrc SNP
 Given Single Node-Pair Ckt: Find IL
 Soln Game Plan:
Convert The
Problem Into A
Basic CURRENT
DIVIDER By
Combining Sources
And Resistors
Engineering-43: Engineering Circuit Analysis
45
 Combine Sources
• Assume DOWN =
POSITIVE
I S ,eq
I S ,eq  1mA  4mA  2mA
 1mA
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Multi-R, Multi-Isrc SNP cont.
 Given Single Node-Pair Ckt: Find IL
 Next Combine
Parallel Resistors
 IL by 3:1 I-Divider
 Then the Equivalent
Circuit →
Engineering-43: Engineering Circuit Analysis
46
Note MINUS Sign
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
I1
6k
6k
I2
C
B
3k
3k
9mA
The SAME Ckt
Can Look
Quite Different
I1  3 99mA   3mA
A
I 2   I1  3mA
I1
B
6k
C
6k
3k
I2
6k
9mA
A
3k
I1
B
C
3k
9mA
3k
6k
A I2
Engineering-43: Engineering Circuit Analysis
47
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
UnTangling Utility
 Redrawing A Circuit May, Sometimes, Help To
Better Visualize The Electrical Connections
6k
I1
6k
B
I2
C
B
3k
I1
9mA
3k
A
A
• Be FAITHFUL to the
Node-Connections
Engineering-43: Engineering Circuit Analysis
48
6k
I2
6k
3k
C
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
3k
Another Example
 For This Ckt
Find the I-Src
Power, P20
+
2k
 Alternatives for P
P20   V I  V 20mA 
• By Joule and
Energy Balance
P20   PR j  RP 20mA 
2
49
3k
20mA
 Use ||-Resistance
• By vi & passive sign:
Engineering-43: Engineering Circuit Analysis
4k V
_
1
1
1
1



R p 2kΩ 4kΩ 3kΩ
63 4
12

 R p  kΩ
12kΩ
13
2
P20  12 13 k 20mA 
4800
P20 
mW supplied
13
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Game Plan  02Feb16
 File: ENGR-43_Lec-02a_Sp16_SP_VIDivide_NodeMesh.pptxPassive Sign
Convention: Current & Voltage-Drop
• Slides 51-55 → Analyze “Ladder” NetWork
by Combining Resistors & Sources
– This is a review from 26Jan16
• Definition of Methods that Produce a Linear
algebra eqn of the form 𝐆𝑣 = 𝑖 or 𝐑𝑖 = 𝑣
• WhiteBd Examples of the Linear Alg Methods
– KCL → Voltage-Node Analysis
– KVL → Current In/Out Analysis
Engineering-43: Engineering Circuit Analysis
50
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Game Plan  02Feb16
 After NODE and MESH/LOOP White
Board Examples Go to
 ENGR-43_Lec02b_Sp16_SuperNM_TheveninNorton.pptx → Cover
• Super Nodes & Super Meshes
– Start at Slide 12
– End at Slide 38
Engineering-43: Engineering Circuit Analysis
51
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Nodal Analysis (based on KCL)
 A Systematic Technique To Determine
Every Voltage and Current in a Circuit
 The variables used to describe the
circuit will be “Node Voltages”
• The voltages of each node Will Be
Determined With Respect To a
Pre-selected REFERENCE Node
– The Reference Node is Often Referred to as
 Ground (GND)
 Or
 COMMON
Engineering-43: Engineering Circuit Analysis
52
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Consider Resistor Ladder
 Goal: Determine All Currents & Potentials in
this “Ladder” Network
 Plan
• Use Series/Parallel Transformation to Find I1
• Back-Substitute Using KVL, KCL, Ohm to Find Rest
Engineering-43: Engineering Circuit Analysis
53
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Series-Parallel Transformations
4k || 12k 12k
 Xform1
• Combine 3 Resistors
at End of Network
 Xform2
6k
I3
6k || 6k
• Combine 3 Resistors
at End of Network
 Note By Ohm’s Law
Vb  I 3  3[k]
Va  I 2  6[k]
Engineering-43: Engineering Circuit Analysis
54
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Xform cont.
 Xform3
I1 
12V
12k
• To Single-Loop Ckt
12V
I1 
 1mA
12k
Va  I1  3k  3V
 Now Back Substitute
• Recall
Va
I2 
 0.5mA
6k
• By KCL
I 3  I1  I 2  0.5mA
Engineering-43: Engineering Circuit Analysis
55
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Xform cont.
 Recall Xform2
Vb  I 3 3k  1.5V
 In Summary
• I1 = 1 mA
• I2 = I3 = 0.5 mA
• I4 = 0.375 mA
• I5 = 0.125 mA
• Va = 3 V
• Vb = 1.5 V = 3/2 V
• Vc = 0.375 V = 3/8 V
Engineering-43: Engineering Circuit Analysis
56
Then
V
I4  b
4k
 0.375mA
 Finally by KCL
I 5  I 3  I 4  0.125mA
Then by Ohm' s Law
Vc  I 5  3k  0.375V
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Node Analysis Perspective
KVL
KVL
KVL
REFERENCE
 Take Node-5 As the Ref, → Vref = 0, Always
  In General: Vx5 = Vx−V5 = Vx−0 = Vx
• Then the KVL Loop Eqns
 Vs  V1  Va  0
 Va  V3  Vb  0
 Vb  V5  Vc  0
V1  Vs  Va
V3  Va  Vb
V5  Vb  Vc
Engineering-43: Engineering Circuit Analysis
57
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
ALWAYS Define Reference Node
 The Statement V1 = 4V
is Meaningless
• UNTIL The Designation
of a REFERENCE NODE
 By Convention The
Ground (GND)
Symbol
Indicates the
Reference Point
• ALL Node Voltages are
Measured Relative to
GND
Engineering-43: Engineering Circuit Analysis
58
 V12 

2V


4V

V12  V1  V2  4V   2V   6V
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Strategy for Node Analysis
VS
Va
Vb
@Va :  I1  I 2  I 3  0

REFERENCE
1.
Identify All Nodes And
Select A Ref. Node
2.
Identify Known
Node Voltages
3.
at Each Node With
Unknown Voltage
Write A KCL Equation
VS  Va Va Va  Vb


0
9k
6k
3k
@Vb :  I 3  I 4  I 5  0
V V V V V
 a b  b  b c 0
3k
4k
9k
@Vc :  I 5  I 6  0

Vc
Vb  Vc Vc

0
9k
3k
Engineering-43: Engineering Circuit Analysis
59
•
4.
Final Desired 
Eqn Set
e.g., (Sum Of
Current Leaving) =0
Replace Currents in
Terms Of Node V’s
Yields Algebraic Eqns
In The Node Voltages
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Node Analysis cont
 If We Know Va, Vb, and Vc, Then
• Can Calc V1, V2, V3 by KVL, Then
– Use Ohm’s Law to Find I1→I5
 i.e., If we Know All Node Potentials,
Then Can Calc All Branch Currents
Theorem:
IF ALL NODE VOLTAGES WITH RESPECT
TO A COMMON REFERENCE NODE ARE
KNOWN, THEN ONE CAN DETERMINE
ANY OTHER ELECTRICAL VARIABLE
FOR THE CIRCUIT
Engineering-43: Engineering Circuit Analysis
60
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Node Analysis Steps
1. Pick the “Best” GND node
2. Label Unknown Voltages; e.g., 𝑉1 , 𝑉2
3. Use KCL to form a linear algebra eqn
of the form: 𝐆𝑉 = 𝐼
4. Solve the 𝐆𝑉 = 𝐼 eqn for 𝑉 using the
Usual Methods
• Substitution, Gaussian Elimination, Matrix
Inversion (ugh!) MATLAB Left Division
Engineering-43: Engineering Circuit Analysis
61
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Node Analysis WhtBd Example
 Solve the circuit below for 𝑉𝑂 by Nodes
Engineering-43: Engineering Circuit Analysis
62
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
>> A = [1 -10 -1; 2 -5 0; 6 -4 3]
A =
Node
Analysis
WhtBd
Example
1
2
6
-10
-5
-4
-1
0
3
>> b = [0; 144; 288]
b =
0
144
288
>> V = A\b
V =
150.2609
31.3043
-162.7826
>> VO = V(3)
VO =
-162.7826
Engineering-43: Engineering Circuit Analysis
63
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Loop Analysis (Based on KVL)
 Loop Analysis is The 2nd Systematic
Technique To Determine All Currents
And Voltages In A Circuit
• IT Is the DUAL To Node Analysis
– It First Determines All Currents In A Circuit And
Then It Uses Ohm’s Law To Compute Voltages
• There Are Situations Where Node Analysis
Is Not An Efficient Technique And Where
The Number Of Equations Required By
Loop Analysis Is Significantly Smaller
Engineering-43: Engineering Circuit Analysis
64
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Node Equation Mechanics
a
Va
R1
Vb
b
R3
• Then select any
form of KCL
c
Vc
I1
I3
R2
Vd
 When The Currents Are
Replaced In Terms Of
The Node Voltages The
Node Eqns That Result
Are The Same Or Equiv.
I2
d
 When Writing
Node Equations

CURRENTS LEAVING  0
 I1  I 2  I 3  0  
Va  Vb Vb  Vd Vb  Vc


0
R1
R2
R3
• At Each Node We Can
 CURRENTS INTO NODE  0
Choose Arbitrary
Directions for Currents I1  I 2  I 3  0  Va  Vb  Vb  Vd  Vb  Vc  0
R1
Engineering-43: Engineering Circuit Analysis
65
R2
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
R3
Node Eqn Mechanics cont.
a
Va
Vb
R1
b
2

• Use Ohm’s Law to
Write The Equation
Directly In Terms Of
The Node Voltages
• By Default Use KCL
In The Form Sum-ofcurrents-leaving = 0
d
Vb  Va Vb  Vd Vc  Vb


0
R1
R2
R3
CURRENTS INTO NODE  0
 I1'  I 2'  I 3'  0  
Vb  Va Vb  Vd Vc  Vb


0
R1
R2
R3
Engineering-43: Engineering Circuit Analysis
66
Vc
CURRENTS LEAVING  0
I1'  I 2'  I 3'  0 

 When Writing The
Node Equations
c
I 3'
I 2'
I1' R
Vd
R3
– But The Reference
Direction For The
Currents Does NOT
Affect The Node
Equation
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Ckts with INDEPENDENT Srcs
 There is NO
Relationship
Between V1 and the
2 mA Source
Current However ...
• The Mesh-1 Current
is CONSTRAINED
by the 2mA Source
– Thus the Mesh-1 Eqn
I1  2mA
Engineering-43: Engineering Circuit Analysis
67
 In General:
• Current Sources That
Are NOT SHARED By
Other Meshes (Or
Loops) Serve To
DEFINE a Mesh (Loop)
Current And Reduce
The Number Of
RequiredBruce
Equations
Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Mesh Analysis WhtBd Example
 Solve the circuit below for 𝑉𝑂 by Meshes
Engineering-43: Engineering Circuit Analysis
68
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Loop Analysis WhtBd Example
 Solve the circuit below for 𝑉𝑂 by Loops
Engineering-43: Engineering Circuit Analysis
69
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Loops vs Meshes
 Meshes are MORE
SYSTEMATIC
than Loops
 LOOPS are more
GENERAL Than
Meshes; i.e., Meshes
are a SUBSET of Loops
 The Choice is NOT Always
OBVIOUS as in the previous example
Engineering-43: Engineering Circuit Analysis
70
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Ckts w/ Independent Sources
i
OUT
0
 At Node-1: −𝑖𝐴 +𝑖1 + 𝑖2 = 0  Replacing R’s w/ G’s
• Using Resistances
 iA 
v1  0 v1  v2

0
R1
R2
 Using Conductances
Eliminates Tedious
Division Operations
Engineering-43: Engineering Circuit Analysis
71
• At Node-1
 iA  G1v1  G2 (v1  v2 )  0
• At Node-2:
−𝑖2 + 𝑖𝐵 + 𝑖3 = 0
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Node Analysis of Indep Src Ckts
 ReOrder Terms in
Eqns for KNOWN iA & iB
 The Model For The
Circuit is a System Of
Algebraic Equations
 The Manipulation Of Systems Of Algebraic Equations
Can Be Efficiently Done Using Matrix Analysis
• c.f., MTH-6 or ENGR-25 (MATLAB)
Engineering-43: Engineering Circuit Analysis
72
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Example
 Write the KCL Eqns
• @ Node-1 Visualize The
Currents Leaving, and
then Write the KCL Eqn
 Similarly at Node-2
v v v v
 i2  2 1  2 1  0
R4
R3
• Could Use (i Entering
Node) Just as well
v1  v2 v1  v2
i2 

0
R4
R3
Engineering-43: Engineering Circuit Analysis
73
 Clear Fractions if Desired
 v2  v1 v2  v1 v1



 i1  R2  R3  R4

R4
R2
 R3

 v2  v1 v2  v1


 i2  R3  R4

R3
 R4

 Now have 2 nice Eqns in
2 Unknowns to solve
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
VB
KCL Eqn Example
 Write KCL At Each
Node In Terms Of
Node Voltages
• 3 Nodes Implies 2
KCL Equations
@A
VA VA

 15mA  0
2k 8k
VB VB
@B

 15mA  0
8k 2k
 Two simple eqns in
Two Unknowns
Engineering-43: Engineering Circuit Analysis
74
B
Mark the nodes
(to insure that
None is missing)
15mA
A
VA
8k
2k
2k
8k
C
Select C as
Reference
 Solving by Algebra,
Find:
VA  24V
VB  24V
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Linear Algebra Analysis
Given
i A  1mA, iB  4mA
R1  12k, R2  R3  6k
 The Node Eqns in
Conductance Form
 Recall R=1/G, Then
Insert Numerical
Values, and Change to
Time Independent
Notation (All CAPS)
 The Math Model
Engineering-43: Engineering Circuit Analysis
75
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Linear Algebra Analysis cont.
 The Numerical Model
 Then V2
 And V1
 Multiply the 1st Eqn
by 4kΩ to Find V1 in
Terms of V2
 Alternatively, Multiply
Both Sides of Math
Model by LCD in kΩ
 12k
 6 k
 Back Sub into 2nd eqn
Engineering-43: Engineering Circuit Analysis
76
• R.H.S. of Eqn Now
in Volts
• V1, V2 CoEffs are No.s
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Linear Algebra Analysis cont.
 The “Clean” Eqns
1
3V1  2V2  12V
 V1  2V2  24V
2


 6V
 15V


 Proceed with Gaussian
Elimination
• Add Eqns to Eliminate V2
2V1  12V
V1  6V
Engineering-43: Engineering Circuit Analysis
77
• Back Substitute to Find V2
  6V   2V2  24V
2V2  30V
V2  15V
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Use Matrix Algebra
 Recall The Math Model
 The Matrix Eqn Soln
1
V G I
• In this Case
 From MTH-6 the Form
of Matrix Multiplication
GV  I
 Calculating the Matrix
Inverse, G-1, is NOT Trivial
• In this Case
G
V
I
• Use Matrix Manipulation
– Adjoint Matrix
– Determinant Calculation
• Or use MATLAB
Engineering-43: Engineering Circuit Analysis
78
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
GV = I  By MATLAB
 Construct the
Coefficient Matrix G
>> G = [1/4e3 -1/6e3;
-1/6e3 1/3e3]
G =
-0.1667
0.3333
Engineering-43: Engineering Circuit Analysis
79
>> I = [1e-3; -4e-3]
I =
0.0010
-0.0040
 Matrix Inversion by
“Left” Division for V
1.0e-003 *
0.2500
-0.1667
 Construct the
Constraint Vector, I
>> V = G\I
V =
-6
-15
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Example Ckt w/ V-controlled Isrc
 Write Node
Equations
 Treat Dependent
Source as a Normal
Current-Source
• Node Eqns
 Express Controlling Variable In Terms
Of Node Voltages
Engineering-43: Engineering Circuit Analysis
80
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Example Ckt w/ V-controlled Isrc
 4 Eqns in 4
Unknowns
• Solve Using Most
Convenient Method
– Choose SUB &
GAUSSIAN ELIM
 Sub for vx
in •vx Isrc
 Continue w/ Gaussian
Elim OR Use
Matrix Algebra
Engineering-43: Engineering Circuit Analysis
81
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Solve Using MATLAB
R1  1k, R2  R3  2k,
R4  4k, i A  2mA, iB  4mA,
  2[ A / V ]
 Define Components (m-file Node_Anal_0602.m)
R1 = 1000; R2 = 2000; R3 = 2000;
R4 = 4000; %resistances in Ohms
iA = 0.002; iB = 0.004; %sources in Amps
Alpha = 2; %gain of dependent source in Siemens
Engineering-43: Engineering Circuit Analysis
82
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Solve Using MATLAB cont
R1  1k, R2  R3  2k,
R4  4k, i A  2mA, iB  4mA,
  2[ A / V ]
 Define Coefficient Matrix
G=[(1/R1+1/R2), -1/R1, 0; % first Matrix row
-1/R1,(1/R1+alpha+1/R2),-(alpha+1/R2); % 2nd row
0, -1/R2,(1/R2+1/R4)] % third row.
G =
0.0015
-0.0010
0
-0.0010
2.0015
-0.0005
Engineering-43: Engineering Circuit Analysis
83
0
-2.0005
0.0008
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Solve Using MATLAB cont
R1  1k, R2  R3  2k,
R4  4k, i A  2mA, iB  4mA,
  2[ A / V ]
 Define Constraint Vector
I=[iA;-iA;iB];
 Solve by Left/Back Division; V in volts
V=G\I % end with carriage return and get
the ReadBack
11.994 V
15.991 V
V =
15.994 V
11.9940
15.9910
15.9940
Engineering-43: Engineering Circuit Analysis
84
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Loop Analysis (Based on KVL)
 Loop Analysis is The 2nd Systematic
Technique To Determine All Currents
And Voltages In A Circuit
• IT Is the DUAL To Node Analysis
– It First Determines All Currents In A Circuit And
Then It Uses Ohm’s Law To Compute Voltages
• There Are Situations Where Node Analysis
Is Not An Efficient Technique And Where
The Number Of Equations Required By
Loop Analysis Is Significantly Smaller
Engineering-43: Engineering Circuit Analysis
85
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Loop Analysis Illustration
V1
 VR1 V2 VR2  V3
+
-
R1
+
-
R3
12V
GND
I
R2
 VR3 
18V
V4
 Apply Node Analysis
 Observe
 Need 3 Eqns to Find All
Node Potentials; 24
 Notice There is Only
ONE Current Flowing
Thru All Components
• A Single Loop Ckt
• Can Use Ohm’s Law to
Determine Voltages
• Have 4 Non-Ref Nodes
 Apply KVL for Clockwise
• One SuperNode
Loop Starting at GND
• One Node Connected to  12[V ]  V  V  18[V ]  V  0
R1
R2
R3
GND Thru a V-src
Engineering-43: Engineering Circuit Analysis
86
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Loop Analysis Illustration cont
V1
 VR1 V2 VR2  V3
+
-
12V
GND
R1 KVL R2
I
R3
+
-
 VR3 
 Note:
18V
V4
• Recalling that V=IR Allows
Writing the Ohm Eqn
“by Inspection” for a
Single Loop Ckt
 The Loop Generates a
 Now Use Ohm’s Law to SINGLE Eqn to Yield the
Express V’s In Terms of Loop CURRENT
the Loop Current
 By KVL
 12[V ]  R1 I  R2 I  18[V ]  R3 I  0
Engineering-43: Engineering Circuit Analysis
87
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Loops, Meshes, Loop-Currents
a
1
2
I1
b
7
3
c
I2

A Loop is a Closed
Path That Does Not
Go Twice Over Any
Node

This Circuit Has
3 Loops
4
e
d
f
6
5
A BASIC CIRCUIT
I3
 Each Component is
Characterized By The
• VOLTAGE Across It
• CURRENT Thru It
1. fabef
2. ebcde
3. fabcdef
Engineering-43: Engineering Circuit Analysis
88
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Loops, Meshes cont.
a
1
2
I1
b
7
3

c
I2
4
e
d
f
6
5
A BASIC CIRCUIT
I3
 A MESH is a LOOP
That Does Not Enclose
Any OTHER Loop
• This Ckt Has Meshes
– fabef
– ebcde
A Loop Current is a
Fictitious or Virtual
Current That is
Assumed to Flow
Around a Loop
•
– I1, I2, I3

Mesh Current =
Current Within a
Mesh Loop
•
Engineering-43: Engineering Circuit Analysis
89
The Loop Currents
of This Ckt
e.g.: I1, I2
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Loops, Meshes cont.
2
a
1
I1
b
3
I2
7

c
Ckt Examples
I a f   I1  I 3
4
I b e  I1  I 2
e
d
f
6
5
A BASIC CIRCUIT
 Claim
• In a Circuit, the Current
Through Any
Component Can Be
Expressed In Terms of
the (perhaps multiple)
Loop Currents
Engineering-43: Engineering Circuit Analysis
90
Ibc  I 2  I3
I3
•
•
The DIRECTION Of
The Loop Currents
is SIGNIFICANT
FACT
– Not ALL Loop
Currents are Required
To Compute All The
Currents Through
Components
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Loops, Meshes cont.
a
1
2
I1
b
3
•
c
7
4
e
d
f
6
5
A BASIC CIRCUIT
I3
 For Every Circuit
There is a MINIMUM
Number of Loop
Currents Needed to
Find Every Current in
the System
Engineering-43: Engineering Circuit Analysis
91

Such A Collection is
Called the “MINIMAL
SET” (of Loop
Currents)
For a Given Circuit Let
•
•

B  Number of
BRANCHES
N  Number of NODES
The Minimum Number
of Loop Currents is
L  B  ( N  1)
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Illustration
 For This Ckt
• B=7
• N=6
• L = 7-(6-1) = 2
 Need Two Loop Currents
• The Currents Shown
are MESH Currents
– Hence They are
Independent and
form a Minimal Set
 Determination of
Mesh Currents
• KVL on Right Mesh
• Using Ohm’s Law
• KVL on Left Mesh
Engineering-43: Engineering Circuit Analysis
92
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Illustration cont.
 SubStituting and
ReArranging
 We Obtain in MATRIX FORM the
Loop Equations for This Circuit
Engineering-43: Engineering Circuit Analysis
93
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
 v R1 
Mesh Practice
 Write The Mesh
Equations
 Some Bookkeeping
• 8 BRANCHES
• 7 NODES
• L = 8-(7-1) = 2
– Need TWO Mesh
Currents
 This is MESH Current
Practice
• Choose as the
Two Loops Meshes
– i1
– i2
Engineering-43: Engineering Circuit Analysis
94

v R3
 vR2 

v R5


 vR4 
 Identify All Voltage Drops
 KVL on Top Mesh
 vS1  vR1  vS 2  vR 2  0
 KVL on Bottom Mesh
 vR 2  vR 5  vR 4  vS 3  vR3  0
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Mesh Practice cont.
 v R1   i1R1
 Now Use Ohm’s Law To
Find The Mesh Current
Equation Set

 i2 R3  v R3
 v R 2   (i1  i2 ) R2
v R5  i2 R5


 v R 4   i2 R4
Engineering-43: Engineering Circuit Analysis
95
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Develop a ShortCut
 Whenever An Element
Has More Than One
Loop Current Flowing
Through It We Calculate
NET Current In The
DIRECTION of TRAVEL
 Draw The Mesh Currents
• Orientation can be
arbitrary, But
Conventionally
Defined as CLOCKWISE
Engineering-43: Engineering Circuit Analysis
96
WRITE THE MESH EQUATIONS
V2
R1
+ -
V1
+
-
I1
R5
R2
I2
R3
R4
 NOW
• Write KVL For Each Mesh
• Apply Ohm’s Law To Every
Resistor
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Develop a ShortCut cont
 At Each Loop must Follow
The Passive Sign
Convention Using Loop
Current REFERENCE
DIRECTION
• This Defines the Polarity of
the Voltage Drops
+ -
V1
+
-
I1
R2
I2
R3
R4
 Note The NET Currents
 V1  I1R1  ( I1  I 2 ) R2  I1R5  0
V2  I 2 R3  I 2 R4  ( I 2  I1 ) R2  0
97
V2
R1
R5
 Then KVL for
Meshes 1 & 2
Engineering-43: Engineering Circuit Analysis
WRITE THE MESH EQUATIONS
( I1  I 2 )
( I 2  I1 )
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Numerical Example
 Use Loop Analysis
to Find Io
 SHORTCUT:
• POLARITIES ARE
NOT NEEDED.
• Apply Ohm’s Law To Each
Element As KVL Is being
written
 KVL for Meshes 1 & 2
 Collect Like Terms
& Solve
12kI1  6kI 2  12
 6kI1  9kI 2  3 2
Engineering-43: Engineering Circuit Analysis
98
and Add
----------------------12kI 2  6V  I 2  1 2 mA
5
12kI1  12  6kI2  I1  mA
4
3
I o  I1  I 2  mA
4
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Numerical Example - Alternate
 Alternative Loop Current
Selection
 KVL for Mesh1 & Loop2
 In This Case one mesh
and one loop
• Io = I1
– This Selection is More
Efficient than 2 small
meshes; Only Need to
Find l1
Engineering-43: Engineering Circuit Analysis
99
 Collect Like Terms
& Solve
12kI1  6kI2  12 3
6kI1  9kI2  9 2 and Substract
----------------3
24kI1  18  I1  mA  I o
4
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Circuits w/ Indep. I-Sources
 Find Both Vo & V1
 There is NO Relationship
Between V1 and the
2 mA Source Current
However ...
• The Mesh-1 Current is
CONSTRAINED by the
2mA Source
– Thus the Mesh-1 Eqn
I1  2mA
Engineering-43: Engineering Circuit Analysis
100
 Recall: In General
• Current Sources That Are
NOT SHARED By Other
Meshes (Or Loops) Serve
To DEFINE a Mesh
(Loop) Current And
Reduce The Number Of
Required Equations
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Circuits w/ Indep. I-Sources cont
 The Mesh-2 KVL Eqn
 ReArranging Find
Equivalent Eqn
 2kI1  8kI2  2V
 Use I1 Constraint that
I1 = 2 mA to Calculate I2
2k  (2mA)  2V 3
I2 
 mA
8k
4
9
 VO  6k I 2  [V ]
2
Engineering-43: Engineering Circuit Analysis
101
KVL
 To Obtain V1 Apply KVL
To Any Closed Path That
Includes V1
0 V1   4  kI1  2V  6k  I 2
 Then
V1  4k  2mA  2V  6k  0.75mA
V1  10.5V
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Numerical Example
 Two Mesh Currents Are
Defined By Current
Sources
I1  4mA
I 2  2mA
Engineering-43: Engineering Circuit Analysis
102
 Only Need Eqn
for Mesh-3
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Numerical Example cont
KVL FOR Vo
 Collect Terms for eqn-3
 2kI1  4kI2  12kI3  3V
 Then I3
I3 
3V  2k (4mA)  4k (2mA) 1
 mA
12k
4
Engineering-43: Engineering Circuit Analysis
103
 Finally Use KVL
to Calculate Vo
6kI 3  3V  Vo  0
3
1

Vo  6k mA   3V   V
2
4

Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
STOP Here if Short on Time
Engineering-43: Engineering Circuit Analysis
104
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Eqns by “Inspection”
 If The Circuit Contains
Only INDEPENDENT
VOLTAGE Sources
Then The Mesh
Equations Can Be
Written “By Inspection”
• MUST HAVE All Mesh
Currents With The Same
Orientation
 In loop “k”
• The Coefficient Of Ik Is
The Sum Of Resistances
Around The Loop
Engineering-43: Engineering Circuit Analysis
105
 The Right Hand Side Is
The Algebraic Sum Of
Voltage Sources Around
The Loop
• VoltageRise = POSITIVE
on R.H.S. of eqn
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Eqns by “Inspection” cont
 The Coefficient Of Ij Is
The Sum Of Resistances
COMMON To Both
k and j and With a
NEGATIVE Sign
 In This Example
• Loop1: k = 1, j = 2
12kI1  6kI2  12V
• Loop2: k = 2, j = 1
 6kI1  9kI 2  3V
Engineering-43: Engineering Circuit Analysis
106
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Equation Practice
 Loop-1
• Coefficient of I1
I1  4k  6k
• Coefficient of I2
I2  0
• Coefficient of I3
I 3  6k
• Right Hand Side (RHS)
 6[V ]
 In Summary for Loop1
 Similarly The Coeffs
for Loop-2
I1 coeff  0
I 2 coeff  9k  3k
I 3 coeff  3k
RHS  6V
Engineering-43: Engineering Circuit Analysis
107
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Equation Practice cont.
 In Summary for Loop-2
 Applying the Method
to Loop-3 Yields
 Solve 3-Eqns in 3-Unknowns Using Normal
Linear Algebra, or MATLAB, Techniques
Engineering-43: Engineering Circuit Analysis
108
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Numerical Example

Use Mesh Eqns to
Determine Vo
1. Draw the Mesh Currents
I2
I1
2. Write the Mesh Eqns for
Mesh-1 & Mesh-2
(2k  4k  2k ) I1  2kI2  3[V ]
 2kI1  (2k  6k ) I 2  (6V  3V )

Divide Both Sides of
Both Eqns by 1kΩ
•

Units on RHS become
V/kΩ, or mA
Solve System of Eqns
Engineering-43: Engineering Circuit Analysis
109
8 I1  2 I 2  3mA
 2 I1  8I 2  9mA 4
and Add
----------------30 I 2  33mA  I 2 
then Vo  6kI2 
11
mA
10
33
V
5 Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Example
WRITE THE MESH EQUATIONS
1. Draw the Mesh
Currents
2. Write Mesh Eqns
by KVL

12V 
12k
4k
4k
I4
I1
2k
6k
MESH 1 : 12kI1  12V  6k ( I1  I 3 )  0
I2

I3

9V
MESH 2 :  12V  4k ( I 2  I 4 )  4k ( I 2  I 3 )  0
MESH 3 :  9V  6k ( I 3  I1 )  4k ( I 3  I 2 )  0
MESH 4 : 9V  4k ( I 4  I 2 )  2kI4  0

Or Eqns by Inspection
18kI1  6kI3  12V
8kI2  4kI3  4kI4  12V
 6kI1  4kI2  10kI3  9V
 Calculate Currents Using
Multi-Eqn Solver Tools
• 4 Eqns in 4 unknowns
 
 RI  V
– Solve using Standard
Linear Algebra Techniques
– Perfect for MATLAB
 4kI2  6kI4  9V
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
All Done for Today
A Different
Type of
NODE
BRANCHES Connect to NODES
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
WhiteBoard Work
 Let’s Use KCL to
Derive the Req for N
Parallel Resistors
Done Previously
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Engineering 43
Appendix
Δ↔WYE
& others
Bruce Mayer, PE
Licensed Electrical & Mechanical Engineer
BMayer@ChabotCollege.edu
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Node Analysis WhtBd Example
 Solve the circuit below for 𝑉𝑂
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BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Node Analysis WhtBd Example
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Node Analysis WhtBd Example
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Node Analysis WhtBd Example
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Node Analysis WhtBd Example
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
>> A = [1 -10 -1; 2 -5 0; 6 -4 3]
A =
Node
Analysis
WhtBd
Example
1
2
6
-10
-5
-4
-1
0
3
>> b = [0; 144; 288]
b =
0
144
288
>> V = A\b
V =
150.2609
31.3043
-162.7826
>> VO = V(3)
VO =
-162.7826
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Mesh Analysis WhtBd Example
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Mesh Analysis WhtBd Example
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Mesh Analysis WhtBd Example
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Mesh
Analysis
WhtBd
Example
>> A = [36 -12 0; 24 -12 0; 0 -1 1]
A =
36
-12
0
24
-12
0
0
-1
1
>> b = [72; 24; 6;]
b =
72
24
6
>> I = A\b
I =
4
6
12
>> V0 = I(3)*12
V0 =
144
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Mesh Analysis WhtBd Example
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Mesh Analysis WhtBd Example
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Mesh Analysis WhtBd Example
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Mesh Analysis WhtBd Example
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Recall Passive Sign Convention
 vR' 
 vR 
i
i'
 If V Drops L→R
• i by Passive Sign
Convention
OHM' S LAW i 
vm  v N
R
'
R
 If V’ Drops R←L
• i’ by Passive Sign
Convention
OHM' S LAW i ' 
Thus v  vR  i '  i
Engineering-43: Engineering Circuit Analysis
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v N  vm
R
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Single Loop Ckts - Background
 Using KVL And KCL We Can Write
Enough Equations To Analyze ANY
Linear Circuit
 Begin The Study Of Systematic And
Efficient Ways Of Using The
Fundamental KCL & KVL Circuit Laws
• This Time →
Single LOOP Circuits
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
The Power of Loop Analysis
 Consider this
Circuit
 Alternative Analyses
• Write N-1 (5) KCL Equations
a
1
2
b
3
6 branches
6 nodes
1 loop
– An Easy Choice
 The Plan for Loop Analysis
• Begin With The Simplest One-Loop Circuit
• Extend Results To Multiple-Source
and Multiple-Resistor Circuits
130
4
f
6
e
5
d
ALL ELEMENTS IN SERIES
ONLY ONE CURRENT
• Determine Only the SINGLE Loop Current
Engineering-43: Engineering Circuit Analysis
c
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
“Inverse” Voltage Divider

 The Std V-Divider
VO 
R2
VS
R1  R2
Inverse
Divider
R1
VS 
R1  R2
VO
R2
VS
+
-
 Example Find VS
• Use Inverse Divider
R1  R2
VS 
VO
R2
20  220
VS 
458.3kV  500 kV
220
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
R2
VO


Example
2
b
 Find
VS 12V
• Vx, Vab
• P3Vx
VS
– The Power Absorbed
or Supplied By the
Dependent Source
Vab  12V  2V  0  Vab  10V
Engineering-43: Engineering Circuit Analysis
132
-
 4V 
4k
1
I
a
+-

VX

3
• Passive Sign Conven.
1 12  4  3VX  VX  0  VX  2V
2 Vab  4  3VX  0  Vab  10V
Vab  VS  VX  0
+
3Vx
 Find DS Power
 Apply KVL
3

Vab
P( 3V X )  3V X I
• Ohm’s Law

I
4V
 1mA
4k
• Then Pwr ABSORBED
P(3VX )  3  2[V ]  1[mA]  6mW
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Example
 Find: VDA, VCD, I
20k
A
12V
9V
B
+ -
I
+
-
• Apply KVL & Ohm
2
E
-12  20k*I  9  30k*I  10k*I  0
1
3V
I
 0.05mA
60k
VDA  12 10k * I  0  VDA  11.5V
1
2
VCD  30k * I  30k  0.05mA  1.5V
133
30k
D
10k
• Ohm’s Law
Engineering-43: Engineering Circuit Analysis
C
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
WhiteBoard Work
 Let’s Work This Problem
8 k
120 mA
4 k
4 k
Io
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Inverse Series Parallel Combo
 Find R: Simple Case
• Constraints
– VR = 600 mV
– I = 3A
– Only 0.1Ω R’s Available
 Recall R = V/I
0.6V
R
 0.2
3A
Since R>Ravail, Then Need to Run in Series
R  2 Ravail  0.1  0.1
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
More Complex Case
 Find R for Constraints
• VR = 600 mV
• I = 9A
• Only 0.1Ω Resistors Available
0.6V
R
 0.0667  66.67 m
9A
 Either of These 0.1Ω R-Networks Will Work
33.33 mΩ
R
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0.1║(0.1↔0.1)
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Effect Of Resistor Tolerance
 The R Spec: 2.7k, ±10%
 What Are the Ranges for
Current & Power?
• I = V/R
I nom 
10V
 3.704mA
2.7k
I min 
10V
 3.367mA
1.1 2.7k
I max 
10V
 4.115mA
0.9  2.7k
• P = V2/R
Pnom
2

10V 

2.7k
 37.04mW
Pmin 
10V 2
1.1 2.7k
 33.67mW
Pmax 
10V 2
0.9  2.7k
• For Both I & P the Tolerance.: -9.1%, +11.1%
– Asymmetry Due to Inverse Dependence on R
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
 41.15mW
Final Example
VB
 Find VS
• Straight-Forward
IB
IS
VB  60k  0.1mA  6V
VB
6V
IB 

 0.05mA
120k 120k
I S  0.1mA  I B  0.1mA  0.05mA  0.15mA
VS  VB  20k  I S  6V  20k  0.15mA  9V
• Or, Recognize As Inverse V-Divider
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Final Example cont
VB
 Inverse Divider
Calculation
IS
VB  60k  0.1mA  6V
IB
As Before 
R||  60k || 120k  40k
VS  VB
R||  20k
R||
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40k  20k
 6V
 9V
40k
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Wye↔ Transformations
 This Circuit Has No
Series or Parallel
Resistors
 If We Could Make
The Change Below
Would Have SeriesParallel Case
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Y↔ Xforms cont
 Then the Circuit Would Appear as Below and
We Could Apply the Previous Techniques
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Wye↔ Transform Eqns
→Y
←Y
 →Y (pg. 58)
Ra Rb  Rb Rc  Rc Ra
Rb
Ra 
R1 R2
R1  R2  R3
R1 
Rb 
R2 R3
R1  R2  R3
Ra Rb  Rb Rc  Rc Ra
R2 
Rc
R3 R1
Rc 
R1  R2  R3
Ra Rb  Rb Rc  Rc Ra
R3 
Ra
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 ←Y (pg. 58)
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
↔Y Application Example
 Connection
c
 Find IS
• Use the →Y Eqns to
Arrive at The Reduced
Diagram Below
c
a
Req
Engineering-43: Engineering Circuit Analysis
143
b
R1
a
R3
R2
b
 Calc IS
Req  6k  3k  9k  || (2k  6k )  10k
VS
12V
IS 

 1.2mA
Req 10k
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Another ↔Y Example
 For this Ckt Find Vo
Keep This
Node-Pair
Convert this Y to Delta
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Another ↔Y Example cont
 Notice for Y→Δ in
this Case Ra =
Rb = Rc = 12 kΩ
• Only need to Calc
ONE Conversion
Ra Rb  Rb Rc  Rc Ra 312k 12k 
R1  R2  R3 

 36k
Rb
12k
36k
4mA
36k
36k
 The Xformed Ckt
12k

12k V
O
• ||-R’s Form a
Current Divider

Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
Another ↔Y Example cont
 The Ckt After
||-Reductions
 Can Easily Calc
the Current That
Produces Vo
IO 
36k
8
 4mA  mA
36k  18k
3
Engineering-43: Engineering Circuit Analysis
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36k ||12k  9k
4mA
36k
IO

9k
VO

 Then Finally Vo
by Ohm’s Law
8
VO  9k   I O  9k   mA  24V
3
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
“BackSubbing” Example
 Given I4 = 0.5 mA, Find VO
 0.5mA
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx
BackSubbing Strategy
 Always ask: What More
Can I Calculate?
• In the Previous Example Using Ohm’s
Law, KVL, KCL, S-P Combinations - Calc:
Vb  6k  I 4
Vxz  Va  Vb
Vb
I3 
3k
I 2  I3  I 4
Vxz
I5 
4k
I1  I 2  I 5
Va  2k  I 2
VO  6k  I1  Vxz  4k  I1
Engineering-43: Engineering Circuit Analysis
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 0.5mA
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx