1 1. lecture: Introduction
6
1.1 Trends in test and measurements . . . . . . . . . . . . . . . .
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1.2 Data acuistition (DAQ) & control systems . . . . . . . . . . .
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1.3 What is an Operating System? . . . . . . . . . . . . . . . . .
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1.4 Protected mode . . . . . . . . . . . . . . . . . . . . . . . . . .
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1.5 Device drivers . . . . . . . . . . . . . . . . . . . . . . . . . . .
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1.6 Workstation vs. PC . . . . . . . . . . . . . . . . . . . . . . .
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1.6.1 Workstation . . . . . . . . . . . . . . . . . . . . . . . .
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1.6.2 PCs . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
2 2. lecture: LabVIEW (LW)
8
2.1 Virtual Instruments . . . . . . . . . . . . . . . . . . . . . . .
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2.2 Express VIs . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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2.3 LabVIEW data types . . . . . . . . . . . . . . . . . . . . . . .
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2.4 How VIs are compiled . . . . . . . . . . . . . . . . . . . . . .
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2.5 LabVIEW debugging techniques . . . . . . . . . . . . . . . . 10
3 3. lecture: LabVIEW 2
11
3.1 Dataflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Property nodes . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4 Clusters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5 Local & Global variables . . . . . . . . . . . . . . . . . . . . . 12
3.6 Case structures . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.7 Event Structure . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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3.8 Secuence structure . . . . . . . . . . . . . . . . . . . . . . . . 13
3.9 Shift registrers . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.10 File I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.11 Software timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.12 Design patterns for loop communication . . . . . . . . . . . . 16
3.13 Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.14 Building an application I . . . . . . . . . . . . . . . . . . . . . 17
3.15 Building an application II . . . . . . . . . . . . . . . . . . . . 17
4 4. lecture: Microcontroller basics
17
4.1 Assembly vs C . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3 Microprocessors vs Microcontroller: . . . . . . . . . . . . . . . 19
4.4 CISC vs RISC . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4.1 CISC (Complex Instruction Set Computer) . . . . . . 19
4.4.2 RISC (Reduced Instruction Set Computer) . . . . . . 20
4.5 Types of microcontrollers . . . . . . . . . . . . . . . . . . . . 20
4.6 Digital data transfer . . . . . . . . . . . . . . . . . . . . . . . 20
4.6.1 Synchronous transfer . . . . . . . . . . . . . . . . . . . 20
4.6.2 Asynchronous transfer (ie. handshaking) . . . . . . . . 20
4.7 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.8 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.9 I²C Inter-intergrated circuit . . . . . . . . . . . . . . . . . . . 21
4.10 CAN (Controller Area Network) . . . . . . . . . . . . . . . . 22
4.11 Sortcore and hardcore microprocessors in FPGAs . . . . . . . 23
4.12 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.13 Alternatives to using microcontrollers . . . . . . . . . . . . . . 24
5 5. lecture: Computer buses and interfaces
24
5.1 The most common data acquisition buses avalibale today . . . 24
5.2 Internal computer buses . . . . . . . . . . . . . . . . . . . . . 24
5.3 PCI (Peripheral Component Interconnect) . . . . . . . . . . . 25
5.4 PCI Express (PCIe) . . . . . . . . . . . . . . . . . . . . . . . 25
5.5 CompactPCI . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.6 PXI and PXI-express . . . . . . . . . . . . . . . . . . . . . . . 26
5.7 Why serial buses? . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.8 External computer ports and buses . . . . . . . . . . . . . . . 26
5.8.1 Serial port: RS-232 . . . . . . . . . . . . . . . . . . . . 26
5.8.2 RS-422 . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.8.3 USB (Universal Serial Bus) . . . . . . . . . . . . . . . 28
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5.8.4 GPIB/IEE-488 (General Purpose Interface Bus) . . . . 28
5.8.5 VXI (VME eXtensions for Instrumentation) . . . . . . 29
5.8.6 Ethernet network . . . . . . . . . . . . . . . . . . . . . 29
5.9 Unicast, multicast and broadcast in compute networks . . . . 29
5.9.1 Unicast . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.9.2 Multicast . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.9.3 Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.10 Differential signaling & twisted paris . . . . . . . . . . . . . . 30
6 6. lecture: Instrumentation and data acquisition
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6.1 Data acuisition (DAQ) . . . . . . . . . . . . . . . . . . . . . . 32
6.2 Single-ended signals . . . . . . . . . . . . . . . . . . . . . . . 34
6.2.1 RSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2.2 NRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3 Differential signals . . . . . . . . . . . . . . . . . . . . . . . . 35
6.4 Amplification . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.5 Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.6 Input coupling . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.7 Hardware filtering . . . . . . . . . . . . . . . . . . . . . . . . 36
6.8 Analog filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.9 ADC resolution . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.10 ADC range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.11 Digital signals: Bits, dynamic range and NSR . . . . . . . . . 38
6.12 Other noise reduction techniques in DAQ systems . . . . . . . 38
6.13 Software filtering . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.14 DAQ Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.15 PXI-based DAQ systems . . . . . . . . . . . . . . . . . . . . . 39
6.16 PXI triggering and timing . . . . . . . . . . . . . . . . . . . . 39
6.17 Device drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.18 NI-DAQmx . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.19 Interrups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.20 DMA (Direct memory access) introduction . . . . . . . . . . . 41
6.20.1 DAQ overwrite error . . . . . . . . . . . . . . . . . . . 42
6.20.2 DAQ overflow error . . . . . . . . . . . . . . . . . . . . 42
6.21 Common pitfalls of data communication . . . . . . . . . . . . 42
6.22 LabVIEW timed loop . . . . . . . . . . . . . . . . . . . . . . 43
6.23 Trigger (from HW or SW) . . . . . . . . . . . . . . . . . . . . 43
6.24 Trigger types . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.25 Signal based vs time-based synchronization . . . . . . . . . . 44
6.25.1 Signal based . . . . . . . . . . . . . . . . . . . . . . . . 44
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6.25.2 Time-based . . . . . . . . . . . . . . . . . . . . . . . . 44
6.26 NTP (Network Time Protocol) . . . . . . . . . . . . . . . . . 45
7 7. lecture: Networked and distributed DAQ
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7.1 Data distribution and remote control . . . . . . . . . . . . . . 45
7.1.1 Sharing data . . . . . . . . . . . . . . . . . . . . . . . 45
7.1.2 Remote control . . . . . . . . . . . . . . . . . . . . . . 45
7.1.3 Distributed execution . . . . . . . . . . . . . . . . . . 46
7.2 Scope of communication . . . . . . . . . . . . . . . . . . . . . 46
7.3 DAQ setups . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.3.1 Local DAQ . . . . . . . . . . . . . . . . . . . . . . . . 46
7.3.2 Remote DAQ . . . . . . . . . . . . . . . . . . . . . . . 46
7.3.3 Networked (distributed) DAQ . . . . . . . . . . . . . . 46
7.4 How to commiunicate with other systems? . . . . . . . . . . . 47
7.5 Network and distributed DAQ . . . . . . . . . . . . . . . . . . 47
7.6 Network DAQ example . . . . . . . . . . . . . . . . . . . . . . 47
7.7 Wireless networks and DAQ . . . . . . . . . . . . . . . . . . . 48
7.8 Rammer (frames) . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.9 Jumbo frames . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.10 IP (Internet Protocol) and TCP (Transmission Control Protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.10.1 TCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.10.2 UDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8 8. lecture: Data storage and high-speed streaming
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8.1 Data streaming . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.2 Memory hierachy . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.3 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.4 Streaming Data with the PCI Express Bus . . . . . . . . . . . 51
8.5 HDD performance . . . . . . . . . . . . . . . . . . . . . . . . 51
8.6 SSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.6.1 SLC (Single Layer Cell) . . . . . . . . . . . . . . . . . 52
8.6.2 MLC (Multi layer cell) . . . . . . . . . . . . . . . . . . 53
8.6.3 TLC (Three layer cell) . . . . . . . . . . . . . . . . . . 53
8.7 Factors that affect streaming performance . . . . . . . . . . . 53
8.8 Determining storage format . . . . . . . . . . . . . . . . . . . 54
8.8.1 ASCII Files . . . . . . . . . . . . . . . . . . . . . . . . 54
8.8.2 Binary files . . . . . . . . . . . . . . . . . . . . . . . . 54
8.8.3 TDM and TDMS (Technical Data Managment Streaming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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8.9 Applications requiring high-speed data streaming (examples)
55
8.10 RAID (Redundant Array of Independent Drives) . . . . . . . 55
8.10.1 RAID-0 . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.10.2 RAID-1 . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.10.3 RAID-5 . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.10.4 Parity: XOR method . . . . . . . . . . . . . . . . . . . 56
8.10.5 RAID-6 . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.10.6 RAID-10 (RAID-1 - THEN RAID-0) . . . . . . . . . . 57
8.11 BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.12 Raid configuration II . . . . . . . . . . . . . . . . . . . . . . . 57
8.13 Drawbacks of traditional streaming . . . . . . . . . . . . . . . 57
8.14 Direct-to-disk controller . . . . . . . . . . . . . . . . . . . . . 58
8.15 32-Bit cs. 64-Bit OS for DAQ applications . . . . . . . . . . . 58
8.16 LabVIEW structure for high-speed acquisition and storage . . 59
9 9. lecture: Parallel Programming - Multicore systems
59
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.2 Multiprocessor & Multicore Processors . . . . . . . . . . . . . 60
9.3 Hyper-threading . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.4 How LabVIEW Implements Multithreading . . . . . . . . . . 61
9.5 Multicore programming goals . . . . . . . . . . . . . . . . . . 62
9.6 Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.6.1 Balancing . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.7 Multicore programming challenges . . . . . . . . . . . . . . . 64
9.8 Data Transfer between cores . . . . . . . . . . . . . . . . . . . 65
10 10. lecture: Real-Time and Embedded systems, FPGAs and
GPUs
65
10.1 Embedded computing . . . . . . . . . . . . . . . . . . . . . . 65
10.2 Hardware accelaration (HwA) . . . . . . . . . . . . . . . . . . 66
10.3 Build or Buy for embedded systems . . . . . . . . . . . . . . . 66
10.4 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.4.1 Common applications for FPGAs in DAQ and control systems . . . . . . . . . . . . . . . . . . . . . . . . . . 67
10.4.2 How to program an FPGA? . . . . . . . . . . . . . . . 67
10.4.3 FPGAs in DAQ-systems . . . . . . . . . . . . . . . . . 68
10.5 Real time OS . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.5.1 What is a real-time system? . . . . . . . . . . . . . . . 68
10.5.2 Real-time OS vs General Purpose OS . . . . . . . . . 69
10.5.3 Ethernet for real-time applications . . . . . . . . . . . 69
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10.6 What to avoid in high-priority code . . . . . . . . . . . . . . . 69
10.7 Interrupts for DAQ . . . . . . . . . . . . . . . . . . . . . . . . 70
10.8 Interrup-driven programming . . . . . . . . . . . . . . . . . . 70
10.9 GPUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.10CUDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.11LabVIEW and GPUs . . . . . . . . . . . . . . . . . . . . . . . 71
11 11. lecture: Time & timers, and GPS introduction
71
11.1 TAI and UTC time . . . . . . . . . . . . . . . . . . . . . . . . 71
11.1.1 TAI (International Atomic TIme) . . . . . . . . . . . . 71
11.1.2 UTC (Coordinated Unviversal Time) . . . . . . . . . . 71
11.2 Leap seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
11.3 GPS time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.4 Computer clocks . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.4.1 Hardware clocks . . . . . . . . . . . . . . . . . . . . . 72
11.4.2 Software clocks . . . . . . . . . . . . . . . . . . . . . . 72
11.5 High-resolution Timers/Counters . . . . . . . . . . . . . . . . 72
11.6 Computer clock drift . . . . . . . . . . . . . . . . . . . . . . . 73
11.7 Satellite navigation . . . . . . . . . . . . . . . . . . . . . . . . 73
11.8 Differential GPS (DGPS) . . . . . . . . . . . . . . . . . . . . 74
12 TODO Instrumentation under linux?
74
• Multicore CPUs and parallel programming
–
Gives increased CPU performance without increased clock rates
• Software-defined instrumentation
• FPGA-enabled instrumentation
• 64-bit operating systems and support
• Wireless
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• The main application domain for Real-Time and embedded computer systems is within data acuisition and control
• DAQ involves collecting signals from measurement sources and digitizing the signal for stoarge, analysis and presentation.
An OS is a collection of programs that acts as an intermediary between the hardware its users, providing a high-level interface to low lever hardware resoures, sucs as the CPU, memory, and IO devices. The OS provides various facilities and services that make the use of the hardware convenient efficient and safe.
Is an operational mode. It allows system software to utilize features such as virtual memory, paging etc and other features desgned to increase an OS’s control over application software In PM, there are four privilege levels or rings, from 0 to 3, with ring 0 being the most privileged and 3 being the least. The use of rings allows for system software to restrict tasks from accessing data or executing privileged instructions. In most environments, the OS and some device drivers run in ring 0, and applications run in ring
3.
Figure 1: Windows protection mode
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Is a computer program allowing higher-level computing programs to interact with a hardware device. Drivers are hardware dependent and OS specific.
1.6.1
Workstation
Is a high-end computer designed for technical or scientific applications, running number- and graphic-intensive applications Typically have slots for PCI and PCI express. Typicall specs (2011):
• 2 x Intel Xeon six Core processors
• 192 GB RAM (Max)
• PCI
• 1 PCI Express Gen 1
• 1 PCI Express Gen 2
• 2 PCI Express Gen 2 (for graphics cards)
1.6.2
PCs
Are about flexibility, they are deigned to meet a much wider variety of computing needs. Typicall specs (2011):
• Intel Core 2 quad processer
• 16 GB RAM (Max)
• 3 PCI
• PCI Express x16
• 2 PCI Express x1
Mostly screenshots to introduce LW
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• LabVIEW programs are called virtual instruments, or VIs, because their appearence and operation imitate physical instruments
• In LW, a VI is:
–
A LW program when its the top-file
–
A SubVI when a VI is used in another VI
∗ A SubVI is a similar to a function in other programming languages. SubVIs makes the code more readable, scalable and maintainable.
• LW includes configuration-based Express VIs
• Examples of a an ExVI: Write to measurement file, spectral measurements, Simulate Signal
• The ExVIs can degrade performance. These should not be used for high-speed data streaming in DAQ applications.
Uses color coding of terminals and block diagram wires
• Orange - Floating-point numbers
• Blue - Integer
• Pink - String
• Dark-blue - Dynamic (Special type for use with Express VIs. Because dynamic data undergoes an automatic conversion to match the indicator to which it is wired.
• Green - Boolean
• When you push the Run button, LabVIEW (the G- compiler) translates the block diagram into clumps of machine code for your platform.
• Compiles after any change that is non cosmetic.
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1. Execution highlighting. From ni.com: Use execution highlighting to view an animation of the execution of the block diagram. Execution highlighting shows the movement of data on the block diagram from one node to another using bubbles that move along the wires
2. Single-stepping
3. Probe. From ni.com: Use the Probe tool to check intermediate values on a wire as a VI runs.
4. Breakpoints
Figure 2: Standard VIs vs. Express VIs
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• When a block diagram node receives all required intputs, it produces output data and passed that data to the next node in the dataflow.
The movement of data through the nodes determines the execution order of the functions on the block diagram.
• Used to manipulate the appearance and behavior of the user interface
(Front Panel controls and indicators)
• Can be multidimensional, but cannot be arrays of arrays
• Must have the sama data type for each element
Figure 3: Filling 10 indexes in an array with a random number
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• Used to group related data
–
Reduce the number of terminals (I/O) required on a SubVI
–
Minimize the number of wires on the diagram
• The elements can be of different data types
• Can not contain a mixture of control and indicators
• Minimize the use (especially global variable)
–
Use wires when possible
–
Each local variable creates a copy of the data
• Global variables can create race conditions
–
When two or more events can occur in any order, but they need to occur in a particular order
–
Use global variables only when no other good options
• To limit the CPU usage while waiting for user interface events (mouse clicks, key pressed)
–
This avoids polling
• Detects all events
• Do minimal processing inside event
• How it works:
–
OS broadcasts system events to applications
–
Registered events are captured by event structure and executes appropriate case
–
Event structure enques events that occur while it’s busy.
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Figure 4: Case structures
• Can be used to enforce the order of execution
• Should however use dataflow programming to control the dataflow
• Memory elements available in for- and while-loops
• Transfer values from completion of one loop iteration to the beginning of the next
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Figure 5: Sequence structure
Shift registers from National Instruments: When programming with loops, you often must access data from previous iterations of the loop in
LabVIEW. For example, if you are acquiring one piece of data in each iteration of a loop and must average every five pieces of data, you must retain the data from previous iterations of the loop. Use shift registers when you want to pass values from previous iterations through the loop to the next iteration. A shift register appears as a pair of terminals directly opposite each other on the vertical sides of the loop border.
• File types supported in LabVIEW:
–
ASCII
–
Binary
–
TDMS
–
Config file
–
Spreadsheet
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Figure 6: Shift register
–
AVI
–
XML
• If you use software timer functions to control a loop, such as the Wait
Until Next ms Multiple, then you can expect differences in the time interval between each iteration of the loop, depending on what other process are running on the computer at that instant. This is beacuse
Windows, Linux, MacOS is non-real time.
• The interval will be larger if you are running background processes you are running More on this in 10. lecture
• Two loops can be software synchronized using the Wait Until Next ms
Multiple in both loops when they have equal frequency
• To prioritize execution of different parallel loops use Wait functions to slow down lower priority loops in the application
• In DAQ applications, you should use hardware timing insted of software timing, if possible.
15

• Master-Slave pattern
• Client-Server pattern
• Producer/Consumer pattern (most common)
• Are used for loop communications in multi-loop programs, to execute code in parallel and at different rates. (Producer, consumer).
• Data stored in a FIFO buffer, and the queue depth is limited (only) by the computer’s RAM
• A read (dequeue) from the queue is destructive
• Can be used when we have multiple tasks that run at different speeds and cannot afford to be slowed down.
Figure 7: Enqueue
Figure 8: Dequeue
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1. Choose a design architecture
2. Start with a paper desing
• Draw block diagrams
• Draw flow charts/state diagrams
3. Prototype the user interface
• Helps defining necessary controls and indicators
4. Divide and conqure
• Break the problem(s) into manageable blocks
• Make SubVIs for each function
• Put the entire design togheter
• The spiral model is a software develpment process
• Idientify risks, and analyse the most important risks
• Data quisition example:
–
The highest risk is whether the system can properly interface to all hardware devices, and acquire, analyse and store and display the data quick enough
–
Therefore; create prototypes to test device communication, acquisition rates etc
–
Then evaluate the results, and continue the process
Microcontrollers can be programmed using Assembly or C.
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Figure 9: Spiral model
Assembly C
+ Full control or resource usage + Efficient code in larger applications
+ Compact/fast code in small applications + Structured code
- Inefficient code in larger applications
- Cryptic code
- Hard to maintain
- Non-portable
+ Easy to maintain
+ Portable
- Limited control of resource usage
- Larger/slower code in small applications
Can use AVR Studio 5 as editor for Assembly and C.
Contain:
• CPU
• Memory
18

• I/O
Characteristics:
• Used for control and measurements (not a general-purpose computer)
• Does one task and runs one program continuously
• Low power (50 mW vs 50W for a PC)
• Dont have keyboards and monitor jacks
• Must use ports to perform I/O.
Microprocessor fra wikipedia: A microprocessor incorporates the functions of a computer’s central processing unit (CPU) on a single integrated circuit
(IC), or at most a few integrated circuits. All modern CPUs are microprocessors making the micro- prefix redundant. The microprocessor is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and provides results as output. It is an example of sequential digital logic, as it has internal memory. Microprocessors operate on numbers and symbols represented in the binary numeral system.
Microprocessor Microcontroller
CPU is stand alone, RAM, ROM, I/O are separate Components on a single chip
Can decide amout of RAM, ROM, I/O
Expansive
Mostly used in PCs
General purpose
Fixed amount of this
Mostly used in embedded systems
Single purpose
For applications in which cost, power and space are critical
4.4.1
CISC (Complex Instruction Set Computer)
• Many modern microcontrollers are based on the CISC concept
• A typical CISC microcontroller has well over 80 instructions, many very powerful and specialised
19

• Pro: Many of the instructions are macro-like, allowing the programmer to use one instruction in place of may
4.4.2
RISC (Reduced Instruction Set Computer)
Pros:
• Smaller chip
• Smaller pin count
• Very low power consumption
Small Medium Large
8 bit
20 pins
8/16 bits
44 pins
32 bit
256 pins
UART ADCs DMA
Ex. Attiny from Atmel Atmega from Atmel ARM9
Increased amount of RAM and features in larger microcontrollers
4.6.1
Synchronous transfer
Data set at constant rate using a shared periodic clock
4.6.2
Asynchronous transfer (ie. handshaking)
Data sent upon request using handshake signals. Asynchronous transfer means that the information is not sent in predefined time slots. Data transfer can start at any given time and it is the task of the reciever to detect when a message starts and ends. Reciever and transmitter both have internal clocks but they are not shared.
• Universal Asynchronous Reciever/Rransmitter
• Is usually an individual integrated ciruit used for serial communications over a computer or peripheral device serial port
20

• Are now commonly included in microcontrollers
Figure 10: UART communication (Fra INF3430)
• Serial Peripheral Interface
• Serial data link (bus) standard that operates in full duplex mode (can recieve and transmit at the same time)
• Short distance communication
• Devices communicate in master/slave mode where the master (only one) device initiates the data frame. Multiple slave devices are allowed with individual slave selects lines.
• Bit rate usually in the MHz range.
• Sometimes SPI is alled a “four-wire” serial bus, contrasting with 3, 2, and one-wire serial buses
–
Serial Clock
–
Serial Data In
–
Serial Data Out
– nCS
21

Figure 11: SPI communication
• Is a multi-master serial computer bus (but only one master at a time)
• Uses only two bidirectional lines
–
Data (SDA)
–
Clock (SCL)
• Speed up to 3.4Mbit/s,but 100-400 kbit/s more common
• Practical communication distances are limited to a few meters
–
The longer cable, the lower the speed.
Figure 12: I²C
• Is multi-master broadcast serial bus standard for connecting electronic control units
22

• CAN bus is designed specifically for automotive (vehicles) applications but now also used in other ares such as areospace, maritime, industrial automation and medical equipment
• Each node is able to send and recieve messages, but not simultaneously
• Bit rates up to 1 Mbit/s are possible at network lengths below 40 m.
• The devices that are connected by a CAN network are typically sensors, actuators, and other control devices. These devices are not connected dicrectly to the bus, but through a host processor and a CAN controller.
CAN bus fra wikipedia: CAN bus (for controller area network) is a vehicle bus standard designed to allow microcontrollers and devices to communicate with each other within a vehicle without a host computer.
• Processor cores inside the FPGA
• Softcore CPU
–
Programmable logic in the FPGA is used to implement a processor (when needed) together with other functionality
• Hardcore CPU
–
The processor is implemented in the FPGA at the production of the circuit
Producer Hardcore Softcore
Xilinx
Altera
PowerPc Microblaze
NIOS II
• Halt normal code exection in order to go do something more important or time sensitive
• Used instead of polling
• Can be generated internally or externally
23

• Interrups are used e.g. for:
–
RESET
– timers
– time-critical code
– hardware signaling
For measurement and control applications, a PC with a suitable DAQ-card can be a more suitable solution
Single-point I/O: Basically, single-point I/O means that only one data point will be read in from the hardware to the software at any point in time. So data will not be placed on a buffer and then brought in to the software in chunks.
Bus Waveform streaming Singlepoint I/O
PCI 132MB/s (shared)
PCI Express 250MB/s (per lane)
PXI 132MB/s (shared)
PXI Express 250MB/s (per lane)
USB
Ethernet
Wireless
60MB/s
125MB/s (shared)
Best
Best
Best
Best
Better
Good
6.75 MB/s (p. channel) Good
Some important bus parameters:
• Bandwith
• Serial/Parallel
• Shared/dedicated resource
• Maximum bus length
• Latency
Multidevice Portability
Better
Better
Best
Best
Good
Good
Good
Good
Good
Better
Better
Best
Best
Best
24

• Internal bus connectors (card slots) makes it possible to insert peripheral electronic boards
• Important buses today:
–
PCI
–
PCI Express
• Supports 32 and 64 bits
• Shared parallel bus
• Deisgned to replace the older PCI and PCI-X
• A point-to-point serial bus, rather than a shared parallel bus
• PCIe slots may contain from 1 to 32 lanes, in powers of two
• Dedicated bandwith for each device/slot
– v1: 250 MB/s
– v2: 500 MB/s
– v3: 1 GB/s per lane
• 16 lane slots is therefore 16 times faster:
– v1: 250 MB/s * 16 = 4 GB/s
– v2: 8 GB/s
– v3: 16 GB/S
• Its electrically a superset of PCI with a different (smaller) physical form factor
• Supports twice as many PCI slots
25

• Designed for front loading and removal from a card cage. The cards are firmly held in position by card guides on both sides, and a face plate with solidly screws into the cage
• Cards are mounted vertically allowing for natural or forced air convection for cooling
• Better shock and vibration characterisics than the card edge connection of the standard PCI cards
• Allows hot swapping, a feature that is very important for fault tolerant systems and which is not possible with standard PCI. Fra wikipedia:
Hot swapping and hot plugging are terms used to describe the functions of replacing computer system components without shutting down the system.
• Based on and compatible with CompactPCI
• PXI defines a rugged PC-based platform for measurement and automation systems.
• One of the most important benefits PXI offers is its integrated timing and triggering features. Without any external connections, multiple devices can be synchronized by using the internal buses resident on the backplane of a PXI chassis.
1. High speed data transfer on long cables: the bits on different wires may not reach the reciever circuit exactly on the same time. Not the case on serial line, therefore one may increase speed without problems
2. Crosstalk between lines at high frequency is avoided by using one or two data lines only
3. Hence, parallel cables are more expensive in production
4. Serial internal buses give less motherboard routing, simpler layout and smaller dimensions
26

5.8.1
Serial port: RS-232
• Point to point interface
• Single-ended data transmission
• Common bit frequencies are 9.6 kHz up to 115.2 kHz
• Maximum cable length is about 15-20 meters at full speed
• Minimal 3-wire connection is: Rx, Tx and GND (two way data flow)
RS-232 fra wikipedia: An RS-232 serial port was once a standard feature of a personal computer, used for connections to modems, printers, mice, data storage, uninterruptible power supplies, and other peripheral devices. However, RS-232 is hampered by low transmission speed, large voltage swing, and large standard connectors. In modern personal computers, USB has displaced RS-232 from most of its peripheral interface roles. Many computers do not come equipped with RS-232 ports and must use either an external
USB-to-RS-232 converter or an internal expansion card with one or more serial ports to connect to RS-232 peripherals. RS-232 devices are still found, especially in industrial machines, networking equipment, and scientific instruments.
Figure 13: RS-232
27

5.8.2
RS-422
• Multi-drop interface with a single transmitter but multiple receivers.
• Differential data transmission: Cancel out the effects of ground shifts and induced noise signals that can appear as common mode voltages on a network.
• Maximum cable length is about 1200 meters
• Maximum data rate is 10 Mbit/s
5.8.3
USB (Universal Serial Bus)
• Differential signaling (5V, 0V) and twisted pair
• Power: Below 1A.
• Maximum cable length: 5 meters, but can be increased up to 30m by using:
–
USB hubs as active USB repeaters
–
Active Cables (bus-powered)
5.8.4
GPIB/IEE-488 (General Purpose Interface Bus)
• 8 bit parallel bus
• Every device on the bus has a unique 5-bit adress in the range from 0 to 30.
• The maximum data rate is about 1MB/s.
• Used in laboratory setups for control and data transfer
28

• Enables networking of instruments for automation of experimental setup.
• From the late 1960s and is still in use.
5.8.5
VXI (VME eXtensions for Instrumentation)
• Based on the VME bus
–
A multi-processor bus
–
Used in the high-end (and high cost) market
–
Expensive and power hungry
• Because VXI is based on the older VME bus, which is not a part of modern computer architectures, it cannot take complete advantage of the advantages in PC technology and thus bruing the benefits of mainstream software, lower cost and high performance to the end user
5.8.6
Ethernet network
• LAN (Local Area Network)
–
A computer network that connects computers and devices in a limited geographical area.
• Wires: 4 pairs of twisted pairs inside a shield which again is twisted.
These 4 twists have a overall shoeld and an outer jacket.
5.9.1
Unicast
Sending of mesages (pachages) to a single network destination identified by a unique address.
5.9.2
Multicast
Sends data only to interested destinations by using special address assignments
29

Figure 14: Twisted pair in ethernet
5.9.3
Broadcast
Transmitting the same data to all possible destinations (every device on the network)
30

Figure 15: Unicast, multicast and broadcast
• Two wires carry equal and opposite signals and the reciever detects the difference between the two
• Noise sources introduces signals into the wires by coupling of electric magnetic fields and tend to couple both wires equally. The noise thus produces a common mode signal which is cancelled at the reciever.
• This method starts to fail when noise source is close to the signal wires; The closer wire will couple with the noise more strongly and the common mode rejection of the reciever will fail to eliminate it. This problem is especially apparent in long cables as one pair can introduce crosstalk in antoher, and it is additive along the length of the cable
• Twisting the pairs counters this effect as on each halv twist the wire nearest to the noise-source is exchanged. Providing the interfering source remains uniform, the induced noise will remain common node.
31

• The twist rate (twists per meter) makes up part of the specification for a given type of cable.
DAQ involves measuring signals (from a real-world physical system) from different sensors, and digitizing the signals for storage, analysis and presentation. A DAQ system consists of:
1. Sensors
2. Signal conditioning
3. Cables
4. DAQ hardware
5. Drivers
6. Software
32

Types of DAQ systems:
1. Laboratory DAQ
• Permanent location
• Can be a large and heavy installation
• Often rank mounted
• PC-based
2. Portable DAQ
• Small and light
• PC-based (conntected to a PC) or,
• Stand-alone units like data loggers that do not need a PC connection
3. Both 1. and 2. can be required to be ruggedized for use in the field
• Shock and vibration tolerant
• Water and dust protected
Types of DAQ signals: Analog input, analog output and digital I/O including data bus signals. Digital signal information: state, rate. Analog signal information: Level, shape, frequency. Two types of signal source:
• Grounded
–
Signal is referenced to a system ground.
–
Examples: Power supply, signal generators, anything that plugs into an outlet ground
• Floating
–
Signal is not referenced to a system ground
–
Examples: Batteries, thermocouples, transformers.
DAQ input channels can be configured in two ways:
• Differential
• Single-ended
–
Referenced Single-Ended (RSE)
–
Non-referenced single-ended (NRSE)
The optimal connection depends on how your signal is grounded
33

• One signal wire for each input signal
• Can be used for the following conditions
–
High level input signals (Higher than 1 V)
–
Short cables
–
Properly-shielded cables or cables travling through a noise-free environment
–
All input signals can share a common reference point (ground)
6.2.1
RSE
The RSE configutration is used for floating signal sources. (Fra NI: In a floating source, the voltage signal is not connected to any absolute reference or any common ground, such as earth or building ground. Floating signal sources are also called nonreferenced signal sources. Some common examples of floating signal sources are batteries, thermocouples, transformers, and isolation amplifiers. Notice in the figure that neither terminal of the source is connected to the electrical outlet ground, so each terminal is independent of the system ground) In this case, the DAQ hardware device itself provides the reference ground for the input signal.
6.2.2
NRSE
The NRSE input configuration is used for grounded signal sources. In this case, the input signal provides its own reference ground and the hardware device should not supply one.
34

• Two signal wires for each input signal
• The measurement is the voltage difference between the two wires
• Recommended for the following conditions:
–
Low-level signals (Less than 1 V)
–
Long cables
–
The input signals requires a separate ground-reference point or return signal
–
The signal leads go through a noisy environment
• DAQ devices with instrumentation amplifiers can be configured as differential measurment systems.
• Any voltage present at the instrumentation amplifier ground is called a common-mode voltage
• The instrumentation amplifier rejects common-mode voltage and common-mode noise
• Used on low-level signals that is fed to a DAQ device.
• Allows maximum use of ADC range and increases accuracy
• Increases signal to noise ratio, because noise are added after the amplifier, and the amplifier is close to the low-level signal source.
• Volatage divider
• Can be needed to get a high-level signal down to the acceptable DAQcard range
• Use AC coulpling when the signal contains a large DC component. If you enable AC coupling, you remove the large DC offset for the input amplifier and amplify only the AC component. This configuration makes effective use of the ADC dynamic range.
35

• Anti-aliasing low pass filter (before the A/D converter): To remove all signal frequencies that are higher than the input bandwidth of the device. If the signals were not removed, they would erroneously appear as signals within the input bandwidth of the device (known as aliasing)
• Filter types: LP, HP, BP, BS, Notch
• Important parameters for a LP-filter selection for DAQ bandwidth:
– f c
– f s
= cut-off frequency
= sampling frequency
–
BW = bandwith
36

• Remember: A lowpass filter with a small transistion band gives a wider passband/BW with a given sample frequency f s and a defined stoppband
• The number of bits used to represent an analog signal determines the resoultion of the ADC
• Larger resolution: more precise representation of you signal
• The resoultion determine the smallest detectable change in the input signal, reffered to as code width or LSB. code width = device range/2 resolution
37

• Pick a range that your signal fits in
–
Smaller ranger gives a more precise represenation of your signal, given that the signal is not clipped
–
If your signal is clipped, you can in general not determine the absolute signal levels
• Bipolar: From negative to positive
• Unipoler: From 0 to a positive value
• SNR = signal to noise ratio
• The number of bits used determines the maximum possible SNR
• Using the entire ADC range (using an amplifier) increases the SNR.
• The mimimum possible noise level is the error caused by the quantization of the signal, referred to as quantization noise.
1. Position noise sources (e.q. motors and power lines) away from DAQ devices, cable and sensor if possible
2. Place DAQ device as close to sensor as possible to prevent noise from entering the system
3. Twisted pairs, coax cable, shielding
4. Software filtering (e.q. averanging)
• Easy flexible, predictable, inexpensive.
• Unable to distinguish aliased signals from true ones.
38

• Most DAQ devices have:
–
Analog input and output
–
Digital I/O
–
Counters
∗ Frequency measurements (digital edge counting)
∗ Angular measurements from angular encoders
• Connects to the bus of your computer
• Compatible with a variety of bus protocols
–
PCI, PXI, CompactPCI, PCIe, PXIe, PCMCIA, USB
• Pros:
–
Rugged packaging that can withstand the harsh conditions that often exist in industrial applications
–
Modular architecture: You can fit several devices in the same space as a single stand-alone instrument, and you have the ability to expand your system far beyond the capacity of a desktop computer with a PCI bus.
• Key advantage: Integrated timing and synchronization.
• PXI chassis includes reference clocks, triggering buses and slot-to-slot local bus for the triggering/timing.
–
Any module in the system can set a trigger that can be seen from any other module
–
The local bus provides a means to establish dedicated communication between adjacent modules.
• PXI systems are composed of three basic components:
39

–
Chassis - contains the backplane for the plug-in DAQ cards. Provides power, cooling and communication buses for the PXI controller and modules.
–
Controller
–
Peripheral modules
• In computing, a device driver or software driver is a computer program allowing a higher-level computer programs to interact with a hardware device.
• A driver typically communicates with the device through the computer bus or communications subsystem to which the hardware connects.
Whan a calling program invokes a routine in the driver, the driver issues commands to the device. Once the device sends data back to the driver, the driver may invoke routines in the original calling program.
Drivers are:
1. Hardware dependent
2. OS specific.
• Software provides ease of use, flexibility, and performance in multiple programming evnironments.
40

• All NI-DAQmx devices unclude MAX, a configuration test utility. You can use MAX to:
–
Do lots of stoff
• The slowest method to move acquired data to system memory is for the DAQ-card to generate an interrupt request (IRQ) signal.
• The actual data move is fairly quick, but there is a lot of overhead time spent saving, setting up and restoring the register information.
• DMA is a system whereby samples (from an ADC) are automatically stored in a system memory while the CPU does something else.
• DMA permits peripherals such as a DAQ card, to transfer data directly to or from memory without having each byte handled by the CPU.
The DMA enables more efficient use of interrups and increases data throughput.
• The process of transferring data is given:
1. When data is ready for transfer, the DAQ card notifies the DMA controller
2. The DMA controller then asserts a DMA request signal to the
CPU, asking its permission to use the bus.
3. The CPU completes it current bus activity, stops driving the bus, and return a DMA ack signal to the DMA controller
4. The DMA controller then reads and writes one or more memory bytes, driving the address, data and control signals as if it were itself the CPU
5. When the transfer is complete, the DMA controller stops driving the bus and deasserts the DMA request signal. The CPU can the remove its DMA ack signal and resume control of the bus
• In single-cycle mode, the DMA controller gives up the bus after each transfer. This minimizes the amount of time that the DMA controller keeps the processor off the memory bus, but it requires that the bus
41

request/ack sequence be performed for every transfer. This overhead can result in a drop in overall system throughput if a lot of data needs to be transferred.
• In burst mode, the DMA controler keeps control of the bus intil all the data buffered by the requesting device has been transferred to memory.
Check out this bad boy
6.20.1
DAQ overwrite error
Indicates that info is lost and occurs when the software program does not read data from the PC buffer quickly enough. Samples that are written to the cirular PC buffer are overwritten before they are read into the application in memory. Solution: use producer-consumer architecture
6.20.2
DAQ overflow error
Indicates the info has been lost earlier in the data aquisition process. Overflow errors indicate the the FIFI memory buffer onboard the DAQ-card has reached its maximum capacity for storing acquired samples and can no longer accpett new samples. An overflow error is symptomatic of a bus transfer rate that falls short of the requested data input rate. Solution: Use a DMA transfer mechanism
• Race conditions - Two requests to the same shared resource
• Deadlock - two or more depended processes are waiting for each other to release the same resource
• Data loss - gaps or discontinuies when transferring data
• Performance degradation - poor processing speed due to dependencies on shared resources
• Buffer overflows - writing to a buffer faster than it is read from the buffer
• Stala data - reading the same data poing more than once
42

A timed loop gives you:
• Possibility to start the loop at a precise time (using a time stamp)
• phase (offset) control
• Possibility to specifies the processor you want to handle execution
• Exection priority
• Precise determinism in a real-time OS
Fra NI: Executes one or more subdiagrams, or frames, sequentially each iteration of the loop at the period you specify. Use the Timed Loop when you want to develop VIs with multirate timing capabilities, precise timing, feedback on loop execution, timing characteristics that change dynamically, or several levels of execution priority.
A trigger is a signal that causes a device to perform an action such as starting an acquisition. You can program your DAQ device to generate triggers on any of the following:
• A software command
• A condition in an external digital or analog signal (e.g. level triggering.
• Start trigger: Start DAQ when an external digital signal have a rising edge
• Pre-trigger: Incude a specified number of samples before the trigger event
• Post-trigger: Wait a specified number of samples after the trigger event before samples are acquired
43

6.25.1
Signal based
• Involves shareing signals such as clocks and triggers directly (wires) between nodes that need to be synchronized.
• In sytems where the devices are near each other, sharing a common timing signal is generally the easiest and most accurate method of synchronization. For example, modular instruments in a PXI chassis all share a common 10 MHz clock signal from the PXI backplane.
• NB: devices must be calibrated to account for the signal propagation delay from the timing source to the device
6.25.2
Time-based
• Involves nodes independently synchronizing their individual clocks based on some time source, or time reference.
• Necessary for long distances
• Because of the inherent instabilities in (crystal oscillator) clock, distributed clocks must be synchronized continuously to a time reference to match each other in frequency and phase. A crystal osciallator has almost 1 minute drift in one month.
44

• Is designed to synchronize the clocks of computers over a network
• Can provide accuracies of better than 10 ms over Ethernet
–
Accuracy depends on the network (LAN vs. Internet)
7.1.1
Sharing data
Transferring the actual data among computers where you can perform different analyses on that data, depening on your need. Some applications require streaming the actual data for additional processing, storage, or monitoring
7.1.2
Remote control
Expands the concept of sharing data to include enabling another computer to connect to the experiment and control that experiment remotely
45

7.1.3
Distributed execution
A system architecture that share the acquisition and analysis of the test among several computers
• Inter-process: The exchange of data takes place within a single application context
• Inter-target: Communication between multiple physical targets, often over a network layer.
7.3.1
Local DAQ
• Signals to be measured and the computer a placed close to each other
• Typically a plug-in DAQ-card is used in a PC, or a USB DAQ or PXI unit is connected to the computer
7.3.2
Remote DAQ
• Transfer data from a remote DAQ device to a single PC (host) for display and storage
7.3.3
Networked (distributed) DAQ
• Distribute measurement data to several clients connected to a network
46

• Enable a central computer to accuire all of the data from several machines and then process or store that data
• Network Data Transfer (TCP/UDP or LabVIEW applications)
• Remote Application Control (from LabVIEW)
–
VI server
• I/O buses
• Requirements for transfer for data and/or control between widely distributed measurement and control devices
• Requires reliable communication between devices
• One PC connected a PXI chassis, accuire, display and store all measurement data from several sensor systems
• Remote clients need to access to the sensor data, to display and process the data in real-time
47

• Pros
–
Remote measurements
–
Can be used where wiring is difficult or cost-prohibitive
–
Flexibility
• Cons
–
Low bandwith
–
Less reliable than wires
–
Possible security restrictions
• En overføringsenhet mellom noder
• Bit som skal overføres, pakkes inn i en ramme med ekstra bit foran og/eller bak. Hensikt:
–
Avgrense rammen
–
Detektere feil
–
Kontrollere flyt
Fra wikipedia: Each received Ethernet frame requires that the network hardware and software process it. Increasing the frame size makes a certain large amount of data transferable with less effort, reducing CPU utilization
(mostly due to interrupt reduction) and increasing throughput by reducing
48

the number of frames needing processing and reducing the total overhead byte count of all the frames sent.
Summary: You can transmit the same amount of data with fewer packets.
• Two of the most important communication protocols used for the Internet
• TCP complements the IP, which is unreliable.
• IP handles adressing and routing the message, while TCP provides a reliable and in sequence data delivery without errors, loss or duplication
7.10.1
TCP
• Is a connection based protocol, which means that a connection must be established before transferring data. It has:
1. Flow control (does not send data faster than the reciever can read)
2. Saturation control (slower transmission when network problems)
3. Retransmission of data when needed (data lost or not ack in time)
• Examples of use of TCP/IP: File transfer (FTP), HTTP
• In order to establish a TCP connection you have to specify an address and a port at that address
7.10.2
UDP
• Used for broadcast and multicast of data
• Not reliable (packets can be lost)
• No
1. Flow control
2. Saturation control
3. No retransmission of data
• UDP share the same delivery problems as IP
49

• Why UDP is fast:
1. UDP does not wait to confirm a connection before data transmission, and therefore no delay is introduced.
2. Small overhead compared to TCP
3. Send rate only limited by the rate of
–
Generation
–
CPU
–
Clock rate
–
Access to Internett Bandwith
• Example of use of UDP: Video conference, Sensor data distribution
Several screenshots of UDP/TCP send/recieve in LabVIEW in the lecture note. Take a look
• Data written to or read from a storage device at a sustained rate is often referred to as streaming
• Trends in data storage:
–
Ever-increasing amounts of data (Big Data)
–
Record “everything” and play it back later
–
Hard driver: faster, bigger and cheaper
–
Solid state drivers (SSD)
–
RAID hardware
–
PCI express since it provides higher, dedicated bandwidth
Registers within the CPU –> Cache -> MM –> Disks –> Off-line storage
(Tape)
50

• SRAM: Each bit stored in a flip flop
• DRAM: Each bit stored in a capacitor (transistor). Has to be refreshed.
• A PCI Express device recieves dedicated bandwith (250 MB/s or more)
• Data is transferred from onboard device memory device, across a dedicated PCI Express link, across the I/O bus and into system memory.
• Remember track and sector
• HDDs Internal Data Rate = density x RPM x disk diamater
• Therefore, outer tracks is faster, inner track slower
–
More data sectors on outer tracks, fewer data sectors on inner trakcs
–
Windows OS allocates file space from outer track and inward
• Sustained streaming rates is most affected by the rotational speed.
51

• Uses flash memory to store data
• Uses microchips which retain data in non-volatile memory chips and contain no moving parts.
• Uses the same interface as HDDs, thus easly replacing them in most applications
• Check out this bad boy
• Three types of SSDs: TLC, MLC, SLC
• Pros:
–
Robustness
–
Increased write/read speeds
–
Doesnt drop in write speed as it fills up
–
Low power consumption
–
Low heat
• Cons
–
High cost
–
Low capacity
–
Great quality variations have been experienced
8.6.1
SLC (Single Layer Cell)
• High performance
• Lower power consumption
• Most program/erase cycles
• Higher cost
• For embedded or industrial systems
52

8.6.2
MLC (Multi layer cell)
• Can store 2 bits in each cell
• Lower endurance limit
• Lower cost
• Good for consumer products
8.6.3
TLC (Three layer cell)
• Lowest endurance
• Slowest
• Best price
• Not suggested for critical or important applications
• Stream to disk or stream from disk can be affected by:
–
Running background programs such as virus scan
–
How the hard drive is formatted to group data
–
Location of the file on the hard drive.
• Users should
–
Have large clusters
–
Enable caching on disk (drives onboard buffer)
–
Turn off System Restore and Recyle bin as these will access the
HDD without your knowledge.
53

When determining the appropriate storage format for the data, consider the following:
• What will you do with you data once you have acquired them?
• Will you write and read data with the same application?
• How much data will you acquire?
• At what rate will you acquire data?
• Will you need to exchange data with another program?
• Will you need to search your data files?
8.8.1
ASCII Files
• Pros
–
Human-readable
–
Portable
–
Can easly add text info for each data column
• Cons
–
Large file size
–
Slow read and write
8.8.2
Binary files
• Pros
–
Compact file size
–
Fast streaming
• Cons
–
Not human readly
–
Less portable
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8.8.3
TDM and TDMS (Technical Data Managment Streaming)
• A file format from NI
• Tree levels of hierarchy
• Optimized for data storage and search.
• Pros:
–
Simple: Easiest approach for storing measurment data in NI SW
–
Flexibel: Add custom attributes to every file
–
Fast: TDMS is the TDM file for streaming applications
• High speed data acquisition
• Radar
• High resolution video
• Is a general term for mass storage schemes that split or replicate data across multiple hard drives
• To increase write/read performance and/or increase safety
• RAID examples: Internal RAID, Server RAID, Network attached storage (NAS) with RAID
Sjekk ut denne bad boyen
8.10.1
RAID-0
• Striping without redundancy
• Unimproved system reliability
• The fastest configuration
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8.10.2
RAID-1
Mirrored (redundancy)
• 100% data redundacy, each piece of data is written to two (or more) hard drives
• No write speed increase over single disk
• Highest overhaed
8.10.3
RAID-5
Distributed parity
• Parity data distributed on all disk
• Can tolerate one drive failure
• More write overhead
8.10.4
Parity: XOR method
• Is used both for the protection of data, as well as for the recovery of missing data
• To calculate the parity for a RAID, the bitwire OR of each drives data is calculated
• The parity data is written to the dedicated parity drive
• In order to restore the content of a failed drive, the same bitwise XOR calculation is performed agains all the remaining drives.
8.10.5
RAID-6
Double distributed parity
• Extends RAID 5 by adding an additional parity block
• Provides fault tolerant from two drive failures
• Very slow write
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8.10.6
RAID-10 (RAID-1 - THEN RAID-0)
• Both increased speed and redudancy
• Can sustain multiple drive failures
• Requires twice the number of hard drives
• Is the first code run by a PC when powered on (boot firmware). When the PC starts up, the first job for the BIOS is to initialize and identify system devices such as the keyboard, mouse and HDD.
• The BIOS then locates boot loader software held on a peripheral device, such as a hard disk or a CD/DVD, and loads and executes that
SW, giving it control of the PC. This process is known as booting, or booting up, which is short for boostrapping. Fra wikipedia: In general parlance, bootstrapping usually refers to the starting of a selfsustaining process that is supposed to proceed without external input.
In computer technology the term (usually shortened to booting) usually refers to the process of loading the basic software into the memory of a computer after power-on or general reset, especially the operating system which will then take care of loading other software as needed.
• BIOS SW is stored in a non-volatile ROM chip on the motherboard.
It is specifically designed to work with each particular model of compurter.
• In order to speed up the write of multiple (simultaneous) files it is recommended to write these files to speparate RAID volumes
• If for example tree equally fast high-speed digital video streams are to be stored on a 12 disk RAID, the RAID could be configured with 3 separate RAID volumes of 4 drives each.
• When streaming to or from controller memory or hard drives, the PCI controller (in the case of PCI), I/O bus, controller memory and proces-
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sor are shared data paths, which divides down data streaming bandwith.
• Additionally, the operating system, drivers and application software managing data flow introduce latencies
• With a PCI Express direct-to-disk controller module, data is streaming directly from the device memory onboard a DAQ-card, across the PCI or PCI Express bus, to the direct-to-disk controller for acquisition
• This gives a minimum use of the PCI-buss and the CPU
• A 32-bit processor can reference 2 32 bytes, or 4GB of memory
• A 64 bit processor are theoretically capable of referencing 2 64 in momery. However, Microsoft have some limitations locations
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• 64-bit versions of OS and applications programs can be slower
• The main benefit of 64-bit for DAQ applications is the large amount of RAM possible
• Other applications that can benefir from 64-bits are those working with very large numbers.
Use a producer-consumer structure. LabVIEW will automatically use multithreading.
• Until recently, the innovations have come in form of higher clock rates
• However, the clock rates has reack their theoretical physical limits, therefore, companies are developing new processors with multiple cores.
• Therefore, when programming, one must use parallel programming techniques to achieve the best performance and throughput.
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• Multiprocessor: Multiprocessor systems contain multiple CPUs that are not on the same chip
–
The multiprocessor system has a divided cache with long-interconnects
• Multicore Processors: Contain any number of multiple CPUs on a single chip
–
The multicore processors share the case with short interconnect.
Figure 16: Multicore processor
• A hyper-threading core pretends to be two “logical” processors to the
OS, allowing the OS to schedule two threads or processes simultaneously.
• It works by duplicating certain sections of the processor.
• Introduced by Intel
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Figure 17: Multiprocessor
• LabVIEW automatically divide each application into multiple execution threads if the tasks are not dependent on one another.
• It tasks are dependent on one antoher, LabVIEW will do the following:
1. Compiles and analyzes diagram and assings code pieces to
“clumps”
2. Information about which pieces of code can run together are stored in a run queue
3. If a block diagram contains enough parallelism, it will simultaneously execute in all system threads
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1. Increase code execution speed
• Execution time: time from start to completion of task (response time)
2. Maintain rate of execution but increase data throughput
• Throughput is the amount of work that can be done in a given time
3. Evenly balance tasks across available CPUs (fair distribution of processing load)
4. Dedicate time-cirital tasks to a single CPU
• One can speed up processor-intensive operations on large data sets by segmenting the data.
In computing, FLOPS (floating-point operations per second) is a measure of a computers´s performance.
• Many applications involve sequential, multistep algorithm. One task can be divided into subtasks.
• In this situation, applying pipeline can increase throughput.
• Pipelining introduces additional latency
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9.6.1
Balancing
• In order to gain the most performance increase possible from pipelining, individual stages must be carefully balanced so that no single stage takes a much longer time to complete than other stages.
• In addition, any data transfer between pipeline stages should be minimized to avoid decreased performance due to memory access from multiple cores.
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1. Race conditions - Two requests to the same shared resource
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2. Deadlock - two or more depended processes are waiting for each other to release the same resource
3. Shared resources (cores must halt in order for other cores to release resources)
4. Data transfer between processor cores
5. Thread (loop) synchronization
• Syncrionization mechanisms in LabVIEW:
(a) Notifiers
(b) Queues (most common)
(c) Semaphores
(d) Rendezvous
(e) Occurences
Physical distance between processor and the quality of the processor connections can have a large effect on execution speed
• An embedded system is a computer system designed to perform one or a few dedicated functions, often with real-time computing constraints.
• Embedded processors can be microprossors, microcontrollers, FPGAs and GPUs
• Embedded systems run with limited computer hardware resources:
–
Limited memory
–
Small or non-existent keyboard
–
Small or non-existent screen
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• Is the use of computer hardware to perform some function faster than is possible in software running on the CPU. Examples of hardware accelleration includes using GPUs
• Main difference between HW and SW accelaration is concurrency, allowing hardware to be much faster than software. Hardware accelerators are designed for computationally intensive code.
• The HW that performs the acceleration, when in a separate unit from the CPU, is referred to as a hardware accelerator.
• Buy COTS (Commercial-off-the-shelf) hardware when possible
• Examples of when a custom build is necessary:
1. High volumes
2. An iteration on an existing custom design
3. Custom size or shape required
4. Very stringent technical requirements (such as ultralow power consumption)
Detta er greit
Remember:
• Pros:
1. FPGAs give low-latency processing
2. High reliability
3. High determinism
4. High performance
5. True parallelism
6. Reconfigurable
• Cons:
1. But have limitations in terms of floating-point computations
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10.4.1
Common applications for FPGAs in DAQ and control systems
• High-speed control
• HW programmable DAQ cards
• Onboard processing and data reduction
• Co-prosessing (A CPU can use FPGA to do some of the computing)
Example: DAQ systems with a camera taking lots of pictures, instead of making the PC responsible for image prossesing, one can add a joint in between the DAQ and PC where FPGA do some image processing
10.4.2
How to program an FPGA?
• HDL (VHDL or Verilog)
• C-code (need a development tool)
• Automatic generaton of VHDL code from
–
Matlab
–
Simulink
–
LabVIEW From LabVIEW to FPGA:
1. Translation of graphic code to VHDL code
2. Optimization (analysis, logic reduction)
3. Synthesis (Place and route, timing verification)
4. Bit stream (10100011010101) LabVIEW supports Xilinx´s
IPs (building blocks)
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10.4.3
FPGAs in DAQ-systems
• DAQ-cards with a programmable FPGA
• Multi-rate sampling
–
Allows different sampling frequencies on the I/O channels
–
For comparision, when using an “ordinary” DAQ-card, all channels must have the same frequency
• Windows, Linux, MacOS, Unix are all non-real time
• A common example of an RTOS is an HDTV receiver and display. It needs to read a digital signal, decode it and display it as the data comes in. Any delay would be noticeable as jerky or pixelated video and/or garbled audio.
10.5.1
What is a real-time system?
• Gives you determinism
–
Real-time doesnt mean “real fast”, but it means that you can determine (predict) accurately when a section of your program will execute
• Hard real-time
–
Systems where it is absolutely imperative that responses occur within the required deadline (Ex: Fligh control systems)
• Soft real-time
–
Allows for some deadlines to be missed with only a slight degradation in performance but not a complete failure (Ex: DAQsystems)
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10.5.2
Real-time OS vs General Purpose OS
Features
General Purpose OS
User interface
Enerprise connectivity
Periphiral interrups
Applications Buffered DAQ
Offline analysis
Data presentation
Real-Time OS
Embedded
Deteministic
Control over OS
Background applications Scedule that ensures that highpriority tasks execute first
Closed-loop control
Time-critical decision making
Extended run time
Increased reliability
Standalone operation
10.5.3
Ethernet for real-time applications
• Standard Ethernet communication utilizes TCP/IP which is nondeterministic. In an effort bo boost deteminism, some network utilize custom technologies in the transport- and network-layers of the ethernet stack.
• These networks use TCP/IP as supplemental channel to provide non real-time data transfers. By bypassing (omgå) the TCL/IP protocols, such proprietary (merkebeskyttet) networks limit the end users ability to use the standard Ethernet products such as routers, switches, firewalls etc.
• Operations that allocated memory:
–
Array functions
–
String manipulation
• Non-deterministic functions
–
File I/O operations
–
Networking functions
–
Some I/O driver calls
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Three approaches to acquiring data from an external device or snchronizing communication between devices:
1. Polling - Involves periodically reading the status of the device to determine wheter the device needs attention
2. Interrups - THe device is configured to interrupt the processor whenever the device requires attention
3. Direct Memory Access (DMA) - A dedicated processor, the DMA controller, transparently transfer data from the device to computer memory or vice versa. Check out this bad boy
• In interrupt-driven systems SW is designed such that when a registrered event, such as a timer, is recieved, a response is fired to respond to this event.
• There are two componants of any intrrupt-driven system: the interrupt and the interrupt handler.
• An interrupt is a signal that is generated by hardware (for instance, the user presses a keyboard button), which indicates an event has occured that should halt the currently executing program
• Interrupt handlers are portions of code that are registered with the processor to execute once a particular interrupt has occured. Once the processor is aware of an interrupt, it halts the currently executing process, performs a context swith and executes the interrupt handler.
Once the interrupt handler code has executed, the processor return control of the previously running program.
• Have more transistors dedicated for processing than a CPU, therefore the performance gain when using GPUs can be significant.
• Can be used in Real-Time High-Performance Computing systems
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Fra wikipedia: CUDA (Compute Unified Device Architecture) is a parallel computing platform and programming model created by NVIDIA and implemented by the graphics processing units (GPUs) that they produce.
CUDA gives program developers direct access to the virtual instruction set and memory of the parallel computational elements in CUDA GPUs.
• GPUs can not be directly programmed with LabVIEW
• However, a framwork is designed to integrate GPU execution into Lab-
VIEWs parallel execution, to execute the CUDA code.
11.1.1
TAI (International Atomic TIme)
As a time scale is weighted average of the time kept by over 300 atomic clocks in over 60 national laboratories worldwide
11.1.2
UTC (Coordinated Unviversal Time)
Is the primary time standard by which the world regulates clocks and time, and is based on TAI but with leap secconds added at irregular intervals to compensate for the slowing of the Earths rotation.
• Time is now measured using stable atomic clocks
• A leap second is a one-second adjustment that is occasionally applied to UTC time in order to keep its time of day close to the mean solar time
–
Solar time is a reckoning of the passage of time based on the suns position in the sky
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• Are necessarly partly because the length of the mean solar day is very slowly increasing, and partly because the atomic, fixed-length SI second, when adopted, was already a little shorter than the current value of the seond of mean solar time
• GPS time is the atomic time scale implemented by the atoic clocks in the GPS ground control stations and the GPS satellites themselves.
• Periodic corrections are performed to the on-board satellite clocks to keep them synchronized with ground station clocks.
• GPS time is NOT corrected for leap seconds
• GPS time os NOT equal to UTC or TAI time
–
Has a constant offset of 19 seconds with TAI
11.4.1
Hardware clocks
• Real Time Clock (RTC) is an integrated circuit on the motherboard
• The RTC has a battery backup power so that it tracks time even while the computer is turned of
11.4.2
Software clocks
• Maintained by the operating systems, based on the RTC interrupts
• When the system starts it sets the system time to be a valued based on the real-time clock of the computer and then regularly updates the time based on interrupts from the RTC.
• High-precision event timer (HPET) is a 64 bit up-counter with a frequency higher than 10 MHz
• Time Stamp Counter (TSC) is a 64-bit regiter in the CPU (cores) that increment each processor clock cycle. However, can be unreliable on a modern multicore computer due to:
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–
Multicore computers have different values in their time-keeping registers
–
Variablility of the CPU frquency tue to power management technologies or performance technologies such as Intel Tubro Boost
Techhnologi.
• A quartz clock typically drift more than 1 second in six days
• The SW clock is a bad timekeeper
• Must be synchonized
• Global navigation system: A satellite navigation system with global coverage
• A satellite navigation systems can give very accurate:
–
Position
–
Velocity
–
Time
• The GPS receiever compare the time of the transmission of the coded signal from the satellite with the time of the arrival at the reciever. This means that a GPS reciever will tell you how far away you are from a satellite, and of course the satellite knows its position. However, by using only one satellite, you can be on an infinite number of places, placed on a sphere around the satellite. Therefore, one must use 3 satellites and use the intersection point of all three spheres to get your exact location. However, one must also use fourth satellite to get the correct time.
• Considerations when measuring distance
–
Variations in netural density
–
Temperature
–
Humidity in the athomsphere
–
Electron density in the ionosphere
• More satellites gives better accuracy.
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• Used to increase the GPS position accuracy
• Reference stations on known locations on the Earch can calulate the position based on C/A coded signalds, an compare with the known location of the station. This gives the postion error from the GPS system, and this error can be broadcasted to all recievers.
• The accuracy depends on the distance from the refernce station(s)
• For further explanation, check out this babe
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