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A CMOCS-Comnatihle C omnct T)Dignlav .... " ............. by MAssACHUSS OF TECh'Nt )OGY Andrew R. Chen OCT 21 Bachelor of Science in Electrical Science and Engineering Massachusetts Institute ot 'lechnology, June 1990 ~ , . . ~ . .. r ran ,r t T~ r AN~ 2005 LIBRARIES /-1 Master of Engineering in Electrical Engineering and Computer Science Massachusetts Institute of Technology, June 1997 Submitted to the Department of Electrical Engineering and Computer Science in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy at the MASSACHUSETTS INSTITUTE OF TECHNOLOGY June, 2005 MASSACHUSETTS INST1ITUTE OF TECHNOLOGY © 2005 Massachusetts Institute of Technology OCTLIBRARIES2005 All Rights Reserved LIBRARIES Signature of Author ................... , ..... Y. Department of Electrical Engineering and Computer Science April 27, 2005 Certified by.............. .............. .. ... , ..................... Hae-Seung Lee Professor of Electrical Engineering / Certified by .............................. Accepted Acceptedby.(y,-~C.i' by ........... .. .. .... [ /if ThesisSupervisor ......... .............. ~~/ ~ Akintunde I. Akinwande Professor of Electrical Engineering Thesis Supervisor .L .................... -: ..--. Arthur C. Smith Chairman, Committee on Graduate Students Department of Electrical Engineering and Computer Science A CMOS-Compatible Compact Display by Andrew R. Chen Submitted to the Department of Electrical Engineering and Computer Science on April 27, 2005, in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering and Computer Science Abstract Portable information devices demand displays with high resolution and high image quality that are increasingly compact and energy-efficient. Microdisplays consisting of a silicon CMOS backplane integrated with light generating or modifying devices, are being developed for direct-view and projection applications. A microdisplay architecture using silicon light emitters and image intensification suitable for a micro-projector application is developed. A standard low-voltage CMOS IC incorporating display drivers and an array of avalanche diodes produces a faint optical image, and an image intensifier efficiently amplifies the image to useful brightness. This architecture has high efficiency and the potential to achieve adequate luminance for projection applications. A proof-of-concept system with 16x32 arrays is implemented and evaluated. A high-performance silicon backplane for the above system is designed, implemented, and evaluated. The backplane is a standard CMOS die including a 360x200 pixel array with silicon light emitters, and 10b precision current-mode driver circuits. The driver circuits can support a number of emissive display technologies including silicon light emitters and organic light emitting diode (OLED). They employ a self-calibration technique based on the current copier circuit to minimize variation and fixed-pattern noise while reducing circuit area by a factor of five to seven compared to a conventional solution. A circuit technique to improve the retention time of dynamic analog memories is also presented. This technique allows a dynamic analog memory to retain 10b precision for 500ms at room temperature. Thesis Supervisor: Hae-Seung Lee Title: Professor of Electrical Engineering Thesis Supervisor: Akintunde I. (Tayo) Akinwande Title: Professor of Electrical Engineering 4 Acknowledgements FIRST I would like to thank my co-advisors Harry Lee and Tayo Akinwande for their support and thoughtful guidance throughout my doctoral program. They have helped me with matters large and small, from technical answers to publishing and professional planning. Their straightforward style and pursuit of quality results are a source of inspiration for many students. I would also like to thank Tom Knight for reading my thesis and providing insights into the design of microdisplays. It has been a privilege to be part of the Lee-Sodini lab, and I am thankful to my friends and labmates for the discussions, help, and fun times we have shared. Iliana Fujimori showed great patience and teaching skills not only as a co-teaching assistant, but also by introducing me to imagers, and sharing test chips with me for making initial measurements. I've learned a lot from Todd Sepke, Anh Pham, and Albert Jerng with whom I've shared a cubicle for the last two years. Mark Spaeth provided a much wisdom in printed circuit board design, and arcade games. Pablo Acosta, Ayman Shabra, Mark Peng, Don Hitko, and Dan McMahill all had answers to my persistent questions as I started my research. I am thankful to Duane Boning for introducing me to the intricacies of process variation in semiconductor manufacturing. and system design. This basic knowledge is valuable at all levels of circuit Thanks to Professor Vladimir Bulovic and Yakov Tischler for help in making optical measurements, and for advice relating to organic LED technology. John Kmyssis and Annie Wang provided help with electro-optical measurements and data analysis. I am grateful for the support of family and encouraged me and helped me to grow. She has hours. Thanks to my friends for sharing these scattered around the country, we are still close. years, and I will always love them. friends. My fiancee Lucy has consistently also put up with my graduate student work years together. Although many of us are My parents have cared for me for all these Integrated circuit fabrication was provided by National Semiconductor. Peter Holloway, Matt Courcy, Mike Guidry, Sangamesh Buddhiraju, and the physical design staff all contributed valuable advice and assistance. This research was funded by the MARCO Focus Center for Circuit & System Solutions (C2S2, www.c2s2.org), under contract 2003-CT-888. 6 Biography ANDREW R. Chen received the Bachelor of Science and Master of Engineering degrees in electrical engineering from the Massachusetts Institute of Technology, Cambridge, in 1996 and 1997, respectively. From 1997 to 1999 he was a design engineer at Intel Corporation, Santa Clara CA, designing circuits for Intel Architecture 32b and 64b microprocessors. He is currently a Ph.D. candidate at the Massachusetts Institute of Technology studying analog and mixed-signal integrated circuit design. His research interests include analog and mixed-signal integrated circuit design, imaging systems, and electronic display systems. 8 Contents 1 Introduction to Displays 1.1 Overview. 1.2 Electronic Display Applications and Technologies 1.3 Brightness and Efficiency ............. . . . 1.4 Microdisplays .............. . 1.5 Micro-projector ............. . 2 3 Background 2.1 Silicon Light Emission .......... 2.1.1 Previous Work and Applications . 2.1.2 Avalanche Breakdown ...... 2.2 Device Measurements ........... 2.2.1 0.8 /tm Technology ........ 2.2.2 0.35/im Technology ....... 2.2.3 0.18tm Technology. 2.2.4 Measurement Summary ..... 2.3 Image Intensification ........... 2.4 Circuit Design for Displays ........ 2.4.1 MOS Transistors ......... 2.4.2 DAC Fundamentals ........ 2.4.3 Calibration Techniques ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 . . 17 . . 18 . . 20 . . 22 . . 23 25 ... . 25 . . . . 25 . . . . 26 28 28 30 .................. .................. .................. .................. .................. 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... ... ... ... 31 .... Micro-projector Design 3.1 3.4 3.3.6 3.3.7 Results 37 37 40 41 45 Design Overview ............. 3.1.1 Background: Two-stage displays . 3.2 Micro-projector Efficacy ......... 3.3 Test Chip Implementation ......... 3.3.1 IC overview ............ 3.3.2 Pixel ............... 3.3.3 3.3.4 3.3.5 ... ... ... . . . . . . Pixel Arrays ............. . Top-level IC Design and Packaging . System Design .. . . . . . . . . Image Intensifier and Optics ..... . Proof-of-Concept System Performance . . . . . . . . . . . . . . . . . . . . . . . . . 9 . · . . . . . . . . . . . ... ... ... ... ... ... ... ... ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 46 47 50 51 51 52 53 54 55 56 . 57 ... CONTENTS 10 3.4.1 3.4.2 3.4.3 3.4.4 4 Single Pixel .............................. Arrays. ................................ Power Measurements ......................... Discussic)n ................... ........... Backplane IC Design 4.1 Pixel Array. 4.2 Row Drivers ........... 4.3 Column Drivers and Calibration 4.3.1 Overview........ 5 6 4.4 4.3.2 Area Comparison .... 4.3.3 Current Copier ..... Biasing ............. 4.5 4.6 RefDAC ............. ArrayDAC ............ 4.7 Design for Testability ...... 4.8 Top-level IC ........... 4.9 System Board and Optics . . . . Measured results 5.1 Electrical Measurements 5.1.1 RefDAC Linearity 5.1.2 ArrayDAC .... 5.2 5.1.3 Column Variation . Optical Measurements .. 5.3 5.4 Power Measurements . . . Sample Images ...... Summary Topics for Future Investigation A Precision Oscilloscope Measurements 58 59 60 63 . . . . . . . . . . . . ................. ................. ................. ................. ................. ................. ................. ................. ................. ................. . . . . . . . . . . . . . . . . . . . . . . . . 63 67 68 68 69 70 75 79 83 86 88 89 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 95 ...... 101 ...... ...... ...... ...... 103 105 108 108 Discussion 6.1 6.2 57 111 . . . . . . . . . . . . . . . . . . .. 111 ............ ........ 112 115 List of Figures . 1.1 Applications of electronic displays ............. 1.2 Flat-panel 1.3 Micro-projector . . . . . . . . . . . . . . . display technologies I-V characteristic ...... 20 . . . . . . . . . .... concept (Fraunhofer-Gesellschaft) breakdown 19 24 2.1 Avalanche 2.2 Cross-section of twin-well CMOS process 2.3 Diode I-V characteristic, 2.4 2.5 2.6 PMOS test device ............................... I-V curve for p+/nwell junction in 0.35/um CMOS technology ....... I-V curve for n+/psub junction in 0.35tim CMOS technology . . . . . ... 2.7 Light emission 2.8 I-V curves for two p+/nwell junctions in 0.18um CMOS technology . . . . 0 . 8 /m . . . . . . . . . . . . . . ..... process 27 .................. . from six parallel test devices 27 ................. . 29 29 30 30 . . . . . . . . . . . . ..... 31 32 2.9 Spectraof light emissionfromjunctionson CMOSdie . . . . . . . . . . . 32 . 2.10 Light output vs. current for junction in 0.18,um CMOS process ..... 2.11 . . . . . Intensifier gain vs. number of MCPs . . . . . . . . . . . . . . . Intensifier resolution vs. number of MCPs . . . . . . . . . . . . . ..... . Simple image intensifier . . . . . . . . . . . . . . . application ....................... 2.12 Microchannel plate (Proxitronic) 2.13 2.14 32 2.16 Gate current for an NMOS device . 34 . 2.15 GaAs Photocathode Sensitivity (Hamamatsu) 34 35 35 ............... 36 ..................... 38 2.17 Sample and Hold Circuit models. Left: ideal, Right: realistic ........ 39 2.18 Current mirror measurements . . . . . . . . . . . . . . . . . ...... 40 3.1 CMOS IC and image intensifier . . . . . . . . . . . . . . . . . 3.2 Two-stage display architecture for projection application (JVC) ....... 46 3.3 Circuit schematic of a single pixel 52 3.4 Block diagram 3.5 IC photomicrograph 3.6 3.7 .. Proof-of-concept system board Proof-of-concept system with intensifier 3.8 Pixel I-V characteristic, VHI sweep 3.9 Test image of IC under microscope of pixel array . .. ..................... . . . . . . . . . . . . . . . 53 . ...... 54 .............................. . 54 56 ...................... .................. 58 ...................... . 45 . . . . . . . . . . . . . . 58 3.10 32-level grayscale gradient. Bottom two rows are at full intensity ...... 59 3.11 Output window of intensifier (20mm) with sample image . . . . . . . ... 60 11 LIST OFFIGURES 12 4.1 4.2 4.3 Overview of CMOS backplane ..... . . . Pixel schematic ............. . 4.4 OLED material layers .......... . 4.5 OLED pixel schematic ......... . 4.6 Row driver circuit . . . . . . . .. . . . 4.7 Rnw drive.rtiming . 4.8 Two-stage calibration technique ........ . . . . 4.9 Column driver calibration overview .. 4.10 Simple MOS current source ........... . 4.11 Simple current copier .............. . 4.12 Reduced transconductance current copier . . . . 4.13 Improved current copier .. . . . . . . .. . . . 4.14 Passgate leakage scenarios: (a) conventional, (b) voltage Array floorplan a.e,'., 4.15 4.16 4.17 4.18 .a·'v ~ s .A ............. e, . . . . . . . . . . . . . . . . Conventional (left) and improved (right) passgate RefDAC reference current generator and switch Bleeder bias voltage generator. VBIAS circuit ................ 4.19 Testability control circuit .......... 4.20 Testability scan chain ............ 4.21 RefDAC block diagram ........... 4.22 RefDAC current copier circuit .. . . . . . 4.23 RefDAC row driver ............. 4.24 RefDAC column driver ........... 4.25 RefDAC cell pattern ............. 4.26 RefDAC copier cell settling time simulation 4.27 Retention time improvement circuit . . . 4.28 ArrayDAC copier schematic ........ 4.29 ArrayDAC block diagram .......... 4.30 ArrayDAC registers ............. . 4.31 ArrayDAC data load control. 4.32 4.33 4.34 4.35 4.36 4.37 4.38 4.39 4.40 ArrayDAC calibration control ....... ArrayDAC calibration control, improved . . 5.1 Synchronization circuit ........................ 5.2 5.3 RefDAC bit currents, first attempt .................. RefDAC bit currents, second attempt ................. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 64 64 65 66 66 67 67 68 69 70 71 72 73 74 ... ... ... ... ... ... ... ... ... ... ... ... ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 77 78 78 78 79 80 80 80 81 82 82 83 84 85 85 85 86 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... :s .............. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Micrograph showing Si-LED pixels, OLED pixel s, and ArrayDACs . . . . 87 Column transimpedance amplifier ..... Die micrograph ............... High-level program flowchart ........ Clock oscillator ............... Timing diagram - simple program ..... Timing diagram - optimized ........ 4.41 Assembled system board .......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 89 92 93 93 94 94 95 96 97 ... ... ... ... ... ... ... LIST OFFIGURES 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 13 RefDAC INL, second attempt .......... RefDAC bit currents, final ........... RefDAC INL, final ............... RefDAC retention test .............. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RefDAC retention test, zoomed in . . . . . . . Transimpedance amplifier circuit . . . . . . . . ............... 100 ArrayDAC INL ................. ArrayDAC retention test ............ ArrayDAC output current distribution ..... ArrayDAC outputs before and after calibration . Sample image for pixel luminance analysis . . Pixel luminance variation by column ...... Column luminance ............... ............... 102 ............... ............... 104 105 ............... ............... 98 98 99 100 101 ......... ......104 103 ............... ......... ...... 106 ......... ...... 107 Silicon backplane IC emitting light, showing a se,ries of ramps ....... Proof-of-concept system with calibrated backplai ne ............. 109 109 5.19 Proof-of-concept system with calibrated backplane and alternative optics . .110 6.1 RefDAC, ArrayDAC, and pixel arrangement. 6.2 Alternative RefDAC, ArrayDAC, and pixel arrangement .116 .116 .117 time . . . . . . . . . . . . . . . . . . . . . . . . . . .117 .118 step response . . . . . . . . . . . . . . . . . . . A.1 Step responses of four oscilloscope probes. A.2 Probe settling behavior ........................... A.3 Four oscilloscope channels, same input ................... A.4 A.5 Longer observation Newer oscilloscope .112 . . . . . . . . . .113 ... ... 14 LIST OF FIGURES List of Tables 1.1 Typical illumination levels 1.2 1.3 Projector illuminance by application . Efficiency of light sources ....... Intensifier Performance with two MCPs 3.2 0.18/um CMOS technology ...... 3.3 Microcontroller interface definition . . . 3.1 4.1 4.2 4.3 4.4 4.5 PreRef switch truth table ........ ArrayDAC current mirror biasing . IC power supplies ............ Input pins ................ Output pins . 20 . . . . . . . . . . . . . . . . . . . . . . 15 . . . . . . 21 . 22 ................... ................... ................... ................... ................... ................... ................... ................... 49 50 55 76 84 90 91 92 16 LIST OF TABLES Chapter 1 Introduction to Displays 1.1 Overview This thesis presents work in electronic display design and integrated circuit design. Electronic systems are becoming increasingly ubiquitous, and displays for a wide spectrum of applications are being developed. An area of special interest is that of personal portable electronics, where all system components must be designed for high levels of integration, compact size, and high energy efficiency. The design of a "micro-projector" for portable electronic systems is presented. The micro-projector produces an image with adequate luminance for projection with high efficiency for battery-powered systems. We propose a micro-projector based on a combination of silicon light emission and image intensification. A standard low-voltage CMOS IC incorporating display drivers and an array of avalanche diodes produces a faint optical image. The image is coupled into an image intensifier that amplifies the image to useful luminance levels. This architecture has high efficiency and the potential to produce adequate luminance for projection applications. The advantages of this architecture are compatibility with mainstream CMOS processes, high efficiency,and potential for projection. Junction diodes which are available in all standard CMOS processes are used to emit light. Process modifications which are often used in imagers [26] and microdisplay ICs are not necessary. These junctions can be integrated with high-performance circuits such as calibrated display drivers. The integrated display can also be integrated with other circuit blocks to achieve a high level of system integration on a single IC. The image intensifier is a vacuum device capable of high gain. It uses the mechanism of cathodoluminescence to efficiently generate light, and can produce adequate luminance for projection applications by using the same principles as projection CRT tubes. A high-performance silicon backplane for the above system is designed and evaluated. 17 CHAPTER 1. INTRODUCTION TO DISPLAYS 18 The backplane is an IC produced in a standard CMOS technology. It includes a 360x200 pixel array with silicon light emitters and 10b precision current-mode driver circuits. The driver circuits can support a number of emissive display technologies including silicon light emitters and organic light emitting diode (OLED). They employ a self-calibration technique to minimize variation and fixed-pattern noise while reducing circuit area by a factor of five to seven compared to a conventional solution. A circuit technique to improve the retention time of dynamic analog memories is also presented. The organization of this document is as follows. The remainder of this chapter is an overview of electronic display technologies and applications. Chapter 2 provides background on silicon light emission, operation of the image intensifier, and circuit design concepts relating to display drivers. Chapter 3 presents the design, implementation, and results of a proof-of-concept display system using two-stage image generation. Chapter 4 presents the design of a high-performance CMOS backplane for the previously described microdisplay architecture. Chapter 5 describes characterization and measurements of the system with calibrated backplane. Finally, chapter 6 summarizes and suggests topics for future investigation. 1.2 Electronic Display Applications and Technologies An electronic display is a device that converts time-sequential electrical signals into spatially and temporally configured light signals (images) useful to the viewer [1]. Electronic displays are used in a broad variety of applications, some of which are shown in Figure 1.1. The variety of applications results in a large number of technologies currently in use [2, 3]. The cathode-ray tube (CRT) has been a workhorse for many years. Newer displays are based on flat-panel technologies which have the advantages of smaller form factor, lighter weight, and the ability to achieve larger sizes than CRTs. Flat panel display technologies can be divided into categories as shown in Figure 1.2. Displays that generate light in response to electrical signals are called emissive displays, and ones that modulate light are called light valve displays. Examples of mechanisms used in emissive displays are electron-hole recombination in semiconductors, ultraviolet radiation exciting a phosphor, or an electron beam exciting a phosphor. Light valves are examples of a broader class of devices known as spatial light modulators (SLM). These create spatial modulation on a plane wave of light by various means, for example by reflection or change in polarization. SLMs require an external source of light which may be a lamp or ambient illumination. The most widely used SLM is the liquid-crystal display. It is versatile and inexpensive, but transmission is typically low and the operation at extreme 1.2. ELECTRONICDISPLAY APPLICATIONSAND TECHNOLOGIES 19 Pixels 10M IM lOOK 10K 1K 0.3" lin 3in 10in 30in l00in diagonal Figure 1.1: Applications of electronic displays temperatures is difficult. Emissive displays potentially have higher efficiency than SLMs because they generate light only when and were it is needed. In contrast, SLM's require a light source to constantly produce the maximum display luminance, and dissipate unwanted light as heat. Emissive and transmissive displays work well under moderate illumination, but have difficulty producing very high luminance for applications in sunlight. Reflective SLMs work well under high illuminance but have reduced energy efficiency under low and moderate illumination levels where they require an external light source. Projection systems have the advantage of producing a larger image than than the system form factor. Two applications of projectors are digital cinema and portable information systems. Digital cinema is an application where very large video-rate images are desirable. Flat-panel displays are available in sizes up to 40 inches, but a projector is lighter, potentially cheaper, and easier to scale to larger sizes. Portable electronic information systems that are becoming smaller and handling increasing quantities of still and video images. In this application the goal is to produce page-sized images for personal viewing while keeping a pocket-sized form factor. The focus of this work is a micro-projector intended personal information systems. These are compact electronic systems that will include communication, computing, multimedia manipulation, and data storage. They have been described in literature with various CHAPTER 1. INTRODUCTION TO DISPLAYS 20 Flat panel displays Emissive semiconductor: OLED UV+phosphor: Plasma electron beam + phosphor: Cathodoluminescence Modulator polarization: Liquid crystal reflection: micromirror transmission: electrowetting Figure 1.2: Flat-panel display technologies Conditions Direct sunlight Open shade Overcast day Twilight Full moon Indoors, exacting visual tasks Indoors, fine assembly work Indoors, office Indoors, home Illuminance, lux 100,000 10,000 1,000 1 to 10 0.1 15,000 1,000 500 100-200 Table 1.1: Typical illumination levels terms, such as "information bank system" [4]. The constraints of these systems are compact size, high energy efficiency to maximize battery life, high resolution, high bit depth, and video speed. 1.3 Brightness and Efficiency This section describes typical illumination levels of various environments, and the required luminance or illuminance levels for displays. Typical levels of illumination are listed in Table 1.1. The ratio of illumination varies over a 1000:1 ratio from full sunlight to indoors at night. This results in a variety of displays optimized for different ambient lighting conditions. The luminance of an emissive display for indoor use such as a television or computer 1.3. BRIGHTNESS AND EFFICIENCY Application Movie theater 21 Illuminance (lux) Comments full control of ambient light 50-80 Office 120-150 Ballroom (dimmed) Training room (dimmed) Training room (full light) 150-200 200 400 high background illumination Table 1.2: Projector illuminance by application monitor is 25-100 footlamberts. Emissive microdisplays used in head-mounted display systems (HMDs) require much higher luminances because optical transmission (throughput) is around 15%. Typical luminance is 1000fL at the display output, which appears as 150fL to the eye. The required luminance of a projector depends on a number of factors. The contrast ratio determines the ratio between maximum projector illuminance and ambient illuminance. The output of the projector is spread over the image area, leading to a tradeoff between illuminance and image size. The properties of the surface where the image is projected also affect illuminance. An ordinary white surface has a gain of unity. Projection screens with non-uniform reflection patterns can increase gain in a preferred direction, at the cost of limited viewing angle and contrast. The illuminance of a projector is: luminance(lumens) 2 ae(m area(m2) * gain = illuminance(lux) (1.1) where the luminous output of the projector is in lumens, the area of the projected image is in square meters, the gain is unitless, and illuminance is in lux. Required illuminance by application is shown in Table 1.2. A variety of light-emitting technologies are used today. Table 1.3 compares some commonly used ones. Metal halide bulbs are attractive for projectors because of their high efficiency, high luminous output, and near point-source emission. Organic and inorganic LEDs are making rapid progress in efficiency, brightness, and the variety of output spectra available. Phosphor-based light emitters include fluorescent lamps and cathodoluminescent devices. In these devices, a phosphor converts energy from ultraviolet light or an electron flux into visible light. Fluorescent lamps are efficient, but because of their large sizes they can only be used as backlights for modulator-based displays which have low efficiency due to transmission losses. The cathode ray tube is an example of a cathodoluminescent display. These can produce extremely high luminance levels, as illustrated by liquid-cooled tubes used in projection televisions. CHAPTER 1. INTRODUCTION TO DISPLAYS 22 Efficiency (lumens/watt) Notes Technology Metal halide (HID) 50-100 10-400W T8 Fluorescent Compact fluorescent 80 30-60 4-foot, 32W Cathodoluminescence OLED 48 10-30+ [5] White inorganic LED 32+ Halogen 12-20 10-100W Incandescent 6-17 7-100W Table 1.3: Efficiency of light sources 1.4 Microdisplays Microdisplays produce high-resolution images typically less than one inch on a side. They are commonly used in both the smallest and the largest display applications. Typical nearto-eye devices are head-mounted displays [6] and video camera viewfinders. In these devices, optics provide magnification for comfortable viewing. Projection applications include high-definition televisions and computer projectors. In these systems, the microdisplay modulates very high luminance levels from an external light source. Microdisplay technologies are also being applied to novel applications such as three-dimensional displays [7], switching of optical communication signals [8], high-end photo printers [9], and optical tweezers [10]. An emerging opportunity for microdisplays is the micro-projector. The micro-projector is part of a pocket-sized personal information device. It projects a high-resolution image approximately the size of a piece of paper (8in = 20cm) for personal viewing. Its main advantage is the ability to produce images of reasonable size with a very small form factor. The micro-projector must produce high luminance, high resolution images while being compact and highly energy efficient. Emissive microdisplays can be designed to have these characteristics. Presently the leading technologies for microdisplays are liquid crystal on silicon (LCOS) [11], micromirrors, and organic LED. These technologies can be constructed on top of a silicon integrated circuit with additional processing. Using a silicon backplane provides access to high-performance circuits at the pixel or array level, and alleviates the problem of large numbers of interconnect wires between the pixel array and driver circuits. Liquid crystal displays use an organic material to modify the polarization of light. Pixels are modelled as capacitive elements and driven with AC voltage waveforms. A variety of circuit techniques for driver circuits have been investigated [12, 13]. Color is usually 1.5. MICRO-PROJECTOR 23 achieved by using patterned color filters and sub-pixels for red, green, and blue, at each pixel location. Micromirrors are an array of mirrors on top of a silicon chip that are controlled electrically. At each pixel location, a mirror reflects light to either the output or a heat sink [14]. Color output is achieved in frame-sequential mode using a rotating color filter wheel. Organic LED is an emissive technology that promises high image quality and reasonable manufacturing cost. OLED microdisplays with silicon backplanes have been demonstrated [15, 16]. They promise excellent image quality and potential power savings because of their emissive nature. OLED performance has been steadily improving, and packaging and sealing [17] have also improved in recent years. Color can be produced either by filter- ing of a white image (similar to the case of liquid crystal), or by stacking layers of different light-emitting materials to produce different colors. 1.5 Micro-projector A micro-projector would allow a pocket-sized electronic system to display high information content images and video at a reasonable size for comfortable viewing. Because a projector produces images larger than its own form factor, the system can be pocket-sized while producing page-sized images. The cost of computation has decreased to a point where the display, user interface, and battery are primary bottlenecks in portable system design. A compact display capable of presenting high resolution images and video enables new uses for portable electronic systems. Figure 1.3 is an illustration of this concept [18]. This contrasts with the flat-panel display approach where the system must be larger than the image size, or the display must be designed to fold or roll-up when not in use. Compact projector systems have been demonstrated and are described in the literature. Keuper [19] describes a projector consisting of a white LED light source, liquid-crystal modulator, and lens. Projectors using lasers, either a raster-scanned single beam or multiple beams in parallel, have also been demonstrated [20, 21, 22]. For near-to-eye applications, a laser beam can be modulated and swept onto the retina to produce an image [23, 24, 25]. Laser-based projectors do not require refractive optics for focusing, which may permit them to be more compact than ones using lenses. They also have good energy efficiency. The disadvantages of these systems are (1) they require precision mechanical systems to position the laser beam, (2) they must address the problem of image flicker because they operate at low duty cycles, and (3) safety concerns if the beam is pointed at the eye, or if higher power is used to produce high luminance images. 24 CHAPTER 1. INTRODUCTION TO DISPLAYS Figure 1.3: Micro-projectorconcept (Fraunhofer-Gesellschaft) Chapter 2 Background This chapter presents previous work and preliminary studies on components of our microprojector design: silicon light emitters, image intensifiers, and calibrated driver circuits. An introduction to light emission from silicon is presented along with measurements of light emitters in standard CMOS processes. The image intensifier and its basic concepts are introduced. Display driver circuits are digital-to-analog converters (DACs). An overview of DACs is presented along with circuit and device considerations that influence their design. A major concern in data converter design is the management of variation that arises from the manufacturing process. A circuit called the current copier can produce precise currents while occupying less area than a conventional solution. The current copier is introduced here, and its implementation is discussed in depth in Chapter 4. 2.1 Silicon Light Emission 2.1.1 Previous Work and Applications The emission of light from silicon p-n junctions was first reported in 1955 [27, 28]. Since then, it has been used for a variety of purposes. Silicon light emitters were used in a data storage system to produce dots on photographic film [29]. Light emission from the channels of MOSFET transistors has been used for debugging and fault analysis of microprocessors [30]. The idea of using integrating light emitters and detectors on the same chip dates back to at least 1965 [31], and the application of on-chip optical interconnect is receiving atten- tion as metal wires have become a bottleneck in the design of high performance integrated circuits [32]. Silicon is an indirect bandgap material, therefore when electrons and holes recombine 25 CHAPTER 2. BACKGROUND 26 the probability of a photon being emitted is small. This is in contrast to the III-V materials used commercially in LEDs that are efficient photon sources. In forward bias, p-n junctions emit photons with energy equal to the bandgap energy. In silicon this is 1.12eV, corresponding to photons with a wavelength of 1100nm. In avalanche breakdown, hot electrons can cause photons with higher energies to be emitted. Lightemitting devices in standard CMOS technologies have been studied [33, 34], and the best reported quantum efficiency is 5 * 10 - 7 phot/elec [35]. Efficiently generating light from a silicon substrate is an area of research interest [36, 37]. Efficiency can be improved by various dopants or altering the shape or material properties of silicon devices [38, 39]. These advances may eventually be integrated into mainstream manufacturing processes. Another solution is the integration of efficient optoelectronic devices on a standard silicon substrate [40]. Novel device and circuit designs for light emitters are being explored, for example a structure to lower the breakdown voltage of silicon light emitters [41]. 2.1.2 Avalanche Breakdown This section explores the properties of silicon junctions in avalanche breakdown used as light emitters. Light emission from avalanche breakdown produces photons with larger energies than the bandgap energy. Emission can be in the visible or near-infrared regions of the spectrum. When a junction diode is biased with a large negative voltage, the electric field across the junction is very large. When a conduction band electron enters the field, or is created by thermal processes, collisions with valence electrons can move them into the conduction band. A cascading or multiplying effect occurs, and the current grows dramatically over a small voltage range. The I-V characteristic of a silicon p+/nwell junction in avalanche breakdown has the shape shown in Figure 2.1. Current through the junction grows until limited by external components such as series resistance or a current source circuit. Operating a junction diode in reverse breakdown is nondestructive if the current through the junction is limited. Spinelli and Lacaita [43] provide a more detailed description of avalanche diode physics. This abrupt characteristic allows the use of low-voltage control circuits. A large DC bias is needed to make the junction enter avalanche breakdown, but once avalanche breakdown occurs the change in voltage required to modulate the current is very small. Consider a junction with the characteristic in Figure 2.1. The cathode is connected to a +12 volt supply, and the anode to a "leakage "current sink of lnA in parallel with an adjustable current 2.1. SILICON LIGHT EMISSION nited le-3 le-4 avalanche le-5 breakdown ~le-6 • le-7 le-8 le-9 leakage le-10 -11 -10 volts -9 -8 Figure 2.1: Avalanche breakdown I-V characteristic NMOS PMOS ~ ~ ~///////////l/~n///~//1. ~/////////N/////r/////N/// a~dri ~ '/////I//NN//N///~////, ~~ Figure 2.2: Cross-section of twin-well CMOS process sink. The voltage at the cathode will be 12-10.5=1.5V for currents up to 100PA, producing a 105 dynamic range which is more than adequate for display applications. In a twin-well CMOS process, as shown in Figure 2.2, the p+/nwell junction is the best suited for integration. It is electrically isolated from other devices on chip. When the nwell is connected to a high voltage and the p+ region connected to a low voltage, avalanche breakdown occurs. No substrate currents are created by this structure, and the n-well voltage can be safely controlled by MOS devices. The p+/nwell junction breakdown voltage is designed to be much higher than the nominal power supply voltage, to ensure proper operation of CMOS circuits. This reduces the energy efficiency of light emitting junctions, which should be designed for avalanche breakdown at the smallest possible voltage. The p+/nwell junction is available in all standard CMOS processes, and low-voltage CHAPTER 2. BACKGROUND 28 devices can be used to drive them. This eliminates the need for more costly high-voltage processes. In addition, other circuit functions that require high-performance devices such as processors or memory can be integrated together with light emitters. In unmodified CMOS processes, avalanche breakdown occurs first around the perimeter of the junction area. This is due to a combination of surface states and the high electric fields at the edges of the junction area. For a microdisplay using front-emission from a silicon IC, lateral breakdown is desirable over vertical breakdown because it occurs closer to the surface and allows more photons to escape. Lightly doped guard rings can be used to modify the doping profile of avalanche diodes if bottom-surface breakdown is preferred, for example for back-emission from a thin substrate [44]. Avalanche diodes are more commonly used as in sensitive imaging devices for photon counting and operation at low light levels, and many articles have been published on their design in that context [42]. An important design consideration is to avoid covering light- emitting junctions with silicide. Most CMOS processes include a mask to selectively block deposition of silicide, and it should be utilized for light-emitting junction areas. Silicides are deposited over diffusion regions to reduce their sheet resistance. They are nearly opaque to light and reduce optical transmission by 80-90% [45]. 2.2 Device Measurements A preliminary study was performed to characterize the light-emitting properties and reverse- breakdown characteristics of p-n junctions manufactured in commercial CMOS processes. Limited information and data on the use of these junctions as light emitters is available, therefore we characterized devices manufactured in commercial 0.8um , 0.35um , and 0. 18pm CMOS processes. In all three processes, the p+/nwell junction showed avalanche breakdown behavior when a large reverse bias was applied. 2.2.1 0.8pum Technology A test device in the Hewlett Packard 0.8[tm (CMOS26G) process is measured. The process has n-wells, one poly layer, and three metal layers. Nominal operating voltage is 5V. The test device is the junction between the a source/drain diffusion of a PMOS transistor and its n-well. Junction area is 50 x 1.5um , and the device is covered with silicide. The electrical characteristics of this device in reverse bias are shown in Figure 2.3. Reverse leakage current rises gradually between 0 and -18V. At -18V, avalanche breakdown occurs and current increases by over six orders of magnitude over a very small voltage range until 2.2. DEVICE MEASUREMENTS Id vs Vd N76VAF -20 -15 -10 -5 0 Diodevoltage (V) Figure 2.3: Diode I-V characteristic,0.8upm process Figure 2.4: PMOS test device it is limited by series resistance. The pictures in Figure 2.4 were created with a CCD camera mounted on a microscope. On the left, the microscope light is on and the four-terminal test device is visible. The device is connected to four metal pads for use with a probe station. The n-well and source/drain pads were bonded to package pins for easier testing, and solder from the bonding process is visible on the two pads on the right side. On the right, the microscope light and room illumination were turned off and a long-exposure image shows light emission from the p-n junction. Current through the junction is 130PA, and light emission is concentrated at the sides and corners of the p+ diffusion area. Light emission was visible in a darkened room, in agreement with published reports of broadband emission from silicon junctions in avalanche breakdown. CHAPTER 2. BACKGROUND 30 Chipl1 - d2626Rverse 03111102achen 1.OE-02- - ----------- 1.0E-03 1.0E-04 i 1.0E-05 X 1.0E-07 .0E6oE . , 1.OE-08 1.OE-091.OE-10 -11 -10 -9 -7 -8 -6 Vd (volts) Figure 2.5: I-V curve for p+/nwell junction in 0.35p1mCMOS technology Chip #1 d2726 03/11/02 achen 0.010.0075 0.005 0.0025 o - 0 -0.0025 -1.5 -0.5 0 0.5 -0.005 -0.0075 -0.01 ..... Vd (volts) Figure 2.6: I-V curve for n+/psub junction in 0 . 35 p1mCMOS technology 2.2.2 0.35pm Technology The characteristics of the p+/nwell junction in the TSMC 0.35/um CMOS technology were measured. The process has n-wells, one poly layer, four metal layers, and silicide block. Nominal operating voltage is 3.3V. Avalanche breakdown of the p+/nwell junction occurs at -10.OV as shown in Figure 2.5. An n+/psub junction in this process was also measured, as shown in Figure 2.6. Reverse breakdown occurs due to tunnelling instead of avalanche breakdown, and the I-V characteristic is much less abrupt. Compared to avalanche breakdown, a much larger voltage swing is needed to produce the same change in current. This makes control with low-voltage devices difficult or impossible. The mechanism of zener tunnelling is not expected to emit photons, therefore this junction is not useful for light emission purposes. 2.2. DEVICE MEASUREMENTS Figure 2.7: Light emissionfrom six paralleltest devices 2.2.3 0.18pm Technology Devices in the TSMC 0.18prm CMOS technology were measured. This process has nwells, thin and thick oxide transistors, one poly layer, six metal layers, and silicide block. Nominal operating voltages are 1.8V for thin oxide devices, and 3.3V for thick oxide devices. The test structure consists of six 12x14[pm junctions connected in parallel, as shown in Figure 2.7. When this image was taken, ID = 700pLA and VD = -10.OV. Reverse breakdown current-voltage characteristics are shown in Figure 2.8. Emission occurs at discrete points mostly around the junction perimeter, and luminance varies between the junction areas due to random manufacturing variation. This variation is exacerbated by the parallel connection of pixels which allow unevenly located "hotspots" to carry most of the total current. To improve uniformity, pixels should be small in size and driven individually by current sources. This technique allows well-controlled transistor electrical characteristics to control light emission instead of poorly controlled junction characteristics. The emission spectrum for a p+/nwell junction on the 0.18p/m CMOS chip is shown in Figure 2.9. In forward bias, the junction emitted photons at its bandgap energy (1.1eV = 1100nm). In reverse bias, a broadband emission spanning the visible and near-infrared wavelengths was observed. This is consistent with published data. By comparing images of the display with a reference target, we estimated the quantum efficiency of silicon light emitters to be - 10- 7 photon/electron. This value are comparable to published results for light emission from silicon devices. The silicide layer was not blocked, so the efficiency of the p-n junction without silicide should be higher. 32 CHAPTER 2. BACKGROUND Chip3 -d3331reverseI-V 0824101 achen -100uA a -10.1V Chip3 -d3334 08124101 achen-100uA @-10.1v 1.OE-03 4 A . t.............................................................. ._ _' .. 1.0E-04 1.0E-05 1.0OE-06 I 1.OE-07 "n4 __ o! _Seris_| - 1.OE-08 r 1.0E-09 .u t ***146- 1.OE-10 I -- I 1.OE-11 -11 -10.5 -10 Vd (volts) i i 1.0E-12j -11 -9.5 -10.5 -10 -9.5 -9 Vd(volts) Figure 2.8: I-V curves for two p+/nwell junctions in 0.18pm CMOS technology Chip #3 d3334 forward20s -08.27.01-achen Chip #3 d3334 reverse20s -08.27.01 35 600 30.0 10 500 , _ -, r-4, - f:'" - 25 400 - - 20 -Series1 15 300 200 1010 0 100 5 800 850 900 950 1000 1050 04 1100 1150 1200 450 550 wavelength(nm) i3s . . . 650 750 850 wavelength (nm) Forward bias Reverse bias Figure 2.9: Spectra of light emission from junctions on CMOS die PMTVoutvs. d - Chip 3 logilog 10102102 achen,Johnkym 10000 1000 0 100 10 10 01 100 -Id(mA) Figure 2.10: Light output vs. current for junction in 0.18,um CMOS process 950 -Snes1| 2.3. IMAGE INTENSIFICATION 33 The relationship between junction current and luminance was measured in a darkened room using a photomultiplier tube. A linear dynamic range of over 100:1 was measured, as shown in Figure 2.10. This measurement was limited by the test apparatus, and the linear dynamic range of the junction is expected to be larger. The linear relationship between current and luminance suggests the use of linear current-mode driver circuits for silicon light emitting junctions. 2.2.4 Measurement Summary The reverse breakdown characteristics of junctions three commercial CMOS technologies were observed. Avalanche breakdown with light emission was observed from the p+/nwell junction in all three technologies, and breakdown voltages ranged between -18 and -10OV. A rough measurement of quantum efficiency agrees with published data, and the emission of a broadband spectrum covering visible and near-infrared also agrees with published data. The linear relationship between current and luminance suggests the use of current-mode driver circuits. 2.3 Image Intensification The image intensifier is a vacuum device that accepts a two-dimensional optical image and produces an amplified version of its input [46]. It is commonly used in night vision and scientific applications. In its simplest form it has two parts: photocathode and phosphor screen, as shown in Figure 2.11. In this example, a lens focuses an image onto the photocathode. The photocathode is a metallic material which emits electrons in response to light by the photoelectric effect. A two-dimensional flux of electrons is accelerated toward the phosphor screen by a large electric field. Electrons strike the phosphor screen, causing photons to be emitted in the same two-dimensional pattern. These typically have gains up to 100 photon/photon. Dark emission from the photocathode is typically very low, resulting in a large dynamic range. Power consumed is proportional to light output, an important trait for portable systems where energy is limited. The device is very efficient because light is produced by cathodoluminescence, using electrons to excite phosphor. A type P-22 phosphor produces 40 lumens/watt with electrons accelerated with 6kV [5, 47]. In addition, phosphor screens are capable of handling large amounts of power and producing high luminance levels as shown by their application to projection tubes. Adding one or more microchannel plates (MCP) increases the gain of the image in- CHAPTER 2. BACKGROUND 34 Objective lens Eyepiece Scene Eye Image Image Figure 2.11: Simple image intensifier application to the Screen Figure 2.12: Microchannel plate (Proxitronic) tensifier. An MCP is a plate of glass with many microscopic holes running through it. A large DC voltage is applied across the plate, creating an electric field through the channels. An electron striking one end of a channel causes secondary electrons to be released, as shown in Figure 2.12. An avalanche effect occurs, and gain of a single MCP can be as high as 5000 electron/electron. 104 The overall gain of an image intensifier with one MCP is 105 . With two MCPs, gain of 106 is achieved. Gain of intensifiers with varying numbers of MCPs is shown in Figure 2.13. While gain increases with more MCPs, spatial resolution decreases because the gaps between MCPs allow electrons to cross-over into adjacent channels. Resolution versus number of MCPs is shown in Figure 2.14. A DC bias current called the "strip current" flows through the MCP. Typical MCP resistances range from 2 * 106 to 1082Q. For best linearity, the strip current needs to be larger than the current of the electron flux being amplified. This additional current reduces the energy efficiency of the intensifier. Intensifier gain and dynamic range can be improved by using a semiconductor material as the photocathode instead of a metal. Quantum efficiency improves by a factor of four over a broad range of wavelengths, resulting in higher gain. The sensitivity of a galliumarsenide based photocathode is shown in Figure 2.15. This cathode has peak efficiency between 650nm and 850nm, and is well matched to the avalanche mode silicon light emitter with spectrum shown in Figure 2.9. Matching photocathode sensitivity to the light source 2.3. IMAGE INTENSIFICATION 35 IntensifierGain vs # of MCPs 1.UtI-+Ud 1.OE+07 = 1.OE+06 0 :1 1.OE+05 0 r- 1.OE+04 - 9 1.OE+03 1.OE+02 1.OE+01 0 1 2 3 MCPs Figure 2.13: Intensifiergain vs. numberof MCPs Resolutionvs # of MCPs E 20 E E i 15 5 10 o 5 0 0 1 2 3 MCPs Figure 2.14: Intensifier resolution vs. number of MCPs CHAPTER 2. BACKGROUND 36 103 102 H- -z -0UJ Z I U On LL i--LL Z LU 101 z 100 0T1 - RADIANT SENSITIVITY - - -' 10-1f 300 ANTIMFFFIINCY. I F . " I..' .. 'I----'-- ' I I 400 500 600 700 800 I 900 1000 WAVELENGTH (nm) Figure 2.15: GaAs Photocathode Sensitivity (Hamamatsu) also improves rejection of spurious input signals and reduces background noise. In the future, the image intensifier could be replaced by smaller or more efficient structures. MEMS micromachining might help to miniaturize the intensifier itself [48], and aid in integrating the intensifier with a silicon integrated circuit. The large glass vacuum envelope could be replaced with a smaller vacuum package. An up-converter might replace the intensifier if the efficiency of silicon light emitters were increased, or if efficient infrared emitters were integrated onto an IC. The up-converter converts photons at one wavelength to shorter wavelength, for example an infrared image can be converted to a visible one. A pixelless up-converter for mid-infrared imaging is described by Luo et al. [49]. It could eventually compete with image intensifiers, with the advantages of being smaller and requiring lower operating voltages. 2.4. CIRCUIT DESIGN FOR DISPLAYS 2.4 37 Circuit Design for Displays The driver circuits for an electronic display are typically digital to analog converters which convert stored digital data into into analog waveforms used to produce an image. Management of leakage currents and device variation are key issues in data converter design. Introductions to these topics are presented, followed by a survey of digital to analog converter topologies and techniques, with emphasis on circuits for display applications. The current copier is a circuit that uses a self-calibration technique to reduce sensitivity to device variation. Its basic concept is presented, along with potential advantages in the design of display driver circuits. 2.4.1 MOS Transistors Leakage Currents Circuit techniques to reduce leakage currents have been proposed, for example a 12b accurate analog storage cell [54]. Our design, as described in Chapter 4, uses circuit techniques to minimize the effects of overlap capacitance and leakage currents on the current copier circuit. In the analog context, the main effect of leakage currents is to reduce circuit precision. An important property of CMOS circuits is their capability to store charge on floating nodes. The sample-and-hold circuit shown in Figure 2.17 is a widely used example of a charge-based circuit. An important figure of merit is how long it can retain a value within a specified level of precision. Non-ideal effects in the sample and hold circuit include off- current through the switch, junction leakage through parasitic source/drain diffusions, and charge injection due to overlap capacitance (CGD) of the switch device. Gate and subthreshold leakage are serious problems for charge-based circuits such as the sample-and-hold. In charge-based circuits, the retention time is how long a circuit can preserve a stored value within a specified level of precision. Long retention times allow the circuits to function longer between calibration cycles, and reduce the amount of resources spent on periodic calibration. A transistor is often used as a MOS capacitor because gate oxide has the highest capacitance per area (fF/,um2 ) of structures available in common CMOS processes. Charge leakage through the gate limits the time period that a sampled value can be retained, and changing device area does not remedy the problem because both capacitance and leakage current are proportional to area. Poly-poly or metal-metal capacitors are available in some processes, although their capacitance per unit area is much lower than the MOS capacitor. 38 CHAPTER2. BACKGROUND Leakagetest NIIOS Vs--Vb=VdO - Die 0 -n 41,UU-I Z 8/02/0 achen . . _...._ .... I 1.OOE-13 Z011", i 1.00E-14 i i i i i Efa1 1,00E-15 i i 41 1 OOE-16 0 0.5 1 1.5 2 Vg (volts) Figure 2.16: Gate current for an NMOS device Gate leakage of a large 1.8 volt NMOS device was measured with a semiconductor parameter analyzer at room temperature as shown in Figure 2.16. For this measurement the source, drain, and bulk are at zero volts. The resulting data are consistent with published results [50, 51], and the primary mechanism for gate leakage is direct tunnelling through the thin (32A) gate oxide. To assess the impact of gate leakage, consider a sample-and-hold implemented in this technology with a voltage tolerance of lmV and a stored voltage around 1.OV. I area Current density at 1.OV is lOfA/,m 2 C AV area (2.1) (2.1) and capacitance per unit area is 8fF/um2 . The retention time is 800us. Display applications require retention times that are larger by orders of magnitude. For example, a display operating at 100 frames per second with one refresh cycle per frame requires a minimum retention time of 1/100 second, or 10ms. In a 0.18tim technology, one solution is to use thick-oxide transistors (70A vs. 32A) at circuit nodes where charge is stored. Thick-oxide transistors are available in most commercial CMOS processes. These devices have thicker gate dielectrics resulting in orders of magnitude less gate leakage. They also have larger minimum feature sizes and worse high-frequency performance than thin oxide devices. Capacitance per unit area is lower than for thin oxide devices, but still higher than other capacitor design options. As CMOS processes scale to smaller dimensions and power supply voltages are reduced, there is pressure to reduce the threshold voltage. Reducing the threshold voltage increases on-current due to a larger (VGS - VT) factor. However it also increases subthreshold conduction by a factor of ten for every 90-100mv decrease in VT. This can be 2.4. CIRCUITDESIGN FOR DISPLAYS 39 I Figure 2.17: Sample and Hold Circuit models. Left: ideal, Right: realistic seen by setting VGS to zero in the equation for subthreshold conduction: ID,OFF= Iseq(- V T)/nkT (2.2) In digital CMOS circuits, leakage currents cause static current to flow from from power to ground. It increases power dissipation and causes reduced noise margins due to signal degradation. In designs with millions of transistors per chip, leakage currents can exceed the currents used in active operation. Negative gate drive (V < 0) and the "stacking effect" have been used to reduce subthreshold conduction currents [52, 53]. Device Variation The design of high-performance data converters depends on an understanding of device variation and how to manage it. Variation is caused by random fluctuations which occur during the manufacturing process, and affects both material properties (doping levels, threshold voltage) and geometries (transistor width and length). The most commonly used variation model for MOSFET threshold voltage and currents is of the form aID k [55]. Other models have also been proposed, i.e. [56]. Maintaining consistent image qualities across a display is a challenging problem, and becomes even more difficult as integrated circuit feature sizes decrease. Traditional analog designs use layout techniques such as symmetry and dummy devices to improve matching. In a microdisplay, devices must be spread over a wide area and such techniques are not practical. To measure variation across large length scales, we designed an NMOS current mirror with 22 legs spanning 2.0 millimeters in the TSMC 0.18pm process. This structure represents a realistic design for a microdisplay where drivers are spaced across a die. All devices were 2*2ipm in size. In a microdisplay, the currents through individual driver circuits are small because there are many operating in parallel. The input current was set CHAPTER 2. BACKGROUND 40 Die 0. ceumrrrt rlrrr tLuA VdmOi, M 1.2DE 1.10- . 1~SH7 1 a 5 7 pIillen 9 11 Figure 2.18: Current mirror measurements at 1LA, and the drain voltage of mirror devices was 0.9V. Threshold voltage for NMOS devices is 380mV from simulation models, and the VGS corresponding to 1,uA is 495mV. The variation between output currents is aID = 2.5%. When there are 1,000 drivers on a chip, circuits should be designed at the 4a or 5a certainty level. This represents 3.5b precision, far short of current application demands. Modem commercial display systems have 8b resolution, and 10-12b displays are being developed. To achieve reasonable resolution, circuit techniques to improve matching between display drivers will be necessary. 2.4.2 DAC Fundamentals Digital to analog converters (DACs) are used in display systems to convert digital data into analog waveforms that control light emitters or light modulators. This section is survey of DAC circuit design techniques with emphasis on converters useful for displays. An ideal unipolar voltage-mode DAC has an output range from zero volts to (2 N - 1) * VLSB volts. It accepts a digital data word d(N: 1) and performs the function: N-1 VOUT = VLSB * i, d(i) * 2 (2.3) i=O The output voltage is discrete, and quantization noise is: VQ,rms= VLSB/xV natively, this can be expressed as the signal-to-noise . Alter- ratio: SNR = 6.02N + 1.76 dB, where N is the number of bits. Johns and Martin [57] provide a discussion of non-ideal behavior in DACs. DACs can be divided into two groups: Nyquist rate DACs that change their outputs once per cycle, and oversampling DACs that change their outputs multiple times per cy- 2.4. CIRCUIT DESIGNFOR DISPLAYS 41 cle. Nyquist DACs can be implemented using voltage-mode or current-mode techniques. Voltage-mode DACs produce an analog voltage using techniques such as a resistor ladder or switched capacitor circuits. The output voltage typically requires buffering with an operational amplifier to reduce output impedance. As an example, Bult and Geelen [58] describe a circuit topology based on the R-2R ladder. Current-mode DACs are attractive in CMOS technology because MOS transistors are voltage-controlled current sources (VCCS) with medium transconductances, allowing precise control of current. A current-mode DAC can be simpler to implement than a voltagemode one because currents can be summed by connecting current sources in parallel. A straightforward example is DAC made by switching 1024 identical current sources, achieving 10b precision at 40MHz in 0.8pum CMOS [59]. Note that a voltage output can be produced by attaching a transimpedance amplifier to the output of a current-mode DAC. Segmented DAC architectures use different techniques to generate portions of the output current, for example [60] describes a DAC with a unary decoded architecture for its MSBs and a binary architecture for its LSBs. The MSBs are optimized for high precision, while the LSBs use a structure that minimizes circuit area. Oversampling converters are attractive for moderate speed applications where digital circuits run much faster than the sampling frequency. For more information, Norwsowthy, Schrier, and Temes have a book on delta-sigma converters [61]. Display drivers typically require large numbers of converters that operate in parallel. Low-frequency operation, low power dissipation, and small circuit area are important, therefore Nyquist rate converters are preferable. Dynamic element matching [66, 67] converts errors due to component mismatch to uniformly distributed white noise. For example in a fully segmented DAC, if all cells have exactly the same duty cycle then the mismatch is averaged out and much greater dynamic precision achieved. Two more examples are swapping current sources at half the time period to build a 14b accurate divide-by-two network [68], and a 14b DAC using a "random walk" cycling scheme [69]. This technique can be used in conjunction with calibration techniques to further improve the performance of data converters. The cost is the complexity of choosing and switching arbitrary elements instead of using fixed patterns. 2.4.3 Calibration Techniques In Chapter 4, a calibration technique based on the current copier circuit is applied to display driver circuits which are current-mode digital to analog converters. Calibration techniques optimized for large numbers of data converters on a single chip are applicable to a variety CHAPTER 2. BACKGROUND 42 of applications. Display drivers are one such application, where a single chip incorporates hundreds of DACs. Other applications currently under development are MEMS actuators, neural network computation systems, and bioelectrical stimulators. In these types of chips, the cost or "overhead" of a calibration technique is divided by the number of converters, and the per-converter cost of adding calibration is reduced. Digital algorithms have been applied to data converters to improve performance, for example calibration and storage of digital correction coefficients in memory [62, 63]. Pipeline converters use redundancy to allow digital calibration and error correction [64]. Digital calibration techniques have been applied to large arrays of moderate resolution DACs for neural type computation cells [65]. The limitation of digital calibration is the cost of additional memory and computation. In a DSP system that already includes a processor and large memory this is not an issue. In applications with resource constraints such as embedded systems or ICs with large numbers of converters on-chip, the digital overhead can be prohibitive. Digital calibration of a data converter may require one or more lookup tables, and the amount of memory needed becomes large if there are many converters on a single chip. Analog calibration techniques have the advantages of full-speed operation, with no digital computation or memory overhead. In applications that require the highest operating frequencies, or where large numbers of converters are included on a single chip, analog calibration is a practical way to improve precision. The current copier uses a self-calibration technique to create a precise replica of a reference current. Its key characteristic is immunity to process variation, allowing it to make a replica current with greater precision than a conventional current mirror occupying the same area. An overview of its history and applications is given here, and it is described in detail in Chapter 4. The current copier circuit was first published in 1989 by a number of groups. Wegmann and Vittoz presented techniques to produce a continuous output current and to produce integer current ratios [70]. Wouter et al. and Groeneveld et al. described a 16b DAC with self-calibration technique [71, 72]. Nairn and Salama proposed an algorithmic ADC based on current copiers [73]. Other DACs using current copiers include a 5b 128x oversampled 44kHz DAC for audio applications made by combining a 4b PMOS and a 4b NMOS converter [74]; a 16b segmented DAC using 32 current copier cells to produce 5 MSB's, and 1 lb divider [75]; and a 14b segmented DAC using with 5b thermometer MSB, 5b thermometer upper LSB, and 4b binary lower LSB [76]. Current copiers can be used to implement switched-current circuits which are analogous to switched-capacitor circuits. Fiez et al. [77] describe a variety of current-mode circuit techniques such as track-and-holds, V-I/I-V converters, and ways to cancel charge 2.4. CIRCUITDESIGN FOR DISPLAYS 43 injection. A good collection of information on switched-current circuits is compiled by Toumazou [78]. Noise analysis of current copiers is complicated by time-dependent sampling behavior. Daubert provides a detailed analysis in [79]. Innovative circuit techniques have been applied to the current copier circuit, for example a regulated-cascode current copier [80]. This boosts output resistance, at the cost of increased power dissipation and complexity. Related calibration techniques for currentmode circuits have been proposed, including a 14b DAC using MOS devices in parallel to create "calibrated" devices [81]. 44 CHAPTER 2. BACKGROUND Chapter 3 Micro-projector Design 3.1 Design Overview A micro-projector utilizing silicon light emission and image intensification is described in this chapter. The goal of this display design is to produce an image with adequate brightness for micro-projection applications while being highly energy efficient to maximize battery life of a portable system. The performance of a proof-of-concept system is calculated, and confirmed on the lab bench. A schematic of the ideal system is shown in Figure 3.1. An integrated circuit produces a faint image which is proximity coupled to the photocathode of the image intensifier. The image intensifier efficiently amplifies the image to useful brightness levels. The output of the image intensifier is a high luminance image that can be viewed directly, or projected with a lens onto a viewing surface. light Figure 3.1: CMOS IC and image intensifier CHAPTER 3. MICRO-PROJECTOR DESIGN 46 high intensity light source A to screen writing light CRT Modulator beamsplitter V lens Figure 3.2: Two-stage display architecturefor projection application (JVC) 3.1.1 Background: Two-stage displays The operation of a display can be divided into two parts. Addressing is the creation of timevarying electrical signals and routing them into an array of display elements. Emission or modulation of light occurs in response to the electrical signals at each display element. Dividing the tasks of addressing and light modulation into two stages allows allows a display to combine the best characteristics of multiple technologies. For example, high speed addressing and high precision driver circuits can operate at low signal levels. Meanwhile the SLM consists of a two-dimensional array of elements operating in parallel at moderate speeds to modulate high optical power. One such system uses a cathode-ray tube and a photoaddressed liquid crystal SLM [82]. First, electrical signals drive a CRT display working at relatively small signal levels. The output of the CRT is a two-dimensional image. A photoconductor receives this image and converts it to a two-dimensional pattern of voltages which control a liquid-crystal light valve. The liquid-crystal light valve modulates light from a high intensity lamp for projection. This architecture, shown in Figure 3.2 was used in the first-generation digital cinema projectors [83, 84]. To produce color images three separate projectors are used to generate the primary colors, and their outputs superimposed. A similar architecture has been used to produce an infrared display for military apA visible light display controls a photoaddressed liquid crystal panel which modulates infrared radiation [85]. A liquid crystal SLM can be used to control a laser [86]. An SLM has been used to produce [87]. It uses a conventional microdisplay to generate a plications. write-light image, and an optically addressed SLM (liquid crystal) to produce the final image. The above examples use liquid crystal SLM's, but it should be noted that other SLM technologies exist, for example one that uses a microchannel plate and dielectric mirror [88]. 3.2. MICRO-PROJECTOREFFICACY 3.2 47 Micro-projector Efficacy In this section the efficacy of the two-stage micro-projector is calculated. Efficacy is defined as the lumens available on the projection screen per watt of input power, and has units of lumens per watt. We will assume that all conversions in the system are linear, and that no components are saturated. The best reported external quantum efficiency of light emitters in a standard CMOS process is 5 * 10 - 7 photons/electron [35]. Our measurements also yielded 2 * 10 - 7 photons/electron for a 0.18 pm CMOS process without silicide block, which is consistent with the published result. This figure is the external quantum efficiency for photons emitted from the front face of the IC. The use of microlenses or light-reflecting metal structures could improve quantum efficiency. External Q.E. = 5 * 10 - 7 photon/electron Photons travel between the silicon integrated circuit and the photocathode of the image intensifier. We will assume the ideal case where the two components are placed in contact with each other. Then, the ratio of emitted photons to photons striking the photocathode is unity. Transmission from IC to photocathode = 100% (ideal) The image intensifier used in the proof-of-concept system is a Hamamatsu V7090U-61N130. It is a Generation III intensifier, with high efficiency gallium arsenide photocathode, one microchannel plate, and P-43 phosphor screen. The photocathode quantum efficiency is 0.25 for 600-850nm photons [89]. This range of wavelengths includes the majority of the silicon emission spectrum. Photocathode Q.E. = 25% The maximum voltage across the microchannel plate (MCP) is 900 volts [89]. At this voltage, MCP gain is 1500 electron/electron. MCP gain = 1500 electron/electron The image intensifier output screen converts electrical energy to optical energy at the output window. It has a sharp emission peak at 540nm, and its quantum efficiency is 95 photons/electron for electrons at 6,000 eV [89, 46]. Phosphor Q.E. = 95 photons/electron 48 CHAPTER 3. MICRO-PROJECTOR DESIGN Multiplying these efficiencies together, the overall intensifier gain is 3 * 104 phot/phot. To calculate luminous efficacy, diode breakdown voltage is - 10OV. The display driver circuit requires some headroom, so the total voltage drop through the silicon light emitting pixels and driver circuits is about 11V. The wavelength of emitted light is 540nm, so the energy per photon can be calculated: A= 5.4 * 10- 7 m v= c A = 5.56 * 1014hertz E = h*v E = 6.626 * 10- 3 4 * 5.56 * 1014= 3.68* 10- 19joules/photon The eye is most sensitive to radiation at 550nm, where one watt of energy equals 680 lumens. The standard relative luminosity factor for 540nm is 0.954 [90]. Luminosity = 680 * 0.954 = 649 lumens/watt The strip current of the MCP must be be considered. For low signal levels, the minimum required strip current is simply the MCP voltage divided by the MCP resistance. Typical values are VMCP= 900V and R = 107Q. For high current applications, the signal current must be less than 7% of total strip current to maintain linear operation [91]. Suppose the total average current through the pixel array is 90mA. The silicon IC dissipates 90mA * 1V = 1W. The image intensifier dissipates negligible energy at the photocathode, 220mW in the MCP (signal=7% of total current), and 100mW at the output screen. Output luminance is 2.4 lumens with total power dissipation of 1.3 watts, yielding 1.8 lumens/watt. Assume the output screen is a lambertian surface, and the projector lens aperture is f/1.4 (NA = 0.36, 12.7% transmission). Photographic objectives with aperture of f/1.4 are common, and projection lenses with apertures from f/1.0 to f/3 are available. Output luminance = 1.8 lumens Transmission of lens = NA 2 = 12.7% Let the final image size be a half-page (5.5x8in, or 14x20cm), and assume the projection surface has unity gain. Area = .028m2 The illuminance from the micro-projector is: 1.81umens+ .028m2 = lllux 3.2. MICRO-PROJECTOR EFFICACY Total pixel array current Electron flux Photon flux from Si Photocathode electron flux MCP1 electron output MCP2 electron output Phosphor screen output Luminance output Efficacy 49 600 ,uA 3.75 * 1015 e/sec 1.9 * 10 9 phot/sec 4.7 * 108 4.7 * 1011 4.7 * 1014 4.5 * 1016 10.6 7.1 e/sec e/sec e/sec phot/sec lumens lumens/watt Table 3.1: Intensifier Performance with two MCPs With one MCP, illuminance is below the level necessary for a micro-projector application (see Table 1.2). The bottleneck is image intensifier gain. Efficacy improves significantly if another MCP is added to the image intensifier. The combination of two MCPs in series boosts image intensifier gain to 106. This decreases power dissipated by the silicon IC and at the same time increases output luminance. With two MCPs, performance is summarized in Table 3.1. Power dissipated by the silicon IC is reduced to only 7mW. The MCPs dissipate 1.1W, and the output screen dissipates .45W. Total power dissipation is 1.5W, and efficacy is 7.1 lumens/watt. This efficacy is high compared to other display technologies. For comparison, a liquid crystal SLM with metal halide light source produces only 0.5-3 lumens/watt due to the low transmission of the SLM [92]. This figure is for large-size projectors using metal halide lamps that produce 100 lumens/watt. These lamps cannot be used in compact projectors, and if they are replaced with LEDs efficacy will be reduced by at least a factor of three, to 0.1-1 lumen/watt. A recently published organic-LED-on-silicon display [93] produces approximately 2 lumens/watt. With two MCPs, the MCP strip current and output screen dominate power dissipation. Assuming the same f/1.4 lens as before, 12.7% of 10.6 lumens are spread over an area of .028m 2 , yielding 49 lux which is adequate for a projector application. A micro-projector with high image intensifier gain can create half-page sized images with worst-case 1.5W power dissipation. This is for the entire image at maximum intensity. If the display is emissive, then realistic estimates of relative brightness are 13% for a screen of text, 68% for a personal computer desktop, and 40% for photographic or video images. realistic estimate is 50% of full intensity, resulting in 0.75W power dissipation. A more Considering that lithium ion batteries in personal portable systems typically have capacities of 2-7 watt-hours [94], a portable system with emissive micro-projector and other functions could have a battery life of 2-7 hours. 50 CHAPTER 3. MICRO-PROJECTOR DESIGN Operating voltage VDD Physical gate length Gate oxide thickness (physical) 3.3 and 1.8 0.35 and 0.16 70 and 32 Silicide (self-aligned) Metal layers volts ,rm A CoSi2 6 Al Table 3.2: TSMC 0.18pum CMOS technology characteristics The dynamic range of the image intensifier is calculated below. Assume all components are operating in a linear manner. The maximum photon flux into the photocathode is 2.8 * 1011 phot/sec. We approximate all photons to be the peak wavelength of the silicon emitters, 700nm. The photocathode diameter is 18mm, so its area is 2.5 * 10- 4 m 2 . The radiant flux is 3.1 * 10- 8 W/cm 2 . The effective background illuminance (EBL) of the V7090U-61-N130 image intensifier is specified as 1.0 * 10- 13 W/cm 2 . The ratio of these two levels is the dynamic range: 3 * 105, which is significantly larger than the 103 ratio required for 10b resolution. In reality, the image intensifier gain rolls off or "saturates" at high input luminance levels. The linear dynamic range is limited at the low end by the EBL, and at the high end by saturation effects. From Hamamatsu datasheets, the linear dynamic range with one MCP is 105. When two or three MCPs are included, the increased gain causes a proportional increase in EBL while saturation occurs at the same level, thus linear dynamic range is decreased. Linear dynamic range is about 200 and 30, respectively. The V7090 series image intensifiers produce low output luminance because they are intended for night vision and scientific applications. An image intensifier optimized for micro-projection could be designed to accomodate higher current levels and provide a larger dynamic range. 3.3 Test Chip Implementation Process Technology A simple microdisplay backplane was designed to test the idea of a display using silicon light emission and image intensification. The TSMC 0. 18,m CMOS technology was used. Some key process features are listed in Table 3.2. This process was chosen to emphasize the ability to integrate a microdisplay in a modern high-performance CMOS process. The display's pixels include lb static memory, therefore area is shared between circuits and light emitters. A small feature size reduces circuit area resulting in higher fill factor. 3.3. TEST CHIPIMPLEMENTATION 3.3.1 51 IC overview The integrated circuit includes light-emitting pixel arrays and other device and circuit experiments. The arrays are described first, followed by the other experiments. The integrated circuit includes two display arrays. Each array measures 16x32 pixels, with a pixel pitch of 25m . Each pixel contains a light emitter, a current source, and a lb SRAM cell. Integrating static memory into each pixel eliminates the need for refreshing. Each array has sixteen digital inputs driving the bitlines. A full decoder permits random row access. Grayscaling can be achieved using pulse-width modulation. The fill factor of the IC array is 3%, and photon and electron scattering increase the apparent fill factor. Simulation indicates that the write time for an optimized 1000x1000 pixel array is 30ns, adequate for real-time video display. 3.3.2 Pixel A pixel element was designed to match the resolution of a commercially available image intensifier. Its size is 25*25m . A schematic diagram of the pixel circuit is shown in Fig- ure 3.3. At its core, cross-coupled inverters form a lb SRAM cell. A complementary passgate is controlled by the WRITEEN signal, which is driven by the rowline. The NMOS transistor in the bottom inverter combined with the VBIAS transistor control the current through the silicon light emitter. VBIAS is a single voltage reference distributed across the chip. For precise control of pixel luminance, current-mode control of diodes is preferable to voltage-mode control because of their sharp avalanche breakdown characteristic. The high voltage supply, Vhi, is 11.5V. Reverse breakdown of the p+/nwell junction occurs at -10V. Because the avalanche breakdown characteristic is extremely abrupt, the MOS transistors see only 11.0-10.0 = 1.0 volt, and this value changes very little regardless of whether the pixel is on or off. For added robustness, a protection diode limits the maximum voltage seen by MOS devices. The light-emitting diode is a p+/nwell junction measuring 10*2um . Luminance is proportional to current, and to the first order independent of junction area. The properties of junctions in TSMC 0.18[m technology were described in section 2.2.3, and Figures 2.8, 2.9, and 2.10. There is additional space available in the pixel array, and the fill factor could be increased by increasing junction area. Micro-lenses can also be added to spread light and improve fill factor. The array is fully static when used in black-and-white (lb) mode. It can also display grayscale images when driven with pulse-width modulation (PWM) input signals. The digital portion of the pixel was designed for a supply voltage VDD of 1.80V. A high CHAPTER 3. MICRO-PROJECTOR DESIGN 52 -0 0 :3 Figure 3.3: Circuit schematic of a single pixel voltage (Vhi = 11V) is used to drive light-emitting diodes in avalanche breakdown. Current vs. Voltage Drive Light-emitting diodes produce light in proportion to diode current. Linear current-mode drivers can provide good control of light output. However, limiting the current leads to long switching transients on the capacitive column lines. Rearranging the fundamental capacitor equation: AT = CCOLUMNAV (3.1) IDRIVE Voltage drive can switch column lines faster because current is not limited, however precise control of light emitters is difficult. The proof-of-concept system uses a hybrid approach. Hybrid approaches have been described in the literature [95], and can provide both fast addressing and good linearity. The per-pixel memory is written by a voltage, so bitline transitions and writes to memory are fast. Within a pixel, the silicon light emitter is controlled by a MOSFET transistor acting as a current source. Switching transitions are fast and provide good timing precision. The luminance of the light emitter is precisely controlled at a fixed level by the current source MOSFET, and can be modulated using pulse width modulation. 3.3.3 Pixel Arrays Two pixel arrays were implemented on the test chip. Each consisted of a 16x32 pixel matrix, wordline decoder, and input buffer circuits as shown in Figure 3.4. The only difference 3.3. TEST CHIPIMPLEMENTATION 53 Pixel Array o 0 16 x 32 U0 a0 111 1111 addr<4:0> I l l l l l l l data<15:0> Figure 3.4: Block diagramof pixel array was resizing of the bias transistor in each pixel. One array was designed for a maximum current of 100uAlpixel, the other was designed for 40[A/pixel. Because of the lb SRAM per pixel architecture, a full decoder was used to control rowlines. The decoder generates a 1-of-32 output when ENABLE is true, or forces all outputs to zero when ENABLE is false. It is built from static CMOS standard cells. Combined with the memory-per-pixel arrray, random access to rowlines allows writing to occur in arbitrary order, which can reduce energy used in addressing. 3.3.4 Top-level IC Design and Packaging The die measures 2.7x2.7mm (7mm 2 ), and was designed for wire bonding into an open cavity DIP40 package. The DIP40 package is used for ease of testing; simple measurements are made with the IC on a solderless breadboard, and a test system is built on a printed circuit board. A chip photomicrograph is shown in Figure 3.5. Bonding pads are placed along all four sides of the die. Large metal busses around the perimeter of the chip distribute VDDand ground. Electrostatic discharge protection circuits are included on all CMOS inputs. CHAPTER 3. MICRO-PROJECTOR DESIGN Figure 3.5: ICphotomicrograph 3.3.5 System Design A printed circuit board to drive the display arrays and to demonstrate its capabilities is shown in Figure 3.6. It includes regulated power supplies, the test chip, and a microcontroller. The Microchip PIC16F874 microcontroller is used for its ease of programming, ability to function with a 1.8V power supply, and large number of I/0 pins. The microcontroller operates at a frequency of 1MHz, and is programmed in assembly and PICBasic. The pseudo-code fragment below is representative of the code used to drive the proof-of- Figure 3.6: Proof-of-concept system board 3.3. TEST CHIPIMPLEMENTATION PIC16F874 PORTA PORTB PORTC PORTD 7 6 d15 spare d7 d14 EN2 d6 5 LED1 d13 EN1 d5 55 4 LEDO d12 a4 d4 3 spare dl 1 a3 d3 2 1 spare spare d10O d9 a2 al d2 dl 0 spare d8 aO dO Table 3.3: Microcontroller interface definition concept system. It blanks the display by writing zeroes to all pixel locations. FOR i = 0 to ADDRESS 31 = i DATA_HIGH = xOO DATA_LOW = xOO ENABLE = 1 ENABLE = 0 NEXT i From the point of view of the microcontroller, the display behaves like an SRAM. The interface consists of a 5b address, 16b data, and an enable signal. The 16F874 has three 8b I/O ports and one 6b I/O port. The signal mapping for the microprocesor is shown in Table 3.3. 3.3.6 Image Intensifier and Optics The intensifier used in this system is the Hamamatsu V7090U-61-N130. The photocathode is of a GaAs(Cs) material, sensitive from 400 to 900nm. It has one microchannel plate (MCP) to provide high luminous gain, up to 3.5 * 104 phot/phot. The output window phosphor is type P-43 which emits light at 540nm, close to the eye's peak response wavelength [89]. The unit is 23mm thick and 45mm in diameter. Since this unit is optimized for scientific and night vision applications, output luminance is low and the unit operates at low power levels. The intensifier requires DC voltages at 800V and 6kV. A matching power supply, Hamamatsu C6706-30, is used. This power supply includes automatic power limiting and shutoff circuitry. In the proof-of-concept system, packaging and mechanical constraints prevent the photocathode from being in contact with the silicon die. A microscope objective lens was used to couple light from the pixel arrays to the intensifier's photocathode, A 20x/0.4NA lens CHAPTER 3. MICRO-PROJECTORDESIGN Figure 3.7: Proof-of-concept system with intensifier was mounted at one end of a hollow tube, and the intensifier attached to the other end. This allowed us to evaluate the proof-of-concept system, although a real system should have intensifier and silicon IC in contact ("proximity focusing") to minimize system volume. Assuming image source is a lambertian surface, the lens captures 16% of the energy radiated by the source and focuses it into an image. In addition, reflections at air-glass interfaces without anti-reflection coating reduce transmission by about 4% per interface. The addition of micro-lenses on the IC could increase coupling by allowing more photons to escape the front surface of the IC. A better solution is the ideal structure where the photocathode is deposited directly on top of the IC dielectric layers. This would eliminate losses due to total internal reflection, increasing the effective quantum efficiency by 80% to 9 * 10- 7 phot/elec. It would also reduce the number of interfaces in the optical path, and associated reflections. A picture of the final test setup is shown in Figure 3.7. The image intensifier is on top of an optical tube attached to a 20x 0.4 N.A. microscope objective lens. The printed circuit board is visible under the optical tube. Black cardboard (visible in the photo) was used to reduce stray light and reflections in the test system. The letters "MIT" are visible in the intensifier's output window. 3.3.7 Proof-of-Concept System Performance This section calculates the performance of the proof-of-concept system built on the lab bench, and compares it to measured results. To compare calculations with measured efficiency, the display was configured with all pixels on.The current through the IC high voltage supply was measured at 1.1mA, or 3.4. RESULTS 57 6.9 * 1015electron/sec. This current level is much smaller than full-scale to ensure linear operation of the image intensifier. The quantum efficiency is the same as before, 5 * 10 - 7 photons/electron, however, in the proof-of-concept system the silicon junctions were covered with a salicide layer. This significantly reduces optical transmission to about 20%, so the photon flux from the surface of the IC is 6.9 * 108 phot/sec. The silicon surface acts as a lambertian source. The lens is a microscope objective with 20x magnification and a numerical aperture (NA) of 0.4, and the system is in air. A lens with this numerical aperture captures 16% of photons emitted from the IC. Assuming reflections and other losses are small, 1.1 * 108 phot/sec strike the photocathode of the image intensifier. The gain of the image intensifier is 3.5 * 104 for Vcathode = -800, Vmcp = 900, and Va = 6000. The flux leaving the output window is 3.9 * 1012 phot/sec., and the P-43 phosphor screen has a sharp emission peak at a wavelength of 540nm. At this wavelength, each photon carries 3.7e - 19 joule, so the radiant flux is 1.4 * 10-6 watt. The luminous output is 1.4 * 10-6 watt * 649 lumens/watt = 9.2 * 10- 4 lumens. The pixel array measures 400*800pLm , and the lens has 20x magnification, so the photon flux is spread over an area 400 larger than the source. The image area is 1.28 * 10- 4 m 3.4 3.4.1 2 . The expected luminance of the display is 0.67 footlamberts. Results Single Pixel The pixel with lb SRAM memory functioned as designed. DC measurements of pixel I-V characteristics are presented below. Figure 3.8 shows current through the light-emitting junction as a function of the high voltage supply VHI. When the pixel is storing a low value (off-state), current is negligible for VHI less than 12.5V. Above this voltage, the protection diode turns on, and a large current flows. For the on-state, diode current is constant at about 200[A for VHI between 11.5 and 12V. In this region there is adequate voltage to bias the junction in avalanche breakdown, and current through the junction is regulated by the MOS transistors acting as a current sink. Below 11V,the current source has inadequate headroom and current is reduced. Simulated results are also included on this graph. Diode models for this process were probably intended for capacitance estimates, and do not accurately predict reverse breakdown I-V characteristics. For light emission characteristics of the p+/nwell junctions in this process, refer to Section 2.2.3. CHAPTER 3. MICRO-PROJECTOR DESIGN Pixel current, Vblas=Vdd=1.80v,Chip #3 3 OE-04 2.OE-04 ----6- OE-04 nnr.M •r . (pixel) ON I(pixel) OFF Sim ~11 I M _ _ 10LT~ 10 Vhi (volts) Figure 3.8: Pixel I-V characteristic,VHI sweep Figure 3.9: Test image of IlC under microscope 3.4.2 Arrays The lower-current array was fully functional. Test images were produced for lb and grayscale modes of operation. This photo was taken in a darkened room with a CCD camera mounted on a microscope. Exposure time was several seconds using a 20x 0.45 N.A. microscope objective lens. Figure 3.9 shows a static lb test pattern. The small white dots in the picture are caused by noise in the CCD camera. Grayscale images can be created using pulse-width modulation, as shown in Figure 3.10. This is a photo of the image intensifier output window, demonstrating operation of the twostage display architecture. The bottom two rows of pixels are at maximum intensity to provide a constant luminance reference. The rest of the pixels are switched to produce a 5b 3.4. RESULTS Figure 3.10: 32-level grayscale gradient. Bottom two rows are at full intensity linear gradient (32 time slots per frame, 60 frames/sec). Bit depth is limited in this demonstration by the speed of the microcontroller. Figure 3.11 shows another lb test pattern, observed on the image intensifier output window. 3.4.3 Power Measurements The proof-of-concept system was assembled in our laboratory. For a static test image with all pixels at maximum brightness, total IC current from the 11V supply is 1.ImA, so the IC dissipates 12mW. Current from the low voltage (1.8V) supply is negligible. The image intensifier is set for maximum gain with Vk-mcp=800, Vmcp=900, Va=6000. Intensifier power is dominated by MCP strip current which is approximately 9002V/107Q = 81mW. Total display power is 12+81=93mW. Because the proof-of-concept system operates at low signal levels, power is dominated by the constant MCP strip current. Output luminance was 1.3 footlambers, measured with a Photo Research PR-880 photometer. The difference between this and the predicted value of 0.67 footlamberts in Section 3.3.7 may be caused by a number of sources. Image intensifier gain varies exponentially with applied voltage, so a small voltage error may cause a large difference in optical gain. The quantum efficiency may be higher because of different device of different junction characteristics, and transmission out of the silicon may be higher because the junctions in the 0.18/pm process are shallower than those reported by Snyman [35]. The image intensifier's high voltage power supply limits its output current to prevent damage to the intensifier. The current limit is small, on the order of microamperes. Leakage currents and surface conduction currents were enough to trip the automatic shutoff circuitry, and this prevented us from measuring the intensifier current directly. The im- CHAPTER 3. MICRO-PROJECTORDESIGN Figure 3.11: Output window of intensifier(20mm) with sample image age intensifier and high-voltage power supply were tested in isolation, and the input power to the power supply was measured. Ideally, efficiency is constant and total power is proportional to power delivered to the intensifier. Lab measurements show the power supply dissipates 200mW while standing idle, and 360mW when showing the test pattern shown in Figure 3.7. Design of an energy-efficient high voltage power supply for the image intensifier will have a significant impact on overall energy efficiency. 3.4.4 Discussion We have demonstrated two-stage image generation using silicon light emitters and an image intensifier. This architecture can produce high-resolution output with high energy efficiency and adequate luminance for a micro-projector. A proof-of-concept system is functional, and performance agrees with design calculations. Two ways to increase system efficiency are increasing the gain of the image intensifier, and improving the efficiency of silicon light emitters. Increasing image intensifier gain allows lower power operation of silicon light emitters, and higher output luminance. As gain increases, less light is required from the silicon light emitters. Power dissipation of the silicon IC decreases, and energy efficiency is dominated by the performance of the image intensifier. The image intensifier uses cathodoluminescence to produce light, and is both energy-efficient and capable of producing high luminances comparable to projection CRT's [96]. Image intensifiers with multiple MCP's can have gains of up to 107 , however 3.4. RESULTS 61 resolution decreases as more MCP's are added [89]. Improving the efficiency of light emission from silicon is an area of active research interest [39, 38, 36], and silicide should be blocked from light-emitting areas to maximize luminous output. 62 CHAPTER 3. MICRO-PROJECTOR DESIGN Chapter 4 Backplane IC Design This chapter describes the design of an integrated backplane for the two-stage microdisplay architecture. The backplane accepts digital input signals and DC reference currents, and produces an image which is coupled to an image intensifier. Its major components are a 360x200 pixel array, row drivers, calibrated column drivers, and testability circuits as shown in Figure 4.1. The following sections describe each of these blocks in detail. 4.1 Pixel Array The 360x200 pixel array occupies most of the IC area. Pixels measure 25/um square because it results in reasonable demands for optical performance, and also allows pitchmatching of driver circuits to the array. The array operates in column-parallel mode, with one row active at a time. The dimensions were chosen to match the 16:9 aspect ratio of the HDTV format. The pixel array includes features to facilitate characterization and measurement, as shown in Figure 4.2. The rightmost column of pixels (column 359) is removed, and the output of its column driver is connected to a package pin for ease of measurement. The three rightmost columns (356-358) are implemented with top-metal electrodes for future testing with OLED technology. The top row of pixels (row 0) is removed, and the output of its row driver is connected to a package pin. The next row (row 1) is replaced with a row of transimpedance amplifiers to permit observation of column driver outputs without loading of the column lines. The remaining 356x198 pixels include silicon light emitters. A schematic of a pixel with silicon light emitter is shown in Figure 4.3. Device D1 is a p+/nwell junction used to emit light. VLOWis set at -10OV.Current flows from the column line through M2 causing D1 to break down and emit light at low levels. Avalanche breakdown in the p+/nwell junction occurs abruptly, therefore the voltage swing at nl necessary 63 CHAPTER 4. BACKPLANE IC DESIGN Test Pixel Array (360x200) Figure 4.1: Overview of CMOS backplane t to pin _1 rowO rowl row2 Amplifier row 0 O r- m CD C,, Si-Pixel Array 356x198 u, co rowl99 00 Column Drivers (ArrayDACs) Figure 4.2: Arrayfloorplan B -- pin 4.1. PIXEL ARRAY 65 rowline D2 M1 V PCH D I I" \/ Figure 4.3: Pixel schematic to turn the pixel on and off is less than 100mV. D2 is a junction diode that prevents ni from falling below ground. When column-driver DACs change their output values, large switching transients can occur. In addition, charge stored on the column-line due to distributed resistance and capacitance can cause nonlinearity. An additional rowline and pass transistor are implemented to suppress these effects. Ml sinks current from ni to VPCH at the beginning of each row period, preventing transient currents from flowing through D1. The tradeoffs of this technique are reduced duty cycle, and a 4% reduction in fill factor due to the additional rowline. OLED pixel Three columns of the pixel array were implemented with top-level metal pads instead of silicon light emitters, for future testing with OLED material. The pixels are on the same 25,um pitch as the rest of the array, and the passivation opening measures 12.4x10.4tPm 2 resulting in a fill factor of 21%. OLED material layers can be deposited on top of the IC. The top level metal pads are the anodes of the OLED devices, and and a common cathode is formed by a layer of transparent conductor such as ITO applied over the OLED layers, as illustrated in Figure 4.4. A schematic of the OLED pixel is shown in Figure 4.5. The dual rowline structure, and the protection diode are the same as in the pixel with silicon light emitter. CHAPTER 4. BACKPLANE IC DESIGN passivation ITO cathode e- injection layer e- transport layer hole transport layer hole injection layer } OLED layers Figure 4.4: OLED materiallayers rowline .. I ,,,, VPIHU I -HZ 11" rowlinepch ---' 'i VDUMP column line Figure 4.5: OLED pixel schematic pad 4.2. ROW DRIVERS 67 chift in " " ~~ Figure 4.6: Row driver circuit I~ /--\~-- rowclk rowclkdn shiftin 2' enable shiftout I rowline rowlinepch Figure 4.7: Row driver timing 4.2 Row Drivers The row drivers are digital buffers controlled by a shift register. The shift register design was chosen for its simplicity and compact area. It requires that rows be accessed in sequential order, which is acceptable given the row-at-a-time operation of the display. There are two sets of rowlines. The first set controls current from the column to the light emitters. An enable signal gates the shift register outputs to allow clearing of the shift register without disturbing the rowlines. The second set of rowlines is used to reduce switching transients, as described in Section 4.1. The logical functions for each of the i rows are: rowline(i) = rowlinepch(i) = shiftout(i) AND enable shiftout(i) AND rowclk AND rowclkdn A rowline driver schematic is shown in Figure 4.6, and a timing diagram in Figure 4.7. The signal rowclkdn is a delayed and inverted copy of rowclk, generated by the FPGA and off-chip delay circuitry. 68 CHAPTER 4. BACKPLANE IC DESIGN IIN ITR<9:0> - calibration calibration -;·--i r;..ii--i--!'i-i·;t i.;.i~- i ili ·--'-) external reference r-i-i-i-i-ij ii-ii i- :;.... · i: ifi i: !·i-·· i-t-iti')i-ii-i( RefDAC 1023 copiers Binary-weighted ArrayDACs IREF<i>=nI.*2i Figure 4.8: Two-stage calibrationtechnique 4.3 Column Drivers and Calibration 4.3.1 Overview The pixel array is driven in column-parallel manner with one row illuminated at a time. Current-mode driver circuits permit precise control of light emitters, however transferring small currents through long column lines with large parasitics is challenging. Long settling times reduce precision at the pixel level, and degrade the quality of the image. One solution is transferring large currents through column lines, and scaling them down at the pixel level [97]. Precharge techniques to reduce settling time have also been presented [98]. In this display, column driver current levels are increased by operating pixels at a low duty cycle. The full-scale pixel current was set by considering the maximum allowable power dissipation for an IC. The maximum dissipation without design for thermal management is about one watt. The high-voltage supply for avalanche junctions is about 10V. Consider a one-megapixel display with one thousand rows. The average full-scale pixel current is 100nA. The row duty cycle is 1/1000, therefore the maximum column driver output current 100pA. Mismatches between column-parallel driver circuits result in fixed pattern noise (FPN) that the human eye detects readily. To achieve a high degree of device matching in column drivers, conventional designs use large geometry devices. In this work, a self-calibration technique which is based on the current copier circuit [99] is used to achieve high precision while reducing circuit area compared to a conventional design. Calibration is performed periodically in two stages as shown in Figure 4.8. The starting 4.3. COLUMN DRIVERS AND CALIBRATION 69 Figure 4.9: Column driver calibration overview point is a DC reference current. This current can be generated on-chip with the use of a bandgap or other precision reference source. For demonstration purposes, in our system it was supplied by an off-chip source. The reference current is copied 1,023 times by an array of identical current-copier cells. This array is called the Reference DAC, or RefDAC. There is only one RefDAC per chip and all column drivers are calibrated against it. It must be highly accurate while operating in subthreshold, therefore a fully segmented architecture is used. The outputs of the cells are grouped to produce ten very precise binary-weighted bit-currents which are used to calibrate the column driver DACs (ArrayDACs). Each ArrayDAC consists of ten current-copier cells that replicate the bit-currents from RefDAC. A binary-weighted architecture is used to minimize area at the cost of some accuracy because there are hundreds of ArrayDACs per chip. The current copier is a dynamic analog memory, therefore the RefDAC and ArrayDACs must be calibrated periodically. To reduce refresh rate and power dissipated during calibration, maximizing the retention time of the current-copier is of prime importance. A circuit technique to improve retention time will be described in Section 4.5. Figure 4.9 is a block diagram showing the major circuit blocks in the calibrated column drivers. These blocks will be described in following sections. 4.3.2 Area Comparison Consider a 10b current-mode DAC implemented as a binary-weighted design with MOS transistors as current sources. Matching between drivers should also be at the 10b level. The MSB is 50[LA, and 3 variation must be less than 0.025%. The MSBs are in strong inversion, and LSBs in subthreshold. Array driver circuits are spatially distributed, so lay- CHAPTER 4. BACKPLANE IC DESIGN 70 lOUT 1 Figure 4.10: Simple MOS current source out techniques to improve matching such as common-centroid are not applicable. The total area of a single DAC implemented this way is 50,000/m 2 , found by extrapolating available process variation data. In contrast, an entire ArrayDAC occupies 7,000,m 2. In the limit of a large display, the area used by the RefDAC and calibration overhead is insignificant compared to the area of the ArrayDACs. On the implemented chip, one ArrayDAC plus 1/360 of the RefDAC occupy 10,600bum2. This represents a 5x to 7x reduction in circuit area. 4.3.3 Current Copier This section describes the motivation for the current copier circuit, its basic operation, and improvements made in the implemented circuit. The circuits are explained as NMOS circuits, although both NMOS and PMOS versions of the current copier are used. In a conventional design, shown in Figure 4.10, MOSFET transistors can be used as current sources. Common models for drain current and threshold voltage variation assume that they are inversely proportional to the square root of device area [100]. kId kct (4.1) kvt aVt= x/-L (4.2) Uld = where kId and kvt are empirically determined constants with units of A/lm and V/um respectively, and W and L are device dimensions. Large devices are required in order to obtain precise currents. The problem is worse in subthreshold (weak inversion) because 4.3. COLUMNDRIVERS AND CALIBRATION A I 71 B (%.jUUT Figure 4.11: Simple current copier threshold voltage variation has an exponential effect on drain current. Furthermore, process variation is increasing in newer CMOS technologies [101]. Instead of using large devices to achieve high precision, a circuit technique can be used to produce precise replicas of a reference current. The circuit is called the current copier [70], and Figure 4.11 is a simplified schematic diagram showing its basic operation. The circuit has two states. In the first state the A switches are closed, the B switch open, and a DC reference current driven into node IIN. Device M1 is diode-connected, and the VGS corresponding to the reference current is stored on capacitor C. Then the A switches are opened and the B switch closed. Transistor Ml acts as a current source producing a replica of the reference current. Device variation in M1 does not affect circuit precision, thus M1 can be small in size. However the circuit is a sample and hold, and its precision is limited by charge injection and leakage currents. Charge injection can be partially cancelled by a properly sized "dummy" device connected to the storage node. Leakage currents are caused by subthreshold conduction in the switch device, and reverse-bias leakage of source/drain diffusions. To find the relationship between leakage currents and change in copier output current, consider the storage capacitor and the small-signal model of M1: AV ILEAK = CSTORE AT iD = gmAvGS Combining these, it can be seen: (4.3) (4.4) CHAPTER4. BACKPLANEIC DESIGN 72 vbias Figure 4.12: Reduced transconductance current copier AiD = 9mILEAK CSTORE (4.5) Output current fluctuation can be reduced by reducing transconductance and leakage current. These will be explained shortly. The remaining two options, reducing \T and increasing CSTORE,translate into increased time spent in calibration and increased circuit area, which are not desirable. A current copier circuit with reduced copier transconductance is shown in Figure 4.12 [71]. M4, called the "bleeder device," is the output branch of a current mirror. There is one reference (diode-connected) device per chip biasing many bleeder devices. The purpose of M4 is to reduce the current through M3 in order to reduce its transconductance, gm,M3. Based on variation analysis, M4 carries the largest amount of current possible while being less than IIN. This constraint is necessary because the NMOS-only current copier can only sink current, not source it. If the nominal value of ID,M4 is chosen 80% of IIN, the current through M3 is reduced by a factor of five. If M3 is in subthreshold operation, gm,M3 is also reduced by a factor of five. An improved current-copier circuit that we developed is shown in Figure 4.13. Transistor M3 is replaced by the stack M8-M10 which has a lower transconductance due to source degeneration. M1 1-M12 are a cascoded "bleeder" device. M14 is the sampling switch and M13 is the charge injection cancellation device. M8 and M9 also raise the voltage stored on capacitor C2 to improve retention time by allowing more negative gate drive on M14 4.3. COLUMN DRIVERS AND CALIBRATION 73 lout -I lii A- n6 M13 I I C2 Figure 4.13: Improved current copier vbias2 - CHAPTER4. BACKPLANEIC DESIGN 74 0 0 I 0 Vstore -- Vhold F--- Vstore Figure 4.14: Passgate leakage scenarios: (a) conventional, (b) voltage control !, 0 I Fh. HOLD Figure 4.15: Conventional (left) and improved (right) passgates when turned off. The target voltage at n5 is 1.OV. To further improve retention time, the voltage applied to the source of M14 is controlled. Consider a conventional NMOS passgate as shown in Figure 4.14. In the worst case, the gate is at OV, the drain at the stored voltage (VSTORE),and the source is at OV. The gate-to-source voltage is zero while VDS is greater than a few kT/q, and subthreshold conduction can be calculated: ID = Ise q(-VT)/kT (4.6) This subthreshold conduction will quickly discharge capacitor C2. A solution is to drive the source voltage to a positive voltage VHOLD,ensuring that VGS,14< 0. Subthreshold conduction is greatly reduced: - VT)/kT ID = Ise q(- VHOLD (4.7) Figure 4.15 shows the leakage reduction concept in its simplest form. On the left is an ordinary NMOS transistor used as a passgate. On the right is the improved passgate. When the clock is high, the two sides are connected. When the clock is low, the two sides are disconnected and the middle node is set to voltage VHOLD- Subthreshold conduction 4.4. BIASING 75 is reduced, and junction leakage becomes the main cause of leakage currents. A similar structure known as the "T-switch" has been used to reduce feedthrough in high frequency switches [102]. In the conventional design (Figure 4.12), the voltage at node n3 may to drop to zero to reduce power consumption by turning off the copier's output current. When this happens, VGS of M5 is zero and subthreshold leakage from n2 to n3 is significant. To avoid this, the input and output current paths (n7 and n6) are separated in our design (Figure 4.13). The voltage at n6 does not affect M14, and n6 can fall to ground while the bit is deselected, for lower power. The voltage at n7 is controlled by connecting it to a voltage source (VHOLD)when the current copier is holding its value. Subthreshold leakage current through M14 is reduced because a large negative gate drive is maintained, and VDS of M14 is also reduced. Circuit operating points and DC operation were verified with simulation. Process variation was analyzed using models provided by the foundry. Predicting the dynamic behavior of sampling circuits is difficult. Modelling charge injection requires two-dimensional analysis of the MOSFET to produce correct results, and a complex task. Models have been developed [103, 52], but accessibility of design tools is limited. For design purposes, we estimated the dummy device M13 would cancel 80% of the charge injection from the sampling switch M14. 4.4 Biasing PreRef The PreRef section supplies the RefDAC with the reference current IIN and the reference voltages for "bleeder" devices. A simplified schematic of the IIN circuit is shown in Figure 4.16. The off-chip reference current is replicated by a ratioed current mirror. The ratio is set to make off-chip currents larger than 1,uA for easier manipulation and noise immunity. This mirror also isolates on-chip circuits from the large capacitances associated with off-chip circuits. A 1-to-4 analog demultiplexer connects the reference current to one of four RefDAC quadrants, which will be explained in the RefDAC section. This multiplexer also controls the voltage of the de-selected outputs. Its logical function is shown in Table 4.1, and it will be used to improve retention time of the current copiers as discussed in a later section. The circuit to generate reference voltages for "bleeder" devices is shown in Figure 4.17. It consists of a ratioed PMOS current mirror at its input. Current from the PMOS mirror CHAPTER4. BACKPLANE IC DESIGN 76 Vdd Vdd RefDAC iin<3:0> ost rol Figure 4.16: RefDAC reference current generator and switch prerefsel3 0 0 0 1 2 1 0 VHOLDEN o 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 O 0 0 O O O 1 1 0 0 RefDAC iin(3) float float float ii. (2) float float iin float (1) float iin float float VHOLD (0) ii. float float float 1 1 VHOLD VHOLD 1 0 1 VHOLD VHOLD iin VHOLD 0 0 1 VHOLD iin VHOLD VHOLD 0 1 iin VHOLD VHOLD VHOLD Table 4.1: PreRef switch truth table iin 4.4. BIASING 77 ib Figure 4.17: Bleeder bias voltage generator flows into an NMOS mirror. The devices in the NMOS mirror are layout-matched to the "bleeder" devices located in the RefDAC current copier cells, and the two output voltages are distributed to the RefDAC. VBIASGEN This block accepts reference currents from off-chip sources and produces the reference voltages for the ArrayDAC current mirror circuits. Figure 4.18 shows a single circuit. There are four circuits total, one for each group of current copiers. This circuit is a mirrorimage of the one used in the PreRef block. Current from an off-chip reference flows into a ratioed NMOS current mirror. The output feeds the input of a PMOS current mirror which is layout-matched to the current mirror output legs located in the ArrayDACs. The two voltage outputs are supplied to the ArrayDACs. For testability, the VBIAS2 node is accessible on a pin through a passgate controlled by the testmode shift register. The testmode shift register circuit is shown in Figure 4.19. When TESTEN is low, the passgate is disabled. When TESTEN is high and the control register output is high, the passgate connects the test node to a package pin. The SHIFTIN and SHIFTOUT pins are connected to form a shift register as shown in Figure 4.20, with the clock, first input, and last output connected to package pins. CHAPTER4. BACKPLANE IC DESIGN 78 asl as2 cu n Figure 4.18: VBIAS circuit It IS To Figure 4.19: Testability control circuit vbiasd2 test control I to pins Figure 4.20: Testability scan chain shift out 79 4.5. REFDAC RefDAC INPI ITS OUTPUTS iout iin vbypl ,vbyp2 current copier rowsi CD rowclk CD o- array 32x32 0) colsi colclk r. It 1 nnhlo VUL IC:L/Il column select -- Figure 4.21: RefDAC block diagram 4.5 RefDAC The RefDAC is an array of 1023 identical NMOS current copier cells, based on the design presented in section 4.3.3. Figure 4.21 shows the current copier array and row and column drivers. A detailed circuit schematic is shown in Figure 4.22. The copier is implemented with a mix of thick and thin oxide NMOS devices. Devices M1 and M12 are 1.8V devices because they have lower variation (k in Equation 4.1). M2, M3, M7, and M9 are 3.3V devices to minimize gate leakage. M4 and M5 are designed conservatively as 3.3V devices in case of large voltage swings at the DAC outputs. The gate voltages of devices M3, M4, and M5 are limited between 0 and 1.7V. When switches are turned on, they also act as cascode devices to improve current copier output resistance. During calibration, the OUT signal is low to disable outputs. Row and column control signals are connected to an AND gate in each cell, so that only one copier is enabled at a time. The RefDAC rowline driver is shown in Figure 4.23, and the column driver in Fig- ure 4.24. The rowline driver includes an edge-shaping circuit to guarantee non-overlap when rowlines are switching [104], and the column driver is a simple shift register with buffers. Row and column driver circuits are implemented with standard cells, and operate between DVDDL=1.7V, and DGND=OV. The RefDAC outputs are ten binary-weighted currents. Current copier cell outputs are connected in parallel to produce the desired current levels. To compensate for process gradients, cells were placed symmetrically around the center of the array The cell layout pattern for the center of the RefDAC array is shown in Figure 4.25. The numbers corre- CHAPTER4. BACKPLANE IC DESIGN 80 r out I us *_ I iout M5 F- iin "ll I DVDDL I DVDDL M4 inrow incol M2 M3 M3 I1IL byp2 bypl Uo M7 l~~~~~~~~ a X n v I I IL M12 M10 I XL I I A J FM', _ M11 i I Figure 4.22: RefDAC current copier circuit Figure 4.23: RefDAC row driver power=DVDDL si col line clk so ground=DGND Figure 4.24: RefDAC column driver M1l 4.5. REFDAC 81 89899898 9 6 9 7 7 9 6 9 8 9 9 8 9 8 9 7 7 9 6 9 8 9 9 8 9 8 9 0 1 9 7 9 9 1 x 9 7 9 8 9 9 8 9 8 9 7 7 9 6 9 8 9 9 8 9 8 Figure 4.25: ReJDACcell pattern spond to the i t h output current where i = 0 is the LSB and i = 9 is the MSB. The it h output current uses 2i current copier cells in parallel. This is a common-centroid pattern. The cell marked "0" produces the LSB, and the cell marked "x" is used for test purposes. The RefDAC array includes a row of dummy cells on each side of the array to improve uniformity between active cells. The overall array size is 34x34 cells. Each cell measures 22.4* 28.8[tm , and the complete RefDAC occupies 1.lmm 2 . The initial RefDAC design had all current copier inputs (IIN) connected together to a single node. Simulations and calculated estimates of settling time indicated the settling time of RefDAC current copiers was too long with this arrangement. The cause was the large capacitive load on the input node. This capacitance consists of gate and interconnect capacitances within the RefDAC array; note that the PreRef block has a current mirror that isolates this node from external capacitances. The input node was divided into four to reduce its capacitance. Each quadrant included eight columns of the RefDAC array. During calibration, a demultiplexer in the PreRef block to steers the reference current to the appropriate quadrant of the RefDAC array. Figure 4.26 is a simulation of RefDAC cell settling behavior. The curves are currents through the copier (M7) and bleeder (M12) devices during a calibration cycle. The reference current is 100nA, "bleeder" or mirror current is constant at 85nA, and the copier settles to 5nA with 10b precision in 70ps. Retention time improvement is implemented with a multiplexer in the PreRef block, and the current copier cells in the RefDAC block. Figure 4.27 shows these elements together Current copier cells are arranged in groups of 256 that share a common input node n7. During calibration, n7 connects between IIN and one current copier cell. Its voltage is three diode drops above ground, so deselected passgates have negative gate-to-source voltages and leakage currents are small. When copier cells are holding their values, n7 is connected to a voltage source and the voltage is set to VHOLD. The voltage at n7 is now controlled at all times. Subthreshold conduction through M14 is reduced, and retention time of the CHAPTER4. BACKPLANE IC DESIGN 82 test i estreTcell snemaric: AUg I/:33:zL3 3 ZL4- Transient Response I ,: /I0/M12/D -: /I0/M7/D 130n 100n m n · n · I 70.0n 40.0n 10.0n -20.n _ . . . .. .. . . . . . . . . . . .. 0.00 30.0u 60.0u time ( s ) 11 III I . 90.0u . .. ~ 120u Figure 4.26: RefDAC copier cell settling time simulation Vh Figure 4.27: Retention time improvementcircuit 83 4.6. ARRAYDAC vDlasZ o vbias1 AVDDH inn in iin out ni it Figure 4.28: ArrayDAC copier schematic current copier cells is greatly increased. 4.6 ArrayDAC There are 360 column drivers (ArrayDACs) on the chip. Each ArrayDAC consists of ten PMOS current copiers which replicate the ten binary-weighted currents from the RefDAC. A circuit schematic is shown in Figure 4.28. It is a PMOS implementation of the RefDAC current copier. ArrayDAC I/O pins are shown in Figure 4.29. The 10b data word controls the OUT switches for the ten current copiers. The calibration input for each copier (IIN) connects to the respective binary-weighted reference current. Signal IN is common to all ten copiers within an ArrayDAC. The output IOUT is connected to the column line. To reduce settling time during calibration, a multiplexer connects the RefDAC outputs to either the left 180, or right 180 ArrayDACs. The multiplexer also implements the retention time improvement technique described in the RefDAC section. The ArrayDACs occupy a total of 2.5mm2 . The current copiers are individually optimized for their respective current levels. There are four sets of bias voltages available for producing bleeder currents. In addition, a current copier cell may contain 1, 2, or 4 legs of the current mirror to produce multiples of the bleeder current. By varying both the number of legs and the bias voltages, a design with very compact area can be implemented. Excluding the transistor used as a storage capacitor, CHAPTER4. BACKPLANEIC DESIGN 84 ArrayDAC bit nominal current bleeder voltage group legs 0 100n D 1 1 200n C 1 2 3 4 5 6 7 8 400n 800n 1.6u 3.2u 6.4u 12.8u 25.6u C C B B B A A 2 4 1 2 4 1 2 9 51.2u A 4 Table 4.2: ArrayDAC current mirror biasing lout data<9:0>o---- 0 iin<9:0> o> . ino inn o ArrayDAC 1, vbiasal a2,b1 b2,cl,c2,d1 ,d Figure 4.29: ArrayDAC block diagram the largest transistors are 4*45am , and the maximum ratio for current mirror devices is 4:1. Nominal currents and biasing arrangements are listed in Table 4.2. Two sets of 10b digital registers are located below each ArrayDAC. One is used to store the present value of the output, the second is used to load the next value in the background. This allows all ArrayDACs to update their output values synchronously. The circuit in Figure 4.30 is used. The signal EN 1 is generated by a shift register that selects one ArrayDAC register to be loaded. This is repeated 360 times to load new values into all 360 first-level register banks. Then the signal EN2 is asserted for one clock cycle by the FPGA, causing the new values to be loaded into the second-level register banks. The EN1 shift register was implemented with the circuit shown in Figure 4.31. The signal clear forces all registers to zero on the rising edge of clk. This eases the process of resetting the display control logic, and also saves time during data loading when only a portion of the display is being utilized. Calibration of the ArrayDACs is controlled by a shift register. Before calibrating an ArrayDAC, its output switches are turned off by setting the data word to zero (Ox3FF). To 4.6. ARRAYDAC 85 DVDDH data<! '<9:0> VE standard cells use DVDDH, DGND Figure 4.30: ArrayDAC registers si enl clk SO clear Figure 4.31: ArrayDAC data load control sout enm Figure 4.32: ArrayDAC calibration control CHAPTER4. BACKPLANE IC DESIGN 86 sout Figure 4.33: ArrayDAC calibration control, improved reduce capacitance on the input node, the ArrayDACs are divided into two groups: columns 0-179, and 180-359 the RefDAC output demultiplexer must select the correct group, and the RefDAC output control must be enabled. A shift register composed of the cell shown in Figure 4.32 selects one ArrayDAC at a time to use the RefDAC outputs as reference currents. A circuit improvement was to change the voltage levels of the in and inn signals. These signals are switched between AVDDH and VBIAS=1.OV,causing the switch devices inside the ArrayDAC current copier to act as cascode devices. A more detailed schematic is shown in Figure 4.33 4.7 Design for Testability Because of the widening gap between the sizes of on-chip circuits and board-level components, testing is an important design consideration. On-chip circuits to support testing and observation are essential. Circuits such as an on-chip sample-and-hold to observe signals without loading critical nodes has been described [105]. The idea has been taken farther, for example an on-chip oscilloscope [106]. This chip included a number of testability features. First, some nodes were routed to pins through passgates controlled by a testmode shift register. This allowed direct observation and measurement of electrical signals. One row driver and one ArrayDAC were configured for direct measurement. The first row driver is identical to all others except that it drives a pad instead of a rowline. The last ArrayDAC (column 359) drives a pad instead of a pixel column. To observe ArrayDAC outputs and switching behavior of the bitlines, the top row of 4.7. DESIGN FOR TESTABILITY .F, , 1ON FO Figure 4.34: Micrographshowing Si-LED pixels, OLED pixels, and ArrayDACs pixels was removed and replaced with transimpedance amplifiers which are described below. Both silicon light emitters and OLEDs can be supported by current-mode driver circuits, although OLEDs typically require larger voltage swings. For future testing, three columns of pixels were built with top-level metal bondpads, as shown in Figure 4.34. This picture shows the bottom-right corner of the pixel array. At top left, pixels with silicon light emitters can be seen. The three rightmost columns of pixels are OLED-style bondpads. The ArrayDACs are located directly below the pixel array. Amplifier Transimpedance amplifiers allow realtime observation of column driver outputs by isolating the column lines from large external capacitances. The circuit for the transimpedance amplifier is shown in Figure 4.35. It is a single transistor common source amplifier with resistor biasing. Nominal bias current is 2001pA, and the input and output operating point CHAPTER4. BACKPLANEIC DESIGN 88 ampso ampout iND. Figure 4.35: Column transimpedance amplifier voltages are 650mV. The ideal transimpedance is 3.7KQ, so the output voltage swing for a full-scale 100pA input is 370mV. When the rowline for row 1 is enabled, the column lines are connected to the transimpedance amplifier inputs. A shift register selects a single amplifier, connects it to the power supply, and enables it to drive a shared output pin. For characterization purposes, the input of the amplifier can be connected to an input pin so that a known current can be applied and the output observed. 4.8 Top-level IC The IC is fabricated in a standard 0.18pm CMOS logic process with one poly and five metal layers, and measures 8mm by 10mm. A micrograph is shown in Figure 4.36. The center of the chip is occupied by the 360x200 pixel array. The RefDAC is located at bottom center. The ArrayDACs are located along the bottom of the array, and row drivers are located along the left edge of the array. The chip is packaged in an open-cavity PQFP package. The RefDAC occupies 1.3mm2 , and the ArrayDACs occupy a total of 2.5mm 2 . Pixel size is 25,um square, the pixel array measures 360x200 corresponding to a 16:9 aspect ratio, and the fill factor of silicon light emitters is 22%. Three columns of pixels were built with 4.9. SYSTEM BOARD AND OPTICS Figure 4.36: Die micrograph top-level metal electrodes instead of silicon diodes to interface with OLED technology. The electrical interface to the backplane IC is described in Tables 4.3, 4.4, and 4.5. 4.9 System Board and Optics The microdisplay backplane IC is packaged in an open cavity PQFP package and mounted on a printed circuit board. The board includes an FPGA to generate digital data and control signals, and DC voltage and current sources. Programs are compiled on a computer and downloaded to the FPGA through a programming cable. Due to packaging and mechanical constraints it was not possible to put the silicon IC in contact with the image intensifier's photocathode. For demonstration purposes, a microscope objective lens was used to couple the image from the silicon IC to the photocathode. The lens and the image intensifier are mounted on opposite ends of an optical tube which is positioned above the silicon IC. The lens has a numerical aperture of 0.25, so it transmits 6% of the light emitted by the silicon to the intensifier. The intensifier is a Hamamatsu V7090U-61-N130, a Generation III intensifier with gallium arsenide photocathode and one microchannel plate. CHAPTER4. BACKPLANE IC DESIGN 90 Name AVDDH VHINWELL DVDDH DVDDL AGND DGND VBULK VDUMP Direction 3VDC Power Supply 3VDC 3VDC 1.7VDC Analog GND Digital GND Substrate GND 0.6VDC -10VDC VLOW VHOLD AMPVDDH AMPGND VPROT Type Notes Power Supply Equal to AVDDH Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Avalanche diode supply 0.3VDC Power Supply 3VDC Power Supply Amplifier GND Power supply For transimpedance amps 0.3VDC Power supply For protection circuits Table 4.3: IC power supplies FPGA and control Control algorithms are implemented on an FPGA for maximum flexibility in testing. A control board based on the Xilinx Spartan-II XC2S50 FPGA is used. This FPGA includes 50,000 gates, and is packaged in a 144-pin QFP package. The I/O circuits operate at up to 3.3V, and the core operates at 2.5V. The register toggle frequency FTOG is stated as 263MHz which is ample for our application. Finite state machines were used to control the various parts of the display backplane. The controller initialized state registers, performed calibration of the RefDAC and ArrayDACs, and drove patterns using the ArrayDACs, as shown in Figure 4.37. A 20MHz reference clock was generated by the crystal-controlled oscillator shown in Figure 4.38. Frequency division and duty cycle control were implemented in the FPGA. DC voltages were generated using linear voltage regulators. Current references were generated using discrete bipolar transistors with large emitter degeneration resistances. A simple control pattern used for electrical measurements is shown in Figure 4.39. First the RefDAC outputs are used to calibrate the ArrayDACs, which requires 25ms. Then, the RefDAC is calibrated against the reference current while the ArrayDACs drive the pixel array. Calibration of the RefDAC takes 70ms, which is longer than the 10b retention time of the ArrayDACs. Therefore, the ArrayDACs only produce output for 35ms (25ms+35ms = 60ms), and are idle for the remaining 35ms. The pixel array is driven for 33% of total time, so this pattern is only useful for testing. An improved control pattern is shown in Figure 4.40. This pattern utilizes the long 4.9. SYSTEM BOARD AND OPTICS Name rowenable rowsi ampsi vbtesten vbsin calsin calen shiftclr shiftsi data(9:0) rowclkdn rowclk enable2 vbscanclk prvholden prselect(3:0) vbiasa vbiasb vbiasc vbiasd priin pribypin prtestclk prsin prtesten refrowsi refrowclk refcolclk refvholden refselect(2:0) latchclk shiftclk calclk outenable ampclk amptestiin amptest Type digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital analog current analog current analog current analog current analog current analog current digital digital digital digital digital digital digital digital digital digital digital digital digital Direction in in in in 91 Notes enable rowlines to turn ON data input for row driver shift register data in for test-amp shift register connect VBIAS nodes to vbtest(3:0) pins in in data in for vbias shift register. Negative true data in for calibration shift reg. Negative true in in in enable for calibration shift register clears ArrayDAC data register enable signals data in for ArrayDAC enable register in 10b image data in in in in in in in in in in in in in controls second set of rowlines clock for rowline shift register load second level of ArrayDAC registers clock for vbias shift register clock for pre-refdac shift register drive preref(3:0) test outputs bleeder current for bits 9,8,7 bleeder current for bits 6,5,4 bleeder current for bits 3,2,1 bleeder current for bit 0 sets refdac reference current sets refdac bleeders clock for preref shift register in data in for preref shift register, Negative true in enables preref shift register in input for refdac row shift register in in in clock for refdac row shift register clock for refdac column shift register enables VHOLD muxes in refdac in RefDAC outputs to left, right, or refiouttest in clock for array registers in clock for first-level ArrayDAC shift register in in in clock for arraydac calibration shift register enables some digital outputs clock for amplifier shift register analog current in test current input for amplifiers digital in select amplifier normal or test mode Table 4.4: Input pins CHAPTER4. BACKPLANE IC DESIGN 92 Name Direction Notes Type vbso arrrowso digital digital out out output of vbias shift register output of row driver shift register prerefso digital out output of preref shift register refrowso refcolso digital digital out out output of refdac row shift register output of refdac column shift register prerefout(3:0) a. voltage or current out test output from PreRef vbtest(3:0) refioutx refiouttest(9:0) arrshiftso arrco1359 arrcalso arrampso arrampout analog voltage analog current analog current digital analog current digital digital analog voltage out out out out out out out out VGS of VBIAS mirrors output of extra copier cell in RefDAC RefDAC output currents, for testing arrayshift shift register output column359 ArrayDAC current out arraydac calibration shift register out amplifier shift register out amplifier current output arrrowlinetest arrrowpchtest digital digital out out output of dummy rowline driver output of dummy rowline driver Table 4.5: Output pins reset set testmode signals calibrate ArrayDACs V calibrate RefDAC drive ArrayDAC pattern NI--I Figure 4.37: High-level program flowchart 4.9. SYSTEM BOARD AND OPTICS 1/6 74HC04 +o% COrDA II Figure 4.38: Clock oscillator RefDAC out I ArrayDAC calibration g b 25ms 35 a 35 60ms Figure 4.39: Timing diagram - simple program CHAPTER 4. BACKPLANE IC DESIGN Ro Ro Ac Ao Ac 25+ 35 Ro Ao 60ms Ro Ro Ro Rc Ro Re Acc Ao lAc Ao JAc_ Ao Ac Ao 7 * 70 = 490ms Figure 4.40: Timing diagram - optimized Figure 4.41: Assembled system board retention time of the RefDAC (500ms). The ArrayDACs alternate between 25ms calibration periods and 35ms array-driving periods. RefDAC calibration is divided between two periods to minimize ArrayDAC idle time. The pixel array is driven for 58% of total time, limited by the retention time of the ArrayDACs and the time required to calibrate them. ArrayDAC calibration and output cycles can be subdivided to improve image quality. For example a fraction of the ArrayDACs could be calibrated after each frame. This would eliminate flicker caused by the idle time during ArrayDAC calibration (25ms). In future implementations, the addition of one or more extra ArrayDACs could permit calibration in the background. This would increase pixel duty cycle at a slight increase in control circuit complexity. The assembled system board is shown in Figure 4.41. The board has four signal layers and measures 4x10 inches. The FPGA is mounted on a daughterboard located on the left side of the main board. The backplane IC is at center, in an open-cavity package covered with a lid. Many test terminals located around the perimeter of the IC. Adjustable DC voltage and current source circuits are located on the right side of the board. Chapter 5 Measured results 5.1 5.1.1 Electrical Measurements RefDAC Linearity To measure the performance of the RefDAC, the ten binary-weighted current outputs are connected to ten pins by enabling a test mode. The RefDAC is calibrated, and the currents are measured individually using an HP4140B picoammeter. During calibration, the RefDAC output currents are disabled. The picoammeter must be synchronized to measure only when outputs are valid. The FPGA generates a synchronization signal at the end of each calibration cycle, and the circuit shown in Figure 5.1 is used to delay the sync signal and invert its polarity for connection to the 4140B trigger input. The following graphs show the operation of the RefDAC in response to varied reference and bleeder current levels (IINand IBYP).The ten binary-weighted output currents are on the X-axis, from LSB to MSB. The measured current is plotted on the Y-axis, expressed as the ratio between measured and nominal values. First, the ordinary current mirrors are measured alone by disabling the current copiers ("uncalibrated"). Calibration is enabled, O 3.3K _m FPGA '/VV~ . .. N3904 I1OOuF 1 _"_2_ 7 47uF Figure 5.1: Synchronization circuit 95 to 4140B sync input 96 CHAPTER 5. MEASURED RESULTS mcr3yref4.m refdac nocal current error 25 aug 04 achen o C o o o X X 0O 0o 0 -5 C) 0- ca -a -10 >15 x 'o X : -20 0 -- X X X I x~~~~~~~~~~~~~~~~~~~~~~. x uncalibrated _ 0 -2_:N -,4n 0 2 I calibrated i I I 4 6 8 10 Bit (Isb-to-msb) Figure 5.2: RefDAC bit currents,first attempt the total "calibrated" output current is measured. In the first measurement, the reference and bleeder current sources are set with IREF = 100nA and IBYP = 85nA. The outputs from the RefDAC are shown in Figure 5.2. The uncalibrated currents are approximately 83% of nominal value (shown as 83%-100% = 17%). There is an offset between the BYP value of -15% and the output value of -17%. This may be caused by mismatch in the current mirror input circuit. When calibration is enabled the output currents are 105% of their nominal values, and 5% higher than the value of IREF. Variation in the uncalibrated currents is mainly caused by mismatch between the bleeder current source devices. Variation in the calibrated currents is caused mainly by charge injection in current copier circuits, and will be explained in more detail later. RefDAC precision can be improved by adjusting the two current references. IREF is reduced by 5%, and IBYP is increased by 3% to make the calibrated and uncalibrated output currents 100% and 85% of nominal value, respectively. The results are shown in Figure 5.3. Based on the measured currents, the response to a ramp input was calculated and corrected for gain and offet errors. These data were used to compare RefDAC performance to ideal data converter performance, shown in Figure 5.4. Integral nonlinearity (INL) is less than ±0.43 LSB, indicating 10.lb precision after calibration. The main source of error in the RefDAC is variation in charge injection. A constant amount of charge injection in all cells does not affect linearity because of the fully segmented architecture. It is variation between the sizes of the passgate and charge injection 97 5.1. ELECTRICAL MEASUREMENTS mcr3yref5.m refdac nocal current error 25 aug 04 achen Jl U ) O O O X X O O a) a) -10 U) ', -15 X X X 00 X X 1-20 O -25_--_ qn 0 2 1.1 _ _ * x uncalloratea 0 calibrated ! . I 4 6 8 _ 10 Bit (Isb-to-msb) Figure 5.3: RefDAC bit currents, second attempt cancellation devices that causes nonlinearity. In a sample-and-hold circuit, the dummy device should exactly cancel the charge injection from the switch device. If the cancellation is not exact, then the change in charge causes a change in voltage: \Q = CAV. If this change in voltage is small, a small-signal model can be used. The effect of AV on the output current is Al = g, * AV. For a given copier, AQ and C are fixed. The change in output current can be minimized by reducing the transconductance g, of the current copier. Transconductance is monotonically increasing with drain current, so reducing the current level through the current copier will reduce g, and the effect of charge injection and charge injection variation on the output current. To illustrate this, note the current copier carries 7nA (95-88=7%) in the second case. Reducing this current should reduce transconductance of current copier circuits, and improve RefDAC precision. In the next experiment, IREF = 96nA and IBYP = 90nA. Current copiers carry 6nA, or 6% of nominal current. Performance of the RefDAC is shown in Figures 5.5 and 5.6. Without calibration the RefDAC precision is 8b, about the same as in the previous measurement. With calibration, the RefDAC achieves 11.5b accuracy. In principle, reducing the difference between IByp and IREF, will minimize charge injection error. However, IBYP must be set to always be less than IREF with four or five sigma certainty because the NMOS current copier can only sink current. RefDAC retention time test results are shown in Figure 5.7 and 5.8. Node IIN (see Fig- CHAPTER 5. MEASURED RESULTS mcr3yref5 pseudo-inl 25 aug 04 achen 0 200 400 600 code 800 1000 Figure 5.4: RefDAC INL, second attempt RefDAC bit-current values 100 o O 95 90 85 -* -÷ 80 * 0 75 I 0 I uncalibrated calibrated I 4 6 Bit (Isb-to-msb) I 8 Figure 5.5: RefDAC bit currents,final 1200 99 5.1. ELECTRICAL MEASUREMENTS RefDAC INL - 1. 0. .0 I -J z -0. 1 iL 200 400 600 code 800 1000 Figure 5.6: RefDAC INL, final ure 4.22 is shared by 256 current-copier inputs and if left floating, its voltage drops rapidly due to parasitic junction leakage currents. In the worst case scenario with VHOLD set to zero, retention time for 10b accuracy is less than ms. When n7 was left floating, results were similar to the line for VHOLD=SOmvand 10b retention time is a few milliseconds. As higher VHOLDis applied, leakage current is reduced. With VHOLD> 300mV, the output current is maintained with 10b accuracy for 5OOms at room temperature. In this case, subthreshold conduction is reduced to negligible levels and junction leakage from source/drain diffusions dominates leakage from the storage node. The RefDAC achieves its design goal of producing highly accurate output currents. The fully segmented architecture improves linearity by causing systematic errors to appear as gain error instead of nonlinearity. Imprecise cancellation of charge injection is the primary source of error, and could be improved in a future manufacturing run by resizing the switch and dummy devices. The retention time improvement is effective and the RefDAC can maintain 10b precision for 500ms. 100 CHAPTER 5. MEASURED RESULTS RefDAC Iref9 VHOLD sweep 0.98 - 0.96 Q 0.94 N E Z 0.92 0.9 0.88 0 100 200 300 Time milliseconds (ms) 400 Figure 5.7: RefDAC retention test ---A~ RefDAC Iref9 VHOLD=300mV Zoom I.UUUV 1.0004 1.0003 1.0002 i i 1.0001 1 i . 0.9999 0.9998 0.9997 0.9996 n Qar 0 100 200 300 Time milliseconds (ms) 400 Figure 5.8: RefDAC retention test, zoomed in 5.1. ELECTRICAL MEASUREMENTS 101 C from cope Figure 5.9: Transimpedance amplifier circuit 5.1.2 ArrayDAC To measure the performance of the ArrayDACs, column 359 which drives an output pin instead of a bitline is used. The output current is connected into an op-amp based transimpedance amplifier, and the voltage output connected to an oscilloscope. Averaging is used to improve measurement precision. The transimpedance amplifier circuit is shown in Figure 5.9. Input bias current must be minimized because of the small currents being measured (100nA LSB). The OP-42EJ was chosen for its combination of low input bias current (200pA max), high gain, and fast settling time. The RefDAC is calibrated, then RefDAC outputs are used to calibrate the ArrayDAC. The ArrayDAC is driven with a digital ramp pattern, and its outputs recorded by the oscilloscope. In order to reduce transient effects, the period of each step is 100OOs.Data from the oscilloscope are transferred to a computer and analyzed in MATLAB. Results are normalized to remove gain and offset errors. The ArrayDAC has 7b precision without calibration, and calibration improves its precision to 8.5b. The lower precision is due to the binary-weighted structure of the ArrayDAC's as an area saving measure. In the layout, a single layout block containing the passgate and charge injection cancellation transistors was designed for the ArrayDAC. The same cell is used in all ArrayDAC copiers. A fixed amount of imbalance between the passgate and charge injection cancellation devices results in the same amount of charge injection in all 102 CHAPTER 5. MEASURED RESULTS ArrayDAC INL 200 400 600 800 1000 code Figure 5.10: ArrayDAC INL copiers. Because the ten current copier cells carry different currents, the transconductances of the copiers are all different, and the same amount of charge error has a different effect on each copier, and causes nonlinearity. This is in contrast to the RefDAC, where all cells are designed to be identical and a fixed offset does not cause nonlinearity. Retention time tests for the ArrayDAC show similar trends to the RefDAC. The ArrayDAC maintains 10b precision for 60ms at room temperature as shown in Figure 5.11. The data for normalized current in Figure 5.11 start at a value greater than unity because of overshoot in the oscilloscope step response. The lower retention time is due to the use of PMOS devices in the ArrayDAC in contrast to NMOS devices in the RefDAC. The substrate and n-well doping levels are different, resulting in different leakage current densities. To summarize, at room temperature the RefDAC requires calibration once every 500ms and the ArrayDACs must be calibrated once every 60ms. These times are much longer than the conventional case without the retention time improvement technique. 5.1. ELECTRICAL MEASUREMENTS 103 mcr6yb.m arraydac leakage 30 aug 04 achen I .UUU3 0.9995 0.999 0 20 40 60 time (ms) 80 100 Figure 5.11: ArrayDAC retention test 5.1.3 Column Variation Variation between the ArrayDAC column drivers results in fixed pattern noise, and must be minimized. The amount of inter-column variation was quantified before and after calibration. In this experiment, 357 ArrayDACs were set to drive the same output value (1/4 scale = 256LSB). The output current of each ArrayDAC was measured using the transimpedance amplifier located at the top of each column and an oscilloscope. Without calibration, the mean current is 217LSB and the standard deviation is 1.2%. The standard deviation is a measure of fixed pattern noise. With calibration the mean current is 256LSB (by definition), and the standard deviation is reduced to 0.55%. Fixed pattern noise has been reduced by a factor of two. The results are plotted in Figure 5.12. Another way of viewing the same data is to compare the output of each ArrayDAC before and after calibration. This is plotted in Figure 5.13. Ideally, the calibrated output currents should be constant and independent of uncalibrated current. This would appear as a horizontal line on the graph. The measured results show a weak correlation between uncalibrated and calibrated currents (m=0.15, b=17.8/uA, and r=-0.33). This weak correlation suggests that the calibration technique is functioning, and improving the uniformity between columns in the display. CHAPTER 5. MEASURED RESULTS 104 ArrayDAC currents 45 40 35 30 25 20 15 10 5 0 210 220 230 240 250 260 LSB Figure 5.12: ArrayDAC output current distribution x 10 - 5 mamp3a2 scatterplot 12 nov 04 achen 2.1 2.08 03 2.06 E 1 2.04 a(b , 2.02 -o 2 1.98 1.98 1.96 1 QA 1.6 1.65 1.7 1.75 1.8 uncalibratedcurrent - amps 1.85 x 10- Figure 5.13: ArrayDAC outputs before and after calibration 5.2. OPTICAL MEASUREMENTS 105 Figure 5.14: Sample image for pixel luminance analysis 5.2 Optical Measurements Optical measurements were performed to measure the uniformity between pixel luminances. Measurements were taken using a sensitive CCD camera mounted on a microscope, and with a photometer. Microscope and CCD For the microscope setup, the PCB with silicon IC backplane was placed on the microscope platen. Drivers were set to maximum current, and the output current time-multiplexed between sixteen rows. Only sixteen rows were evaluated at a time in order to increase the duty cycle, and reduce the long integration times required by the CCD camera. The microscope is a Nikon Eclipse L200, used with a 20x/0.45 NA objective lens. A Qimaging Retiga 1300 camera is attached to the camera port, and controlled by a computer with QCapture software. For each measurement, two images are taken to implement correlated double sampling (CDS). First, an image is captured with the silicon backplane emitting light. Then, the VLOW supply is turned off, and an image of background illumination captured. The second image is subtracted from the first to remove background illumination and fixed noise from the imager (hot pixels). A sample image showing the top left comer of the pixel array is in Figure 5.14. This image is divided into colums (16 pixels each), and statistics are computed for variation within the column and variation between columns. Ideally, pixel luminance within a column should be constant because all pixels share the same driver circuit. Measurements show there is signficant pixel-to-pixel variation due to manufacturing variation. In Figure 5.15, the standard deviation of pixel luminance is plotted for each of 24 measured columns, and averages 6.8%. 106 CHAPTER 5. MEASURED RESULTS Pixel Variation vs. Column - i8889u 'u -- · 9 8 75 'a 4 cl 0 5 10 15 20 25 column Figure 5.15: Pixel luminance variation by column The measured variation is the sum of multiple independent sources. These include pixel luminance variation which we want to measure, variation from the imaging process (optical transmission, camera artifacts), and variation from image recognition and processing. The microscope and optics were tested with a uniform test target. Uniformity was within a 5% range across the entire image. The 5% figure includes light falloff, dust, and in-camera variation. This suggests UOPTICS is about 1%. Variation in pixel recognition occurs because the boundary of a pixel, and thus its area, may be interpreted differently by different identification methods. For example, a digitized image was loaded into MATLAB and the boundary of a single pixel was manually identified a number of times. The result of ten trials was 9SOFTWARE = 1.7%. Assuming these effects are independent, OcPIXEL is 6.5%. This result is useful for characterizing the display, unfortunately the amount of pixel luminance variation makes it difficult to quantify the difference between calibrated and uncalibrated driver circuits. The measurement precision needed to measure 8.5b driver circuits is less than 0.5%, which is much smaller than the variation due to other sources. In addition, a gradient was observed in the mean column luminances as shown in Figure 5.16, which may have been caused by focus error. Photometer For photometer measurements, the PCB with silicon backplane IC was rigidly attached to an X-Y micrometer stage. The X-Y stage was placed on top of a Z-stage. This combination allowed precise control of X-Y position and focusing. 107 5.2. OPTICAL MEASUREMENTS Mean Pixel Luminance vs. Column - i8889u ._d a0 xCa a) 0 5 10 15 20 25 column Figure 5.16: Column luminance The PhotoResearch PR-880 photometer was used with MS-lOx lens. When used with the 1/4 degree aperture, the measurement area is a 25,um diameter. The photometer is capable of measuring the luminance of a single pixel on the IC. The photometer with lens are mounted on a sturdy tripod with lens pointed downward at the IC. Light shields made of dark colored paper were used to reduce background illumination. To reduce vibration, the photometer was operated via RS-232 serial link to a computer. In a room with dim light, the light emission from silicon was visible through the viewfinder. This was encouraging to observe, and also aided in aiming the photometer. With the pixels off, background luminance was 1.04 * 10 - 3 (arbitrary units) with a standard deviation of 1.4 * 10 - 4 . With the full-intensity test pattern, measurements were around 1.3 * 10-2, so background uncertainty CrBACKGND= 1%. Measuring a single pixel repeatedly indicates same-pixel measurement variation is UMEAS = 2.4%. The variation between six illuminated pixels in a single column was aCOL = 6.9%. This suggests pixel luminance variation alone is 6.4%, which agrees with the result in the previous section. Summary Two sets of measurements using different equipment indicate that the standard deviation of pixel luminance variation for a constant drive current is 6%. The equipment used consisted of a CCD camera mounted on a precision microscope, and a PR-880 photometer. Measurement of ArrayDAC performance via optical measurements is difficult because the pixel variation is much larger than the 8-10b precision levels achieved by the electrical circuits. Although this variation level seems large, it is uncorrelated with position. Randomly CHAPTER 5. MEASURED RESULTS 108 distributed variation is smoothed by the eye as long as there are no low-frequency artifacts such as fixed pattern noise. We have shown that calibration improves the matching between column drivers to reduce fixed-pattern noise. Electrical measurements show this result clearly; optical measurements with larger sample sizes should also support this con- clusion. Pixel variation could be reduced with the addition of sensors and feedback circuitry. Photodetectors in each pixel would enable the use of analog feedback techniques [107], or digital correction techniques to reduce pixel variation. 5.3 Power Measurements Power is dominated by the current supplied to the pixels, where the maximum current with all pixels on is 360 * 100,uA = 36mA. This current flows to the VLOW supply at -11 volts, so total power is 400mW. Calibration of the RefDAC and ArrayDAC is much smaller; the RefDAC uses two reference currents: 85nA and 100A, and the ArrayDAC uses the RefDAC outputs totalling 102gA. 5.4 Sample Images A sample image consisting of a series of 7b grayscale ramps is shown in Figure 5.17. This is a long-exposure image of the silicon IC, taken with a sensitive CCD camera. It illustrates light emission from silicon. The banding and irregularity in this image are caused by postprocessing; the image from the camera was very smooth. For this test pattern, the row time was 100ps and frame rate was controller-limited at 22fps. The proof-of-concept system with the calibrated backplane IC is shown in Figure 5.18. The IC is mounted on a printed circuit board at bottom. A microscope objective is used to couple light from the IC to the input window of the image intensifier. The image intensifier is located on top of an optical tube. A zoomed-in portion of the ramp test image is visible in the image intensifier's output window. An alternative setup of the proof-of-concept system is shown in Figure 5.19. The microscope objective lens is replaced with a lens intended for video that provides lower magnification. This makes the entire display is visible in the intensifier output window. Hardware was machined from aluminum stock to position the lens and intensifier. The lens is a 1:1.4/25mm Schneider-Kreuznach Xenon in CS-mount. It is mounted on the bottom side of the aluminum bar with extension tubes. The intensifier is mounted on top of the bar, and the "ramps" test image can be seen in the output window. 5.4. SAMPLE IMAGES Figure 5.17: Silicon backplane IC emitting light, showing a series of ramps Figure 5.18: Proof-of-concept system with calibratedbackplane 109 110 CHAPTER 5. MEASURED RESULTS Figure 5.19: Proof-of-conceptsystem with calibratedbackplane and alternative optics Chapter 6 Discussion 6.1 Summary A microdisplay architecture using silicon light emitters and image intensification is designed and evaluated. A standard low-voltage CMOS IC incorporating display drivers and an array of avalanche diodes produces a faint optical image, and an image intensifier efficiently amplifies the image to useful brightness. This architecture has high efficiency and the potential to achieve high brightness suitable for micro-projection. Calculations indicate that a high-resolution monochrome micro-projector can achieve an efficiency of 7 lumens/watt. A proof-of-concept system with 16x32 pixel arrays is implemented and evaluated. A CMOS-based microdisplay backplane for use in conjunction with the above system is designed, implemented, and tested. The backplane is a standard CMOS die including pixels with avalanche diodes, and current-mode driver circuits. Current-mode driver circuits support a number of emissive display technologies including silicon light emitters and organic LED (OLED). The integrated display drivers employ a self-calibration technique to minimize variation while reducing circuit area. Area occupied by display driver circuits has been reduced a factor of five to seven compared to a conventional design. Calibration improves RefDAC precision from 8b to 11.5b, and ArrayDAC precision from 7b to 8.5b. ArrayDAC precision could be further improved by adjusting the sizes of charge injection cancellation devices. Circuit techniques to improve retention time in current copiers have been developed. Retention time of the RefDAC and ArrayDAC have been improved from a few milliseconds to 500ms and 60ms at room temperature, respectively. Variation in column driver (ArrayDAC) outputs, which produces fixed pattern noise, has been reduced by more than a factor of two. Pixel luminance variation is measured 111 CHAPTER6. DISCUSSION 112 ArrayDACs IN . 7 :9 0 REF< > Ref DAC Si i- i 11 V LOW OLED 01 v/K Figure 6.1: RefDAC, ArrayDAC, and pixel arrangement at 6.4%, which is comparable to other display technologies currently in use and could be reduced by the use of additional calibration or feedback techniques. 6.2 Topics for Future Investigation Improving Calibrated Precision The reason for the reduced precision of the ArrayDACs is an offset in the charge injection cancellation scheme as explained in Section 5.1.2. In a textbook example, the dummy device is exactly half the size of the passgate. When the passgate switches, exactly half of the channel charge and overlap capacitance couples to the storage node, and the dummy device cancels this coupling. In practice, size mismatches and differences in node impedances affect the distribution of charge. In both the RefDAC and ArrayDAC circuits, there is an imbalance between the passgate and dummy device sizes, resulting in uncancelled charge injection. This problem could be fixed by resizing the passgate and dummy device transistors for better cancellation. If re-sizing is not feasible, the voltage used to control charge cancellation devices could be adjusted. This would allow fine adjustment of the amount of charge injected by cancellation devices. The retention time measurements show that the NMOS current copiers used in the RefDAC have a much longer retention time than the PMOS current copiers in the ArrayDACs. The present arrangement of RefDAC, ArrayDAC, and pixels and the polarity of currents is shown in Figure 6.1. To improve calibration performance, the RefDAC should be implemented with PMOS devices and ArrayDACs with NMOS devices, as shown in Figure 6.2. The RefDAC only needs to maintain high precision for long enough to calibrate the ArrayDACs, or about 25ms. In contrast, the ArrayDAC retention time must be maximized 6.2. TOPICSFOR FUTUREINVESTIGATION 113 VHI VA RefDAC Si IIN i I OLED N ~REF<9 : 0 > ArrayDACs Figure 6.2: Alternative RefDAC, ArrayDAC, and pixel arrangement in order to minimize the amount of time spent in calibration which forces the array to be dark. Changing the circuits to reverse current polarities of the RefDAC and ArrayDACs is straightforward. An effect of this change is the common terminal of the light emitters is now the anode, and compatibility with OLED materials may be affected. Technology Choices Because of the dynamic nature of the MOS sample-and-hold structure, calibration must be done at frequent intervals. The use of non-volatile analog memory could greatly reduce the frequency of calibration [108]. The backplane could be calibrated infrequently, or only in response to predetermined events such as power-on reset or temperature changes. Dualgate CMOS technologies that accommodate floating-gate memory structures are available, and commercial applications are appearing [109]. The 360x200 CMOS backplane IC supports both silicon light emitters and organic LED technologies. This document has focused on the silicon light emitters. Manufacturing processes to deposit OLED materials on silicon ICs are becoming stable and available, and an OLED-on-silicon demonstration system can be assembled. This would demonstrate the versatility of the circuit techniques implemented on the backplane IC. The circuits described in this work may eventually be implemented with organic transistors, leading to a fully integrated display based on organic semiconductors [110]. The circuit techniques in this document can also be used in conjunction with field emitters integrated on a silicon substrate. A silicon IC with field emitters [111] could replace the photocathode in an image intensifier structure. It would directly emit electrons instead of converting junction currents to light on the IC, and light to electrons in the image intensifier. 114 CHAPTER 6. DISCUSSION Appendix A Precision Oscilloscope Measurements This section describes some of the issues involved in obtaining precise voltage measurements using an oscilloscope. Traditional oscilloscopes provide measurement precision adequate for a medium resolution display ( 8 bits), with good timing accuracy. Newer oscilloscopes with data memory and computational ability can perform data averaging to reduce noise and improve voltage accuracy. Probes and input circuitry designed for moderate precision can be a limiting factor in this type of system. First, four high-impedance passive probes were tested on the same input channel of a Hewlett-Packard 54532A oscilloscope which had not been calibrated in a number of years. The response to an 0.8v, ms square pulse is shown in Figure A. 1. Three HP 10441A probes produced similar results, and a probe from another manufacturer is clearly not matched to the input characteristics of the oscilloscope. Removing the worst of the group, the step responses of the remaining three probes is shown in Figure A.2, zoomed in show high precision. An unusual transient behavior with long settling time is seen. The four input channels were sequentially connected to the same signal source and probe. Figure A.3 shows the variation in the responses between different channels. Channel two appears to have the fastest settling time of the four. Expanding the pulse width and time base reveal that the performance is actually worse, as seen in Figure A.4. The settling time is on the order of 2-3ms, and the previous waveforms were far from their final values. Tuning the passive probe, or using a BNC cable connected to oscilloscope input did not significantly improve the long settling time. Calibration was needed, however measurements were needed in a short amount of time. As a temporary solution a newer, recently calibrated oscilloscope was borrowed. The newer scope was an Agilent 54832D mixedsignal oscilloscope. Used with the same passive probes as before, the step response had a faster settling time as shown in Figure A.5. Measurement performance was greatly improved compared to the previous oscilloscope, and this setup was used for most measurements presented in this document. Settling time for a large voltage step is a few hundred microseconds for 10b (0.1%) precision. Critical measurements were performed at appropriate speeds for high measurement accuracy. To summarize, both the oscilloscope and probes need to be calibrated periodically to produce precision results. Long transient responses can result when equipment is mismatched out of calibration. 115 APPENDIXA. PRECISIONOSCILLOSCOPEMEASUREMENTS 116 probe1 .m hp54542a cal-out,probe overshoot CH1 19 aug 04 achen 0. 0. o C 0 o-0. -a -0. _n -v. vu 0 0.2 0.4 0.6 Time milliseconds 0.8 1 FigureA.1: Step responses offour oscilloscope probes probe1 .m hp54542a cal-out,probe ^ ^^^ -O.UUY settling CH1 19 aug 04 achen -0.01 o -0.011 o ( -0.012 c -0.013 0 a- _-0.01 4 a, no-0.015 -0.016 -_n n 7 -v.v,,0 0 0.2 0.4 0.6 Time milliseconds 0.8 Figure A.2: Probe settling behavior 1 117 channels.m hp54542a cal. signal 19 aug 04 achen -u.u.C 0 0.2 0.4 0.6 0.8 1 time milliseconds Figure A.3: Four oscilloscope channels, same input mlong1.m pulsegen to bnc to scope 19 aug 04 achen 1.93 1.925 1.92 1.915 , 1.91 c ° 1.905 -. 1.9 1.895 1.89 1.885 0 1 2 3 4 time milliseconds Figure A.4: Longer observation time 5 6 APPENDIXA. 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