RF Power CMOS
by
Jorg Scholvin
Submitted to the Department of Electrical Engineering and Computer Science
in Partial Fulfillment of the Requirements for the Degrees of
Bachelor of Science in Electrical Science and Engineering
and
Master of Engineering in Electrical Engineering and
Computer Science
at the
BARKER
Massachusetts Institute of Technology
May 23, 2001
r-7-
MASSACHUSETTS INSTITUTE
OF TECHNOLOGY
JU L 11 2001
Copyright 2001 Jorg Scholvin. All rights reserved.
LIBRARIES
The author hereby grants to M.I.T. permission to reproduce and distribute publicly paper
and electronic copies of this thesis and to grant others the right to do so.
Author
Depahient df Electrical Engineering and Computer Science
May 23, 2001
Certified by
Jesus A. del Alamo
Professor of Electrical Engineering
>Thesis Supervisor
Accepted by
Arthur C. Smith
Chairman, Department Committee on Graduate Theses
2
RF Power CMOS
by
Jorg Scholvin
Submitted to the
Department of Electrical Engineering and Computer Science
May 23, 2001
In Partial Fulfillment of the Requirements for the Degree of
Bachelor of Science in Electrical Science and Engineering
and Master of Engineering in Electrical Engineering and Computer Science
ABSTRACT
In the mobile wireless industry, system size and cost are important factors for having a
competitive product. Because of this, in the future system-on-chip (SOC) solutions are
likely to emerge. For wireless communications products, this means that the power
amplifier (PA) needs to be integrated with the rest of the analog and digital circuitry. This
thesis has experimentally studied the suitability of a commercial 0.25 gm logic CMOS
device technology for RF power applications. In particular, the suitability of the standard
BSim3v3 device model for accurately capturing RF power behavior has been evaluated.
Our study includes DC, small-signal RF, and large-signal RF characteristics. It was found
that there are severe discrepancies between the BSim3v3 model and the measured results.
A new model was constructed by adding a passive circuit topology that accounts for
device parasitics not captured by the BSim3v3 model. The newly developed circuit
model has been shown to accurately predict the device's RF power behavior. The
physical origins of the new circuit elements and their dependencies on device layout have
been identified.
Thesis Supervisor: Jesu's A. del Alamo
Title: Professor of Electrical Engineering
3
4
Acknowledgements
My sincere thanks go to Professor Jesus del Alamo for his ideas, guidance, and support
that has allowed me to complete this work. I also want to thank him for the opportunity to
do undergraduate research work in his group that raised my interest in research and the
field of semiconductor modeling. Also, I want to thank everyone in the del Alamo
research group for their support: Jim Fiorenza, Samuel Mertens, Niamh Waldron, and
Joyce Wu. Also, I want to thank Don Hitko for helping numerous times over the past two
years with problems of the network analyzer setup.
I would like to thank our sponsor Global Communication Devices (GCD), and Geoff
Dawe for supporting this work and making it possible to have the devices fabricated at
TSMC. I also want to thank Ethan Dawe at GCD for doing the device layouts.
I would like to thank Ali Boudiaf and ATN-Microwave, for making it possible to use
their load-pull system.
I want to thank Agilent Technologies for generously donating the software, ADS, without
which this work would not have been possible.
Finally, I'd like to thank my parents for their support and initiative that led me to where I
am now.
5
6
Contents
List of Figures
11
List of Tables
17
Chapter 1
19
Introduction
19
1.1
1.2
1.3
Motivation
Previous Modeling Work on RF-CMOS
Thesis Goals and Outline
19
20
21
Chapter 2
23
Measurement Setups
23
2.1
Device Design and Layout
23
2.2
DC Measurement Setup
27
2.3
S-Parameter Setup
31
2.4
Large Signal Characterization
34
2.5
Intermodulation Distortion (IM 3)
36
2.6
De-Embedding
40
2.7
Summary
41
Chapter 3
43
Simulation Setups
43
3.1
DC Verification
43
3.2
S-Parameter Simulations
48
3.3
Power-Sweep
50
3.4
IM 3 Simulations
52
7
3.5
Summary
54
Chapter 4
55
Results: Comparison of Measurements and Simulations
55
4.1
Intrinsic BSim Model
55
4.2
Modifying the BSim Model
62
4.2.1
Output Resistance
62
4.2.2 Gate Resistance
63
4.2.3
64
Gate, Source, and Drain Inductances
4.2.4 Body Resistance
65
4.2.5 Gate-to-Drain Capacitance
66
4.2.6 Small Signal Comparison of the Complete Model
67
4.3 Large Signal Comparison of Complete Model
69
4.4
72
Summary
Chapter 5
73
Relation of New Model Parameters to Device Design
73
8
5.1
Output Resistance, Rout
73
5.2
Gate Resistance, Rg
75
5.3
Body Resistance, Rb
78
5.4
Inductances
80
5.4.1
Gate Inductance, Lg
84
5.4.2
Drain Inductance, Ld
85
5.4.3
Source Inductance, L,
86
5.5
Gate-to-Drain Capacitance, Cgd
87
5.6
Summary
89
Chapter 6
91
Conclusions
91
6.1
Conclusions
91
6.2
Suggested Future Work
92
Appendix A
95
References
103
9
10
List of Figures
Fig. 2.1-1 Device design space. The lines connecting points indicate constant total widths
25
of 10, 20, 40, 80, 160, 320, 640, and 1280 prm.
Fig. 2.1-2 Device layout for the 16x20 gm device. Left: pads (blue) and metal4 lines
(green) to the device. Right: Device itself, showing the metal4 lines (green), metal2 (red
area), metall (blue) and contact holes (white squares). The gates, which are not shown,
26
run between the metall fingers.
Fig. 2.1-3 Vertical cross-section of the device and metal layers, for the source or drain
path. The gate would be routed on the metal2 level rather than the metal 1, and then
26
brought down to the poly silicon with vias.
Fig. 2.2-1 DC Measurement Setup. The Bias-T has the purpose to avoid oscillations.
28
Fig. 2.2-2 Output Characteristics of the 16x10 pm device, with Vgs from 0 to 2.4 V in 0.2
28
V steps.
Fig. 2.2-3 Output Conductance for the 16x10 gm device, with Vgs from 0 to 2.4 V in 0.2
29
V steps.
Fig. 2.2-4 Transfer Characteristics of the 16x10 gm device, with Vds from 0 to 2.4 V in
29
0.2 V steps.
Fig. 2.2-5 Transfer Characteristics of the 16x10 gm device, with Vd, from 0 to 2.4 V in
30
0.2 V steps.
Fig. 2.2-6 Subthreshold Characteristics of the 16x10 gm device, with Vds from 0 to 2.4 V
30
in 0.2 V steps.
Fig. 2.3-1 S-Parameter Measurement Setup
32
Fig. 2.3-2 Measured S-parameters for the de-embedded 16x20 gm device biased at
32
Vds=2V, Vgs=1.4V
Fig. 2.3-3 Measured Y-parameters for the de-embedded 16x20 grm device biased at
33
Vds=2V, Vgs=1.4V
Fig. 2.3-4 Measured h211 and Gt for the de-embedded 16x20 pm device biased at
33
VdS=2V, Vgs=1.4V
Fig. 2.4-1 Power-sweep measurements for the 08x20 gm device biased at VdS=2 V,
35
Vgs=1. 4 V
11
Fig. 2.4.1-1 Intermodulation and fundamental output power as a function of the input
power
35
Fig. 2.4.1-2 Output frequency spectrum
37
Fig. 2.4.1-3 IM 3 measurement versus total available power, for the 32x20 gm device
biased at VdS=2 V, Vgs=1.4 V. The left graph shows IM 3 (bottom) and the total output
power (top), both in units of dBm, similar to the sketch of Fig. 2.4.1-1. The right graph
shows 4IM
3 in units of dBc. One can see that the difference of IM 3 [dBm] and P0 ,t [dBm]
amounts to the IM 3 [dBc], with a slope of two.
39
Fig. 2.5-1 Simple model of the device including the pad parasitics
40
Fig. 2.5-2 Y-Parameter measurements, illustrating the impact of the de-embedding. Each
graph shows the pad, the device + pad, and the de-embedded measurement (see legend
below)
42
Fig. 3.1-1: DC Simulation Setup for output, transfer, subthreshold characteristics and gm
and gd.
44
Fig. 3.1-2 Simulated output characteristics of the 08x20 pm device, with Vgs from 0 to
2.4 V in 0.2 V steps
45
Fig. 3.1-3 Simulated output conductance of the 08x20 gm device, with Vgs from 0 to 2.4
V in 0.2 V steps
45
Fig. 3.1-4 Simulated transfer characteristics of the 08x20 pm device, with Vds from 0 to
2.4 V in 0.2 V steps
46
Fig. 3.1-5 Simulated transconductance of the 08x20 pm device, with Vds from 0 to 2.4 V
in 0.2 V steps
46
Fig. 3.1-6 Simulated Subthreshold characteristics of the 08x20 gm device, with VdS from
0 to 2.4 V in 0.2 V steps
47
Fig. 3.2-1 S-Parameter simulation setup
47
Fig. 3.2-2 Simulated S-parameters for the 16x20 gm device biased at Vds=2 V, Vgs=1.4 V
49
Fig. 3.2-3 Simulated Y-parameters for the 16x20 pm device biased at Vd,=2 V, Vgs=1.4 V
49
Fig. 3.2-4 Simulated h211 and Gtu for the 16x20 pm device biased at Vds=2 V, Vgs=1. 4 V
49
12
51
Fig. 3.3-1 Power-Sweep simulation setup
Fig. 3.3-2 Power-sweep simulations using the BSim3 model only, for the 08x20 pm
51
device biased at VdS=2 V, Vgs=1.4 V
Fig. 3.3-3 Simulated Gain vs. Pin for the 08x20 pm device using the modified model, at
Vgs=1.4 V, Vds=2 V. Shown for three different values of probe resistance. The difference
52
in gain between highest and lowest probe resistance is about 0.5 dB
53
Fig. 3.4-1 IM 3 Simulation setup
Fig. 3.4-2 IM 3 Simulation versus total available power, for the 08x20 Rm device biased at
Vds= 2 V, Vgs=1. 4 V. The left graph shows IM 3 (bottom) and the output power (top) both
54
in units of dBm. The right graph shows IM3 in units of dBc
Fig. 4.1-1 Output Characteristics of the 16x10 pm device, with Vgs from 0 to 2.4 V in 0.4
56
V steps
Fig. 4.1-2 Output Conductance for the 16x10 pm device, with Vgs from 0 to 2.4 V in 0.4
56
V steps. Left: linear scale, right: semi-log scale
Fig. 4.1-3 Transfer Characteristics of the 16x10 Rm device, with
0.4 V steps
Fig. 4.1-4 Transconductance of the 16x10 ptm device, with
steps
Vd,
Vds
from 0 to 2.4 V in
57
from 0 to 2.4 V in 0.4 V
57
Fig. 4.1-5 Subthreshold characteristics of the 16x10 pm device, with Vd, from 0 to 2.4 V
in 0.6 V steps. The lowest measurement line is for Vds=0 V, the simulations yield 0 A
58
current here, so they are not shown
Fig. 4.1-6 S-Parameters for the 16x20 pm device using the TSMC BSim3v3 model,
59
biased at Vgs=1. 4 V, VdS=2 V
Fig. 4.1-7 Y-Parameters for the 16x20 pLm device using the TSMC BSim3v3 model,
60
biased at Vgs=1. 4 V, Vd,=2 V
Fig. 4.1-8 Figures of merit 1h
211 and Gtu for the 16x20 jm device using the TSMC
60
BSim3v3 model, biased at Vgs=1. 4 V, Vds=2 V
Fig 4.1-9 Power sweep simulations for the 16x20 Rm device using the TSMC BSim3v3
61
model, at Vgs= 1 .4 V, Vd,=2 V
Fig. 4.1-10 IM 3 simulations for the 16x20 jm device using the TSMC BSim3v3 model,
61
at Vgs=1. 4 V, Vds=2 V. Left: Pout (top) and IM 3 [dBm]. Right: IM 3 [dBc]
13
Fig. 4.2.1-1 Y22 before (left) and after (right) adding the output resistance Rout
63
Fig. 4.2.2-1 Y21 before (left) and after (right) adding the gate resistance Rg
63
Fig. 4.2.3-1 Y2 1 before (left) and after (right) adding the inductances in the gate, source
and drain
64
Fig. 4.2.4-1 Y22 before (left) and after (right) adding the body resistance Rb
65
Fig. 4.2.4-2 Simplified small-signal model illustrating the effect of the body resistance,
Rb. Without Rb, there is only a capacitor between the drain and source. With Rb in place,
there now is an RC network between the two ports, giving rise to the observed changes in
66
Y22
Fig. 4.2.5-1 S12 before (left) and after (right) adding the gate to drain capacitance Cgadext
66
Fig. 4.2.6-1 Modified BSim3v3 model topology to take RF effects into account
67
Fig. 4.2.6-2 S-Parameters for the 16x20 gm device using the modified model, biased at
Vgs= 1.4 V, Vd,=2 V
68
Fig. 4.2.6-3 Y-Parameters for the 16x20 gm device using the modified model, biased at
Vgs=1.4 V, Vds=2 V
68
Fig. 4.2.6-4 Figures of merit jh21I and Gtu for the 16x20 gm device using the TSMC
BSim3v3 model, biased at Vgs=1.4 V, Vds=2 V
69
Fig. 4.3-2 Power sweep simulations and measurements for the 16x20 gm device using the
modified model, at Vgs=1. 4 V, Vd=2 V
71
Fig. 4.3-3 IM3 simulations and measurements for the 16x20 gm device using the
modified model, at Vgs=1. 4 V, Vds=2 V. Left: Pout (top) and IM 3 [dBm]. Right: IM 3 [dBc]
71
Fig. 5.1-1 Rout as a function of unit width (left) and number of fingers (right).
74
Fig. 5.1-2 R..t as a function of total device width
74
Fig. 5.1-3 Output characteristic around the DC bias point for the output resistance
measurement under RF and DC conditions
75
Fig. 5.2-1 Rg as a function of unit width (left) and number of fingers (right)
76
Fig. 5.2-2 Rg as a function of the ratio of unit finger width and number of fingers. The
line is drawn at unity slope
77
14
Fig. 5.3-1 Rb as a function of unit width (left) and number of fingers (right)
77
Fig. 5.3-2 Device layout for the 16x10 gm device. Shown are the p- and n-implants, the
poly-silicon gate (red lines), and contact holes (white squares) from the metall layer. The
body contacts are shown in blue
79
Fig. 5.3-3 (left) Body resistance as a function of the inverse body-contact perimeter,
(right) Body resistance - perimeter product, illustrating the inverse proportionality of Rb
and the body perimeter
79
Fig. 5.4-1 Device layout for the 16x10 pm device. Shown are the metal layers (blue:
meatli, red: metal2, green: metal4) and the metal] to device contact holes. Left:
Complete picture, including probe-pads, right: close-up on the device. The gate is coming
in from the middle left pad, the drain from the middle right pad. The four top and bottom
82
pads are the source, coming in to the device from the top and bottom.
Fig. 5.4-2 The sum of the inductances as a function of unit finger with and the inverse of
82
the number of fingers. The sum is roughly independent of the layout.
Fig. 5.4-3 S- and Y-parameters for different values of L, and Ld, while keeping L,+Ld
constant. The device is the 16x20 gm biased at Vgs=1. 4 V, Vds=2.0 V. The values are
83
L=22 pH + AL, Ld=IOOpH - AL with AL of range ± 10 pH.
Fig. 5.4.1-1 Lg as a function of unit width (left) and number of fingers (right)
83
Fig. 5.4.1-2 Layout sketch of the gate structure. The periodic structure of 2 gate fingers is
84
indicated by the lines
Fig. 5.4.2-1 Ld as a function of unit width (left) and number of fingers (right). Also
85
shown is the difference between Ld and Lg
Fig. 5.4.3-1 L as a function of unit width (left) and number of fingers (right)
86
Fig. 5.4.3-2 Simplified sketch of the source inductances. As more fingers are added, the
overall inductance decreases because inductors are added into the source metal line in
87
parallel.
Fig. 5.5-1 Cgd as a function of unit width (left) and number of fingers (right)
88
Fig. 5.5-2 Cgd as a function of total device width
89
Fig. 5.5-3 Y1 for the 16x05 pm (left) and 128x05 pm (right) device, for different values
of Cgd between 10 and 55 fF. The relative impact of Cgd on the 128x05 gm device is very
small, explaining why for wide devices, Cgd does not follow the observed line in Fig.
89
5.5-2.
15
Fig. A-I Parameter sweep of R..t for the 16x20 gm device model biased at Vgs=1. 4 V,
95
Vds=2.0 V
Fig. A-2 Parameter sweep of Rg for the 16x20 gm device model biased at Vgs=1.4 V,
96
Vds=2.0 V
Fig. A-3 Parameter sweep of Rb for the 16x20 gm device model biased at Vgs=1. 4 V,
97
Vds=2.0 V
Fig. A-4 Parameter sweep of Lg for the 16x20 gm device model biased at Vgs=1. 4 V,
98
Vds=2.0 V
Fig. A-5 Parameter sweep of Ld for the 16x20 pm device model biased at Vgs=1.4 V,
99
Vds=2.0 V
Fig. A-6 Parameter sweep of Ls for the 16x20 gm device model biased at Vgs=1. 4 V,
100
Vds=2.0 V
Fig. A-7 Parameter sweep of Cgd for the 16x20 pm device model biased at Vgs=1. 4 V,
101
Vd,=2.0 V
16
List of Tables
Table 1.1 PA performance figures for various CMOS technologies. The amplifiers are
multistage, typically 2-stage, amplifiers. For comparison, three non-Silicon PA have been
included. The figures are the ones reported in the papers, and do not mention the
compression point at which the data was read off. Therefore direct comparison is
17
difficult, yet the numbers give a sense of the orders of magnitude in PAs.
Table 1.2. Device performance at the 1dB compression point of the device reported in [4]
18
17
18
Chapter 1
Introduction
1.1 Motivation
The focus of this thesis is on the modeling and understanding of standard CMOS devices
for RF power applications. In a wireless system, the power amplifier (PA) is a crucial
component, and being able to implement it together with digital and RF analog circuitry
would allow to have a system-on-chip (SOC) solution, which will result in improved cost
efficiency, and overall smaller system size.
There has been some recent work on RF power amplifiers using logic CMOS
technologies. Table 1.1 summarizes the performance of these amplifiers [1-3].
Technology
0.24 m CMOS
0.35 gm CMOS
0.35 gm CMOS
0.35 gm CMOS
0.8 gm CMOS
0.8 pm CMOS
0.8 m CMOS
Bipolar
GaAs
GaAs (PHEMT)
Frequency Supply
[GHz]
Voltage
2.4
2.5
2.5
1.9
2
2
1.9
2
1.9
3
2.5
0.8
1.9
3
2
3.3
3.4
1.9
3.6
1.9
Pou
[dBm]
18
22
30
30
20
30
24
27
22.5
31
Gain
[dB]
11
20
20
not reported
13
25
17
35
29
30
PAE
[%]
24
44
48
41
16
42
32
35
29
45
Reference
[1]
[2]
[2]
[1]
[1]
[3]
[1]
[2]
[2]
[2]
Table 1.1 PA performance figures for various CMOS technologies. The amplifiers are
multistage, typically 2-stage, amplifiers. For comparison, three non-Silicon PA have
been included. The figures are the ones reported in the papers, and do not mention the
compression point at which the data was read off. Therefore direct comparison is
difficult, yet the numbers give a sense of the orders of magnitude in PAs.
19
For evaluating device performance, we have to look at only the device itself. Table 1.2
lists the published performance figures for a commercial device [4].
Technology
0.24 pm CMOS
Frequency
[GHz]
2.4
Pou
[dBm]
19
Gain
[dB]
11.2
PAE
[%]
26
Table 1.2. Device performance at the ldB compression point of the device reported in
[4]
There are several interesting questions as one considers the suitability of logic CMOS for
RF power applications:
-
How far can logic CMOS technology go in delivering the RF power amplifier
(PA) function?
-
How does this picture change as CMOS continues to be scaled down?
-
What can be done to logic CMOS device and process design to improve its RF
PA capabilities? How can the device layout be optimized for the PA function?
-
How well can device model developed for logic capture RF power behavior?
How can we improve these models?
In this work, we will try to answer the questions in the last item, modeling of RF-CMOS
devices. Improved and accurate models will help allow better designs of RF CMOS PAs.
1.2 Previous Modeling Work on RF-CMOS
RF-CMOS modeling is a relatively new field. The BSIM3v3 model has been shown to
give good results for RF simulations when extended by a gate resistance [5] and a
substrate network [4]. The need for these additions and an overview of some different
20
substrate network topologies has been described in [4], discussing their suitability to
match the RF power measurements. However, neither of the two papers [4,5] discusses
linearity for their modified BSim3v3 model. With the modulation schemes for digital
wireless applications depending on a linear PA, the linearity figures of merit (IM 3 in this
work) become increasingly important.
The small-signal RF accuracy of the BSim3v3 model and the addition of model elements
to match S-parameter measurements has been more thoroughly studied, than the largesignal RF-CMOS models mentioned before [6,7]. From these publications, we can see
that the gate resistance (being the most important element to add) occurs in all of the
proposed models. However, there is a fairly large discrepancy on the other parameters, in
particular the substrate network. Different models all claiming an accurate fit can be seen
in [4-10].
1.3 Thesis Goals and Outline
The goal of this thesis is to show that an accurate RF device model can be built from the
BSim3v3 model, and that it will be able to predict the results of DC, S-parameter and
load-pull measurements. We will derive such a model by adding new circuit elements to
the BSIM3v3 model, which itself will not be changed. Also, an explanation for the new
model elements in terms of the layout of the device will be given.
21
Here is how this thesis is organized. Chapter two will first describe the devices, the
measurements that have been carried out, and shows typical measurement data. The
measurements consist of DC, S-parameter, and load-pull (POt, Gain, LI, PAE and IM 3)
measurements. Chapter three will describe the simulation setups for the measurements of
chapter two, and show typical simulation results obtained from TSMC's BSim3v3 device
model. Having thus established the measurement and simulation setups, chapter four will
compare the measurements with the BSim3v3 model. Finding that the model is not
accurate enough, new elements will be added to create a device model that can accurately
predict the S-parameter and load-pull measurements. The model is build step-by-step,
with the goal to match the S-parameter measurements up to 20 GHz. The model element
values are obtained without taking the load-pull data into account. At the end, a
comparison of the new model with S-parameter and load-pull measurements is done to
prove the model's accuracy in predicting the load-pull measurements. Having now an
accurate model at hand, chapter five analyzes the new model elements and connects them
with the device layout. This is done by looking into how the element values change as the
device is scaled either in the unit finger width or in the number of fingers dimension. The
work concludes with chapter six, presenting our conclusions and suggestions for future
work.
22
Chapter 2
Measurement Setups
This chapter describes the devices and the measurement setup used in this thesis, and
shows
typical
measurement
results.
The
measurements
performed
are
DC-
characterizations, S-parameter measurements, and large signal measurements of Po
0 t,
Gain, IL, PAE, and IN4 3 as a function of Pin. We also show how the non-linearities of the
device mathematically give rise to the intermodulation distortion (IM 3).
2.1 Device Design and Layout
The devices used in this thesis are fabricated in the digital 0.25 Rm CMOS process of
TSMC. Parameters available in the device design are the dimensions of the device
(number of fingers, unit finger width), and the layout style of the device. This gives us
three dimensions along which to explore device behavior. The layout style involves the
routing of source, drain and gate interconnects and is important for the parasitics, but not
the device behavior as such. Thus, we decided to reduce to two dimensions, namely the
number of fingers and unit finger width. This space is explored in detail around a center
design point. This allows a reasonable investigation of both dimensions, while keeping
the number of test devices within reasonable bounds.
In the equations in this thesis, we will use the following symbols for the number of
fingers, unit finger width and total width:
23
Wg
=
total gate width
Wg
=
unit finger width
nf
=
number of fingers
where Wg = nf x wg
Fig. 2.1-1 shows the design space of the devices used. The center device was chosen to
be 16 fingers, 20 Rm unit finger width (16x20 [tm). From here, we can explore in three
directions, holding one parameter constant at a time: the horizontal shows varying
number of fingers, while the unit finger width stays fixed. In the vertical, the number of
fingers stays constant, and the unit width changes. Furthermore, one can move along lines
of constant total width trading off number of fingers and unit finger width. All variations
of parameters occur in factors of two. The device layout for the 16x20 jim device is
shown in Fig. 2.1-2. A schematic of the vertical cross-section showing the metal layers
can be found in Fig. 2.1-3.
In addition to the devices, de-embedding structures are necessary to remove the impact of
the pads and metal lines on RF measurements. These are identical to the device layouts,
except that they have the device contacts removed so only the pad and interconnect
parasitics are measured.
24
rn
I I I I I ' ll
I I II
I I I I.
45 -
40
35
30
F-l.
E)
25
20
15
10
5
nL
100
101
102
number of fingers
Fig. 2.1-1 Device design space. The lines connecting points indicate constant total
widths of 10, 20, 40, 80, 160, 320, 640, and 1280 gm.
25
Fig. 2.1-2 Device layout for the 16x20 gm device. Left: pads (blue) and metal4 lines
(green) to the device. Right: Device itself, showing the metal4 lines (green), metal2 (red
area), metall (blue) and contact holes (white squares). The gates, which are not shown,
run between the metall fingers.
_ _ _ _ _ Al pad
metal4
to
vias
metal 1
device
/0
device layer
poly gates
Fig. 2.1-3 Vertical cross-section of the device and metal layers, for the source or drain
path. The gate would be routed on the metal2 level rather than the metall, and then
brought down to the poly silicon with vias.
26
2.2 DC Measurement Setup
The devices are characterized using a HP 4155 Semiconductor Parameter Analyzer, on a
Cascade
Wafer
Probe Station. The measurements
are performed on die. All
measurements are performed around 23'C. The HP 4155 is connected to a HP 41501B
High Current unit, to allow biasing currents up to 1 A. The setup is shown in Fig. 2.2-1.
The line between the device and the measurement equipment contains a bias T, which
separates the RF and DC components. The RF component is connected to a 10 dB
attenuator, which is necessary to prevent the DC measurement from suffering from
oscillations caused by RF noise.
A typical DC measurement result is shown in Figs. 2.2-2 to 2.2-6, including the output
characteristics, output conductance (gd), transfer characteristics, transconductance (gm),
and subthreshold characteristics for the 16x10 pm device. In the output characteristics,
the drain-source voltage is swept for a set of given gate voltages (Fig. 2.2-2). Taking the
derivative, we obtain the output conductance,
gd (Fig. 2.2-3).
In the transfer
characteristics we sweep the gate voltage, maintaining a constant drain-source voltage
(Fig. 2.2-4). The derivative obtained here is the transconductance, gm (Fig. 2.2-5). If we
plot the transfer characteristics on a semi-log scale, we get the subthreshold
characteristics, which allows looking closely at device behavior below the threshold (Fig.
2.2-6). Also, it allows for a good assessment of the drain induced barrier lowering
(DIBL).
27
U
-
LE
-=
-~
DC
IRF
Open
Fig. 2.2-1 DC Measurement Setup. The Bias-T has the purpose to avoid oscillations.
600
500-
400-
300-
200-
100-
0V
0.0
0.5
1.5
1.0
2.0
2.5
Vds [V]
Fig. 2.2-2 Output Characteristics of the 16x10 gm device, with Vgs from 0 to 2.4 V in
0.2 V steps.
28
1000
900 800 700 600 c>
500 -
01
400 300 200 100 0.0
0.5
1.5
1.0
2.0
2.5
Vds [V]
Fig. 2.2-3 Output Conductance for the 16x10 pm device, with Vgs from 0 to 2.4 V in 0.2
V steps.
600
500
-
400
-
300 -
200
-
100
-
00.0
0.5
1.5
1.0
2.0
2.5
Vgs [V]
Fig. 2.2-4 Transfer Characteristics of the 16x10 J.m device, with VdS from 0 to 2.4 V in
0.2 V steps.
29
350
300250E 200E 150CM
10050-
0
0.0
---wwwwwo
,
0.5
1.0
1.5
2.0
2.5
Vgs [V]
Fig. 2.2-5 Transfer Characteristics of the 16x10 gm device, with Vds from 0 to 2.4 V in
0.2 V steps.
1E2
1E1
-
11E-1 E
11E-2-
1E-3 1E-41 E-5 1E-6
I
0.00
0.25
0.50
0.75
1.00
Vgs [V]
Fig. 2.2-6 Subthreshold Characteristics of the 16x10 gm device, with VdS from 0 to 2.4
V in 0.2 V steps.
30
2.3 S-Parameter Setup
Fig. 2.3-1 shows the S-Parameter measurement setup. An Agilent 8510C network
analyzer is used to perform the measurement, with the HP 4155/HP 41501B connected to
it to supply the DC biasing through a bias-T inside the network analyzer. The network
analyzer is capable of measuring up to frequencies of 50 GHz.
A typical S-parameter measurement from 500 MHz to 20 GHz is shown in Fig. 2.3-2, for
the 16x20 gm device after de-embedding. The device is biased at Vgs=1. 4 V,
Vds=2.0
V.
De-embedding is important to remove the parasitic effects of the probe-pads from the
measurement, which would otherwise mask the device behavior. Our de-embedding
structures are identical to the devices, except that the contact layer to the device itself has
been removed. Measurements of the device and the de-embedding structure are then
taken. Assuming a primary parallel nature of the pad parasitics (capacitance dominates)
the device can be de-embedded by subtracting the de-embedding structure's Yparameters from the device Y-parameters [11]. The result is a S-parameter measurement
of the device, without the impact of the pad-parasitics. The Y-parameters after deembedding are shown in Fig. 2.3-3. Fig. 2.3-4 shows the short circuit current gain (1hn)
and the unilateral gain (gtu), both of which are important figures of merits for device and
circuit designers. The de-embedding process will be described in more detail in section
2.5.
31
~1~
I
Fig. 2.3-1 S-Parameter Measurement Setup
S12
Sll and S22
W.416w 00.50
S21
K'>
10 01,05 0MO 0.,15
1 12
freq (500.0MHz to 20.00GHz)
freq (500.0MHz to 20.00GHz)
freq (500.0MHz to 20.00GHz)
Fig. 2.3-2 Measured S-parameters for the de-embedded 16x20 gm device biased at
Vds=2V, Vgs=1.4V
32
Y1 2
Y11
Y11
Y12
1E-1
1
,O
1E-2-
1E-1-
1E-3-
1E-2m
1E-4-
1E-3-
1E-5-
1 E-4-I=
1E-6-
A
m
C0
m
m
0
0
1E6
-)(-
freq, Hz
-- -
uag (Y)
Y22
Y21
-
1E102E10
freq, Hz
Real {Y)
2E-1
2E-1
1E-1-
1 E-1
1 E-2
1E-2-
5E-2
1 E-1
1 E-21E-3-
Cn
0
c 1E-3-
00)
1E-2
1 E-44 = r
1 E-3
lElO 2E10
1E9
m
mi
w0
C0
freq, Hz
K)
m
0
freq, Hz
Fig. 2.3-3 Measured Y-parameters for the de-embedded 16x20 pm device biased at
VdS=2V, Vgs=1. 4 V
1h21 I
Gtu
40
20
30-
15-
V
V
2010-
10'
5:
S-
0'
m
m
o-
(0
freq, Hz
m
0J
m
(D
m
m
o)
0
freq, Hz
Fig. 2.3-4 Measured h211 and Gtu for the de-embedded 16x20 gm device biased at
VdS=2V, Vgs=1. 4 V
33
2.4. Large Signal Characterization
Large signal characterization was performed on selected devices at 2.45 GHz. This
included power-sweeps, IM3 measurements, and load-pull contour measurements.
Measurements were done on a Load-Pull System at ATN Microwave Inc. The
measurement allows determining the device behavior as a function of the input power,
and source- and load-impedance.
In the power-sweep measurement, the available input power (which we will refer to
simply as input power) is swept, while the source and load impedances are held constant.
From this measurement the 1 dB compression point can be determined. A load-pull (or
source-pull) measurement is then performed at the 1 dB compression point, varying the
load (or source) impedance over a specified area of the Smith chart, while holding the
input power constant. This helps to find a more optimal impedance. Generally, the
power-sweep and load/source pull sequence is repeated until a stable optimum is reached.
For modeling purposes, it is not necessary to run this cycle too many times. While it is
important that the measurements are done in a region close to the optimum, finding the
optimum itself is not essential. In our case, the sequence was a power sweep, followed by
a load-pull at the 1 dB point, followed again by a power sweep at the load impedance that
was giving the maximum output power. All power-sweep data used in this work is data
from this stage. The optimized impedances are recorded and are later used in the
simulations.
34
A typical result of a power sweep is shown in Fig. 2.4-1. For low power levels, the output
power as a function of available input power has a slope of one,. As the input power
increases the device eventually goes into compression and the slope flattens. The
difference between input and output power is the gain, which starts to drop as the device
goes into compression. The supply current equals to the DC current until the device
enters compression. As the power is increased, the power added efficiency (PAE) goes
up, because more power is delivered to the load for the same DC power dissipation.
However, as the device enters compression, the efficiency will eventually decrease again,
because the gain decreases due to compression. This cannot be seen in Fig. 2.4-4, because
the device was not measured too far into compression.
15
10500
-513L
-10
-1
-30
E
V
M
C
-25
-20 -15
Pin [dBm]
-10
-5
19.5
19.018.518.017.517.016.5- ,-I
-30 -25
0.0365 .
20
0.03607-
15
0.0355-
0-
-30
-10
-5
_1
-
105
0.0350 0.0345
r
-20
-15
Pin [dBm]
. .
. .. i
-25
. .i.
-15
-20
Pin [dBm]
. 1 . .
-10
-5
1~
-30
-25
-20 -15
Pin [dBm]
-10
.5
Fig. 2.4-1 Power-sweep measurements for the 08x20 pm device biased at VdS=2 V,
Vgs=1.
4
V
35
2.4.1. Intermodulation Distortion (IM 3)
In digital wireless communication systems, linear modulation methods (QAM, PAM,
PSK) require good linearity of the power amplifier. A typical measure for linearity is the
intermodulation distortion, IM 3 . The measurement principle and definition of IM 3 is
explained in [12-14]. It evaluates the intermodulation distortion by introducing two
closely spaced tones at the input.
Distortion arises from non-linearities in the amplifier. If we assume a memoryless timevariant system, the output y(t) to an input x(t) can be written as a Taylor expansion.
Considering only the first three terms,
2
3
y(t)=a Ix(t)+a 2x(t) +a 3x(t)
[Eq 2.4.1-1]
We let the input be a sum of two tones,
x(t) = A 1 cos(w It) + A 2cos(o 2t)
[Eq 2.4.1-2]
where the two frequencies are
9
1,2
=w
0
±AO
[Eq 2.4.1-3]
If we now insert the 2-tone input into equation [2.4-1], the higher order terms will result
in products of cosines of both frequencies. Simplifying this into a sum of single cosines,
we observe cross-terms:
36
y(t)= al +
a 3 A2 Acos(wlt) + a, + -a 3 A2 Acos(w 2t) +
4
4
The later two terms are at frequencies
w = w0 ± 3Ao
[Eq 2.4.1-5]
Their amplitude depends on how linear the system is (i.e. a 3 small). The output spectrum
is shown in Fig. 2.4-6. In the IM 3 measurement, the first and second terms of [2.4.1-4] are
Pout [dBm]
01P
fundamental
3
fund. output
power
IM
I3
I"p 3
3
P.M [dBm]
IMoutput power
Fig. 2.4.1-1 Intermodulation and
fundamental output power as a
function of the input power
2o] - W2
(1
W2
2w 2 - W1
Fig. 2.4.1-2 Output frequency spectrum
the fundamental outputs, while the third and fourth terms are the third order
intermodulation outputs. Obviously, the form of the system given in equation [2.4.1-1]
does not have to be limited to the third power of x. If we were to include higher order
terms (with coefficients getting smaller for higher orders), the coefficients in equation
[2.4.1-4] will have additional terms. Also, there will be other frequencies at which
interference occurs. However, those frequencies tend to be further away from the channel
and at lower amplitudes. [13] lists a table of higher order terms and other intermodulation
frequencies.
37
If we plot the power of the fundamental and intermodulation terms of equation [2.4.1-4],
we see that the power of the interfering tones increases at a higher slope on a dBml/dBm
plot. This is because of the cubic nature of the
3 rd
order term. If we extrapolate, the lines
will intersect. This point is called the 3 rd order intercept point. Extrapolation is required,
because the device will go into compression before it reaches the intercept point. The xand y- axis coordinates of the intercept point are referred to as the input- and output IP 3 's,
HP 3 and OIP 3 . Figure 2.4-5 illustrates this.
A potential source of confusion can be the input power. It is important to know whether
Pin means available power, or power into the device, and whether it refers to the power of
each individual tone, or the power of both tones. In this work, Pin for the IM 3
measurement refers to the overall available power of both tones combined. A similar
ambiguity can arise when referring to Pout. In this work, Pout for the IM43 measurement
means the overall power out of both tones. A typical
in Fig. 2.4.1-3, showing
4IM
3 measurement result is displayed
4IM
3 in a dBm as well as dBc plot.
Having the correct definition of IM 3 is important. The measurement can be taken in units
of dBm and dBc. When in units of dBm, the measurement is the power of the third order
IM tone (as in Fig. 2.4.1-1). Both the high and low IM tones are recorded, this work uses
the average of both. We can use the average as long as the low and high IM 3 are close
together in their values. When the high and low IM 3 diverge, the linearity is no longer
accurately described by the IM3 measurement. In units of dBc, the measurement is
38
--
relative to the carrier power, which is equivalent to subtracting the fundamental output
power [dBm] from the IM 3 output power [dBm].
It should be noted that for modem digital communication circuits, the adjacent channel
power ratio (ACPR) is of great importance. It involves a more complex and timeconsuming measurement. However, the ACPR can be related to the IM3 data and
reasonably well estimated from it [15].
IM3 vs. Pin
IM3 vs. Pin
-10
20
15-
10-
E'
M-10-15
co
-
-25-
25
-20
--
m-35-
-30-5
0
-40-
-40-
-45-
-5 0
-
-60
-22.0
-5 0 -55
-22.0
I
I
I
-12.0 -7.00 -2.00
-17.0 -12.0 -7.00
Pin [dBm]
Pin [dBm]
Fig. 2.4.1-3 IM 3 measurement versus total available power, for the 32x20 gm device
biased at Vds=2 V, Vg,=1.4 V. The left graph shows IM43 (bottom) and the total output
power (top), both in units of dBm, similar to the sketch of Fig. 2.4.1-1. The right
graph shows IM 3 in units of dBc. One can see that the difference of IM3 [dBm] and
Pout [dBm] amounts to the IM3 [dBc], with a slope of two.
-2.00
-17.0
39
2.5. De-Embedding
When doing RF measurements, the network analyzer calibration takes account of the
wire and probe dissipation. Thus, the measurement plane is the tip of the microwave
probes. Ideally, we would like to measure the device itself only, without any
interconnects and pads. To achieve this, we could use a method similar to the network
analyzer calibration, using open, short and through structures [16-20]. However, this
would require not one but three de-embedding structures for each device. Given a fixed
chip size, this would cut the number of devices we can explore in half.
A more primitive method is to assume that most of the parasitics will be in parallel with
the device, as shown in Fig. 2.5-1. In this case, only one de-embedding structure is
needed. It will be identical to the device, but with device contacts removed. To de-embed,
we can see that the device and the parasitic network are in parallel. Thus, if we have a
measurement of the parasitic network, we can obtain the intrinsic device data by
subtracting the parasitic network measurement in Y parameter space from the 'device +
G
D
SS
Fig. 2.5-1 Simple model of the device including the pad parasitics
40
parasitics' measurement.
Fig. 2.5-1 shows the Y-parameters before and after the de-embedding, along with the
measured de-embedding structure. We can see that the measured pads are strongly
influencing the measurement of Y11 and Y22 . This is because the source is overlapping
with the drain and gate. The gate and drain are well separated, and thus do not have a lot
of parasitic interaction. The effect of the de-embedding on Y21 is small, because the
device's high gain results in the intrinsic Y21 being orders of magnitudes larger than the
pad-parasitics. On the other hand, the intrinsic device has a very small Y 12 , and the deembedding has a small effect on the real part of Y12 , seen in Fig. 2.5-1.
2.6. Summary
This chapter has described the measurements performed on the CMOS devices.
Characterization consisted of DC, S-parameter, and large signal measurements. For the
S'-parameters, de-embedding is important to allow a look at the device behavior without
having the pad parasitics interfering. In the large signal measurements, definitions of
input and output power levels were made. This is important because one term can have
several different interpretations.
41
WIVNI - 91ft-A
9E-2
6E-2
1E-2 -
1E-2
1E-3 -
1E-4 1E-3
1E9
1E10
--
-
---- ----
- -
I
-1
3E11
I
1E9
1EIO
3E11
1EI0
3E10
freq, Hz
freq, Hz
-
1E-2
1 -1
'
3E-2
1E-2-
1E-31E-41E-5-
1E3-
1E-6-
'
1E-7
41
1E9
1E10
3E10
I
1E9
freq, Hz
2E-1
1E-1
freq, Hz
2~E~
-
1E-1 -
1E-21E-21E-3-
S1E-3 -
1E-41E-5-
11-1'
1E9
1E10
3E10
1E-4 -T
I
1E9
freq, Hz
IE10
3E11
1EI0
3E10
freq, Hz
6E2
4E-2
1E-2 -
1E-21E-3 -
1E-3 1E-4 t
I
1E9
1E10
freq, Hz
3E10
1E9
freq, Hz
Fig. 2.5-2 Y-Parameter measurements, illustrating the impact of the de-embedding. Each
graph shows the pad, the device + pad, and the de-embedded measurement (see legend
below)
-----
---
42
Device+Pad Measurement
(-- Pad Measurement
De-embedded Measurement
- --
2!Smae!
-=
Chapter 3
Simulation Setups
The modeling that has been carried out in this thesis is based on the BSim3 model
supplied by TSMC for their devices. This chapter describes the simulation setup, which is
done in Agilent Advanced Design System, version 1.5 (ADS 1.5). The graphs are based
on simulations with the TSMC BSim3 model only, and do not include any modifications
to the model, which will be made in chapter 4. This chapter shows the simulation suites
and the results, for DC, S- and Y-Parameter, IM 3 and power-sweep simulations. All
simulations are performed using only the TSMC BSim3v3 device model, except for the
IM 3 and power-sweep simulations, which included the measured pad data as well.
3.1. DC Verification
Before looking at the AC performance, it is important to model the DC characteristics.
This assures that threshold voltage and other important DC parameters are accurate. A
picture of the DC simulation setup and the simulation results are shown in Fig. 3.1-1. and
3.1-2-6 respectively. The simulation includes the probe resistance, which we measured to
be on the order of 0.5 to 1.2 Ohm, depending on the quality of the contact.
43
DC Simulation
Constants
Bias Point for SP simulation
SVAR
VAR4
Vgsul.5
Vds=2.5
D C Sin u atbn:
DC
Transer
DC
Output
FQPARAMETER SWEEP
Deuce Dimensions
ParamSwep
Outputsweep
Start=u
Stop=2.4
Step=0.2
IM VAR
DeuceAutomatic
Width=20 um
Fingers=08
Ad=56e-12
Pd=5.e-6
AslO09e-12
Ps 50.9e-6
PARm-AMETER SWEEP
ParamSweop
TransferSweep
Start=O
Stop=2.4
Step=0.2
DC
Subthreshold
PARAMETER SWEEP
R
RRPROBE
DC Block
DC Bloc
Term
Termi
Num=1
Z=0
DCFeed
DCFeed1
betymensistan
v-VAR
1
VAR3
RPROBE=0.5
TS Cmodel25U
De
ce
Ohm
i2 Ohm
Ohm
R
RI
R=RPR
DC
Block
C6iCIF11&k2
DCjeed2
Term2
Nurm=2
Z--50
R
R4
R=RPROBE/4
V_DC
+
Vgste
- - Vdc=Vgs
-1
~1
4 because 4
+
--
tips contacting source
-1
V_DC
Vdrain
Vdc=Vds
*
Oh,
ParamSweep
SubthresholdSweep
Start=
Stop=10
Step= 1
SWEEP PLANSweepPlan
Subthl
Start=0.5 Stop=2.5 Step=0.5 Lin=
Start=.1 Stop=0.1 Step= Lin=1
UseSweepPlan=
SweepPlan=
15 MeasEqn
gd=-dif(Output.DC.Vdrain.i,Vds)
totatwidth=160 um
gm=-ditt(TransferDC.Vdrain.i,Vgs)
Fig. 3.1-1: DC Simulation Setup for output, transfer, subthreshold characteristics and
g. and gd.
44
-ga-
I
600
500 -
400
-
300
-
200
-
100
-
-.ma --a
0-
2.0
1.5
1.0
0.5
0
Vds
2.5
M
Fig. 3.1-2 Simulated output characteristics of the 08x20 gm device, with Vgs from 0 to
2.4 V in 0.2 V steps
1000
900800700600, ,
5004003002001000-
0.0
0.5
1. 5
1.0
2. 0
2.5
Vds [VJ
Fig. 3.1-3 Simulated output conductance of the 08x20 gm device, with Vgs from 0 to 2.4
V in 0.2 V steps.
45
600
/
500-
400-
Y 300-
200-
100-
0.0
0.5
2.0
1.5
1.0
2.5
Vgs [V]
Fig. 3.1-4 Simulated transfer characteristics of the 08x20 gm device, with VdS from 0 to
2.4 V in 0.2 V steps.
350
300 250
-
E 200
-
C,)
E 150
0>
-
100
-
50 -
0.0
0.5
1.5
1.0
2.0
2.5
Vgs [V]
Fig. 3.1-5 Simulated transconductance of the 08x20 gm device, with Vd, from 0 to 2.4 V
in 0.2 V steps.
46
1 E2
1E1-
1E-11 E-2
1 E-3
1 E-4
1 E-5
1E-6
1.00
0.75
0.50
0.25
0.00
Vgs [V]
Fig. 3.1-6 Simulated Subthreshold characteristics of the 08x20 9m device, with Vd,
from 0 to 2.4 V in 0.2 V steps
SP
Sinl ubtim:
Probe
Resistance is
betan 0.5 and 1.2 Ohm
Srmar s
RPROBE=0.8
SP M ess ini
D ata:
Ohm
I-Probe
-
ld-Prmonitor
S2
R
DCBock
3
R1
R=RPRk
Cead'!
Ter
~
Trml
DC.Feed2
TSf Cmode(25uSUb2
DeN c
Num=1
Z=50
Ohm
R
V_DC
R4
Rgt
RPROBE/4
+
+
z--.
SVde=Vgs
Me
C
v
Fil
Tem
Term
Term2
NuM=2
Tsrm3
Num=3
Z=50 Ohm
=OM
aamdSP
c:UORG\SPdata
p16x10.S2P"
Term
Tarm4
Num4
Z=50 Ohm
Vdain
Vdc=-Vds
S-Parameter Simulation
CmVAR
0 1S-PARANETERS
SParam
SimSP
Start=500 MHz
Slop=20 GHz
Sfap=50 MHz
MeasEqn
DevicManusl
DC
DCSim
Vgw1.4 V
Vdv-2 V
Wdth=10 um
Fingem=16
NoFinger:8
Vg=1.4
FingeaVV10 um
Vd=2
Ad=5.6e-11
Pd=1 129-6
AW8.26:-11
P=3.65 -6
Fig. 3.2-1 S-Parameter simulation setup
47
3.2 S-Parameter Simulations
The S-Parameters simulation setup includes the same probe resistances, and ideal bias
T's to mix the RF and DC signals. Both an S-Parameter as well as a DC simulation are
done. The purpose of the DC simulation is to sweep the gate voltage Vgs, while
monitoring the drain current. This allows adjusting the gate voltage in the S-Parameter
simulation, such that the drain current coincides with the measured current level. This
method compensates for very small inaccuracies in the model's threshold voltage. In Fig.
3.2-2-4, the simulation results for a 16x20 gm device are shown.
48
I
12
S11 and S22
frq
2
22.
S21
G
(0-0.15 -0.10 -0.05 0. )0 0.05 0,005
.
.
freq (500.0MHz to 20.00GHz)
freq (500.0MHz to 20.00GHz)
freq (500.0MHz to 20.00GFz)
.
Fig. 3.2-2 Simulated S-parameters for the 16x20 pm device biased at Vds=2 V,
Vgs=1. 4 V
Y1
1
1E-1
1
Y11
Y12
4
IE-1
1E-2-
1E-21E-3-
1E-3-
1E-4-
1E-4-
1E-5-
1E-5
1E-6-
1E0 2E10
lE9
Real
---
(Y)
freq,
freq,Hz
mg {Y)
Hz
Y22
Y21
6E-2
5E-2
6E-2
2E-2
2E-2
1E-2-
IE-2
I
4E-2
1E-2-
3E-2 2:
1E-3-
m
ID
0
IE-3
0
freq, Hz
freq, HZ
Fig. 3.2-3 Simulated Y-parameters for the 16x20 pm device biased at VdS=2 V,
Vgs=1. 4 V
| h21
I
Gtu
40
20
30-
15
20
10
5
10
0-
0
freq, Hz
00
freq, Hz
4
Fig. 3.2-4 Simulated jh21| and Gw for the 16x20 m device biased at Vds=2 V, Vgs=1.
V
49
3.3 Power-Sweep
The power sweep setup uses the harmonic-balance simulation component in ADS. The
schematic in Fig. 3.3-1 shows the power source, biasing, device and the load impedance.
Load and source impedances can be adjusted and are incorporated into the source and
load elements. The main structure and equations are already supplied by ADS in the RF
power-amplifier design guide, which is a library of simulation setups and result displays.
The measured load and source tuner impedances are presented to the device.
An important part of the simulation setup is the de-embedding. While in the S-parameter
case the measured data has been de-embedded before comparing it to the simulations, it
is done inversely here. The measured large signal data is not de-embedded. To compare it
with the device simulations, we have to add in parallel to the intrinsic device the
measured Y-parameters of the pad and interconnect parasitics. This can be seen in the
schematics in Figs. 3.3-1 and 3.4-1.
In the simulations and power-sweep graphs of Figs. 3.3-2 and 3.4-2, the input power Pin
refers to the available input power from the source, as described in section 2.5.
In Fig. 3.3-3, the impact of the probe resistance on the Pin vs. Po
0 t simulation is shown, by
sweeping its value between 0.25 and 1.5 Ohm. This range of values was reported for the
probe resistance, depending on the quality of contact [21]. We see that the uncertainty
introduced by the probe resistance in the Po
0 t level is roughly 0.5 dB.
50
IProbe
IProbe
M VARVA
DeviceAutomatic
Vg=.4000000v
Vhgh+ Vshigh
DC Feed
F-
VCL
Ad56e-12
12SRC2
Pd=5.6
maLoad
GLre at0.1347270
VARli ag-0.5744116
Ge
low
V
Vigrs<2D
DCFeed
G3
L
VdcVigh
Gam moSource
Vdc=Vlow
As=109e-12
GSre
-GSIm
PS=50.9e-6
...
91-0.5103185
ag-0.5358872
VAR
DeE.
ZLZ
GLoo d-GLre@I+j*Glimag
Glna
GSo ure-GSreaI+rGSimg
Zinadd5(1+GLood)/(1-GLoad)
bdIng
I-Probe
Zsou rce-50*(I+GSource)/(.-G
I_inpuw
Sour
R
R2
VV pa1t,
P_1Toe
PORT1
R
RI
R-RPROBE
DCB3ock
DC1BIk
Num-1
R-RPROIB
TS
Vlioo d
DCBlock
C1
modeI25uSub2
I od
DeieTerm
em
-Zsourco
Num=2
P-dbmtow(RFpoer)
Freq-RFfreq
R
R-RPROBE/4
J
VAR
VAR3
RPROBE-0.8
VAR
Z-Zood
1
Ohm
M B C .31908 opt( 1.3 V to 1.43 V)
H81
Freq{I)-RFfreq
PinSweep
WVAR1
RFfreq-2.45 GHz
ZZkad.1I((l-Pload)/(1+Pknad))*50
Start=-30.000000 Stop-6.0000000 Step=1 UnUseSweepPlan=
SvmepPurnm
Order[11.5
UaeKrylov -
Z2Ioad-(0.314+0.838*j)50
SwoepVar."RFpooer"
PIoad-0.75'exp(168.5/180'pij)
Peource-0.71*exp(148.5/180pi*)
Z2ource(0.84+2.366j)*50
ZZsource.1I((I-Psource)/(1+Psource))*50
Vhigh-2.0 V
SwsepPlen=PinSweep
Fig. 3.3-1 Power-Sweep simulation setup
T
0
a.
15
22.
10-
21
20-
5+
C
0
-5-
189
18
-1
-25
-30
:g
-20 -15
Pin [dBm]
-30
-5
17
30
-25
-20 -15
Pin [dBm]
-10
-5
-25
-20 -15
Pin [dBm]
-10
-5
25
0.0320
0.0315 '
0.03100.03050.03000.0295-1
0.0290 -.
-10
20
w 15
Ui
10
Ia.
5
1
--25
1
I
I I
I
-20 -15
Pin [dBm]
-10
-5
0I-30
Fig. 3.3-2 Power-sweep simulations using the BSim3 model only, for the 08x20 gm
device biased at VdS=2 V, Vgs=1.4 V.
51
AN
19.0
18.5
, 18.017.5-
L
C
(
17.0-16.5
PROBE=0.250
PROBE=0.875
IPROBE=1.500
-30
-25
-20
-15
-10
-5
Pin [dBm]
Fig. 3.3-3 Simulated Gain vs. Pin for the 08x20 gm device using the modified model, at
Vgs=1. 4 V, Vds=2 V. Shown for three different values of probe resistance. The
difference in gain between highest and lowest probe resistance is about 0.5 dB.
3.4 TM 3 Simulations
Fig. 3.4-1 shows the IM 3 simulation setup. It is very similar to the Power-Sweep setup,
except that two signals are introduced at the input of the device. The equations for
computing IM 3 are supplied in the ADS RF-PA design guide. As described in section 2.4,
two different types of units are often used with IM 3 , dBm and dBc. To convert the IM 3
[dBm] to IM 3 [dBc], the fundamental output power is subtracted from the output power
of the IM 3 tone.
Again, the issue of input power definition is important. In this schematic, RFpower is the
available input power of both tones combined, resulting in an individual tone available
power of RFpower-3dB. In the results graphs, the total available input power Pin equals
RFpower.
52
Although the measurements did not record the output power of the fundamental tones, we
can compute them from the IM3 [dBm] and IM 3 [dBc] data. We can extract the output
power of each tone, by subtracting IM3 [dBm] from IM3 [dBc].
I
IProbe
Probe
*h
VAR
VD
+Vs-low
RC
. Vo _DC
Li
DCFeed
L2
DCFeed
~
+
Va-DCg
V d c V h igh
G=3
-
VAR
ZLZS
GLoad=GLreal+j*GLimag
GSource=GSreal+j*GSimag
Ztoad=50*(1+GLoady(1-GLoad)
Zsource=50*(1+GSourcey(1--GSource)
De mbe ding
IProbe
I input
DCBlock
V np ut
DC181k
P nTone
pwePrmoe
PbIRT1
Num=1
Z=ZsDUrCO
Freq[1]=RFfreq-fspacing/2
Freq[2j=RFfreq-fspecing/2
U
V
R1
R=RPROBE
R
OCBlock
R2
R=RPROBE C1
TS Cmodel25uSub2
De
Vlood
lood
Te m
Termi
Num=2
Z=Zload
ce
R3
R=RPROBE/4
SP[1]=dbmto%,RFpoWer-3)
P[21=dbmtow(RFpower-3)
IVAR1
tspacng=10tz
MaxIMD order=5
VAR
DeviceManual
Vgs=1.4000000 V
Vds2.0000000 V
Wdth=20 um
Fingers=08
Ad=56e-12
Pd=5.6e-6
As=109e-12
Ps=50.9e-6
pidB=-6 _dBm
GLreal=-0.3259549
GLimag=0.5156097
SVAR
GammaSource
GSreaG=O.2120332
GSimag=0,7298232
ih
Vdc=Vlow
S2
GammaLoad
IVAR
VAR33
1 1HARCM BALANCE
RPROBE=0.8
HB1
MaxOrder=Max IMO order
Freq[1}=RFfreq-Tpacing/2
Freq[2}=RFfreq+fspacing/2
Ordeq1}=5
Order[2]=5
UseKrylov
SweepVar="RFpower'
SweepPlan="PinSweep"
R
Ohm
SVYEEPR.AN
(VAR
VAR2
ZO=50
VAR
PSVlow
ImpedancesZIbb=Z+j 0
I tofund =
+ J*0
ZI 2 = ZO+ j-0
ZI_3 = ZO +j*O
Z1_4 = ZO+ j'O
Z_1_5 = ZO + j*O
;Source Impedances=
Z_s_bb=Z0+j*0
Z-s-fund = ZO + J0*
Z_s_2 = ZO +
Z ZOjO
Z_s_4 = ZO + j*0
Z-Si5 =Z +ej*O
;Load
j*O
PiS
Star =27 000000 Stop=-3.0000000 Step=1 Lin=
UseS weepPlan=
Swee pPlan=
Vlow=1.3200000
EVAR
MVAR4
RFfreq=2.45 Gt-z
ZZload=1/((1-PloadY(1+Pload)r50
Z2Ioad=(1.088+0.633*jr50
0
Pload=0.59*exp(76.818
*pi*j)
Psource=0.74*eoxp(46.4/180*pi*j)
Z2ource=(0.84+2.366*j)50
ZZsource=1((1Psourcey(1+Psource))50
Vhigh=2.0 V
Fig. 3.4-1 IM 3 Simulation setup
53
- --
AA
F.-
IM3 vs. Pin
- I
'; I
-
- -
IM3 vs. Pin
10
-10
0
-15
-10-25
E
m -20
m -30-35
~
-40
-40
0u
-50
-45
-60-
-50
-70
o
o
. 0
o
6
6o
6 6
0
Pin [dBm]
o
o
00
oo
0
o
0
0
6
0
0o
Pin [dBm]
Fig. 3.4-2 IM 3 Simulation versus total available power, for the 08x20 pm device
biased at VdS=2 V, Vgs=1.4 V. The left graph shows IM3 (bottom) and the output
power (top) both in units of dBm. The right graph shows IM3 in units of dBc.
3.5. Summary
The simulation setups have been described, showing both the simulation schematics in
ADS as well as sample simulations obtained by using the BSim3v3 model. The
simulations consisted of DC, S-parameter, and large signal simulations. The large signal
simulations have to be broken up into 1-tone and 2-tone simulations. The latter is used to
simulate the IM 3 behavior, while the 1-tone measurement gives Pout, Gain, Id and PAE vs.
Pin.
54
4; AI
Chapter 4
Results: Comparison of Measurements and Simulations
This chapter compares the measurements with the simulations. First only the BSim3v3
model for the device is used. Then we build a new model that gives more accurate small
and large signal simulations. A comparison of the final model with measured data
concludes this chapter.
4.1 Intrinsic BSim Model
We will compare the DC, S-Parameter, and large signal simulations as predicted by the
BSim3v3 model to the measurements. Figs. 4.1-1 to 4.1-5 show the DC characteristics of
the 16x10 gm device.
We can see that the output characteristics in Fig. 4.1-1 are well matched for low Vgs, yet
for higher Vgs the model does not predict the flattening of LI that is probably due to selfheating. This can also be seen in the output conductance in Fig. 4.1-2. It would be nice to
be able to take self-heating into account, however the transistor models in ADS do not
support it currently.
Looking at the transfer characteristics in Fig. 4.1-3, we see that again for low
VdS
the
match is very good, while for higher Vgs the model overestimates the current slightly. The
threshold voltage is modeled reasonably accurate. A clearer view is possible through the
55
transconductance plot in Fig. 4.1-4. Here, we can see that gm is predicted correctly in
shape, with a slight mismatch at high Vds. Lastly, Fig. 4.1-5 shows the subthreshold
characteristics. Overall, the match is good here, too, indicating that the short channel
effects are modeled well.
600
500-
400-
300-
200-
100-
2.5
2.0
1.5
1.0
0.5
0.0
Vds [V]
Fig. 4.1-1 Output Characteristics of the 16x10 pm device, with Vgs from 0 to 2.4 V in
0.4 V steps.
1000
1E3
900 800 -
1E2
700 -
600
1E1
Simulation
-]
Measurement
500
400
300
1E-1
200 100 -
0.0
0.5
1.5
1.0
Vds [V)
2.0
2.5
0.0
0.
1.0
1.5
2.0
2.5
Vds IV]
Fig. 4.1-2 Output Conductance for the 16x10 pm device, with Vgs from 0 to 2.4 V in 0.4
V steps. Left: linear scale, right: semi-log scale.
56
600
-- l
500-
--
Simulation
Measurement
400-
2 300-
200-
100-
0.5
0.0
2.0
1.5
1.0
2.5
Vgs [VI
Fig. 4.1-3 Transfer Characteristics of the 16x10 pm device, with Vds from 0 to 2.4 V
in 0.4 V steps.
350
300
250
E 200
E 1505
-El-
Simulation
100
-V
Measurement
50
500.0
0.6
1.5
1.0
2.0
2.5
Vgs [V]
Fig. 4.1-4 Transconductance of the 16x10 pm device, with VdS from 0 to 2.4 V in 0.4
V steps.
57
1 E2
1E11
1E-1E
Z 1E-21E-31E-4-
-EB-
Simulation
1
Measurement
1 E-5
1E-6
0.00
0.25
0.50
Vgs [V]
0.75
1.00
Fig. 4.1-5 Subthreshold characteristics of the 16x10 gm device, with VdS from 0 to 2.4
V in 0.6 V steps. The lowest measurement line is for Vds=O V, the simulations yield 0
A current here, so they are not shown.
Altogether, the DC characteristics are well captured by the intrinsic BSim3v3 model, so
that there will be no need to append or modify the DC model.
Figures 4.1-6 to 4.1-8 show a comparison of AC simulations and measurements of the
16x20 gm device. Fig. 4.1-6 shows the S-parameter comparison. Both Sn and S22 are
significantly off from the measurements. S12 and S21 are also not matching well with the
measurements. Overall, the S-parameter simulations are not particularly accurate.
Similarly, the Y-parameters in Fig. 4.1-7 also show significant discrepancies between the
measured and BSim3v3 model. Finally, in Fig. 4.1-8, the model predicts
1h211 well,
although above 10 GHz the shapes diverge. Gtu is not well modeled, being several dB
above the measurement.
58
The missing accuracy of the S-parameter simulations will directly translate into an
impedance mismatch during the large signal measurements. This is because these
simulations are done with identical load and source impedances as in the measurements,
yet the reflection coefficients that the simulated device presents are different from those
of the measured device. Thus the simulations will have an impedance mismatch. The
results of the power sweep simulations compared to measurements are shown in Fig. 4.19. The simulations include the BSim3v3 model and, in parallel, the pad measurements as
described in Chapter 3. Fig. 4.1-10 shows the IM 3 BSim3v3 simulation and measurement
comparison. The BSim3v3 models IM3 almost 30 dBc below the measurement value.
S12
S1 I and S22
N21
-4- 11 swma"o
22]Iic
-9
22 WMo
freq (500.0MHz to 20.00GHz)
CLq4
freq (5000MHz to 20.00GHz)
freq (500.0MHz to 20.00GHz)
Fig. 4.1-6 S-Parameters for the 16x20 gm device using the TSMC BSim3v3 model,
biased at Vgs=1. 4 V, Vds=2 V.
59
MM
MOMMEMMORPEP77--
I
Y1 2
Y 11
1 E-1
1
1E-2-
1E-1-
1E-3-
1E-2-
E 1 E-4-
E
A)
--. 1E-3T1
I E-4-
I
m 1E-5-
7
I E-6i
-~N)
m
MM
(C)
Imag(Y)
Imag{Y)
-4-
0
---
freq, Hz
(0
m
0
Measuremen
a
freq, Hz
-&-
Real{Y) Simulation
-v--
Real{Y) Measurement
Y22
u..
*
5E-2
1 E-1
2 -1
*
K)
m
m
Simulatio
Y21
2E-1
1IE-1 -
I
E-1
I.1
1 E-21 E-3-
1E-2-
1E-2 Z--5
E
-1E-2 Z
0)
1 E-4-
1 E-3-
-1E-3
m
(O
m.
m
K3
m
-A
m
0
0
(0
K)
m
0D
freq, Hz
freq, Hz
Fig. 4.1-7 Y-Parameters for the 16x20 gm device using the TSMC BSim3v3 model,
biased at Vgs=1. 4 V, Vd,=2 V.
| h21
Gtu
40
25
30
20_
20
1510-
10
50-
0
m
freq, Hz
m
m
0
0
m
__m
_
1
---
--V-
0
Simulatio
freq, Hz
Fig. 4.1-8 Figures of merit h2 11 and Gtu for the 16x20 gm device using the TSMC
BSim3v3 model, biased at Vgs=1. 4 V, VdI=2 V.
60
m
0
27
15
10E
25--
5-
23-
0
a.0
21 -
-5-
I.f
-
-30
-25
-20
-10
-15
-5
19- V
-30
Pin [dBm]
0.070
25
0.068 -
20-
--0.00 as "'04'
:z0. 066 -
-5
-10
-15
Pin [dBm]
-20
-25
*, 1510-
0.064-
5-
0 .0 6 2.
01
-30
-25
-20
-15
-10
-5
Pin [dBm]
-30
-
*1'
-15
-20
-25
-5
-10
Pin [dBm]
Simulion
Fig. 4.1-9 Power sweep simulations for the 16x20 gm device using the TSMC
BSim3v3 model, at Vgs=1. 4 V, Vds= 2 V.
-
0-
10
0--
-10-
-107
-20-
-20
-30-
-E--
Simulation
----
Measurement
-30C9
0
CL
0o
-40'
M -40-
-50'
-50-
-60
-60-
-70-
-70-
-80-90-
-8-Simulation
-80.
-100-
-27
-22
-12
-17
[dBm]
Pin
-7
-90
i -27.0 -22.0
I
II
i
I
1
-17.0
-12.0
Pin [dBm]
I
1
-7.00
Fig. 4.1-10 IM 3 simulations for the 16x20 gm device using the TSMC BSim3v3
model, at Vgs=1. 4 V, Vds=2 V. Left: Pout (top) and IM3 [dBm]. Right: IM3 [dBc]
61
4.2. Modifying the BSim Model
In order to get a more accurate large signal fit, the first step is to match the small signal
AC characteristics. The S-parameters were measured with an input power of about -30
dBm, which is equivalent to the lower input power of the power-sweeps (the load and
source impedances are 50 Ohm in the S-parameter case). A good fit for the S-parameters
should therefore lead to improved large signal simulations, for low input powers at least.
Appendix A shows the S- and Y-parameters of the simulations as each of the model
parameters is swept up- and down from its optimal point in the final model. Following
this helps to understand the impact of the model parameters on the device behavior.
Starting with the S- and Y-parameter plots from Figs. 4.1-6 and 4.1-7, we will add
elements first that only influence one curve of the S- or Y-parameters.
4.2.1. Output Resistance
The real part of Y22 (from hereon denoted as Real[Y22] ) at low frequency is the DC
output resistance of the device. Fig. 4.2.1-1 shows Y22 , and we can see a mismatch of
Real[Y22] at low frequency. The simulation shows too high an output resistance. To
correct this, a resistor is added in-between the drain and source. The value of the resistor
is determined such as to match only the very lowest frequency parts of Real[Y22]. This is
because the shape at higher frequencies is influenced by other elements in the device.
62
Because the resistor is added in parallel between the drain and source, it will only
influence Real[Y22]. A negligible change will occur in Y21, the other Y-parameters are
not affected.
Y22
Y22
5E-2
1E-1
5E-2
1E-1
1E-2-
1E-2 -
CO)
1E-3-
-1E-2
E
1E-3
C
-1E-2
1E4-
1E41E10 2E10
1E9
-
~
freq, Hz
-~-5-
ImagY Simulation
ImagY) Measurement
Real{Y) Simulatim
Real{Y) Measurement
r
m
CD
r
freq, Hz
Fig. 4.2.1-1 Y22 before (left) and after (right) adding the output resistance Rout.
4.2.2. Gate Resistance
In the TSMC BSim3v3 model, the gate resistance model parameter is set to zero. While
the gate resistance is negligible for very narrow devices, RF power devices have very
wide fingers and thus the gate resistance will be an important parameter [4-7,9,10]. In the
Y21
Y21
2
2E-1
1E-1 -
2E-1
-1E-1
1E-2 -
-1E-2
1E-3
_
E
2E-1
E-1
2E-1
1E-1 -
">-
E-2
.E 1E-2 -
1E-3
1E-3
m
m
CO
0
freq, Hz
0
U5
-A--
Imag(Y) Simulation
-X-
Imag(Y)
-2--
Real(Y) Simulation
-V-
Real(Y) Measurement
-L
0
Measurement
freq, Hz
Fig. 4.2.2-1 Y21 before (left) and after (right) adding the gate resistance Rg.
63
-
i-@Mffi
-
-t
- enow-
--
-
-
-
- ,,- -4
S-parameters, the gate resistance primarily affects SII by reducing the radius of the circle
that S11 typically traces. Alternatively, its impact can be seen in Y21, where the gate
resistance causes Real[Y21] to bend. Fig. 4.2.2-1 illustrates this. Furthermore, while the
gate resistance does not have an impact on
1h211,it reduces
Gt.. This eliminates some of
the excess gain of the simulations.
4.2.3. Gate, Source, and Drain Inductances
While the simulations now give a reasonable fit at low frequencies, we can see several
changes of sign in the measured Y-parameters, most prominently in Imag[Y21] as shown
in Fig. 4.2.3-1. These do not occur in the simulations. They can be explained by the
presence of parasitic inductances in the gate, source, and drain. When adding the
inductances to the model, the sign changes are now modeled correctly. The reason that
Real[Y21] is also matched, even though we do not see a sign change, is that there is a
sign change in Real[Y21] which occurs at higher frequencies above the 20 GHz that the
graph shows.
Y21
Y21
3E-1
2E-1
1E-1 -
2E-1
1E-1
2E-1
1 E-1
1E-11 E-2
.
2.
V E 1E-2-
1E-2 -E-2
1 E-3
1E-3
-
01
freq, Hz
0
-
--
--
Imag(Y) Simulation.
SCIulaDia,
l magjY I Measurement0
Real{Y) Simulation
Real{Y) Measurement
(
0
freq, Hz
Fig. 4.2.3-1 Y2 1 before (left) and after (right) adding the inductances in the gate, source
and drain.
64
=M
4.2.4. Body Resistance
The importance of the substrate network has been discussed in various papers [8,9] as
having an impact on the S-parameter and large signal characteristics. For our model, a
simple resistance between the body and source appears sufficient to capture the substrate
effects. This is equivalent to the model in [7,8] and the reduced version of the model
proposed in [4]. The best way to observe the effect of the body resistance is by looking at
Real[Y22] as shown in Fig. 4.2.4-1. Adding the resistance allows the curves to match. In
the simplified small signal model, shown in Fig. 4.2.4-2, the body resistance results in an
RC-network consisting of a parallel
Rb-Csb
in series with Cdb. This network is between
the drain and source node, in parallel with the intrinsic device, which explains why its
primary impact is on Y22 . However, through the backgate transconductance generator
gmb, Rb also affects Y21.
Y22
Y22
5E-2
1 E-1
5E-2
1E-1
1E-2 -
1E-2 -
1E-3-
1E-3E1E-2
1E4-
-1E-2
.9
IE-41 E-5
1E-5 -
m M
m
freq, Hz
---
Imag{Y } Simulan
-(-
Imag{Y) Measurement
-8-
Rea(Y) Simulation
M
m
W
m
-
freq, Hz
ReaW(Y) Measurement
Fig. 4.2.4-1 Y22 before (left) and after (right) adding the body resistance
Rb.
65
R
+
Port
Drain
Rout
Port
Gate
CD-
Csb
Port
Source
C
Cdb
VCCS_Z
TI
gmVgs+gmbVbs
T
V ba c k
Vb a c k
V
ack
Fig. 4.2.4-2 Simplified small-signal model illustrating the effect of the body resistance,
Rb. Without Rb, there is only a capacitor between the drain and source. With Rb in place,
there now is an RC network between the two ports, giving rise to the observed changes
in Y 22 .
4.2.5. Gate-to-Drain Capacitance
Having now a very accurate model, we can as a final step add a small capacitor between
the gate and drain. The effect can be best seen in S12. The Cgd-ext helps to move Si 2 out,
matching it closer to the measured results, as seen in Fig. 4.2.5-1.
S12
Bsbnuaton
S12
..-
Measurement
/
/
CO)
6
6
i
1~
I
0
,/'
co4~
-
cyl
U'
to
C0 ,V
7-
freq (500.0MHz to 20.GHz)
fq (500.0MHz to 20.00GHz)
Fig. 4.2.5-1 S1 2 before (left) and after (right) adding the gate to drain capacitance Cgd.ext.
66
4.2.6. Small Signal Comparison of the Complete Model
The complete model is shown in Fig. 4.2.6-1. Comparisons of the measured and
simulated S-parameters for the 16x20 gm device using the improved model are shown in
Fig. 4.2.6-2. The fit is good, with a small discrepancy in S11 and S12 at frequencies
approaching 20 GHz. The Y-parameters are compared in Fig. 4.2.6-3, and show very
good agreement throughout the frequency range. The mismatch is below 10% for most of
the Y-parameter curves. Lastly, Fig. 4.2.6-4 shows the figures of merit 1h21I and Gt, with
is due to
very good agreement, although 1h
2 11is a little bit too low in the simulations. This
a slight overestimation of Imag[Y1 1] of 20% in the model, as can be seen in Fig. 4.2.6-3.
This 20% overestimation results in the simulated 1h2 11being lowered by 1.6 dB, which is
C
Cgd-ext
L
L
Ld
Lg
Port
Port
DrainPort2
Num=1
GatPortl
Num=2
R
Rout
R
Rg
s
R
Rb
TSMCdevice25u4
Intri isicDevice
Port
SourcePorti
L
Ls
Num=3
Fig. 4.2.6-1 Modified BSim3v3 model topology to take RF effects into account
67
the discrepancy of h21j we observed in Fig. 4.2.6-4.
0
S11 and S22
25
S21
Siaom
S22 Mesuemmn
freq (500.0MHz
freq (500.0MHz to 20.00GHz)
freq (500.OMHz to 20.00GHz)
to 20.00GHZ)
Fig. 4.2.6-2 S-Parameters for the 16x20 gim device using the modified model, biased
at Vgs=1. 4 V, Vd,=2 V.
Y12
Y11
1E-1
1
I
1E-2 -
1E-1 -
1E-3 -
1E-2 -
1E-4-
1E-3 -
E-5
1 -
1E-4 1 E-5
-
1E-6 -
-
m
m
(0
S -
0
~1
Imag{Y)}Simulation
--
Imag{Y) Measuremenw
ReaIY) Simnation
-v-
Rea(Y} Measurmnwt
-X-
freq, Hz
-
freq, Hz
Y22
Y21
2E-1
1E-1
2E-1
1E-1 -
5E-2
1E-1
1E-2-
~
1E-3-
1E-2
1E-2 -
-1E-2
1E-4-
I
m
(D
m
1E-A
m
N'%
1E-5 --
mL
(0
0
freq, Hz
m
N
0
0
freq, Hz
Fig. 4.2.6-3 Y-Parameters for the 16x20 pm device using the modified model, biased
at Vgs=1. 4 V, VdS=2 V.
68
----
!@- I sli
--
-.
2;
A
-
-
-
---
- -
Gtu
I h21 I
40
20
30
15-
20
10-
10
5
0-
0
-C
M
M
M
-f3-Simulation
0
0
-- Meurem.n.
1E102E10
1E9
freq, Hz
freq, Hz
of
Fig. 4.2.6-4 Figures merit 1h
211 and Gtu for the 16x20 gm device using the TSMC
BSim3v3 model, biased at Vgs=1.4 V, VdS=2 V.
4.3. Large Signal Comparison of Complete Model
Having built a model that accurately models the S-parameters, we will now test it against
the large signal measurements. There are six devices, 08x20 gm, 16x05 gm, 16x20 gm,
16x40 gm, 32x10 gm and 64x05 gm, for which power sweeps were performed
measuring P0 ut, gain, drain current, PAE, and IM3 as a function of available power (Pin).
After deriving the proposed model additions for each of these devices, S-parameter, and
power sweep results were compared. All devices showed an equal accuracy in modeling
the measurements, so we will only present the results of the 16x20 gm device here.
Figs. 4.3-2 shows the output power vs. input power for the measured device and the
model. The model accurately predicts the magnitude and shape of the measurements.
Looking at the Gain vs. Pin in Fig. 4.3-2 allows to see the model's accuracy more easily
then in the Put vs. Pin graph.
69
The low input power current should be identical for the measurements and simulations, as
discussed in 3.2. This is achieved by changing the gate voltage to compensate for small
threshold voltage mispredictions of the BSim3v3 model. The results of the drain current
as a function of Pi. are shown in the third graph of Fig. 4.3-2. The current, together with
the Pi,-Pout graph, will determine the power added efficiency, PAE. The results, the last
graph of Fig. 4.3-2, show a very good agreement between measurements and simulation.
Fig. 4.3-3 shows IM 3 and Pout in dBm, and IM 3 in dBc as a function of input power. The
30 dBc discrepancy seen in section 4.1 has been eliminated, and the simulated IM 3 and
Pout curves now track the measurements very closely. Important for the IM3 match is to
have an accurate match of Pout. Because IM 3 [dBc] equals the difference of IM 3[dBm] and
Pout, any mismatch in Pout is exactly transferred into the IM 3 [dBc] curve.
70
23
15
10-
22-
-
5
0
CL
-5-
21-
C
0
0! 20-
exole
I
-30
-20 -15
Pin [dBm]
-25
-10
9
-5
-30
-20 -15
Pin [dBm]
-10
-5
-25
-20 -15
Pin [dBm]
-10
-5
0
0.070 ,I
5-
0.069-
-25
1I
0
1.
0.068-
5-
0.067--,
-30
r
0T
-30
-5
-10
-20 -15
Pin [dBm]
-25
--
ion
simwa
-'- Meas renmnt
Fig. 4.3-2 Power sweep simulations and measurements for the 16x20 pm device using
the modified model, at Vgs=1. 4 V, Vd=2 V.
0
15
-55-
-10-15+
-5-
-20E -15-
CO
-25C
c
-25-
CO,
-30--35-
a.. -35-
-40
-45-
-45-
-50+
-- '
-55-
-27
-22
Lie:zmucj
"'ment
-12
-17
Pin fdBml
-55-7
-27.0
-22.0
-12.0
-17.0
Pin [dBm]
-7.00
Fig. 4.3-3 IM3 simulations and measurements for the 16x20 gm device using the
modified model, at Vgs=1.4 V, VdS=2 V. Left: Pot (top) and IM 3 [dBm]. Right: IM3
[dBc]
71
4.4 Summary
We have compared the measurements with the BSim3v3 model and noted a significant
discrepancy between the S-parameter and large signal simulations and measurements. A
new model has been derived based on the BSim3v3 model that includes the six new
elements, by only using S-parameter measurements. The new model was then compared
against the S-parameter and large signal measurements. It showed a significant
improvement, giving a good match to the S- and Y-parameters and all important powersweep figures, including the linearity figure IM 3.
72
Chapter 5
Relation of New Model Parameters to Device Design
Having shown the capability of the model in Chapter 4, we will now take a closer look at
the extracted model parameter values for the new elements that have been added to the
device equivalent circuit model. We will examine these parameters in different devices.
We will investigate in particular the impact of the number of gate fingers, the unit finger
width and the total width of the device.
5.1 Output Resistance, R,t
The output resistance parameter is a fitting parameter that appears to simply compensate
for the overestimation of Rut in the intrinsic BSim3v3 model. The dependence of Rout
on unit finger width and number of fingers is shown in Fig. 5.1-1. It is inversely
proportional to the total device width, as can be seen in Fig. 5.1-2.
At RF, the BSim3v3 model overestimates the output resistance (as seen in section 4.2.1
and Fig. 4.2.1-1.). Looking at the DC comparison in 4.1, Fig. 4.1-2 shows that Rut is
lower for the BSim3v3 model, thus at DC, the model underestimates the output
resistance. The model, which does not include self-heating effects, lies between the DC
and the RF measured output resistance. The fact that the DC and RF measured output
resistance is different is not a contradiction! Fig. 5.1-3 illustrates a zoom of the output
characteristics around the DC bias point. If we were to increase Vds by AVsweep, in the DC
73
I
am =
--
9 -- -
I- - - - -
case, we would move along the solid curve. The increase in VdS increases the power and
thus temperature, which leads to more self-heating a smaller increase in current. If
instead we now have an RF sweep, the additional current for the same AVsweep is higher,
because the temperature of the device does not increase during the short RF sweep. This
is similar to a pulse measurement.
---
2500
16 fingers
-+- 20um finger width
-
5000
-
-
E 4000
0 3000
g 2000
0
-
E 2000
1500 * 10000
5 500-
urn finger width
-
CC 1000-
0-
0
I
0
+5
20
40
60
I
0
unit finger width [um]
0.1
0.05
1 / number of fingers
Fig. 5.1-1 Rout as a function of unit width (left) and number of fingers (right).
I
* 20um finger width E5 urn finger width A 16 fingers
4500-
4000350030000 2500*; 20000
c 1500 1000500 -
0
0.01
0.02
1 / total gate width [1/urn]
Fig. 5.1-2 Rout as a function of total device width.
74
0.03
I
0.15
I -
DC bias point
Modeled
....-
Measured DC sweep
Measured RF sweep
IAIRF
.
AVsweep
Fig. 5.1-3 Output characteristic around the DC bias point for the output resistance
measurement under RF and DC conditions
5.2. Gate Resistance, Rg
We would expect the gate resistance to be proportional to the ratio of finger width and
number of fingers. Shorter fingers result in a shorter gate and thus less resistance, which
makes Rg proportional to the unit finger width. Fingers in parallel result in gate resistors
in parallel, thus Rg is inversely proportional to the number of fingers.
In addition to this, we also expect a small constant resistance in series with the finger
resistance. It consists of two parts: device layout independent via resistance that results
from routing from metal4 to metal2. The second part will be the resistance from the
metal2 layer to the gate finger. It includes the contact resistance between metal 2 and
poly and the poly resistance up to the edge of the gate finger. This resistance ought to be
inversely proportional to the number of fingers, since for every two gate fingers there is
one contact, and more fingers means more resistors in parallel. Hence, we expect that:
75
R9
=Rvia +Rof
-+
nf
Rvia
[Eq. 5.2-1]
Rg0
nf
and Ronst are in units of Ohm. The resistance of the gate finger, Rgo, has units of
Ohm/length. We expect Rgo -s- to be the dominating term in Eq. 5.2-1, as long as the
nf
ratio of wg and nf does not become too small. In Fig. 5.2-2, the Rg is plotted against the
wg/nf ratio. We can see a constant slope of one for the data, indicating that indeed the
Rgo w
term is the dominating one in Eq 5.2-1.
nf
Keeping in mind that the probe resistance can be as high as 1.2 Ohm, and that the
simulations used a probe resistance of 0.8 Ohm, the value of Rg has an uncertainty due to
the probe resistance of about 0.4 Ohm. In addition, for small values of Rg, the impact of
Rg on the S- and Y-parameters is less significant, making it difficult to find the exact
value by optimizing.
+* 20um finger width -U-5 um finger width
-A-16 fingers
15
10
-
rm,
-C
E 10-
-
8 6-
2-
0)5-
0-1
0--
0
20
40
unit finger width [urn]
60
0
0.05
0.1
1 / number of fingers
Fig.5.2-1 Rg as a function of unit width (left) and number of fingers (right)
76
0.15
. 20 urn finger width 0 5 urn finger width A 16 fingers
100 -
A
10 -
E
0.110
1
0.1
0.01
unit finger width / number of fingers [um]
Fig. 5.2-2 Rg as a function of the ratio of unit finger width and number of fingers. The
line is drawn at unity slope.
-Ar140 120 -
200150
-
O 100
-
'E'
E 100-
$
S80 6040200
0
20um finger width -M-5 um finger width
---
16 fingers
S50f
I
20
40
unit finger width [urn]
0
60
0
'
0.05
0.1
0.15
1 / number of fingers
Fig. 5.3-1 Rb as a function of unit width (left) and number of fingers (right)
77
5.3 Body Resistance,
Rb
The body resistance, shown in Fig. 5.3-1, has an interesting behavior, which we will
understand by looking in more detail at the device layout. The resistance decreases both
with unit finger width and number of fingers. The layout of the 16x10 pm device is
shown in Fig. 5.3-2. There are body contacts surrounding the device. This leads to
different path lengths to the nearest contact location, depending on where in the device
area one starts. Furthermore, we can see that the contact density parallel to the gates is
much higher, so that we would expect to have a better conducting (i.e. lower resistance)
contact along these sides than along the sides perpendicular to the gates. In Fig. 5.3-3 we
see the body resistance as a function of the inverse of the body perimeter. The body
perimeter is the total length of the body contacting the active device area. The results
show that the body resistance is proportional to the body perimeter, which is emphasized
by plotting the product of Rb and the body perimeter. The product is nearly constant,
indicating that indeed both parameters are inverse proportional to each other.
78
..
....
.........
..
Fig. 5.3-2 Device layout for the 16x10 gm device. Shown are the p- and n-implants,
the poly-silicon gate (red lines), and contact holes (white squares) from the metall
layer. The body contacts are shown in blue.
Anf=16 *wg=Sum
*wg=20um
*32xlOum
Anf=16 Owg=5um *wg=20um
200'
20000-
180
160140
120
18000 16000140001200010000
2.100
$ 8060
8000-
*
16000
A
40-
4000 -
W3 2x10um
+
% A
2000
0
20
0,
0
0.005
0.01
0.015
0.02
0.025
11 body perimeter [1/um]
0.03
0.035
0
50
100
150
200
250
300
body perimeter (um]
Fig. 5.3-3 (left) Body resistance as a function of the inverse body-contact perimeter,
(right) Body resistance - perimeter product, illustrating the inverse proportionality of
Rb and the body perimeter.
79
5.4. Inductances
The inductances take not only the line inductances of the intrinsic device portion into
account, but also the metal line and via inductance from the pad to the device layer. This
is because our de-embedding mainly removes parallel (i.e. capacitive) effects, but not
serial elements such as inductors or resistors. Therefore, to understand the behavior of the
inductance values, we will need to first know more about the dimensions of the metal
interconnect lines. The signal is routed from the pads to the device on the metal4 layer.
We will now describe the geometry of these lines:
For clarity, the layout is reproduced in Fig. 5.4-1. There are two source lines of constant
width of 5.1 gm and a line of length of
isource
= 155pm - 0.98pm -(n+1)
[Eq. 5.4-1]
The gate and drain lines are identical shapes between the pads and the device. The line
length is given by
,gatedrain- 33-m --
w
2 p
[Eq. 5.4-2]
The width is roughly proportional to the number of fingers, with an upper limit of 4Ojim.
80
Wgate,drain
=min(lM
m -nf ,40pm)
[Eq. 5.4-3]
The metal4 lines described by Eqs. 5.4-1 to 5.4-3 are only a part of the total inductance,
which is also influenced by the vias, and the metall and metal2 lines that route the
signals to the device contacts.
For the discussion of each inductance we will state how the inductances should behave
with the layout. However, the data often deviates, showing different behavior than what
we expected. One example are the drain and source inductance values. The drain and
source layouts in the intrinsic device are identical, and the source has a much longer and
thinner metal path to the pads than the drain. Yet, in the data, the drain inductance is
often twice as much as the source inductance.
In Fig. 5.4-3, we trade off the drain and source inductance. As we can see, the relative
error is very small, making it difficult for the optimizer to find exact values. In fact,
looking at the sum of all three inductances, we can see in Fig. 5.4-2 that their sum stays
roughly independent of the device layout. We believe that the optimizer was not capable
of finding the exact inductance values. This is possible to see in the next three sections,
when the behavior of the individual inductances is described.
81
M
Fig. 5.4-1 Device layout for the 16x10 pm device. Shown are the metal layers (blue:
meatli, red: metal2, green: metal4) and the metall to device contact holes. Left:
Complete picture, including probe-pads, right: close-up on the device. The gate is
coming in from the middle left pad, the drain from the middle right pad. The four top
and bottom pads are the source, coming in to the device from the top and bottom.
*20 um finger width E5 um finger width A 16 fingers
250-
250-
U
200-
200150 -
150 -
-
100-
M #
+
A
+
3
+20 um finger width E5 um finger width A 16 fingers
A
S100-
50-
500
0
0
10
20
30
40
unit finger width [um]
50
0
0.05
0.1
0.15
1 / number of fingers
Fig. 5.4-2 The sum of the inductances as a function of unit finger with and the inverse
of the number of fingers. The sum is roughly independent of the layout.
82
S11
S12s
and S22
1
21
~9Snm~akx
sI M....M
S14
£22 ShMb"
~MOMIeI
U,
freq (500.0*wIr to 20.00GHZ)
freq (500.OtI-. to 20.00GHZ)
freq (500.0MI- to 20.00GHz)
Y12
Y11
1
1E-2-
1E-
E
1E-2-
1&3-
1&-4-EA
1E3-
$ 1E-4-
1E-5-
1E-61E10
1E9
2E10
freq, Hlz
--
i.m
- -Re
(I
1E1O
1E9
....
2E10
freq, Hz
iMftu~e
Y22
Y21
6E-2
1EL1
2E-1
3E-
wqwIEIIE,
1E-2-
1E1 1E-2
1E3-
-1E-3
1E-4-
I
-1E2
1E-2
1E-5
1E10
1E9
2E10
i
i
1E9
i
1E10
.
2E1D
freq, Hz
freq, Hz
Fig. 5.4-3 S- and Y-parameters for different values of L and Ld, while keeping Ls+La1
constant. The device is the 16x20 gm biased at Vgs=1.4 V, Vds=2.0 V. The values are
L=22 pH + AL, Ld=100pH - AL with AL of range ± 10 pH.
-A100
-+-20um finger width --
16 fingers
100 80 S 604020
-
80Z
60-
0>
4020
5 um finger width
-0
-
0-
00
40
20
unit finger width [urn]
60
0
0.05
0.1
0.15
1 / number of fingers
Fig. 5.4.1-1 Lg as a function of unit width (left) and number of fingers (right)
83
5.4.1. Gate Inductance, Lg
When we increase the unit finger width, while keeping the number of fingers constant,
two parameters change that have an influence on the total gate inductance: the unit finger
width, and the metal4 line length. Increasing the unit finger width should decrease the
inductance due to added parallel inductances in the gate fingers. At the same time, the
metal4 line is shortening, leading to a decrease of its inductance. In Fig. 5.4.1-1 we see
that the gate inductance decreases with unit finger width.
Fig. 5.4.1-1 also shows the gate inductance as a function of the number of fingers.
Scaling in this dimension, we would expect a decrease with the number of fingers. If we
look at the layout, the metal4 line has approximately the same size as the device. This
makes the layout is symmetric, and we can slice the layout into periodic sections of 2
fingers, as shown in Fig. 5.4.1-2. Thus, adding more fingers means to have a complete
structure added in parallel, and thus the inductance should decrease. The discrepancy
observed is due to the difficulty in optimizing the inductance values as mentioned in 5.4.
to pad
metal4
via
gate
Fig. 5.4.1-2 Layout sketch of the gate structure. The periodic structure of 2 gate fingers
is indicated by the lines
84
5.4.2 Drain Inductance, Ld
The drain inductance is shown as a function of number of fingers and unit finger width in
Fig. 5.4.2-1. We would expect the same layout dependencies as the gate inductance
previously. Increasing the gate width leads to a shorter metal4 line length, and to a lower
finger inductance. Increasing the number of fingers should lead to the same parallel
behavior as shown in Fig. 5.4.1-2. However, this behavior is not observed in Fig. 5.4.2-1.
Again, we believe this is due to the difficulty in optimizing the inductance values as
mentioned in 5.4.
-i-16 fingers
-+-
Ld, 20um finger width
--
Ld, 5 um finger width
120100~
200-
80.
_,
60-
150-
r' 100-
40-
50 -
20-
0
0~
0
20
40
unit finger width [urn]
60
0
0.05
0.1
0.15
1 /number of fingers
Fig. 5.4.2-1 Ld as a function of unit width (left) and number of fingers (right). Also
shown is the difference between Ld and Lg
85
5.4.3. Source Inductance, L,
The source inductance as a function of number of fingers and unit finger width is shown
in Fig. 5.4.3-1. The sketch in Fig. 5.4.3-2 shows how we expect the dependencies on the
layout to be. The overall metal line is constant. This means that the fingers have to be
added from bottom to top in the schematic, keeping the source metal line constant. Thus,
additional fingers will result in adding inductors in parallel and decreasing the source
inductance. Similarly, a wider unit finger width leads to lower finger inductances, also
decreasing the overall inductance. These dependencies are observed in Fig. 5.4.3-1.
-,-16
finger width -U-5 um finger width
+20um
fingers
40-
80-
30 -
60-
S20-
S40-
10-
S2000
20
40
unit finger width [um]
60
0
0.05
0.1
1 / number of fingers
Fig. 5.4.3-1 L, as a function of unit width (left) and number of fingers (right)
86
0.15
..........
to ads
source metal
AAA
AAA
AAA
source fingers
Fig. 5.4.3-2 Simplified sketch of the source inductances. As more fingers are added, the
overall inductance decreases because inductors are added into the source metal line in
parallel.
5.5. Gate-to-Drain Capacitance, Cgd
Fig. 5.5-1 shows the dependence of
Cgd
on unit finger width and number of fingers. It is
difficult to make out a clear layout dependency from these graphs, because of the up and
downward shaped curves. However, if we plot the data vs. the total device width, Wg, we
can see that at least up to Wg = 320 gm, Cgd is proportional to the total device width. The
reason why this is not seen also for the very wide devices at Wg=640pm and 1280pm is
that the impact of Cgd on the Y-parameters is decreasing as the device gets wider. The
primary impact of Cgd is on Y 12 . Fig. 5.5-3 shows a comparison of Y12 for the 16x05
sm
and the 128x05gm device, for various values of Cgd. We can see that the relative
uncertainty is much larger for the 16x05pm device. In fact, for the 128x05 gm device, the
87
I &-,1ti11
M~~~~~11
E
-
relative uncertainty is so small that for the optimizing algorithm, Cgd appears as a
parameter with almost no influence. This will cause the parameter to drift somewhat
randomly around its initial value during the optimization, which can be seen in the spread
of Cgd as the device gets wider.
-4-20um finger width --
-h-16 fingers
25
-
40-
20
-
S30 -
15-
5 urn finger width
20 -
0
0 10
00
60
40
20
0
unit finger width [um]
0.1
0.05
1/ number of fingers
Fig. 5.5-1 Cgd as a function of unit width (left) and number of fingers (right)
+20 urn finger width E 5 urn finger width A 16 fingers
35-
30-
M
25-
2015-
1050~
0
200
400
1000
800
600
total device width [urn]
Fig. 5.5-2 Cgd as a function of total device width
88
1200
1400
0.15
Y12
Y12
1E-1
1E-1
1E-2-
1E-2-
IE-3-
1E-3-
1E-4-
1 E-4 -
1E-5-
1E-5-
1 E-6 -
E-6
1E10 2E10
1E9
freq, Hz
1E10 2E10
1E9
freq, Hz
Fig. 5.5-3 Y12 for the 16x05 gm (left) and 128x05 gm (right) device, for different values
of Cgd between 10 and 55 f. The relative impact of Cgd on the 128x05 pm device is
very small, explaining why for wide devices, Cgd does not follow the observed line in
Fig. 5.5-2.
5.6. Summary
We have explained the physical origins of the new model parameters. The parameter
values were linked to the unit finger width and number of fingers, to show their
dependence on these two dimensions. The elements were found to be a function of
different layout characteristics, such as total device width (ROt, Cgd), unit finger width
(Rg), number of fingers (Rg), body perimeter (Rb). The sum of the inductances was found
to be independent of the device layout.
89
90
Chapter 6
Conclusions
6.1. Conclusions
We have characterized the 0.25 m CMOS technology from TSMC for RF power
applications. Based on the TSMC BSim3v3 device model for this technology, we
successfully built a large signal model that enables us to accurately model the RF power
performance of the devices. The BSim3v3 model without adding the new elements would
yield poor RF power modeling results.
The values of the new model elements are found through matching the simulations with
S-parameter measurements, without the need of an actual load-pull measurement. Having
built the model on S-parameter small signal measurements, we showed that the model
also gives excellent predictions of the load-pull characteristics at 2.45 GHz, including the
figures Pout, Gain, Id, PAE and IM3 as a function of Pi.
Explanations of the origin of the new model elements have been given, looking at how
the parameter value changes, as the device is either scaled in number of fingers or unit
finger width. Finally, a physical explanation for the observed changes was given, based
on the device layouts.
91
6.2. Suggestions for Future Work
An ideal model should be valid for a broad range of biasing conditions, and the model
parameters should be possible to be obtained from device dimensions and processing
parameters. Currently, the model parameters are optimized to match the S-parameter
measurements, at a single bias point that was also used for the power characterization. In
order to achieve the goal of bias independence and analytical expressions for the model
parameters, more work has to be done. This will involve a more extensive mapping of the
parameters for different bias points, as well as trying to get rough analytical expressions
for the new model parameters.
It would be interesting to study the impact of the device layout, and the body contact
location in particular. This would involve developing a model that connects the RF power
figures of merit with the device layout. Breakdown measurements for devices of various
dimensions may give further insights, especially when studying the body contact
locations.
The model described in this thesis matches the load-pull measurements very closely. In
order to validate the model for power amplifier design, one could compare a load- or
source impedance contour plot, to see how well the model performs in regions of greater
impedance mismatch. If the performance is adequate, one can use the model to design a
power amplifier to the specifications of various wireless applications. To find the biasing,
power levels and impedances, either the traditional load-pull method can be used (using
92
load-, source-pulls and power-sweeps to approach the optimal point), or more preferably,
one can use the ADS algorithms to find the best point by optimization.
The load-pull measurements in this thesis were done only at 2.45 GHz. The model
accuracy is roughly constant over the measured range up to 20 GHz. It would therefore
be worth measuring at other frequencies (around 900 MHz and 5 GHz) and to compare
load-pull measurements at those frequencies with what the model would predict. Because
the S-parameter model is uniformly accurate, we have all reason to believe that the loadpull accuracy at other frequencies would be similar to the one demonstrated in this work.
It would be interesting to use the model developed to design and build a power amplifier.
This should also help demonstrate the accuracy of the model.
Another path to investigate would be the RF power performance of the devices for
possible changes in processing parameters. This could be done through sweeping
parameters of the BSim3v3 model that have a direct connection with the processing
conditions, and registering their impact on the simulated device performance. The
difficulty here is that it requires a very good knowledge of the process itself, which may
be hard to obtain.
Testing the model against other generations (for example, the 0.18 tm technology) would
help to verify that the model is universally applicable, and that it is not just tailored to the
devices measured in this thesis.
93
Finally, we believe that with the model proposed in this thesis, it should be possible to
design a power amplifier without the need of performing large-signal measurements.
Only DC- and S-Parameter characterization will be necessary to determine the value of
the model elements.
94
Appendix A
This appendix shows the S- and Y-parameters of the 16x20 Pm device biased at Vgs=1.4
V, Vds=2.0 V. The model used in the simulation has optimized parameter values. Each
figure shows one of the new elements swept from 1/3 to 3 times its optimal value.
812
S11 and 822
S.N
gr
S21
2
-P
freq (500.0M-tz to 20.00GI-e)
f req (500.0rI-k to 20.O0G~i-)
Y11
5-1
-
1
aama
freq (500.0-k to 20.00Gl-e)
Y12
IE-2-
1-1 PP~
15-2-
1E-31E-4-
1-3-
2E1&2
15-4-
1E5-I1E-6-
I
1E10 2E10
25110
1E10
1D
freq, Hz
Y22
freq, Hz
Y21
2&61
151-
5&-2
1
415-I1E-2 -
'1
I
-15-2 Zca
15-2-
1E60
1E6
freq, Ht
15-3-
-1-2
I5-4 1E10
2E1
2E10
freq, Ht
4
Fig. A-1 Parameter sweep of R0 ut for the 16x20 gm device model biased at Vgs=1.
V, Vds=2.0 V
95
$11
S12
and 822
--E3-
sh-won
821
Maaen
S3i6Md
S22l
-- }-p-
16
0
freq (500.0iz to 20.00GHz)
freq (500.0Miz to 20.00GHz)
f req (500.0AIz to 20.00GHz)
Y12
Y11
IE-1
1
1-2-
1E-1-
1&3-
1-2-
1E-4-
15-3-
E1&51&.4-
1-6-
1F-5 -
1E'10 2E10
3-1
-
- -
M
+< InmY"
-s-V-
freq, Hz
Y21
2E-1
-
16
"
R-IIY
1E10
2E1 0
freq, Hz
Y22
R..imim
M...."'
1-1
RF&2
10 1
1&.1-
-1-2-
-1-2
1-3-15&2
1E-2-
15-4-1-3
1E9
1E10
freq, Hz
1E10
2E10
2E10
freq, Hz
Fig. A-2 Parameter sweep of Rg for the 16x20 gm device model biased at Vgs=1.4
V, V&=2.0 V
96
$11 and S22
-g-
I~1
2
S12
6I
821
_-_Simmae
-L-uzZ4t
SshImhn
0,
S
~bS
~
/
/
.77/
freq (500.0%t to 20.00GHz)
freq (500.0Niz to 20.00GHz)
freq (500.0N-z
to 20.00GHz)
Y12
Y11
1
1E-2
15-2-
1&1-
15-315
1-2-
15-4-
1-3-
-iif
2
15.4-
15&6-
-I
t-n
15-5-
-+--
1E'10 2E00
ia.
freq, Hz
Y21
2&1
1E-1
1&1-
2E10
freq, Hz
Y22
_____2F-1
2&1
1E10
i.. 6 jmj.S--..
+:.m
T-x--
85&2
15&1
1&2-15.2
15.2-
i
1&3-1E.2
1E&4-
-1&.3
11E60
2E1
freq, Htz
Fig. A-3 Parameter sweep of Rb for the 16x20
V, Vds=2.0 V
1E10
2E10
freq, Hz
sm device model biased at Vg,=1.4
97
$12
$11 and $22
f-t(-- SnM.O,
--- S22
S21
_
W-W--emmant
ou
-
-_
~VT
f req (500.ON1-z
freq (500.0Wft
f req (500.Obz to 20.00GHz)
to 20.OOGl-z)
to 20.00GHz)
Y12
Y11
15.1
1
1E-2-
1&-1-
E1&3-
1E-2-
1&4-
1-3-
1-5-
1E-4-
1-61E60 2E10
1E9
1E10 2E 10
freq, Hz
Y22
freq, Hz
Y21
9-2
3-1
1&1-
1E-3-1E-2 2
1&2-
-1-2
15-4
1E10
f req, Hz
2E10
10E
1ED
2E10
freq, Hz
4
Fig. A-4 Parameter sweep of Lg for the 16x20 gm device model biased at Vgs=1.
V, VdS=2.0 V
98
S12
S11 and 822
-s-
Co
swwaiw
I1
S
U2Is..
(
A
.
2
G
50 IQ
freq (500.Ov-Iz to 20.00GHz)
freq (500.0 -z to 20.00GHz)
treq (500.ONIz to 2000DGHZ)
sliN'
/k
Y12
Y11
1E-1
15-2-
15-1-
1-3-
~2. 1-2-
1--41-3 1E5-
1E-4-
1-6+-:-a
1E10 2E10
-*-
freq, Hz
Y21
i--
-- B- P.ImY)SI.wI
2&~
35&1
yMC
1E60 2E00
1E9
h..jmY)M.....
1
freq, Hz
Y22
7-2
1&115
1 1
1&1-
-1-2
1-2-
-15-2
-1-3
1E10
freq, Hz
I
1-3-
15-4-
I
Soo
1-2-
1E 1EI0 2E10
2E10
freq, Hz
Fig. A-5 Parameter sweep of L4 for the 16x20 gm device model biased at V,,=1.4
V, Vd1=2.0 V
99
SI1 and
-4-
Siu]ti
Si 12
S22
S21
Leazzz2
-1MhA"
-p- n MnWM
6
6
/
Y12
Y1 1
1E-1
1
1-2-
15-1 -
-3
freq (500.0I-Iz to 20.00GFIz)
freq (500.0f~z to 20.00GHz)
freq (500.0Iz to 20.00GHz)
1&21E-41&31E51&4-
1&62E10
+
mms-'""
3-1
4
0
E10
1E9
2E10
freq, HZ
Y22
freq, HZ
Y21
6-2
1-1
2E-1
15-1
0 0 4 4
15-2
1-1-
-
i
-15-2
1-2-
-
1--
-1-2
15-4_
0000 01
15-5
1E10
freq, Hz
1E10
2E10
2E10
freq, Hz
Fig. A-6 Parameter sweep of L for the 16x20 gm device model biased at Vg,=1.4
V, Vd,=2.0 V
100
S
2
S12
S11 and S22
-g
uiimS
21
LizJw~
-+K
4
--M- 50.Memmit
9,
15 /
f req (50Q.0FWiI-
freq (500.0Ntz
freq (500.Ohf- to 20.00GFtz)
to 20.OOGIk)
to 20.00G~z)
Y12
Y11
15.1
16
1&2-
15.1-
E1-315&21&.4-
1531-4"I L-n 1,
15-6.
1E10
-B- R*.Y
freq, 1-k
15.1
_____2&1
0
wove
2E1C
freq, Hz
Ii m..E
Y21
25&1
1&.1-
10
1E91E
2E10
Y22
.
. 5&.2
IE-1
1-2-
i
1-3-1&2 E3
1&E2-
-1&.2
15-4-
11 r-
1E10
freq, HFt
a
I
II-
r-%
1E10
2E10
2E10
freq, Hz
Fig. A-7 Parameter sweep of Cgd for the 16x20 pm device model biased at Vg,=1.4
V, Vd1s=2.0 V
101
102
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