by Mark Adamiak, General Electric , USA
Synchrophasors
Wide Are Monitoring
32
I see Synchrophasor
technology as
"LAZER"
of the utility
industry
Synchrophasors...
in the beginning,
( as I remember it )
This was the beginning, but the
technology is still in its infancy.
The transition of power system protection
from electromechanical and static techniques to digital can
best be described as an evolution of computer hardware,
concepts, and algorithms. The original concept of using a
computer to protect power lines can be traced to George
Rockefeller’s master’s thesis back in 1969. Starting around
1970, Westinghouse (yes, they used to make relays) started
a research project to demonstrate the ability of a computer to
capture waveform data, process it, and make a decision. In
this same time frame (1971), there was interest in American
Electric Power and General Electric (1975) to explore similar
uses of computers for protection and control. The original
AEP effort was a joint effort with IBM who, as owners of the
main frame, had just recently introduced the concept of the
mini-computer. For this project, IBM provided their System
1 AEP System Map
The old map, displaying the major AEP locations
Captured
data was used
to examine
Marysville Substation
instantaneous phase
angles
between
Rockport Substation
Rockport and
Marysville
PAC.AUTUMN.2007
7 minicomputer (Fig.2). This machine was 1.2 m square
and stood about 1.6 m high. The minicomputer was leading
edge technology for its day – having 128kb of memory and
a “huge” 10MB hard disk. The machine was programmed
via punched cards (key punch machine visible on the right
of Fig. 2. What was most unique about this implementation
was that this computer was fitted with a high-speed
modem, which was capable of communicating with an IBM
mainframe at the blazing speed of 600 bps (the rest of the
world was still communicating at 300 bps). A 12-bit A/D
converter was interfaced with the machine and voltage and
current waveforms were isolated, filtered, and sampled at 12
samples per cycle. The original AEP processing algorithm, as
developed by Arun Phadke, Ted Hlibka (Fig. 2), and Mohamed
Ibrahim was a least squares estimate of the voltage and current
phasors which then fed into a fault calculation process.
In 1972, the completed system was installed on the
AEP system in Appalachian Power Company’s Matt Funk
substation. The computer monitored voltages and currents
on the Matt Funk – Glen Lynn 138kV line. A software
disturbance detector, when triggered, would force a capture
of the samples of voltage and current immediately before and
after the trigger. The captured file could be uploaded via the
modem (an overnight exercise) to an IBM mainframe located
at AEP’s then headquarters at 2 Broadway in New York City.
The uploaded file was then massaged using the Tektronics
Plot10 software and plotted on a Calcomp flatbed plotter
– effectively the worlds first digital fault recorder.
As computer hardware and performance improved,
work on enhanced algorithms at AEP followed right
behind. Specifically, the Digital Equipment Corporation
(DEC) introduced the PDP 11/70, which became the “next
generation” hardware platform for AEP’s digital relay research.
It was on this platform that the Fourier Transform was first
introduced as the mechanism for computing the Voltage and
Current phasors that were used in the calculation of distance
to fault. Additionally, it was also on this platform where
the concept of a Symmetrical Component Distance Relay
was introduced. Test data for the algorithm was provided
by a low-power model power system that was capable of
“continuous” short circuit currents. The system could be
configured for multiple voltage levels, line lengths, and bus
33
configurations. Voltages and currents were measured using
isolated voltage dividers and current shunts (nichrome wire)
respectively. The low-level signals (+/-10V) were filtered and
fed into a multiplexed A/D converter (DEC ADF-11) which
had Direct Memory Access (DMA) directly into the memory
of the 11/70. The voltages and currents were sampled at
720 samples per second – resulting in a sampling angle of 30.
This sampling angle was chosen as the Fourier coefficients
for Sine and Cosine were 0, +/-1, +/-0.5, and +/- 0.866.
Multiplication of these coefficients with the sampled data
values was fairly simple – except for the value of 0.866. This
multiplication was implemented by scaling the input signal
by 0.866 in hardware and sampling the signal a second time
as the A/D converter was faster than an accurate multiply.
The PDP 11/70 computer was a good proving ground
but in 1979, it became time for the next step – development
of a system for a substation test. The hardware that was
identified for this migration was the Plessey Miproc
computer. The Miproc was an early Reduced Instruction
Set Computer (RISC) that was built around the “Harvard”
architecture of separate Program and Data memories. It was
in the migration of the distance algorithms to the Miproc that
the Synchrophasor was identified, specifically, when I was
working on the “memory voltage”. With memory voltage,
when a fault occurred, a one-cycle old phasor value of Positive
Sequence Voltage (computed by a Fourier algorithm) was
frozen and used as a direction check for 3-phase faults when
the positive sequence voltage collapsed to less than 10% of
nominal. During testing of the algorithm, I noted that after
the fault cleared and before the “frozen” value of voltage
was released, there was a measurable phase angle difference
between the frozen value and the most recent voltage phasor.
I brought this phenomenon to the attention of Dr. Arun
2 The Beginning
IBM System 7 Minicomputer & Key Punch Machine
Phadke at AEP and Dr. Jim Thorp (who was working part time
for AEP at the time). The ensuing analysis highlighted the fact
that, given the fixed sample rate of the system, the Fourier
phasor angle would rotate at a rate equal to the off-nominal
frequency of the power system. Specifically, if the power
system frequency was greater than nominal, the Fourier
phasor would rotate in the counter-clockwise direction, if
the frequency was less than nominal, it would rotate in the
clockwise direction, and if the frequency was precisely at
nominal, the phasor would stay at a fixed phase angle. In
the system on which this was discovered, the sample clock
was fixed and adjusted to 720 Hz (12 samples per cycle on
a 60 Hz system - 0.064%). Subsequent testing on the AEP
model power system (Fig. 3) confirmed the ability to calculate
frequency and rate of change of frequency.
The next step in the process came with the realization
by Phadke and Thorp that if the clock driving the A/D
converter/Fourier calculation was “common” throughout
a region, then “Synchronized” measurements could be
made over the region. This vision initiated a search for a
common clock source. The search began with the time
code transmitted from Fort Collins, CO known as WWVB.
WWVB is transmitted as a 60 KHz amplitude modulated
signal, however, it has no automatic correction for the
transmission time delay. Considering the 2000 miles from Ft.
Collins to New York City, there is a time delay of about 10ms.
Although a local correction could be applied, atmospheric
conditions always added a random time delay. LORAN C
was also considered but again, the accuracy wasn’t there and
Cesium clocks were not affordable for substation installation.
In parallel with the development of the Synchrophasor
concept, a new timing technology known as the Global
Positioning System (GPS) was beginning to appear. GPS
3 Development
Subsequent Testing on the AEP Model Power System
PAC.AUTUMN.2007
Biography
Mark Adamiak
received his BS and
ME degrees from
Cornell University
and MS-EE from
the Polytechnic
Institute of New
York. He worked for
American Electric
Power (AEP) in the
System Protection and Control
section, where his
assignments included R&D in digital
protection and
control, relay and
fault analysis, and
system responsibility for power line
carrier and fault
recorders. Since
1990 Mark is with
General Electric
and is currently an
Advanced Technology Programs
manager.
Synchrophasors
Wide Are Monitoring
34
was a satellite based timing system where time and orbital
location information from multiple satellites were received by
a single receiver. The receiver could then accurately compute
time and location. GPS promised sub-microsecond absolute
time accuracy over the entire earth. The first GPS satellite
was launched in 1978 and by 1985, there were 11 satellites
in orbit – enough for at least 12 hours of daily visibility. This
was the timing source that we needed.
In the1987/1988 time frame, work began at Virginia Tech
(where Dr. Phadke had relocated) in conjunction with AEP on
a system to compute synchronized phasor measurements on
what was originally known as a Phase Angle Measurement
(PAM) unit the name of which has since transitioned to Phasor
Measurement Unit (PMU). Demonstration sites were chosen
in AEP’s Marysville and Rockport 765kV substations. The
first PMUs were built on a Motorola 68020 VME system. The
system consisted of a VME chassis, a power supply, and a 16
channel A/D converter. An external signal processing system
provided signal conditioning, surge suppression, and Anti
Aliasing filtering. The A/D converter was synchronously
triggered by an Odetics GPS clock at 720 samples per second.
The synchronized phasors were then computed through a
Fourier transform with the goal of streaming the phasors from
a substation to a central location.
The substation to headquarters communication channel
available on the AEP system in 1988 was a 4800 bps
link through the AEP analog microwave system. Given
this bandwidth, optimization of the packet carrying the
synchrophasors was paramount. The obvious format was the
4 Ye Old PAM Data
Frequency and phase angle plot
use of binary-formatted data to transmit the synchronized
phasors and system frequency (even Arun Phadke had to
agree…). For this first installation, a streaming rate of 12
packets per second was chosen with a packet content of
positive sequence voltage and system frequency – which just
fit into the 4800 bps bandwidth.
The packet needed to contain an absolute “time stamp” in
order to uniquely identify the received packet in time. The
first time stamp implementation was based on the wellknown format of: Year-Month-Day-Hour-Minute-SecondSample count. Paul Sorenson (then at AEP) was asked to
create a Phasor Data Concentrator on a PDP 11/73 computer
that had multiple serial ports and a 100MB disk drive (which
was quickly migrated to a DEC MicroVAX). It was explained
to Paul that he had to align each received packet based on
the Year-Month-Day-Hour-Minute-Second-Sample count
field. As he tried to implement the alignment algorithm, he
found that sorting on so many fields was problematic. Paul
then made the suggestion to use the Network Time Protocol
(NTP) Second of Century field, which was a 32-bit integer
count of seconds since January 1, 1900 which (Note: this
was changed in the C37.118 revision of the Synchrophasor
standard to January 1, 1970 providing time stamping until
the year 2106). This change enabled the PDP computer to
capture two simultaneous streams of data at 12 packets per
second and store them to disk – effectively the worlds first
Phasor Data Concentrator - PDC.
The two units were installed in the field in late 1988 and
began streaming data into the Columbus, OH PDC. Captured
data was used to examine instantaneous phase angles
between Rockport and Marysville – which were subsequently
validated against state estimation data. Additionally, plots
were made of frequency and phase angle (Fig. 4). These units
remained in service for over a decade – at which point in
time, newer units and higher-speed communications became
available.
As more PMUs are installed around the globe, more data
will be available, and more and more applications will be
envisioned and developed.
The ultimate vision
is a completely monitored
power system that
dynamically detects
and controls all aspect
of the largest machine in
the world –
the electric power grid.
PAC.AUTUMN.2007