Berkeley
The ABC’s of PA’s
Prof. Ali M. Niknejad
U.C. Berkeley
c 2014 by Ali M. Niknejad
Copyright Niknejad
Advanced IC’s for Comm
Class A Review
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Class A Amplifiers
Class A amplifiers have a collector current waveform with
100% duty cycle. In other words, the bias current IQ > io ,
where io is the current swing.
The advantage of Class A amplifiers is high linearity, clean
sinusoidal waveforms (little harmonic filtering needed), and
simple design (not relying too much on transistor
non-linearity).
The disadvantage of Class A is low efficiency and maximum
power consumption at zero output power!
Dynamic Class A (modulate bias current) is an attractive
solution for some applications. Envelope following Class A
combined with dynamic Class A is even better.
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CE/CS Class A
VCC
RL
vo
vin
The CE amplifier has the advantage of higher power gain
(there is voltage gain and current gain).
The collector effciency is given by
ηc =
1
vo io
PL
1
= 2
= v ×i
Pdc
VCC IQ
2
The efficiency is maximized if we can set the voltage swing
and current swing independently.
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CE/CS Voltage Swing
VCC − VCE!sat
VCC
VQ,high
VQ,mid
VQ,mid
VQ,low
VCE!sat
VCE,sat
We see that to avoid clipping, we should bias the transistor at
the midpoint between VCC and VCE ,sat (or Vdsat ).
Thus
vo ≤
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VCC
2
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CE/CS Current Swing
IQ
0A
The current in the transistor cannot go negative. Therefore,
the maximum current is set by the bias current
io ≤ IQ
The efficiency is therefore limited to 25%
η =v ×i =
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1 1
×
2 2
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Optimum Load
It’s important to note that to achieve these optimum
efficiencies, the value of the load resistance is constrained by
the current and voltage swing
VCC
v
vo
=
Ropt =
io
IQ
i
Since the load resistance is usually fixed (e.g. antenna
impedance), a matching network is required to present the
optimum load to the amplifier.
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Inductor Loaded CE/CS
VCC
RF C
C∞
vin
vo
RL
If we AC couple a load RL to the amplifier, then the Q point
of the amplifier collector voltage is set at VCC through the
choke inductor.
The maximum swing is now nearly twice as large. Notice that
the collector voltage can swing above the supply rail.
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Swinging both ways...
VCC
+
+
VCC
−
VCC
−
+
VCC
−
vin
vo
RL
Recall that the voltage polarity across the inductor is given by
dI /dt, which can go negative. Thus the collector voltage is
equal to the supply minus or plus the absolute voltage across
the inductor.
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Improved Class A Efficiency
Since the swing is almost double, the efficiency now
approaches 50%
vo ≤ VCC
η=
1 io vo
1
≤
2 VCC IQ
2
In practice, due to losses in the components and back-off from
maximum swing to minimize distortion, the actual efciency
can be much lower.
Package parasitics (see later slides) also limit the voltage
swing.
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Complete Class A Output Stage
VCC
Lres
Cm
vo
vin
Lm
Cpar
R0
In practice the collector inductor can double as a resonant
element to tune out the collector parasitics.
The coupling capacitor Cc can be replaced by a matching
capacitor Cm .
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Class A Power Capacity
A good metric when comparing PA’s is to measure the output
power versus the peak voltage and current stress imposed on
the device
These peak stresses are set by breakdown considerations. For
Class A operation, we can apply
PC =
Pout
Vmax Imax
Vdrain,max = 2VDD
Idrain,max = IQ + IL = 2IQ
1
Pout = VDD IQ
2
1 1 1
1
PC = · · = = 0.125
2 2 2
8
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Emitter Degeneration
VCC
Emitter inductance has a
detrimental effect on PA
efficiency since it reduces the
swing. The voltage across
the emitter is given by
VE = jωLE io
RF C
C∞
vin
vo
RL
+
VLE
−
For a current swing of 1A at 1 GHz, a typical parasitic
inductance of 1 nH will “eat” up 6.28V of swing! We need to
reduce LE or to use a much higher VCC .
In practice both approaches are taken. We choose a
technology with the highest breakdown voltage and the
package with the lowest LE .
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Class B PA’s
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Class B
+
vin
−
vbias
VCC
The above circuit utilizes two transistors. Each device only
delivers a half sinusoid pulse and the full sinusoid is recovered
by phase inversion through the transformer.
The base and collector bias voltages come from the
transformer center tap. The base (or gate) is biased at the
edge of conduction (threshold).
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Class B Waveforms
vc (t)
ic (t)
VCC
p(t)
0V
Since the voltage at the load is ideally a perfect sinusoid, the
voltage on the collectors is likewise sinusoidal.
The power dissipated by each transistor is thus the product of
a sine and a half sine as shown above.
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Class B Efficiency
The average current drawn by each transistor is given by
1
IQ =
T
Z
0
T
Ip
ic (t)dt =
T
Z
0
T /2
Ip
sin ωtdt =
2π
Z
π
sin θdθ =
0
Where Ip is the peak voltage drawn from the supply.
The peak current drawn from the supply is just the load
current swing reflected to the collector, Ip = io × n.
vo
1 Ip
η=
2 2IQ
VCC
Note that the total DC current draw is twice IQ since both
devices draw current from the supply.
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Ip
π
Class B Efficiency (cont)
Since the collector voltage swing can be as large as VCC
(similar to an inductively loaded Class A), the efficiency is
bounded by
1 Ip
1 Ip
η≤
=
2 2IQ
4 IQ
π
η ≤ ≈ 78%
4
This is a big improvement over the peak efficiency of Class A.
Note that the average current naturally scales with output
power, and so efficiency drops more gracefully as we back-off
from peak power.
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Efficiency versus Back-Off
η(V )
sB
50%
s
cla
s
clas
A
VCC
The efficiency drops linearly as we back-off from the peak
output voltage
where vc is the collector voltage swing, which is just n times
smaller than the load voltage, vc = vo /n.
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Tuned Class B
VCC
RF C
vin
C∞
vo
RL
vbias
A tuned Class B amplifier works with a single devices by
sending half sinusoid current pulses to the load. The device is
biased at the edge of conduction.
The load voltage is sinusoidal because a high Q RLC tank
shunts harmonics to ground.
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Class B Tank
In a single transistor version, the “minus” pulse is in fact
delivered by the RLC tank. The Q factor of the tank needs to
be large enough to do this. This is analogous to pushing
someone on a swing. You only need to push in one direction,
and the reactive energy stored will swing the person back in
the reverse direction.
The average current drawn from the supply is the same as
before, IQ = Ip /π. The harmonic current delivered to the load
is given by Fourier analysis of the half pulse
Z π
Z π
1
1 − cos 2θ
2
Ip
sin θ sin θdθ = Ip
dθ
Iω1 =
2π
π
2
0
0
=
Ip
1π
Ip =
π2
2
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Class B Waveforms
vc (t)
ic (t)
VCC
0V
We see that the transistor is cut-off when the collector voltage
swings above VCC . Thus, the power dissipated during this
first half cycle is zero.
During the second cycle, the peak current occurs when the
collector voltage reaches zero.
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Class B Efficiency (again)
The efficiency is therefore the same
η=
1π
π
1 Iω1 vc
≤
=
2 IQ VCC
22
4
The DC power drawn from the supply is proportional to the
output voltage
VCC Ip
Pdc = IQ VCC =
π
vc
nvo
Ip =
=
Ropt
Ropt
The power loss in the transistor is given by
Z π
1
pt (t) =
Ip sin θ(VCC − vc sin θ)dθ
2π 0
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Transistor Power Loss
Integrating the above expression
π
VCC Ip
vc
(− cos θ − 2π
pt (t) =
2π
Ip
0
vc Ip
1
=
2VCC Ip −
π
2π
2
Ip
vc Ip
VCC −
π
4
vc Iω1
= IQ · VCC −
2
= Pdc − PL
=
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Class B Power Capacity
Recall the definition for PC
PC =
Pout
Vmax Imax
Vmax = 2VCC
Imax = Iout
Note that the output power is related to the fundamental
coefficient of a half sine wave, or 1/2 the peak
Iout
1
Pout = VCC
2
2
PC =
Iout
1
2 VCC 2
2VCC Iout
= 0.125
Same as Class A
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Dynamic PA
Supply
DC-DC converter
Envelope
Cm
vo
Lm
vin
R0
Dynamic Bias
Envelope tracking supply and dynamic class-A
Efficiency always close to peak efficiency of amplifier (say
30%) regardless of PAR
Need a very fast DC-DC converter
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Class C PA’s
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Conduction Angle
Often amplifiers are characterized by their conduction angle,
or the amount of time the collector current flows during a
cycle.
Class A amplifiers have 360◦ conduction angle, since the DC
current is always flowing through the device.
Class B amplifiers, though, have 180◦ conduction angle, since
they conduct half sinusoidal pulses.
In practice most Class B amplifiers are implemented as Class
AB amplifiers, as a trickle current is allowed to flow through
the main device to avoid cutting off the device during the
amplifier operation.
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Reducing the Conduction Angle
ic (t)
ic (t)
vc (t)
vc (t)
The most optimal waveform is shown above, where a current
pulse is delivered to the load during the collector voltage
minimum (ideally zero)
As the pulse is made sharper and sharper, the efficiency
improves. To deliver the same power, though, the pulse must
be taller and taller as it’s made more narrow. In fact, in the
limit the current spike approaches a delta function.
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Class C
VCC
RF C
vin
C∞
vo
RL
Vbias < Vthresh
Class C amplifiers are a wide family of amplifiers with
conduction angle less than 180◦ . One way to achieve this is to
bias a transistor below threshold and allow the input voltage
to turn on the device for a small fraction of the cycle.
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Class C Linearity
Q
010
011
100
001
000
101
110
I 2 + Q 2 = A2
I
111
The Class C amplifier is very non-linear, and it is only
appropriate for applications where the modulation is constant
envelope. For instance, FM uses a constant amplitude carrier
and only modulates the frequency to convey information.
Likewise, any digital modulation scheme with a constellation
on a circle is constant envelope
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Polar Modulation
A(t)
C∞
B(t) cos (ωt + φ(t))
RL
A0 cos (ωt + φ(t))
Vbias < Vthresh
While the amplifier is a non-linear function of the input
amplitude, the Class C amplifier can be made to act fairly
linearly to the collector voltage.
By driving the amplifier into “saturation” in each cycle, e.g.
with a large enough swing to rail the supplies, then the output
power is related to the voltage supply. Collector modulation
then uses the power supply to introduce amplitude
modulation into the carrier.
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Class C Approximate Analysis
IDD
2y
IDQ
Assume current pulses are sine wave tips, conduction angle is
2y
−1 IDQ
y
=
cos
IDD cos y = IDQ
IDD
−IDQ + IDD sin θ IDD cos θ ≥ IDQ
iD (θ) =
0
otherwise
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Class C Average Current
To make the integral easy to calculate, change variables to
the range of y to 0.
IDC from supply:
Z 2π
Z
1
1 y
IDC =
iD (θ)dθ =
(IDD cos θ0 − IDQ )dθ0
2π 0
π 0
1
(IDD sin y − IDQ y )
π
IDD
=
(sin y − y cos y )
π
IDC =
IDC
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Class C Analysis (cont)
Output voltage is: VOM = Fund{−iD (θ)RL }
Since iD is an odd function, the Fourier series will only yield
sine terms
Z
Z
−2RL 2π
2RL y
VOM =
iD (θ) sin θdθ =
(IDD cos θ−IDQ ) cos θdθ
2π
π 0
0
VOM =
IDD sin 2y
2RL IDD y
(
+
− IDQ sin y )
π
2
4
IDD RL
VOM =
(2y − sin 2y )
2π
Note: IDQ sin y = IDD cos y sin y = IDD
2 sin 2y
DC power from prev page:
PDC = IDC VCC = IDDπVCC (sin y cos y )
Assuming that max swing ∼ VCC :
IDD RL
VOM ≈ VCC =
(2y − sin 2y )
2π
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Class C Efficiency
PDC ≈
2
2VCC
sin y − y cos y
RL 2y − sin 2y
Power to load (assuming VCC swing): PL =
Ideal Efficiency:
η=
2
VCC
2RL
PL
1 2y − sin 2y
=
PDC
4 sin y − y cos y
lim η(y ) = 100% (ideal class C)
y →0
η(π) = 50% (tuned-circuit Class A)
η(π/2) = 78.5% (single-ended Class B)
For small conduction angle current pulses approach
delta-function.
Many practical issues make Class C difficult to design.
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Power Capacity of Class C
0.4
Power Capability
Vdrain,max = 2VCC
0.3
Class A
Class B
0.2
= IDD (1 − cos y )
0.1
0.0
ID,max = IDD − IDQ
PC =
0
50
100
150
200
250
300
Conduction Angle
350
=
Po
2VCC IDD (1 − cos y )
1 2y − sin 2y
4π 1 − cos y
The power capacity of Class C is low at low conduction
angles. Peak is Class AB.
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Class D and F
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Class F Circuit
3ω0
ω0
RL
The above circuit isolates the fundamental resonant load from
the drain at the third harmonic, allowing the drain voltage to
contain enough third harmonic to create a more square like
waveform.
It can be shown that just adding a third harmonic boost the
efficiency from 78% (Class B) to 88%.
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Class F
ic (t)
vc (t)
Since it’s difficult to create extremely narrow pulses at high
frequency, we can take a different approach and attempt to
square up the drain voltage.
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Quarter Wave Class F
RF C
ℓ = λ0 /4
Z0
ω0
RL
In this circuit a quarter wave transformer converts the low
impedance at the load (due to the capacitance) at harmonics
of the fundamental to a high impedance for all odd harmonics.
Even harmonics are unaltered as they see a λ/2 line.
In theory then we can create a perfect square wave at the
drain of the transistor and thus achieve 100% efficiency.
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Ideal Class D Switching Amplifier
VDD
S2
RL
S1
If give up linearity, then we can create some intrinsically
efficient amplifiers using switches. An ideal switch does not
dissipate any power since either the voltage or current is zero.
By varying the switching rate, we can impart phase/frequency
modulation onto the load.
A real switch has on-resistance and parasitic off capacitance
and conductance.
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MOS Class D Inverter
VDD
RL
Switching amplifiers are realized with transistors operating as
switches. MOS transistors make particularly good switches.
The input voltage is large enough to quickly move the
operating point from cut-off to triode region.
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Class D Waveforms
VDD
vd (t)
id (t)
0V
The MOS drain voltages switches from VSS to VDD at the
rate of the input signal.
A series LCR filter only allows the first harmonic of voltage to
flow into the load. Since current only flows through a device
when it’s fully on (ideally VDS = 0), little power dissipation
occurs in the devices.
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Class D Efficiency
We can see that the efficiency has to be 100% for an ideal
switch. That’s because there is no where for the DC power to
flow except to the load.
The collector voltage can be decomposed into a Fourier series
VDD
(1 + s(ωt))
2
4
1
1
s(θ) = sign(sin(θ)) =
sin θ + sin 3θ + sin 5θ + · · ·
π
3
5
vd =
The load current is therefore
iL =
4 VDD
2VDD
sin θ =
sin θ
π 2R
πRL
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Class D Efficiency (cont)
The load power is thus
PL =
V2
iL2 RL
2 V2
= 2 DD ≈ 0.2 DD
2
π RL
RL
The drain current are half-sinusoid pulses. The average
current drawn from the supply is the average PMOS current
IQ =
Ip
2 VDD
= 2
π
π RL
PDC = IQ · VDD =
2
2VDD
= PL
πRL
As we expected, the ideal efficiency is η = 100%
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Class D Reality
As previously noted, a real Class D amplifier efficiency is
lowered due to the switch on-resistance. We can make our
switches bigger to minimize the resistance, but this in turn
increases the parasitic capacitance
There are two forms of loss associated with the parasitic
capacitance, the capacitor charging losses CV 2 f and the
parasitic substrate losses.
The power required to drive the switches also increases
proportional to Cgs since we have to burn CV 2 f power to
drive the inverter. A resonant drive can lower the drive power
by the Q of the resonator.
In practice a careful balance dictates the maximum switch
size.
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Differential Class D
f0
L1
C1
RL
VDC
+
vin
−
+
−vin
−
Differential circuit have a huge benefit in ICs. First they have
common mode rejection and also inject (ideally) less common
mode into the supplies. Makes system integration easier (e.g.
VCO pulling). Also differential allows higher swings on load
for a fixed supply, and less impact from bond-wire inductors.
Downside: Need a balun.
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Differential Class D Analysis
Assume a high Q tank so that the output current is sinusoidal
(phase φ will be computed)
iout = Io sin(θ + φ)
The voltage at the secondary of the transformer is given by
vo (θ) = nVDC s(t) − n2 Io Ron sin(θ + φ)
The fundamental component of the secondary load voltage is
given by
vL (θ) = RL iout = nVDC
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4
sin(θ) − n2 Io Ron sin(θ + φ)
π
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Class D Analysis (cont)
From the above relation, it’s clear that the voltage and
current are in phase (φ = 0)
Io =
1
4nVDC
πRL 1 + n2 RRon
L
Each transistor conducts a half sinusoid pulse (similar to
differential Class B), so it’s DC value is
id1,DC = id2,DC =
nIo
π
The DC power consumed is therefore
PDC = VDC (id1,DC + id2,DC ) =
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8n2 VDC
1
2
π RL 1 + n2 RRon
L
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Class D Efficiency
From the AC and DC power, we are now in a position to
calculate the efficiency
2
8n2 VDC
1
1
Pout = I02 RL =
2
πRL 1 + n2 RRon
L
η=
Pout
1
=
PDC
1 + n2 RRonL
Note that the switch on resistance is a key factor. We cannot
arbitrarily increase it due to CVf 2 losses.
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Estimating Switching Losses
We can estimate the switching losses by noting that the
device “on”-resistance is related to the device gds,lin = gm,sat
Ron =
ωT =
1
1
≈
gds
gm,sat
1
gm
=
Cgs + Cgd
Ron (Cgs + Cgd )
The total input power involves switching approximately
2Cgs + 2γCgs , where γ is a technology parameter relating the
drain-bulk capacitance to the gate-source cap. Take γ ∼ 1 for
an upper bound
2
2
2
Ploss = Ctot VDC
f = 4Cgs VDC
f = 4VDC
f
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1
ωT Ron
Class D Power Handling Capability
The power handing capability of Class D is given by
vdrain,max = 2VDD
idrain,max = nIo
PC =
Pout
η
=
≤ 0.159
2 · vdrain,max · idrain,max
2π
This compares favorably with Class A amplifiers.
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Class D−1
VDC
vs1
IDC
f0
IDC
vs1
is1
IDC
L1
is1
vs2
i1
C1
is2
RL
The “Dual” Class D amplifier (interchange voltage/current ⇒
square wave current, sinusoidal voltage, parallel LCR filter)
Chokes act like current sources. ZVS by “design” but only if
there is no device capacitance to begin with.
0
0<θ<π
vs1 =
4
− π IDC RL sin(θ) π < θ < 2π
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Class E
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Class E Amplifier
Switching PA like Class D but can absorb transistor parasitic
capacitance into load network. This allows the switch to
become very large (low on-resistance).
The load network is design to ensure zero switching condition.
Figures: “Class-E RF Power Amplifiers,” by Nathan O. Sokal,
Design Automation, Inc
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Switching RF Power Amplifier
Switching amplifier = LC network and a switch
Low Q
Source: Patrick Reynaert and Michiel Steyaert
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Switching RF Power Amplifier
Switching amplifier = LC network and switch
High Q
Source: Patrick Reynaert and Michiel Steyaert
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Switching RF Power Amplifier
Switching amplifier = LC network and switch
perfect Q
Source: Patrick Reynaert and Michiel Steyaert
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Switching RF Power Amplifier
Switching amplifier = LC network and switch
Source: Patrick Reynaert and Michiel Steyaert
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Switching RF Power Amplifier
Output power of Class E is low
Pout,E < 0.045
2
Vmax
RLOAD
Pout,A < 0.125
2
Vmax
RLOAD
Compare to Class A
0.35um technology, Vmax = 8V ⇒ Pout < 60mW at 50Ω
Source: Patrick Reynaert and Michiel Steyaert
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Class E Waveforms
CMOS Power Amplifiers for
Wireless Communication,
King-Chun Tsai, Ph.D.
Dissertation, UC Berkeley,
2007.
VDDπ
Lωo
Figure 6-3 Circuit configuration and characteristic
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waveforms of a Class-E PA
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Class E Issues
Problems with Class E include low power gain and large
voltage swings. The drain waveform can swing to more than
3.5 times the supply voltage. This means the transistors have
to be able to handle much larger voltages.
Efficiency for this class of PA is extremely good. Power
capacity PC < 0.107, much better than Class C low
conduction angle operation.
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will discuss the injection locking mechanism in greater details later in this chapter.
First GSM CMOS Class E
Use standard CMOS to achieve output power of 1W
Measured efficiency > 50%
Use cross-coupled devices to boost driver capability (requires
injection locking)
Figure 7-1 Schematic of the 1-W 1.9GHZ CMOS Differential
Class-E power amplifier
149
CMOS Power Amplifiers for Wireless Communication, King-Chun
Tsai, Ph.D. Dissertation, UC Berkeley, 2007.
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Output Matching
Use chip-on-board testing (avoid lead inductance)
Use a microstrip balun to convert from differential to
single-ended to drive antenna
Source: “A 1.9-GHz, 1-W CMOS Class-E Power Amplifier for
Wireless Communications,” King-Chun Tsai and Paul R. Gray
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RF CMOS Class-E PA
Implemented in a 0.18 um CMOS technology
Source: Patrick Reynaert and Michiel Steyaert
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Chip micrograph
Source: Patrick Reynaert and Michiel Steyaert
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Other Classes
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Class S
If the switching rate is much higher than the fundamental,
then amplitude modulation can be converted to pulse-width
modulation.
A low-pass filter at the output faithfully recreates the
envelope of the signal.
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Class S Amplifier
VDD
Amplitude
to PWM
RL
Class S amplifiers are commonly used at low frequencies
(audio) since the transistors can be switched at a much higher
frequency than the fundamental.
This allows efficiencies approaching 100% with good linearity.
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Pulse Density Modulation
RF Pulse Train
Mixer
PA
Filter
Pulse-density
modulation process
Inherent linearity
Improved efficiency in power backoff, but ...
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Pulse Density Modulation Process
AM process ⇒ Extra harmonics
Tradeoff between oversampling ratio and Q
Out of band spectrum
Efficiency
Noise shaping: digital ∆ − Σ
Conclusions
No major efficiency advantage with Q< 5-10
Linearity may be the compelling factor
(almost) pure digital implementation!
Need to run PDM process *as fast as possible*
Niknejad
Advanced IC’s for Comm