Berkeley
MOS Wideband Noise and Distortion Amplifier
Examples
Prof. Ali M. Niknejad
U.C. Berkeley
c 2014 by Ali M. Niknejad
Copyright Niknejad
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ching
propdback
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imum
e well
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from
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Wideband Noise Cancellation
BRUCCOLERI et al.: WIDE-BAND CMOS LOW-NOISE AMPLIFIER EXPLOITING THERM
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 2, FEBRUARY 2004
gro
is
B.
wh
trib
the
A.
Fig. 2. Matching MOSFET (a) noise and (b) signal voltage at nodes X and Y
for the amplifier in Fig. 1(c) (biasing not shown).
Take advantage of amplifier topologies where the output
thermal noise flows into the input (CG amplifier, shunt
feedback amplifer, etc).
Cancel thermal noise using a second feedforward path. Can
we also cancel the distortion?
is larger than 1 NEF, as discussed in the previous section. Let
us now analyze the signal and the noise voltages at the input
node X and output node Y, both with respect to ground, due
of the impedance-matching MOSFET.
to the noise current
and
,
Depending on the relation between
flows out of the matching
a noise current
MOSFET through and
[Fig. 2(a)], with
. This
current causes two instantaneous noise voltages at nodes X and
Y, which have equal sign. On the other hand, the signal voltages
at nodes X and
Y have opposite
sign [Fig. 2(b)],
the Klumperink, B. Nauta, “Wide-Band
Source:
F. Bruccoleri,
E.because
A. M.
is negative, assuming
. This difference
gain
in sign for noise
and signal
makes it possible
to cancel
the
CMOS
Low-Noise
Amplifier
Exploiting
Thermal Noise Canceling,” JSSC,
noise of the matching device, while simultaneously adding the
vol. 39,
Feb. 2004.
signal contributions
constructively.
This is done by creating a
new output, where the voltage at node Y is added to a scaled
Fig. 3. (a) Wide-band LNA exploiting noise canceling. (b) Elementary
Advanced
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implementation
amplifier
A plus adder (biasing not shown). (c) Matching
negative replica of the voltage at node X. A proper Niknejad
value for
Up
Th
by
ma
tha
dis
EF
Noise Cancellation LNA
Motivated by [Bruccoleri, et al., ISSCC 2002]
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130nm LNA Prototype
130nm CMOS, 1.5V, 12mA
Employ only thin oxide transistors
W.-H. Chen, G. Liu, Z. Boos, A. M. Niknejad, “A Highly Linear
Broadband CMOS LNA Employing Noise and Distortion Cancellation,”
IEEE Journal of Solid-State Circuits, vol. 43, pp. 1164-1176, May 2008.
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Measured LNA S-Parameters
Matches simulations well. Very broadband performance.
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Measured Noise Performance
Noise cancellation is clearly visible. This is also a “knob” for
dynamic operation to save current.
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Measured Linearity
Record linearity of +16 dBm for out of band blockers (at the
time of publication).
Linearity works over entire LNA band.
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Linearity Bias Dependence
As we vary the bias of key transistor, we simulate the effects
of process/temp variation. There is a 50 mV window where
the performance is still acceptable.
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LNA Distortion Analysis
TION CANCELATION DESIGN
59
R1
Vb1
Let’s assume that the drain current
is a power-series of the Vgs voltage:
V1
M1
gm’ current
Cs
Vx
id = gm1 Vgs +
C 12
Rs
The purpose of the “differential”
input is to cancel the 2nd order
distortion of the first stage (to
minimize 2nd order interaction):
M2
Vs
V2
Vb2
gm3 3
gm2 2
V +
V
2! gs
3! gs
R2
re 4.6: Circuit schematic to remove IM3 second-order interaction
0 − g0
00 + g 00
gmn
gmn
mp 2
mp 3
vin +
vin
00
2
6
urrent generated by gm of both transistors, similar to that by gm as well as
iout = ids,n +ids,p = (gmn + gmp ) vin +
00 currents are combined and
oise, is departing from each other. With C12 , gm
0 of both transistors,
or R1 in parallel with R2 . The current generated by gm
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Distortion Equivalent Circuit
MPLEMENTATION
68
R1
RL
Vb1
Vb5
C 13
V1
Vout
M1
Cs
Rs
M3
C 24
M2
Vs
M5
C 12
Vx
M4
Vx = A1 (s1 ) ◦ Vs + A2 (s1 , s2 ) ◦ Vs2 + A3 (s1 , s2 , s3 ) ◦ Vs3
V2
Vb2
Assume R1/R2 and RL are
small so that ro non-linearity
is ignored.
V1 = B1 (s1 ) ◦ Vs + B2 (s1 , s2 ) ◦ Vs2 + B3 (s1 , s2 , s3 ) ◦ Vs3
R2
Vb3
Vb4
V2 = C1 (s1 ) ◦ Vs + C2 (s1 , s2 ) ◦ Vs2 + C3 (s1 , s2 , s3 ) ◦ Vs3
Vx − V2
Vx
Vx − V1
Vs − Vx
+ im2 +
+
im1 +
=
ro1 independently through an external
ro2voltage sourceZx (s)
Zs (s)
erization, each transistor is biased
Vx − V1bias branch.VAC1coupling between
V1 −stages
V2was
ed through on-chip diode-connected
im1 +
=
+ poly resistor was
ented with the aid of capacitors
ro1C , C and C Z. Low-value
1 (s) silicide Z
12 (s)
for the resistors used in the schematic. Since a very high IIP is pursued, adding an
Vx − V2
V2
V2 − V1
=was avoided. Otherwise
+ the measured
im2for+50 ⌦ measurement setup
output bu↵er
ro2
Z2 (s)
Z12 (s)
Figure 5.1: Complete LNA schematic
13
24
Z1 = R1 ||
Zs = Rs +
s
3
y will be easily colored by the intrinsic distortion of the bu↵er circuit itself. Therefore
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ow load resistance of 60 ⌦ was adopted to facilitate the linearity measurement.
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1
sC1
Zx =
1
sCs
1
sCx
Drain Current Non-Linearity
Assuming that the gates of the input transistors are grounded
at RF:
0
00
gm1
gm1
2
3
im1 = − gm1 (−Vx ) +
(−Vx ) +
(−Vx )
2
6
g 00
g0
= gm1 Vx − m1 Vx2 + m1 Vx3
2
6
0
00
gm2
g
im2 = gm2 Vx +
Vx2 + m2 Vx3
2
6
Solve for first order Kernels from:
A1 (s) − B1 (s)
A1 (s) − C1 (s)
A1 (s)
1 − A1 (s)
+ gm2 A1 (s) +
+
=
ro1
ro2
Zx (s)
Zs (s)
A1 (s) − B1 (s)
B1 (s)
B1 (s) − C1 (s)
+
gm1 A1 (s) +
=
ro1
Z1 (s)
Z12 (s)
A1 (s) − C1 (s)
C1 (s)
C1 (s) − B1 (s)
gm2 A1 (s) +
=
+
ro2
Z2 (s)
Z12 (s)
gm1 A1 (s) +
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Simplified First-Order
At the frequency of interest, Z12 ∼ 0 and B1 ∼ C1
(Z1 (s) k Z2 (s)) + (ro1 k ro2 )
H(s)
Z1 (s) k Z2 (s)
A1 (s)
B1 (s) = A1 (s) =
Z1 (s)kZ2 (s)+(ro1 kro2 )
1+(gm1 +gm2 )(ro1 kro2 )
Zs (s)
1+
H(s) = Zs (s) 1 + (gm1 + gm2 )(ro1 k ro2 ) + (Z1 (s) k Z2 (s)) + (ro1 k ro2 )
Zx (s)
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Second-Order Terms
Retaining only 2nd order terms in the KCL equations:
gm1 A2 (s1 , s2 ) −
gm2 A2 (s1 , s2 ) +
gm1 A2 (s1 , s2 ) −
gm2 A2 (s1 , s2 ) +
0
gm1
2
0
gm2
2
0
gm1
2
0
gm2
2
A1 (s1 )A1 (s2 ) +
A1 (s1 )A1 (s2 ) +
A1 (s1 )A1 (s2 ) +
A1 (s1 )A1 (s2 ) +
A2 (s1 , s2 ) − B2 (s1 , s2 )
ro1
A2 (s1 , s2 ) − C2 (s1 , s2 )
ro2
A2 (s1 , s2 ) − B2 (s1 , s2 )
ro1
A2 (s1 , s2 ) − C2 (s1 , s2 )
ro2
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=
=
+
+
A2 (s1 , s2 )
Zx (s1 + s2 )
B2 (s1 , s2 )
Z1 (s1 + s2 )
C2 (s1 , s2 )
Z2 (s1 + s2 )
+
+
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=
−A2 (s1 , s2 )
Zs (s1 + s2 )
B2 (s1 , s2 ) − C2 (s1 , s2 )
Z12 (s1 + s2 )
C2 (s1 , s2 ) − B2 (s1 , s2 )
Z12 (s1 + s2 )
Second-Order Kernels
Solving above equations we arrive at:
1 (g 0 − g 0 )(r
o1 k ro1 )Zs (s1 + s2 )A1 (s1 )A1 (s2 ) + 4A2 (s1 , s2 )
m1
m2
A2 (s1 , s2 ) = 2
H(s1 + s2 ) + 4H(s1 , s2 )
Z1 (s1 +s2 )kZ2 (s1 +s2 ) 1
0
0
− Z (s +s )kZ (s +s ) 2 (gm1
− gm2
)(ro1 k ro1 )Zs (s1 + s2 )A1 (s1 )A1 (s2 ) + 4B2 (s1 , s2 )
x 1 2
s 1 2
B2 (s1 , s2 ) =
H(s1 + s2 ) + 4H(s1 , s2 )
Zs (s1 + s2 )
1
4A2 (s1 , s2 ) = Z12 (s1 + s2 )A1 (s1 )A1 (s2 )
×
2
Z1 (s1 + s2 ) + Z2 (s1 + s2 )
0
0
g ro1 Z2 (s1 + s2 ) − gm2 ro2 Z1 (s1 + s2 ) 0
0
(gm1 − gm2 )(ro1 k ro2 ) + m1
ro1 + ro2
4B2 (s1 , s2 ) = −
1
2
Z12 (s1 + s2 )A1 (s1 )A1 (s2 )
Z1 (s1 + s2 )
1
Z1 (s1 + s2 ) + Z2 (s1 + s2 ) ro1 + ro2
Zs (s1 + s2 ) 0
gm1 ro1 Z2 (s1 + s2 ) + ro2 1 +
+
Zx (s1 + s2 )
0
0
Zs (s1 + s2 ) gm2 ro2 (1 + gm1 ro1 ) + gm1 ro1 (1 + gm2 ro2 )
×
Zs (s1 , s2 )
1
×
Z1 (s1 , s2 ) + Z2 (s1 , s2 ) ro1 + ro2
!
(ro1 + Z1 (s1 + s2 ))(ro2 + Z2 (s1 + s2 ))
+
(1 + gm1 ro1 ) ro2 + Z2 (s1 + s2 ) + (1 + gm2 ro2 ) ro1 + Z1 (s1 + s2 )
Zx (s1 + s2 ) k Zs (s1 + s2 )
4H(s1 , s2 ) = Z12 (s1 + s2 )
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Third-Order Terms
gm1 A3 (s1 , s2 , s3 ) +
+gm2 A3 (s1 , s2 , s3 ) +
=−
00
gm2
6
0
A1 (s1 )A1 (s2 )A1 (s3 ) − gm1 A1 (s1 )A2 (s2 , s3 ) +
A1 (s1 )A1 (s2 )A1 (s3 ) +
0
gm2 A1 (s1 )A2 (s2 , s3 )
+
A3 (s1 , s2 , s3 ) − B3 (s1 , s2 , s3 )
ro1
A3 (s1 , s2 , s3 ) − C3 (s1 , s2 , s3 )
ro2
Zs (s1 + s2 + s3 )
B3 (s1 , s2 , s3 )
Z1 (s1 + s2 + s3 )
gm2 A3 (s1 , s2 , s3 ) +
=
6
A3 (s1 , s2 , s3 )
gm1 A3 (s1 , s2 , s3 ) +
=
00
gm1
C3 (s1 , s2 , s3 )
Z2 (s1 + s2 + s3 )
00
gm1
6
+
00
gm2
6
+
0
A1 (s1 )A1 (s2 )A1 (s3 ) − gm1 A1 (s1 )A2 (s2 , s3 ) +
A3 (s1 , s2 , s3 ) − B3 (s1 , s2 , s3 )
ro1
B3 (s1 , s2 , s3 ) − C3 (s1 , s2 , s3 )
Z12 (s1 + s2 + s3 )
0
A1 (s1 )A1 (s2 )A1 (s3 ) + gm2 A1 (s1 )A2 (s2 , s3 ) +
A3 (s1 , s2 , s3 ) − C3 (s1 , s2 , s3 )
C3 (s1 , s2 , s3 ) − B3 (s1 , s2 , s3 )
Z12 (s1 + s2 + s3 )
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ro1
Third-Order Kernel
Assuming Z12 ∼ 0 (at s1 + s2 + s3 ):
A3 (s1 , s2 , s3 ) =
0 + g 0 )A (s )A (s , s ) + 1 (g 00 + g 00 )A (s )A (s )A
−Zs (ro1 k ro2 ) − (gm1
1 1
2 2 3
1 1
1 2
1
m2
m2
6 m1
H(s1 + s2 + s3 )
−Z1 (s1 + s2 + s3 )
B3 (s1 , s2 , s3 ) =
A3 (s1 , s2 , s3 )
Zx (s1 + s2 + s3 ) k Zs (s1 + s2 + s3 )
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Output Voltage
The output voltage is given by a new Volterra series. Assume
for simplicity the following:
Vout =
gm3 V1 + gm4 Vx +
0
g0
g 00
g 00
gm3
V12 + m4 Vx2 + m3 V13 + m4 Vx3
2
2
6
6
× ZL
The fundamental and third-order output are therefore:
Vout,fund = (A1 (s) ◦ Vs ) × gm4 + (B1 (s) ◦ Vs ) × gm3 × ZL
Vout,3rd =
(A3 (s1 , s2 , s3 ) ◦ Vs3 ) × gm4 + (B3 (s1 , s2 , s3 ) ◦ Vs3 ) × gm3
+ (A1 (s) ◦ Vs )3 ×
00
g 00 gm4
+ (B1 (s) ◦ Vs )3 × m3
6
6
0
0
+ (A1 (s1 )A2 (s2 , s3 ) ◦ Vs3 ) × gm4
+ (B1 (s1 )B2 (s2 , s3 ) ◦ Vs3 ) × gm3
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× ZL
Focus on Third-Order Output
At low frequencies:
A1 /B1 ∼ Rin /R1
A2 /B2 ∼ −Rs /R1
A3 /B3 ∼ −Rs /R1
Vout,3rd =
(A3 (s1 , s2 , s3 ) ◦ Vs3 ) × gm4 + (B3 (s1 , s2 , s3 ) ◦ Vs3 ) × gm3
+ (A1 (s) ◦ Vs )3 ×
00
gm4
g 00 + (B1 (s) ◦ Vs )3 × m3
6
6
0
0
+ (A1 (s1 )A2 (s2 , s3 ) ◦ Vs3 ) × gm4
+ (B1 (s1 )B2 (s2 , s3 ) ◦ Vs3 ) × gm3
× ZL
First term cancels like thermal noise
Second term: New distortion generated at output. Cancel
with MGTR.
Thrid term: Due to second-order interaction: Must use g 0 = 0
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Two-Tone Spacing Dependence
Because 2nd order interaction is minimized by using a PMOS
and NMOS in parallel, the capacitor C12 plays an important
role.
When second order distortion is generated at low frequencies,
f1 − f2 , the capacitor C12 has a high reactance and distortion
cancellation does not take place.
There is therefore a dependency to the two-tone spacing.
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Power Supply Ripple
In RF systems, the supply ripple can non-linearity transfer
noise modulation on the supply to the output.
This problem was analyzed by Jason Stauth: Energy Efficient
Wireless Transmitters: Polar and Direct-Digital Modulation
Architectures, Ph.D. Dissertation, U.C. Berkeley.
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Supply Noise Sources
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Multi-Port Memoryless Non-linearity
The output voltage is a non-linear function of both the supply
voltage and the input voltage. A two-variable Taylor series
expansion can be used if the system is memory-less:
Sout (Sin , Svdd ) = a10 Sin + a20 Sin2 + a30 S3in + · · ·
+a11 Sin Svdd + a21 Sin2 Svdd + · · ·
2
3
+a01 Svdd + a02 Svdd
+ a03 Svdd
+ ···
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Supply Noise Sideband
Assume the input is at RF and the supply noise is a tone.
Then the output signal will contain a noise sideband given by:
Sin = vi cos(ω0 t)
Svdd = vs cos(ωs t)
1
vout (ω0 ± ωs ) = a11 vi vs
2
2a10 1
Sideband(dBc) = dB
·
a11 vs
2a10
PSSR = dB
a11
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Multi-Port Volterra Series
Extending the concept of a Volterra Series to a two input-port
system, we have
vout (t) =
∞
∞ X
X
Fmn (v1 (t), v2 (t))
m=0 n=0
Z
∞
Fmn (v1 (t), v2 (t)) =
−∞
···
Z
∞
−∞
hmn (τ1 , · · · , τm+n )
v1 (t − τ1 ) · · · v1 (τ − τm )v2 (t − τm+1 ) · · · v2 (τ − τm+n )
×dτ1 · · · dτm+n
Sout = A10 (jωa )◦ S1 + A20 (jωa , jωb )◦ S12 + A30 (jωa , jωb , jωc )◦ S13 + · · ·
+A01 (jωa )◦ S2 + A02 (jωa , jωb )◦ S22 + A03 (jωa , jωb , jωc )◦ S23 + · · ·
◦
+A11 (jωa , jωb ) S1 S2 + A21 (jωa , jωb , jωc )◦ S12 S2 + A12 (jωa , jωb , jωc )◦ S1 S22 + · · ·
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Example
2
3
id = gm1 vgs + gm2 vgs
+ gm3 vgs
+ ···
2
3
−gmb1 vsb − gmb2 vsb
− gmb3 vsb
+ ···
2
2
+gmo11 vds · vgs + gmo12 vds · vgs
+ gmo21 vds
vgs + · · ·
+C1
d
C2 d 2
C3 d 3
(vdb ) +
(v ) +
(v ) + · · ·
dt
2 dt db
3 dt db
Several important terms:
gm , and go non-linearity is usual transconductance and output
resistance terms
gmo is the interaction between the input/output
Cj is the output voltage non-linear capacitance
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First Order Terms
y1 (jω) = g o1 + jωC
yx (jω) = (jωLC )−1
ys (jω) = (jωLs )−1
First-order transfer function: (RF Node Transfer)
gm1
A110 (jω) = −ys (jω)
K0 (jω)
K0 (jω) = (gm1 + gmb1 + y1 )(yx + yL ) + ys (yx + y1 + yL )
Supply Node Transfer: (superscripts are node numbers)
gm1 (yx + yL )
A101 (jω) =
K0 (jω)
y
(g
m
+
y
+
gmb
x
1
1
1 + ys )
A210 (jω) =
K0 (jω)
yx yL
A201 (jω) =
K0 (jω)
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Mixing Product
The most important term for now is the supply-noise mixing
term:
vout (ω0 ± ωs ) = A111 (jω0 , jωs )◦ [Vi (ω0 ), Vs (ωs )]
A111 (jωa , jωb ) = ys
gmo11 K1 + 2y2 K2 + 2g m2 K3 − 2gmb2 K4
K0
K1 (jωa , jωb ) = A201 [1 + A110 (jωa ) − 2A210 (jωa )] − A101 (jωb )[1 − A210 (jωa )]
K2 (jωa , jωb ) = A201 (jωB )[A110 (jωa ) − A210 (jωa )] + A101 (jωb )[A210 (jωa ) − A110 (jωa )]
K3 (jωa , jωb ) = A201 (jωb )[1 − A110 (jωa )]
K4 (jωa , jωb ) = A210 (jωa )A201 (jωb )
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PSSR Reduction
PSRR = dB[
g m1
]
gmo11 K1 + 2y2 K2 + 2g m2 K3 − 2gmb2 K4
Increase gm1
Reduce second order conductive non-linearity at drain (go2 )
Reduce the non-linear junction capacitance at drain
Reduce cross-coupling term by shielding the device drain from
supply noise (cascode)
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Output Conductance Non-Linearity
For short-channel devices, due to DIBL, the output has a
strong influence on the drain current. A complete description
of the drain current is therefore a function of f (vds , vgs ).
This is especially true if the device is run close to triode region
(large swing or equivalently high output impedance):
2
2
ids (vgs , vds ) = gm1 vgs + gds1 vds + gm2 vgs
+ gds2 vds
+
3
3
+ gds3 vds
+
x11 vgs vds + gm3 vgs
2
2
x12 vgs vds
+ x21 vgs
vds + · · ·
gmk =
1 ∂ k Ids
1 ∂ k Ids
1 ∂ p+q Ids
; gdsk =
; xpq =
p
q
k
k
k! ∂Vgs
k! ∂Vds
p!q! ∂Vgs
∂Vgs
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Total Distortion
Including the output conductance non-linearity modifies the
distortion as follows
2 + c v3 + · · ·
vds = c1 vgs + c2 vgs
3 gs
−1
c1 = −gm1 (RCS ||gds1
)
−1
c2 = −(gm2 + gds2 c12 + x11 c1 ) · (RCS ||gds1
)
3
c3 = −(gm3 + gds3 c1 + 2gds2 c1 c2 + x11 c2 + x12 c12 + x21 c1 ) · (RCS ||g
Source: S. C. Blaakmeer, E. A. M. Klumperink, D. M. W. Leenaerts,, B. Nauta, “Wideband Balun-LNA
With Simultaneous Output Balancing, Noise-Canceling and Distortion-Canceling,” JSSC, vol. 43, Jun.
2008.
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Example IIP Simulation
Contributions to c2 are shown above.
For low bias, gds2 contributes very little but x11 and gm2 are
significant. They also have opposite sign.
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PA Power Supply Modulation
When we apply a 1-tone to a class AB
PA, the current drawn from the supply
is constant.
For when we apply 2-tones, there is a
low-frequency component to the input:
Vin = A sin(ω1 t) + A sin(ω2 t)
ω1 + ω2
ω1 − ω2
t sin
t
= 2A cos
2
2
= 2A cos(ωm t) sin(ωc t)
This causes a low frequency current to
be drawn from the supply as well, even
for a balanced circuit.
P. Haldi, D. Chowdhury, P. Reynaert, G. Liu, A. M Niknejad, “A 5.8 GHz 1 V Linear Power Amplifier
Using a Novel On-Chip Transformer Power Combiner in Standard 90 nm CMOS,” IEEE Journal of
Solid-State Circuits, vol. 43, pp.1054-1063, May 2008.
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Supply Current
The supply current is a full-wave rectified sine.
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Fourier Components of Supply Current
Substitute the Fourier series for the sine and cosine.
Note that an on-chip bypass can usually absorb the higher
frequencies (2fc ) but not the low frequency beat (fs and
harmonics)
4 cos(2ωm t)
2
4 cos(2ωc t)
2
+
− ··· ×
−
− ···
is = k
π π
3
π π
3
8 cos(2ωc t)
8 cos(2ωm t)
= k ··· − 2
+ 2
− ···
π
3
π
3
8 cos(ωs t)
8 cos(2ωc t)
+ 2
− ···
= k ··· − 2
π
3
π
3
Niknejad
Advanced IC’s for Comm
Supply Ripple Voltage
The finite impedance of the supply means that the supply
ripple has the following form.
Vdd = VDD + A2 · cos(ωs t) + · · ·
Assuming a multi-port Volterra description for the transistor
results in:
So = F1 (ωa )◦ S1 + F2 (ωa , ωb )◦ S12 + F3 (ωa , ωb , ωc )◦ S13 + · · ·
G1 (ωa )◦ S2 + G2 (ωa , ωb )◦ S22 + G3 (ωa , ωb , ωc )◦ S33 + · · ·
H11 (ωa , ωb )◦ (S1 · S2 ) + H12 (ωa , ωb , ωc )◦ (S1 · S22 )+
H21 (ωa , ωb , ωc )◦ (S12 · S2 ) + · · ·
S(ω1 ± ωs ) = H11 ◦ (S1 · S2 )
Niknejad
Advanced IC’s for Comm
Experimental Results
Even though the PA is fully balanced, the supply inductance
impacts the linearity.
Measurements confirm the source of the IM3 at low offsets
arising from supply modulation.
Niknejad
Advanced IC’s for Comm
MOS CV Non-Linearity
Cox
u
act
al
VF B
VT
Cgs , Cµ and Cdb all contribute to the non-linearity.
As expected, the contribution is frequency dependent and very
much a strong function of the swing (drain, gate).
Gate cap is particular non-linear around the threshold of the
device.
Niknejad
Advanced IC’s for Comm
PMOS Compensation Technique
Make an overall flat C -V curve by adding an appropriately
sized PMOS device.
Source: C. Wang, M. Vaidyanathan, L. Larson, “A
Capacitance-Compensation Technique for Improved Linearity
in CMOS Class-AB Power Ampliers,” JSSC, vol. 39, Nov.
2004.
Niknejad
Advanced IC’s for Comm
Jiashu
2:1
1V
30fF
600fF
1V
G
2:1
2.2µm
1x
PPD
control
6.6µm
6.6µm
11µm
2x
8µm
20µm
bbl<0>
S
PPD
13µm
bbe<0>
G
24µm
24µm
40µm
Early PA array
bbe<0>
bbe<1>
bbe<2>
bbe<3>
Late PA array
identical
bbe<3:0>
bbl<3:0>
“Digital” PA cell at 60 GHz uses non-binary weighted
elements for RF-DAC to compensate for amplitude
compression.
Phase AM-to-PM distortion is compensated by switching in
capacitance versus codeword.
Source: Jiashu Chen, Lu Ye, D. Titz, F. Gianesello, R. Pilard, A. Cathelin, F. Ferrero, C. Luxey, A.
Niknejad, “A digitally modulated mm-Wave cartesian beamforming transmitter with quadrature spatial
combining,” IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 17-21
Feb. 2013, pp. 232-233.
Niknejad
Advanced IC’s for Comm