Berkeley
Active Devices for Communication Integrated
Circuits
Prof. Ali M. Niknejad
U.C. Berkeley
c 2014 by Ali M. Niknejad
Copyright Niknejad
Advanced IC’s for Comm
Overview of Key Device Parameters
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Generic Three Terminal Device
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Large Signal Equations
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Generic Device Behavior
slope is output resistance of device
resistor (triode) region (very small output voltage)
non-linear resistor region (small output voltage)
“constant” current region (large output voltage, current nearly
independent of output)
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Large Signal Models
+
Vi
−
I = f (Vi )
Resistors and capacitors are non-linear
Rπ and Ro depend on bias point
Rg (intrinsic) depends on channel inversion level
Rb can change due to current spreading effects
Cgs varies from accumulation to depletion to inversion
Junction capacitors vary with bias
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Small Signal Models
rx
Cµ
rπ
Cπ
+
vπ
−
ry
gm v π
ro
rz
In small signal regime, R and C linear about a bias point:
For
BJT:
rx = rb
For a
FET
input:
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Cgs
1
Rg = Rnqs + Rpoly
d
d = 3 ↔ 12
1
Rnqs ∼
5gm
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Various Figures of Merit
Intrinsic
Voltage
Gain (a0 )
Power Gain
Unilateral Gain
Noise
Noise figure (NF and Noise Measure M)
Flicker noise corner frequency
Unity Gain Frequency
fT
Maximum Osc Freq fmax
Gain (normalized to current): gm /I
Gain Bandwidth
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Other Important Metrics
Complementary devices
Device with same order of magnitude of fT / fmax
Lateral pnp a “dog” compared to vertical npn
Availability of Logic
Low power/high density
Useful with S/H (sample hold) and SC (switch capacitor)
circuits
Important for calibration
Breakdown voltage
Power amplifiers, dynamic range of analog circuitry
Thermal conductivity
Power amplifiers
Quality and precision of passives
Inductors, capacitors, resistors, and transmission lines
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Current Gain
io = gm vgs =
gm vgs
jω(Cgs + Cgd )
Ai =
ii
io
ii
Since id = gm vgs , and vgs jω(Cgs + Cgd ) = is , taking the ratio
we have
gm
id
=
Ai =
is
jω(Cgs + Cgd )
Solving for |Ai = 1|, we arrive at the unity gain frequency
gm
ωT = 2πfT =
Cgs + Cgd
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Why fT ?
vi
It is not at first obvious why fT plays such an important role
in analog (and digital) circuits. To see this, consider the
simple cascade amplifier, where a single stage amplifier drives
an identical copy. The gain of this first stage is given by the
intrinsic gain of the amplifier, and the 3-dB bandwidth is
limited by the pole at the high impedance node
ω0 =
1
ro,1 ((1 + |A2 |)Cgs,2 + Cd1,tot )
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Cascade Example
Here Cd1,tot is the total drain capacitance
(Cgd + Cds + Cwire + · · · ) and the effect of Miller
multiplication is captured by boosting the second stage input
capacitance by the gain A2 . If the second stage is a cascode
with a small voltage gain between the gate/drain, then A2 can
be made smaller than unity to minimize its impact. So if we
neglect the Miller effect, we have
ω0 =
ro (Cgs
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1
+ Cd,tot )
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Gain/Bandwidth Product
In most applications, we intend to embed this amplifier in a
feedback loop, so the gain-bandwidth product is of interest.
For a feedback system, we know that we can approximately
trade gain for bandwidth. So if we place the amplifiers in a
feedback loop, we have
Gain = A0
BW = ω0
Gain × BW = A0 ω0 < gm ro
=
Cgs
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1
ro (Cgs + Cd,tot )
gm
≈ ωT
+ Cd,tot
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fT in Digital Circuits
Even in a digital circuit, we find that fT plays a key role.
Consider the time constant of a simple gate, such as an
inverter. If the fan out of an inverter is unity, in other words
the inverter drives an identical copy of itself, then the load of
the inverter is approximately Cgs + Cd,tot .
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fT in Digital Circuits (cont)
The discharge current takes a complicated form, but to first
order the transistor acts like a switch with on-conductance
gds = gm (in triode region), so the discharge time is given by
the product
Cgs
1
=
τT =
gm
ωT
For larger fan-out (FO) circuits (and/or gates), we just scale
fT by the FO.
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Bipolar Junction Transistors
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BJT Cross Section
base
n+ poly contact
n+ emitter
p+
n
collector
field oxide
n+ buried layer
p-type substrate
Most transistor “action” occurs in the small npn sandwich
under the emitter. The base width should be made as small as
possible in order to minimize recombination. The emitter
doping should be much larger than the base doping to
maximize electron injection into the base.
A SiGe HBT transistor behaves very similarly to a normal
BJT, but has lower base resistance rb since the doping in the
base can be increased without compromising performance of
the structure.
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Bipolar Small-Signal Model
B
Cµ
rb
C
Rπ
E
re
rc
Cπ
+
vin
−
gm vin
ro
Ccs
The resistor Rπ dominates the input impedance at low
frequency. At high frequency, though, Cπ dominates.
Cπ is due to the collector-base reverse biased diode
capacitance.
Ccs is the collector to substrate parasitic capacitance. In some
processes, this is reduced with an oxide layer.
Cπ has two components, due to the junction capacitance
(forward-biased) and a diffusion capacitance
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Bipolar Exponential
Due to Boltzmann statistics, the collector current is described
very accurately with an exponential relationship
IC ≈ IS e
qVBE
kT
The device transconductance is therefore proportional to
current
qIC
dIC
q qVBE
gm =
= IS
e kT =
dVBE
kT
kT
(1)
(2)
where kT /q = 26mV at room temperature. Compare this to
the equation for the FET. Since we usually have
kT /q < Vgs − VT , the bipolar has a much larger
transconductance for the same current. This is the biggest
advantage of a bipolar over a FET.
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Control Terminal Sensitivity
BJT:
10 = exp
∆VBE =
10 =
√
VGS,1 − VT
VGS,2 − VT
2
VGS,1 − VT
10 =
VGS,1 + ∆VGS − VT
√
1 − 10
∆VGS = √
(VGS,1 + VT ) ≈ 1V
10
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kT
× ln 10 ≈ 60mV
q
MOSFET:
q∆VBE
kT
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Bipolar Unity Gain Frequency
The unity gain frequency of the BJT device is given by
ωT =
gm
gm
=
Cπ + Cµ
Cdiff + 2Cje0 + Cµ
(3)
where we assumed the forward bias junction has Cje ≈ 2Cje0
Since the base-collector junction capacitance Cµ is a function
of reverse bias, we should bias the collector voltage as high as
possible for best performance.
The diffusion capacitance is a function of collector current,
Cdiff = gm τF
ωT =
gm
1
=
2C
+C
gm τF + 2Cje0 + Cµ
τF + je0gm µ
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(4)
Bipolar Optimum Bias Point
220
No Kirk Effect
160
fT (GHz)
80
ωT →
40
0
10−4
10−3
1
τF
10−2
IC
We can clearly see that if we continue to increase IC , then
gm ∝ IC increases and the limiting value of fT is given by the
forward transit time ωT ≈ 1/τF
In practice, though, we find that there is an optimum collector
current. Beyond this current the transit time increases. This
optimum point occurs due to the Kirk Effect. It’s related to
the “base widening” due to high level injection. (Not Star
Trek!)
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Base Transmit Time
Ci = Cj + Cdiff ≈ Cdiff = τF · gm
Base transmit time
Current gain unity freq.
1
gm
fT =
≈
2πCi
2πτF
fT ≈
2µn kT
2πWB2 q
fT ∝
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1
WB2
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CMOS FET Transistors
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CMOS Cross Section
NMOS
PMOS
VDD
S
n+
G
p+
S
D
p+
p+
G
n+
Lov
D
n+
L
n-well
p-type substrate
Modern CMOS process has very short channel lengths
(L < 100nm). To ensure gate control of channel, as opposed
to drain control (DIBL), we employ thin junctions and thin
oxide (Tox < 5nm).
Due to lithographic limitations, there is an overlap between
the gate and the source/drain junctions. This leads to overlap
capacitance. In a modern FET this is a substantial fraction of
the gate capacitance (up to half).
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CMOS DNW Device
PW
NW
PW
NW
PW
P-Substrate
In a standard CMOS process, only the PMOS is isolated by
the n-well. All NMOS devices share a common body (psub).
This means that the body-source cannot be tied together
(unless grounded) and moreover, digital substrate noise
couples to sensitive analog and RF circuits
In many processes, a deep n-well (“DNW”) can be used to
isolate the p-well. This is like a triple-well process, allowing
isolated NMOS transistors. The DNW is formed from a ring
of NW and an overlapping DNW region.
PW
NW
PW
NW
DNW
P-Substrate
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PW
FET Small Signal Model
Cgd
Rg
G
D
Cgs
S
RS
+
vgs
−
gm vgs
Cgb
gmb vbs
ro
Cdb
Csb
B
The junctions of a FET form reverse-biased pn junctions with
the substrate (well), or the body node. This is another form
of parasitic capacitance in the structure, Cdb and Csb .
At DC, input is an open circuit. The input impedance has a
small real part due to the gate resistance Rg (polysilicon gate
and NQS) and Rs,d account for junction and contact
resistance.
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FET Simplified Models
In the forward active (saturation) region, the input
capacitance is given by Cgs
2
Cgs = W · L · Cox + Cpar
3
Don’t forget that layout parasitics increase the capacitance in
the model, sometimes substantially (esp in deep submicron
technologies). Ro is due to channel length modulation and
other short channel effects (such as DIBL).
Cgd
G
D
Cgs
S
+
vgs
−
gm vgs
Cgb
gmb vbs
ro
Cgd
G
Cdb
D
Cgs
S
Csb
+
vgs
−
gm vgs
ro
B
For low frequencies, the resistors are ignored. But these
resistors play an important role at high frequencies.
If the source is tied to the bulk, then the model simplifies.
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Cdb
FET Extrinsic Model
G
Rge
S
Cgse
Cgde
Rse
Rde
Cbse
Cbde
Rs,bs
D
Rs,bd
Rbe
B
Substrate parasitics, gate resistance, source/drain resistances,
extra metal and contact resistance and capacitance. At very
high frequencies, the distributed inductance of the leads.
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Intrinsic Voltage Gain
Important metric for analog circuits
Av ,mos = gm ro =
VA
2IDS VA
=2
Vdsat IDS
Vdsat
Av ,bjt = gm ro =
qIC VA
VA
= 2 kT
kT IC
q
Communication circuits often work with low impedances in
order to achieve high bandwidth, linearity, and matching.
To achieve high fT , the Vdsat is relatively large so the current
is increased to obtain sufficient gain.
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Voltage Gain for Tuned Amplifiers
Inductive loads are also common to tune out the load
capacitance and form a resonant circuit. The gain is thus
given by
Av = gm Rp = gm ω0 QL
In a given process, there’s a maximum Q that we can obtain,
usually Q ∼ 10 at 1 GHz in a typical 90nm process with thick
metal options. The inductance cannot be increased without
bound due to area limitations and ultimately due to the
tuning requirements
1
ω0 L =
ω0 (Cgs + Cdb + Cpar )
ω0 L ≤
Av = gm ω0 QL = gm Q
1
ω0 Cgs
gm
1
fT
1
=
·Q ·
=Q·
ω0 Cgs
Cgs
ω0
f0
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A0
A0
DC Gain for Short Channel Devices
L=100nm
L=200nm
L=250nm
L=500nm
L=1000nm
Vgs=1.2V
1e-07 2e-07 3e-07 4e-07 5e-07 6e-07 7e-07 8e-07 9e-07 1e-06
L (m)
0
0.2
0.4
0.6
Vds
0.8
1
CMOS is running out of steam because the DC gain per device
is dropping with smaller L. This makes design very difficult,
especially since the DC gain drops with supply voltage.
Most fast transistor come with the penalty of lower speed of
operation.
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1.2
Normalized Gain
For a bipolar device, the exponential current relationship
results in a high constant normalized gain
gm
q
1
=
≈
IC
kT
26mV
For a square law MOSFET, in saturation we have
2
gm
=
IDS
VGS − VT
In weak inversion, the MOSFET is also exponential
gm
q
1 1
=
≈
IDS
nkT
26mV n
The factor n is set by the ratio of oxide to depletion
capacitance
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MOSFET in Subthreshold
In sub-threshold, the surface potential varies linearity with VG
The surface charge, and hence current, is thus exponentially
related to VG
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I-V Curves Vgs
Ids
Vds=50mV
Vds=250mV
Vds=650mV
Vds=1.25V
0
0.2
0.4
0.6
Vgs
0.8
1
1.2
The I-V curve of a given transistor with fixed dimension (W
and L) reveals most of the salient features. For example, a
plot of Ids versus Vgs for a family of Vds quickly reveals
current drive capability. If a device is biased in weak or
moderate inversion, then the logarithmic plot is more useful as
it expands this regime of operation.
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log(Ids)
I-V Curves Vgs (log)
Vds=50mV
Vds=250mV
Vds=450mV
Vds=750mV
Vds=850mV
Vds=1.25V
0
0.2
0.4
0.6
Vgs
0.8
1
1.2
The leakage currents (sub-threshold slope) is important in
analog applications that use the transistor as a switch. If the
device cannot be turned off, then it’s very difficult to build
high precision discrete time circuits.
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Ids
I-V Curves Vds
0
0.2
0.4
0.6
Vds
0.8
1
1.2
Plotting the current versus drain-source voltage, or a plot of
Ids versus Vds for a family of Vgs shows the current saturation
behavior of a device. The output conductance is more easily
observed using small-signal parameters as discussed shortly,
but certain trends can be observed even from the raw I-V
curves.
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MOS Transconductor Efficiency
Since the power dissipation is determined by and large by the
DC current, we’d like to get the most “bang for the buck”.
From this perspective, the weak and moderate inversion
region is the optimal place to operate.
The price we pay is the speed of the device which decreases
with decreasing VGS
Current drive is also very small.
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gm
Transconductance (Vgs )
L=100nm
L=200nm
L=250nm
L=500nm
L=1000nm
0
0.2
0.4
0.6
Vgs
0.8
1
1.2
The value of gm increases with Vgs . For the diffusion
component of current, at low overdrive, the increase in gm is
exponential due to the exponential dependence of current on
gate voltage.
For the drift component of current, Ids is proportional to the
amount of charge in the channel and the carrier velocity. The
channel charge scales in proportion to the gate bias, so for a
fixed mobility, we expect
the gm
to increase linearly.
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600
CLM
DIBL
SCBE
400
Mobility
e
gm vs. Vgs (cont)
1
2
Vds (V)
3
4
200
0
Effective Field
In fact, for low fields, due to Coulomb scattering, the mobility
will experience an enhancement due to screening provided by
the inversion layer, and the increase in gm is faster than linear.
On the other hand, due to high field effects, we know the
mobility will eventually degrade as carriers are pushed closer
to the silicon-insulator interface, where surface scattering
causes the mobility to drop.
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gm
gm vs. Vds
L=100nm
L=200nm
L=250nm
L=500nm
L=1000nm
0
0.2
0.4
0.6
Vds
0.8
1
1.2
The trend for gm as a function of Vds can be divided into two
regions. In the triode region of operation, increasing Vds
increases the current, so the overall gm increases.
As the device nears saturation, one would expect the gm to
saturate.
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gds
Output Conductance
L=100nm
L=200nm
L=250nm
L=500nm
L=1000nm
0
0.2
0.4
0.6
Vds
0.8
1
1.2
gds in triode region is very large since the drain voltage has a
direct impact on the channel charge. In fact, to first order,
gds = gm since varying the gate has the same impact as
varying the gate due to the presence of the inversion layer,
making the drain terminal just as effective as the gate-source.
In a long channel device, in the so-called pinch-off region, the
device terminal no longer controls the channel charge directly,
and the output conductance drops dramatically.
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ro
Output Resistance
L=100nm
L=200nm
L=250nm
L=500nm
L=1000nm
0
0.2
0.4
0.6
Vds
0.8
1
1.2
The drain still modulates the depletion region width, which
indirectly impacts the device through channel length
modulation (CLM).
In short channel devices, both because of the increase in the
relative magnitude of the change in channel length δL relative
to L, but also due to Drain Induced Barrier Lowering (DIBL).
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Output Resistance Broken Down
14
Triode
12
CLM
DIBL
SCBE
Rout kΩ
10
8
6
4
2
0
1
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2
Vds (V)
3
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4
FET Unity Gain Frequency
Long channel FET:
Note that there is a
peak fT since
eventually the
mobility of the
transistor drops due
to high vertical fields
fT =
gm
1
2π Cgs + Cgb + Cgd
assuming Cgs Cgb + Cgd
fT =
1 gm
1 3 µn
=
(VGS − VT )
2π Cgs
2π 2 L2
Short channel limit:
IDS ≈ vsat Qinv W = WCox (VGS − VT )vsat → gm = WCox vsat
fT =
1 gm
3 WCox vsat
1
=
∝
2π Cgs
2 WLCox
L
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Scaling Speed Improvements
100
rt
sho
10
fT
1
0
1980
lon
1985
g-
ch
an
l
ne
re
gio
nne
-cha
l reg
ion
n
1990
year
1995
2000
2005
CMOS transistors have steadily improved in performance just
as predicted by theory. In the short channel regime the
improvements are linear with scaling.
At the same time, the decreasing supply voltage has led to a
reduced dynamic range. Also the maximum gain has not
improved as much· · ·
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fT
fT versus Dimension
Vgs=1.2V
1e-07 2e-07 3e-07 4e-07 5e-07 6e-07 7e-07 8e-07 9e-07 1e-06
L (m)
The well known improvement in fT with channel scaling is
shown here. Since both gm and Cgs depend linearity on the
width, only the channel length L matters.
Shorter channel lengths improve both the gm and lower the
capacitance of the device. In the velocity saturated limit, only
the drop in capacitance plays a role.
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Cgs versus Bias
Cgg
Classical
Cox
Quantum
Poly Depletion
VF B
VT H
VGB
The MOS capacitor of modern devices does not follow
classical equations due to polysilicon depletion and quantum
effects ...
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fT
fT versus Bias
L=100nm
L=200nm
L=250nm
L=500nm
L=1000nm
0
0.2
0.4
0.6
Vgs
0.8
1
1.2
To go fast, you must burn power ...
It is important to note that fT is usually measured using
scattering parameters and so using the “DC” values of gm and
C will fail to capture fT at high frequency. We will return to
this point in the RF section of this chapter.
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High Frequency
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Maximum Two-Port Power Gain
Measure or calculate two-port parameters at a particular
frequency. To obtain maximum gain Gmax , design an input
and output matching network to satisfy the following
conditions
YS = Yin∗
∗
YL = Yout
where YS and YL are the source and load admittance seen by
the two-port and Yin and Yout are the input and output
admittance seen looking into the two-port when loaded by
these matched admittances.
This leads to two equations and two unknowns (4 real).
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Maximum Power Gain fmax
fmax = max. freq. of activity = max. freq. of oscillation =
freq. when power gain = 1
2
Gp ≈
fT
f
C
4rx go + gm Cπµ + 4rxgo
Gmax ≈
fmax
fT
=1
2
8πrx Cµ fmax
s
fT
=
8πrx Cµ
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Cµ
rx
Cπ
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+
vπ
−
gm vπ
go
FET fmax
Source
Gate
Drain
L
WF
Cgso
Rg
Rbb
gm
2πCgg
fT
q
2 Rg (gm Cgd /Cgg ) + (Rg + rch + Rs )gds
Rd
Ids
gds
Csb
Rsb
fmax ≈
Cgdo
Cgs
Rs
p-sub
fT ≈
Cdb
Rdb
Bulk
Minimize all resistances
Rg –use many small parallel gate fingers, < 1µm each
Rsb , Rdb and Rbb – substrate contacts < 1 − 2µm from device
Rs , Rd – don’t use source/drain extensions to reduce L
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SiGe HBT and CMOS FinFETs
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SiGe Technology
Higher Performance: Demonstrations of fT > 500GHz and
approach 1THz.
Problem:
As WB decreases → rb increases
Solution:
SiGe base allows for higher fT
without reducing WB
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SiGe HBT Action
A SiGe BJT is often called an HBT (heterojunction bipolar
transistor)
Ge epitaxially grown in base
Causes strain in crystal
Causes extra potential barrier for holes (majority carrier) in the
base from flowing into emitter
Beneficial effects
WB decreases, NB increases, rb low
NE decreases, Cj decreases
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GaAs/InP Technology
108
Carrier Drift Velocity (cm/s)
InP
GaAs
Si
10 7
Ge
10 6
Si
10
5
10 2
10 3
10 4
105
106
Electric Field (V/cm)
One of the primary advantages of the III-V based transistors is
the higher peak mobility compared to Si. With short channel
devices, most of the current flow is due to velocity saturation,
which greatly limits the advantages of III-V over silicon.
The insulating substrate also allows higher Q passives.
The extra cost of these technologies limits it to niche
applications such as very high frequencies, high performance,
and power amplifiers.
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FinFETs and Multigate Transistors
To combat the problems with scaling of MOSFETs below
45nm, Berkeley researchers introduced the “FinFET”, a
double gate device. (Intel uses this technology at the 22nm
node)
Due to thin body and double gates, there is better “gate
control” as opposed to drain control, leading to enhanced
output resistance and lower leakage in subthreshold.
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FinFET Structure and Layout
Gate straddles thin silicon fin, forming two conducting
channels on sidewall
Multi-finger layout very similar to RF layout.
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An Aside on Thermal Conductivity
GaAs
Semi-insulating substrate
Not very good conductor of heat
High quality passive elements (next topic)
Si
Semi-conducting substrate
Good conductor of heat
Lossy substrate leads to lower quality passives
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An Aside on Thermal conductivity (2)
Also depends on packaging
Example: in flip-chip bonding, thermal conductivity function of
number of bumps rather than substrate
Back-side of die can lose heat through radiation or convection
through air but thermal contact is much more effective
Flip chip bonding
Wire bonding
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FET/BJT Comparisons
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High BJT Transconductance
gm =
q qVBE
qIC
dIC
= IS
e kT =
dVBE
kT
kT
For fixed current, BJT gives more gain
Precision
Important in multiplication, log, and exponential functions
More difficult in FETs due to process/temp. dependence
IS process dependent in BJT ... use circuit tricks
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Advantages of BJT
gm
q
1
=
=
IC
kT
25mV
gm
2
1
=
≈
ID
VGS − VT
250mV
For high-speed
applications, need to bias
in strong
inversion...Results in ∼10x
lower efficiency
IC ∝ e −E /kt = e qVBE /kT
For a BJT, this relationship is fundamental and related to the
Boltzman statistics (approximation of Fermi-Dirac statistics)
For a MOSFET, this relationship is actually only valid for a
square-law device and varies with VT (body bias) and
temperature
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Advantage of BJT over FET (2)
log(IC )
Better precision
About 4 decades
(420mV) of linearity
Example:
VBE 1 + VBE 2 = VBE 3
IC
VBE = VT ln
IS
IC 3
IC 1 · IC 2
=
IS1 · IS2
IS3
420mV
Can build exp, log, roots, vector mag
Lower 1/f noise corner
Lower offset voltage
VOS ∼ 1mV
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VBE (V)
Disadvantage of BJT
rb hurts gain (power), NF
SiGe allows fast transistors with low rb
Exponential transfer function (advantage and disadvantage)
Exponential → non-linear
Expensive in high volumes, cheaper in low volumes
Absence of a switch
Old CMOS gets cheaper!
45nm ∼ $1M mask → 0.25µm $50k mask
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Advantage of FET over BJT
Cheaper and more widely available (many fabs in US, Asia,
and Europe)
Square law → less distortion
PMOS P-FET widely available, only ∼ 2× less performance.
Triode region → variable resistor
Widely available digital logic
Low leakage in gates
Sample and hold (S/H) and switch cap filters (SCF)
Dense digital circuitry / DSP for calibration
Offset voltages and mismatches can be compensated digitally
Dense metal layers allows MIM (“MOM”) capacitors for free
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References and Further Reading
UCB EECS 142/242 Class Notes (Niknejad/Meyer)
UCB EECS 240 Class Notes (Niknejad/Boser)
Analysis and Design of Analog Integrated Circuits, Paul R.
Gray, Robert G. Meyer. 3rd ed. New York : Wiley, c1993.
Manku, T. “Microwave CMOS-device physics and design,”
IEEE Journal of Solid-State Circuits, vol.34, (no.3), March
1999. p.277-85. 32
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