IC220 Computer Architecture
12-week Exam
SOLUTION to SAMPLE exam
Last Name ____________________ First Name _______________
Section: 1001
3001
Alpha _____________________
5001
Note: This exam is closed-book, closed-notes.
No calculators are permitted.
To receive partial credit, show all work.
WORK QUICKLY AND DO THE EASY PROBLEMS FIRST!
Possibly useful information:
1. A copy of the single-cycle datapath is provided to you – see last page.
2. For function calls:
Integer values are passed in $a0, $a1, $a2, $a3
Floating point values are passed in $f12, $f14
Integer values are returned in $v0
Floating point values are returned in $f0.
3. ALU control
ALUOp = 00  ALU will Add
ALUOp = 01  ALU will Subtract
ALUOp = 10  ALU will perform action indicated by the instruction’s function field
NOTE: This is an exam that will be given to multiple sections and possibly to students after the
primary exam day. You may not discuss it with anyone until after XXX
(4 pts) Express -910 in the following binary forms:

6 bit, two’s complement
+9 = 001001
To get -9, flip bits then add 1 = 110110+1 = 110111.

6 bit, sign magnitude
+9 = 001001. Just add sign bit:
101001.
(2 pts) Add the following 4-bit binary, two’s complement numbers.
(1 pts) Did overflow occur?(circle one) Yes No
0011
+ 0101
1000
(2 pts) Below is a 4-bit binary, two’s complement number. What would the equivalent number be as an 8-bit
binary, two’s complement number?
1110
-- sign bit is 1, use it to extend:
11111110
(2 pts) Assume $t0 and $t1 both hold the values of two small positive integers. Write some brief MIPS code
to compute the product $t0 * $t1 and store the result in $s0. You may NOT use any pseudo-instructions.
mult $t0, $t1
mflo $s0
(1 pts) Which kind of logic is a flip-flop?
COMBINATIONAL
RELATIONAL
SEQUENTIAL
TRANSITIVE
(1 pts) If a multiplexor has four data inputs, how many selector bits does it need?
Answer: _____2_________
SOLUTION to IC220 SAMPLE exam
1
(8 pts) Convert the following C code into MIPS.
float GoNavy (int k, float C[]) {
return C[4] / C[k];
}
// k in $a0, base pointer of C in $a1
GoNavy:
lwc1 $f2, 16($a1)
# f2 = C[4]
# Code to load C[k].
sll $t0, $a0, 2
add $t1, $a1, $t0
lwc1 $f4, 0($t1)
&C[k] =
# t0
# t1
# f4
a1+4*a0
= 4*a0
= a1+$*a0 = &C[k]
= C[k]
# Now divide, result into $f0
div.s $f0, $f2, $f4
jr $ra
# return
SOLUTION to IC220 SAMPLE exam
2
(5 pts) From the truth table below, reduce the function y (show work and correct K-Map).
W
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
Y
0
1
0
1
0
1
0
1
Z
0
1
0
0
1
1
1
0
XY  W Y
Z = _______________________
W X Should NOT be included (redundant, so not minimal)
(NOTE: K-map not shown above, but required to be in the a correct solution)
(4 pts) Simplify the following two equations. SHOW your work.
(F  G)  (F  G  H )  (F  G)  (F  G  H )  (F  G  F )  (F  G  G)  (F  G  H ) 
 ( F  G )  ( F  G  H )  ( F  G )  (1  H )  ( F  G )
( A  A)( B  0)(C  1)  (C  0)( D  1)  (1)( B )(1)  (0)(1)  B
(3 pts) Draw a picture of a circuit for the following. Do NOT simplify anything, just draw according to the
formula:
z  ( A  B )( B  C )
.
(3 pts) A certain multiplexor has 8 data inputs. Draw a picture of this multiplexor, showing all inputs and
outputs.
(See Notes. Should have 8 inputs on left, 3 control bits (top or bottom), and one output on right)
SOLUTION to IC220 SAMPLE exam
3
The questions on this page all refer to the Single-Cycle Datapath
(see attached figure)
(4 pts) Provide the requested control signals for the following instruction. Show don’t cares if appropriate.
sw $t0, -16($t1)
(just show the answer – no explanation needed)
ALUOp
=
00 (force ALU to add)
ALUSrc
=
1 (feed constant, like -16, to ALU)
Branch
=
0
MemtoReg
=
X (not storing anything in register file, so doesn’t matter what send back)
MemRead
=
0
MemWrite
=
1
RegDst
=
X (not storing anything in register file, so doesn’t matter what send back)
RegWrite
=
0 (do NOT want to store anything in register file)
(4 pts) Provide the requested control signals for the following instruction. Show don’t cares if appropriate.
add $t0, $t1, $t2
(just show the answer – no explanation needed)
ALUOp
=
10 (can’t tell what to do from opcode – must look at function field)
(00 can’t work b/c this control must be based only on opcode, and that only says “R-type”)
ALUSrc
=
0 (want Read Data 2 (e.g. $t1) to go to ALU)
Branch
=
0
MemtoReg
=
0 (send result of ALU back to register file)
MemRead
=
0 or X
MemWrite
=
0 (do NOT want to write to memory)
RegDst
=
1 (destination is $t2, this comes from rd field for R-type instruction)
RegWrite
=
1 (want to store final result in register file)
SOLUTION to IC220 SAMPLE exam
4
(11 pts) Consider the hypothetical MIPS instruction baleq (branch and link on equal). This instruction has the
same format (instruction encoding) and has the same basic functionality as a normal “beq” instruction. In
addition, if and only if the branch is taken then the address of the next sequential instruction after the “baleq”
instruction is written to register $ra (which is register #31). Formally, it does this:
if (Regs[rs] == Regs[rt]) {
// branch IS taken so do two things…
PC = BranchTarget
// 1. take the branch, same as normal beq
Regs[31] = PC+4
// 2. Save PC+4 to register #31
else {
PC = PC+4
// branch is NOT taken: goto next instruction
}
Example: baleq $s0, $t1, Label37
- If $t0 equals $t1, then this instruction will branch to Label37 AND it is hard-wired to write PC+4 to
register $ra (#31).
- If $t0 does NOT equal $t1, then this instruction will simply move on to the next instruction (at
PC+4).
The specific value of the opcode is irrelevant, so we’re omitting the details.
a.) (6 pts) On the next page is a copy of the Single-Cycle Datapath we have discussed in class. Add any
hardware (gates, adders, wires, etc.) to this figure that is necessary to support the new baleq
instruction. Be sure to draw your changes neatly and clearly. Plan in advance how your
picture can clearly indicate what is happening!
Your changes must NOT break the functioning of existing instructions!!!!
c.) (5 pts) Show the control signals here for this new instruction. Show don’t cares if appropriate. If you
need any new control signal(s), add them and also show their value(s).
ALUOp
=
01 (need subtract for beq)
ALUSrc
=
0 (feed ReadData 2 to ALU)
Branch
=
1
MemtoReg
=
X (new mux makes this irrelevant)
MemRead
=
0 or X
MemWrite
=
1
RegDst
=
2 (feed new option of 31 as destination for register)
RegWrite
=
X (irrelevant b/c of new mux at top of register file)
=
1 (this does TWO things:
NEW:
baleq_ctrl
a. Causes PC+4 to be sent to WriteData input of the register file. This always happens with this
instruction, but it will be ignored if the branch is not taken.
b. Modifies mux above the register file so that the value from the AND gate (the Taken? signal) is
provided to the RegWrite input of the register file (instead of RegWrite from “Contrl” unit). Thus a
new value will be written into $ra if and only the AND gate computes the Taken? is true.)
SOLUTION to IC220 SAMPLE exam
5
Use this page for your answer for the new instruction.
If you need to start over, clearly cross out this page, and use the copy on the back of this paper instead.
SOLUTION to IC220 SAMPLE exam
6
Use this page for general reference, or if you need to start over on adding the new instruction.
Work on this page will NOT be graded unless the picture on the other side is clearly crossed out.
SOLUTION to IC220 SAMPLE exam
7