Readout and Control Optimization for a High
Performance MEMS Accelerometer
by
Nick Homer
Submitted to the Department of Electrical Engineering and Computer
Science
in partial fulfillment of the requirements for the degree of
Master of Engineering in Electrical Engineering
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
June 2002
@ Nick Homer, MMII. All rights reserved.
The author hereby grants to MIT permission to reproduce and distribute
publicly paper and electronic copies of this thesis document in _hole or in
part.
MASSAC40ETTS INSTITUTE
OFTECHNOLOGY
JUL 3 1 2002
LIBRARIES
Author ...
~
Department of Electrical Engineering and Computer Science
May 11, 2002
C ertified by .......
.......................
Professor Jeffrey Lang
Professor of Electrical Engineering and Computer Science
Thesis Advisor
.
C ertified by .......
........................................
David McGorty
S---
Charles Starjk Draper Laboratory
fhesjgs*pervisor
Accepted by ............
Arthur C. Smith
Chairman, Department Committee on Graduate Students
Readout and Control Optimization for a High Performance
MEMS Accelerometer
by
Nick Homer
Submitted to the Department of Electrical Engineering and Computer Science
on May 11, 2002, in partial fulfillment of the
requirements for the degree of
Master of Engineering in Electrical Engineering
Abstract
Draper Laboratory is developing a high performance microelectromechanical pendulous accelerometer. It has a very wide dynamic range specification of 500 Ig to 50 g, thus placing
very stringent bounds on the amount of noise introduced in the processing of the signal. The
purpose of this thesis is to design the closed loop controller and signal processor for that
accelerometer. An electrostatic force-feedback mechanism is chosen, and the nonlinearity
due to the square nature of the force.is analyzed and compensated. A design which meets
the dynamic range criterion is presented, and the results of its implementation are shown.
A new design which meets tighter specifications for velocity random walk is then presented
for implementation in an Application Specific Integrated Circuit.
Thesis Advisor: Professor Jeffrey Lang
Title: Professor of Electrical Engineering and Computer Science
Thesis Supervisor: David McGorty
Title: Charles Stark Draper Laboratory
3
Z
4
Acknowledgments
I would like to thank all of the people who have helped me in the development of this project
and the writing of my thesis. Especially crucial to the understanding and completion of my
work at Draper Lab were Dave McGorty and Richard Elliott. I would also like to thank
my thesis supervisor, Professor Jeffrey Lang, as well as my family and friends, who have
supported me throughout college and my time at Draper.
This thesis was prepared the The Charles Stark Draper Laboratory, Inc., under
Internal Company Sponsored Research Project Number 18520.
Publication of this thesis does not constitute approval by Draper or the sponsoring
agency of the findings or conclusions contained herein. It is published for the exchange and
stimulation of ideas.
5
6
Contents
1
Introduction
1.1
1.2
13
1.0.1
Technology Background
. . . . . . . . . . . . . . . . . . . . . . .
13
1.0.2
Design Background . . .
. . . . . . . . . . . . . . . . . . . . . . .
14
1.0.3
Design Specifications . .
. . . . . . . . . . . . . . . . . . . . . . .
16
Scope of the Thesis . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .
17
1.1.1
Control Details . . . . .
. . . . . . . . . . . . . . . . . . . . . .. . 18
1.1.2
Readout Details . . . . .
. . . . . . . . . . . . . . . . . . . . . . .
19
1.1.3
Design Approach . . . .
. . . . . . . . . . . . . . . . . . . . . . .
19
Organization of the Thesis . . .
. . . . . . . . . . . . . . . . . . . . . . .
20
2 Plant Model
21
2.1
Sensor dynamics
2.2
Pick-off Electronics . . . . . . . . . . . . . . . . . . . . . . .
24
2.3
Nonlinearity sources
. . . . . . . . . . . . . . . . . . . . . .
26
2.4
M odulation
. . . . . . . . . . . . . . . . . . . . . .. . . . . .
28
........................
21
2.4.1
Carrier generation
. . . . . . . . . . . . . . . . . . .
28
2.4.2
Harmonic Distortion due to Square Wave Modulation
28
7
2.5
3
29
31
3.1
Compensator criteria . . . . . . . . . . . . . . . .
. . .
32
3.2
Implementation Details . . . . . . . . . . . . . . .
. . .
34
3.2.1
Register Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
3.2.2
Square Root Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . .
36
3.2.3
Quantization Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
Random Walk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
Noise Propagation through Electrostatic Torquer
40
4.1
Linearization
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
4.2
Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
4.3
Effect of intermediate blocks . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
4.3.1
Effects on Signal
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
4.3.2
Effects on Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
4.3.3
Noise is filtered before squaring......
. . . . . . . . . . . . . . .
45
. . . . . . . . . . . . . . .
47
4.4
5
. . . . . . . . . . . . . . . . . . .
Compensator Design and Implementation
3.3
4
Instrinsic Noise
Closed loop response
. . . . . . . . . . ......
Sigma Delta Modulation for A/D and D/A Conversion
49
5.1
Sigma Delta Modulation Background ............
. . . . . . . .
50
5.2
E - A Converter Noise .........................
. . . . . . . .
52
5.2.1
Quantization Noise .......................
. . . . . . . .
52
5.2.2
Other noise in the SDM
. . . . . . . .
52
. . . . . . . .
53
5.3
...............
Sigma Delta Analog to Digital Converter . . . . . . . . . .
8
5.4
6
Decimation for Oversampling A/D converters
. . . . . . . . . . . . . . . . .
55
5.4.1
sincK Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
5.4.2
Interpolation for Oversampling D/A converters
. . . . . . . . . . . .
57
5.5
Design of E - A Digital to Analog Converter . . . . . . . . . . . . . . . . . .
58
5.6
Second Order E - A Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
Conclusion
63
6.1
Design Specification Check . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63
6.1.1
Dynamic Range (500 pg to 50 g)
. . . . . . . . . . . . . . . . . . . .
63
6.1.2
Velocity Random Walk (0.035
. . . . . . . . . . . . . . . . . . .
64
6.1.3
Scale Factor Nonlinearity (0.03% Full Scale) . . . . . . . . . . . . . .
64
6.2
Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
6.3
Actual Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66
6.4
Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
9
/)
List of Figures
1-1
Open loop sensor configuration
1-2
. .
. . . . . . . . . . . . . . . . . . . .
15
Top view of sensor
. . . . . . . . .
. . . . . . . . . . . . . . . . . . . .
15
1-3
Side view of sensor
. . . . . . . . .
. . . . . . . . . . . . . . . . . . . .
16
1-4
Closed loop sensor configuration
. . . . . . . . . . . . . . . . . . . .
17
1-5
Preliminary feedback loop design
. . . . . . . . . . . . . . . . . . . .
19
2-1
Plant in system . . . . . . . . . . .
. . . . . . . . . . . . . .
22
2-2
Forces acting on mass . . . . . . . .
. . . . . . . . . . . . . .
22
2-3
Mass-Spring-Damper Sensor Model
. . . . . . . . . . . . . .
23
2-4
Transfer function '
. . . . . . . . . . . . . .
25
2-5
Diagram of pick-off circuit.....
. . . . . . . . . . . . . .
25
2-6
Nonlinearity due to torque constant mismatch . . . . . . . . . . . . . . . . .
27
2-7
Square-Sine Modulation scheme . . . . . . . . . . . . . . . . . . . . . . . . .
28
3-1
Closed loop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
3-2
Closed loop responses to (a) entire system (b) sensor noise . . . . . . . . . .
35
4-1
Closed loop block diagram . . . . .. . . . . . . . . . . . . .
41
4-2
Linearization of Electrostic Force about V
(s)........
10
-
v
. . . .
...
. 41
4-3
Return Path Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
4-4
Modulation, Gain, and Slew Rate Limiting Block h(t) . . . . . . . . . . . . .
43
4-5
Power Spectral Density and Histograms of Filtered White Noise . . . . . . .
46
4-6
Feedback Loop Block Diagram with Noise Sources . . . . . . . . . . . . . . .
47
4-7
Closed Loop Signal and Noise Responses . . . . . . . . . . . . . . . . . . . .
48
4-8
Closed loop responses to (a) analog SDM quantization noise (b) digital SDM
quantization noise and (c) sensor and pre-amp noise . . . . . . . . . . . . . .
48
5-1
A 1-bit oversampling converter with noise shaping . . . . . . . . . . . . . . .
51
5-2
Noise shaping loop with the linear noise model of the quantizer
. . . . . . .
51
5-3
Noise Transfer Function of a bandpass E - A design tuned to 20kHz . . . .
54
5-4
E - A A/D converter system
. . . . . . . . . . . . . . . . . . . . . . . . . .
55
5-5
Frequency response of sinc 3 filter with R=16 . . . . . . . . . . . . . . . . . .
56
5-6
Aliasing around DC with (a) OSR of 128 and sampling frequency of 5 MHz
and (b) OSR of 32 and sampling frequency of 40 kHz . . . . . . . . . . . . .
57
. . . . . . . . . . . . . . . . . . . . . . . . . .
58
5-7
E - A D/A converter system
5-8
Torque E - A loop block diagram (a) with quantizer (b) with linear noise model 60
5-9
Bode plot for E - A STF (solid) and NTF (dotted) . . . . . . . . . . . . . .
62
6-1
Accelerometer estimate under 1 g and -1 g fields . . . . . . . . . . . . . . . .
68
6-2
Residual error in bits under 1 g field
. . . . . . . . . . . . . . . . . . . . . .
69
11
List of Tables
. . . . . . .
14
. . . . . . . . . . . .
51
1.1
Existing MEMS accelerometers compared to HPA specifications
5.1
Reduction in quantizer bits as order p of noise shaping
6.1
Summary of noise sources and their output-referenced magnitudes in the
6.2
closed loop system under 1 y . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
Summary of Resource Usage . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
12
Chapter 1
Introduction
1.0.1
Technology Background
Within the last decade, the technologies used to fabricate solid-state electronics have been
applied to inertial sensors such as gyroscopes and accelerometers. [3] This has provided a
proliferation of small, reliable, cheap inertial sensors for military and commercial use. There
are several technologies and many successful implementations of MEMS accelerometers, although variations on pendulous accelerometers and vibrational accelerometers are the most
common. A major limitation of current accelerometers is their accuracy and precision, and
for applications such as precision control and inertial guidance superior performance is required. Many accelerometers are commercially available with 5mg resolution that require
external electronics or a microcontroller unit (MCU) to read out the data.[10] The High
Performance Accelerometer (HPA) developed in this thesis will have a resolution of 500pg
with integrated readout circuitry to communicate with a host computer. Table 1.1 compares the specifications of the HPA to two popular commercial accelerometers-the Analog
Devices ADXL250[1] and the MEMSIC MX1010C[6]. The Draper HPA will be designed to
outperform these lower cost, commercially available accelerometers.
13
Noise Density (mg/vH-z)
Dynamic Range (g)
Size
ADXL250
1.5
6mg to 50g
10 x 10 x 5 mm
MX1010C
1.5
1mg to log
10 x 10 x 5 mm
HPA Spec.
0.085
500pg to 50g
I x I x 1 mm
Table 1.1: Existing MEMS accelerometers compared to HPA specifications
1.0.2
Design Background
There are three common pendulous accelerometer readout methods: piezoelectric materials
directly convert mechanical work into charge, piezoresistive materials change their resistance
in response to pressure or work, and capacitive designs measure capacitance change due to
the acceleration of a proof mass. The HPA employs the capacitive method. A capacitive
approach allows several advantages over both piezoelectric and piezoresistive sensors. In
general, the low thermal coefficient of expansion of many materials can produce a thermal
coefficient of capacitance about two orders of magnitude less than the thermal coefficient of
resistance of doped silicon. Thus, capacitive methods are often much less temperature sensitive than piezoresistive approaches. Also, capacitive methods can sense DC accelerations,
whereas piezoelectric methods require dynamic input of some minimum frequency. One
downside to the use of a capacitive sensor is that it is sensitive to noise from electromagnetic
sources due to low signal levels, to which the piezoelectric and piezoresistive methods are
less sensitive.
The sensor that is used in this project has gone through a number of iterations at
Draper Laboratory. It consists of a silicon proof mass, two torque plates and two sense plates
(see Figure 1-2). The asymmetric pendulous proof mass is supported by a pair of flexure
pivots and the sense and torque plates are all built on the substrate. The proof mass rotates
when the sensor is accelerated along the vertical axis because of its asymmetry. As the mass
tilts, it accumulates charge because of changing capacitance between the mass and the sense
electrodes, and this charge is detected by a charge amplifier connected to the proof mass.
All of the previous system architectures based on this sensor have been run open
14
Proof Mass
-V
Charge
Amplifier
sq(wt)
V_out
Sense electrodes
Figure 1-1: Open loop sensor configuration
I roof MassI
Left
Torque Plates
Right
Sense
Plate
Left
Sense
Plate
Right
Torque Plates
Figure 1-2: Top view of sensor
loop. To measure a 50g acceleration in this way would require that the spring constant be
very large (i.e. a very stiff spring) to avoid the nonlinearities associated with bending the
thin connecting pieces, but a large spring constant meant that the sensitivity must be low,
and the dynamic range constraint could not be met.
15
Ax
A
xo'
Left Torque
Left Sense
|
Right
ense
Right Torque|
Figure 1-3: Side view of sensor
With a closed loop design, the position of the mass can be kept near the null position, so the sensor can be made much more sensitive without incurring nonlinearities due the
bending of the mechanical spring and the charge readout from the parallel plate sense capacitors. Metal plates are used both to capacitively sense the position of the proof mass and
to provide an electrostatic force to rebalance it. The force on the torque plates is controlled
by feedback from the charge measurement (see Figure 1-4).
1.0.3
Design Specifications
The following design constraints must be met by the closed-loop accelerometer:
16
torque-left
-V
Charge
Amplifier
sq(wt)
V
out
-
torque-right
Figure 1-4: Closed loop sensor configuration
Full Scale Range
Bias In Run Stability
Resolution
Velocity Random Walk
Scale Factor
Scale Factor Non-linearity
Bandwidth (3dB)
Operating Temperature Range
1.1
±50 g
100 pIg
500 pg
0.035 a
(85
300 PPM
9)
0.03 Full Scale
100 Hz
-40 0 C to 85 0 C
Scope of the Thesis
The HPA system can be divided into two main parts: the first is the sensor, pickoff electronics, and other analog electronics to amplify the signal to useful levels. The other part
consists of the signal processor and the controller, implemented fully digitally, which close
the loop and provide the acceleration estimate. This thesis will describe the design and
implementation of the second part. Models of the physical and analog components of the
system will be developed and verified in Chapter 2, and will be used in the design of the
digital electronics and control scheme.
17
1.1.1
Control Details
There are a few sources of nonlinearity in this system which can be improved by a reasonable
choice of feedback control. The first is the nonlinearity of the sensor as it is pulled far away
from its null position. The source of this nonlinearity is covered in more depth in Chapter
2. The solution taken to this problem is to linearize the sensor about its null position and
attempt to maintain this position with feedback control.
The second source of nonlinearity is due to the use of electrostatic force for feedback
control. The electrostatic force generated in this system is always attractive and proportional
to the square of the voltage applied. In order to use this method of control over the range
of accelerations specified, linearization about a single operating point is not possible, and a
square root module must be provided to make the system approximately linear.
The square root algorithm is difficult to perform precisely with analog electronics,
so a digital implementation is chosen. This necessitates the inclusion of analog to digital and
digital to analog converters in the system. E - A modulators are used for both conversions,
which oversample the input and push the noise out past frequencies of interest.
There
is a tradeoff concerning the oversampling rate: too little oversampling will not allow the
precision we desire, but too much oversampling will increase the delay of the decimation
filter to unacceptable levels, causing the loop to be unstable.
The initial setup for the
feedback loop is shown in Figure 1-5.
The electronics will be package in three separate chips and connected on a breadboard. A Xilinx FPGA will contain a decimator, square-root module, compensator, and
digital sigma-delta converter, while an ASIC will be made with the analog part of the control loop. Finally, the sensor is packaged individually.
18
a(t)
Sensor
Charge Amplifier -a(t)
Compensator
(1)2
Figure 1-5: Preliminary feedback loop design
1.1.2
Readout Details
The estimate of the acceleration of the mass d(t) can be made proportional to the restoring
force required to rebalance the proof mass to the null position (fcomp(t) in Figure 1-5). With
this setup, we would like to make the transfer function
(s) approximately second-order.
To read the data out to an external computer, a decimator and a serial interface
will be developed which will be implemented in the FPGA. The FPGA will communicate
with the host computer over a custom synchronous serial interface, as well as implementing
an RS-232 interface for testing purposes.
1.1.3
Design Approach
The design approach for the digital electronics used in this project was attempted mainly
from a control perspective, because of the closed loop setup necessary to achieve the goals.
The fusion of the control systems design with that of digital design was especially difficult
because of the highly nonlinear and discrete nature of many of the system components.
Much of the design work was performed using low-order analog approximations of the digital
systems, with the full models later substituted into the simulations to make sure that the
19
analog models accurately described system performance.
1.2
Organization of the Thesis
Chapter 2 begins by exploring the dynamics of the accelerometer and its associated electronics. Next, in Chapter 3, the controller is designed to null the position of the accelerometer
through electrosatic feedback with a square root module in the return path. The ramifications of the square root-square nonlinearity on the linearity of the system and the noise
output and resolution of the system is addressed in Chapter 4. When it is shown that the
square nonlinearity amplifies the noise in the return path dependent on the signal level,
the design of the output D/A converter becomes crucial to meeting the noise specification.
Chapter 5 then introduces the design methodologies and tradeoffs associated with E - A
converters, which were chosen as appropriate A/D and D/A converters for this application.
20
Chapter 2
Plant Model
As was shown in Chapter 1, the HPA sensor consists of a pendulous silicon proof mass.
When accelerated, it tilts from its null position, and this movement is detected capactively.
A second stage, known as the charge amplifier, is needed to "pick-off" a signal proportional
to the angle of deflection and convert this signal to a useful voltage for processing.
Together, the proof mass and charge amplifier consitute the plant of this system.
A two-pole model P(s) will be developed to describe their behavior. P(s) will not be an
exact model, because there are various sources of nonlinearity inherent in the plant, and the
sources and magnitudes of these effects are presented. It is shown that a closed-loop control
scheme which attempts to keep the proof mass in its null position will serve to minimize
most of the plant nonlinearities.
Finally, a modulation scheme is presented and the effects of various sensor parameters on intrinsic noise generation are analyzed.
2.1
Sensor dynamics
The HPA sensor consists of a proof mass suspended asymmetrically in air by an elastic silicon
flexure arm. As it accelerates, both a viscous damping force and an elastic restoring force
21
P(jsj
__
__
()
q, (t)
a(t)
+
Sensor
Charge Amplifier
Compensator
acomp( )
()2
Figure 2-1: Plant in system
act to impede its motion.
Each of these forces effects have nonlinearities associated with
them which grow with the deflection from the resting position. One of the chief reasons for
closed loop control is to null the position of the proof mass and thereby minimize the effect
of the nonlinearities. In this chapter, a simple mass-spring-damper model (see Figure 2-3)
is developed that will be used for the design and simulation of the system.
L
kO+
bOw(x) = ma
Figure 2-2: Forces acting on mass
Figure 2-2 shows how the pendulous mass reacts when placed in an acceleration
22
Damper
Spring
k
b
Mass
X
M
Figure 2-3: Mass-Spring-Damper Sensor Model
field. The force balance on the pendulum is
ma
ET
f
=
=
If 0 is kept small, then sin
xma sin(0)dx - bw - kG
(12 - 12 )ma sin 0 - bw - kO
~ 0 and Ax f
d,0. Equation 2.1 simplifies to m#
( 2.1)
=
(l-
l)ma0 - b - kG, and its Laplace transform is Equation 2.2.
-(s)
O
1_
12
_ 12)
=
a
s2+
(2.2)
bs+
The sense plates are placed symmetrically about the pivot of the proof mass a
distance xO below the proof mass and a distance d, to the sides. As the mass rotates about
its center, the capacitance between the sense plates and the proof mass changes.
C =
C
In the null position, C, = C, = CO
Ac
xo + Ax
(2.3)
Ac
(2.4)
A
X-
Ax
If the voltage on the two sense plates are set equal
and of opposite signs, the differential capacitance of the system is proportional to the charge
23
on the proof mass.
Q,
=
CiVS+C(-V)
=
V(CI-
Cr)
-2VC
0
AX+
XO
When Ax <
(A)3
2
-+
-
- - +-
---
-
2 +(X3
AX
IA
_VSCO
=
A)
1--+ A-±(x
=VCO
+
Ax
+-
(2.5)
XO
'\XO)
xO, Q ~ -2V 3 C0 x, and Ax = dsinO ~ d,0. Then the overall
response of the sensor is approximately Equation 2.6 for small deflections.
The transfer
function of the accelerometer model used in this design is plotted in Figure 2-4.
-2VsCode (12
(s
-1k)
2xo
a (S)
2
m
2.2
(2.6)
+ bS +k
m
Pick-off Electronics
The pick-off circuit is the charge amplifier shown in Figure 2-5. The charge
Q,
on the proof
mass produces a current at the input of the op-amp of
i, =
dQ,
di = VS
d( AC)
dt
dv5
+ AC d
(2.7)
With v, == V e'jwt
i,= [V
%) + ACjwl ejwt
(2.8)
Then if w is chosen large enough, then the first term is dominated by the second, and
24
Bode Diagram
-40
-45-
60
-
- --
--
55 -
-
--
-
-
-
- -.- ---
-
- -
-
--
- --
-50 -
-..
.
-65--70 ------
-7 5 - --
-
-
-
-
-
---
_0
-45
i-ure
-90
- -.-.-.-.-.-.-.--
-135
-functn
.Transfe
2-4:
(
-
-
1 80 - .- . . .-.- . -.
.- -
-.-.-
- - --
--
- -
--
-
-1
103
Frequency (Hz)
Figure 2-4: Transfer function
(s)
R
C
-V
Cr
sq(wt)
V_out
C_1
-- +
Figure 2-5: Diagram of pick-off circuit
we can see that the current will be proportional to the differential capacitance modulated by
the sense voltage. To measure DC signals, V, must be a carrier at some frequency fm > 0.
In order to avoid flicker (1/f) noise as well as aliasing into the signal band, fm is nominally
set to 20kHz, somewhat above the frequencies of interest in the sensor.
Assuming an ideal op-amp model, the output voltage Vee will be the negative of
25
the product of the input current and the feedback impedance. With v, set as a square wave
with magnitude V, and radian frequency wm =
V (S) =
2
1
I i =
f
R 1 C~s+1~ RfCfs+l
If the time constant is set such that Rf C
like an integrator and V = (sq(wmt).
(s)
2.3
7fm,
V (s)
a
>
C
sq(wot)
8ddt
(2.9)
1, then the feedback impedance behaves
Then the plant transfer function is
C0 Vdo(l( l12
CXo(S2 +bS+
sq(wmt)
(2.10)
Nonlinearity sources
There are a few sources of nonlinearity in the sensor.
" The restoring torque due to the torsion of the suspending arms is not linear over the
entire range of motion, but stiffens with greater deflections. Thus, Equation 2.1 is
an approximation where the final term kG approximates the restoring force Frest =
kG + k 2 02 + k3 03
+
- -- ~ kG for small angles of deflection
0.
" The charge measurement has higher order dependencies, as can be seen in Equation
2.5, which simplifies to
Q=
-2VCod,9/xo for small deflections.
* The proof mass is placed asymmetrically on the flexure while the torque plates are
symmetrically placed. This results in a nonlinearity when switching between the two
sides of the proof mass because the application of a voltage to the left side produces a
different torque than the sample voltage applied to the right.
Because this gain is effectively in the return path of the closed-loop feedback structure,
the effect on the output will be mitigated, but still be detectable due to a small change
in the dc gain of the closed-loop system. For example, if the system has forward transfer
26
acceleration
-A
square voltage
(VA2)
Figure 2-6: Nonlinearity due to torque constant mismatch
function G(s) and return path transfer function H(s), the DC gain of the system will
be R (0) =
G(O)
1+G(O)H(O)
Assuming that the DC loop gain G(O)H(O)
>> 1, K(O)
Then if torque coef-
1
ficients differ by Akr, the full-scale nonlinearity of the system will be approximately
equal to
k
for small Ak,.
Thus, the nonlinearity propagates linearly through the
closed-loop system. The nonlinearity will also impart a bias to signals which are applied to both torque plates. If a sine wave of amplitude A were passed through, it
would result in an output with mean - [(1 - kr)2A - 2A]
=
-.
Similarly, any zero
mean signal will acquire a bias when switched onto these mismatched torquers because
half the area under the signal (i.e. the half which is applied to the torquer with a
smaller constant) will be reduced in magnitude compared to the other half.
An effective way to null this factor is to measure the nonlinearity and pre-multiply the
force correction signal depending on which side of the sensor is being torqued. If a high
precision multiplier is added to the return path of the system, then this nonlinearity
can be virtually eliminated. In the HPA design, a 24-bit multiplier was used in the
feedback path, allowing for very precise scale factor compensation.
The precision of the compensation values is limited only by our ability to measure
them. Fortunately, opening the loop and bypassing the integrator in the forward path
27
allows us to measure these values with great precision when the acceleration input is
known.
* The largest nonlinearity is the square nature of electrostatic force used to balance the
sensor in the feedback path. The effects of this nonlinearity will be further explored
in Chapter 4.
2.4
Modulation
The ramifications of the square wave modulation scheme used to pick off the charge from
the sensor are explored in this section.
2.4.1
Carrier generation
A square wave can be generated by a simple digital counter that rolls over every M cycles
of the system clock. An in-phase sine wave can be generated by storing M samples of a sine
wave at the system clock rate and using the counter value as an index into the table in which
these values are stored.
2.4.2
Harmonic Distortion due to Square Wave Modulation
X(t)
h(t)|
,x
sq(wct)
X
(t)
sin(wet)
Figure 2-7: Square-Sine Modulation scheme
When multiplying by a square wave, the signal is upmodulated by the fundamental
frequency as well as all of its odd harmonics. When we demodulate with a sine wave, the
signal around the fundamental is returned to DC, while the imaged replicas remain at the
28
even harmonics.
The harmonic content can then be filtered out with an appropriate low
pass filter to restore the original signal. Because the signal energy was spread over all the
harmonics, the square-sine modulation scheme does not have unity gain, but instead the
gain calculated below. Ignoring the A/D, the demodulated signal is
(2.11)
sin(went)
sq(wct) =
nodd
x(t)sq(wet)
Xm(t)
=
ym(t)
= xm(t) *h(t)
=
(t)
(x(t) * h(t)) sq(wet)
= (x(t) * h(t)) sq(wet) sin(wet)
-- sin(went)
= (x(t) * h(t)) sin(wet)
nodd
=
(x(t) * h(t))
7M
004
~
sin(42 (wct) + sin(wct)
1:
\
7r/2
2.5
,
n odd
(2.12)
mrn
The time average (sin(mwet) sin(nwet))
pair exhibit a DC gain of
sin(went)
n=3
n , so the modulator/demodulator
1/2,
m
0,
m f n
~ 0.6366.
Instrinsic Noise
Due to the very small level of the charges in the sensor, amplification is necessary to produce
useable voltages for the digital electronics. There is a non-significant level of noise produced
by the charge amplifier, most of which is thermal (T)
noise from the feedback capacitor Cf
(see Figure 2-5). This noise will be modelled as an additive white gaussian noise (AWGN)
process with power or .
The current design of the sensor that was used for testing had a noise density of
29
approximately 287 ig/VHIz at the output of the amplifier, which is unacceptably high, since
the sensor noise itself far exceeds the random walk specification of 85 pjg/Iz.
To improve
this value, one can either make the sensor itself more sensitive by increasing the size of the
proof mass or use lower noise amplifiers.
If the proof mass size is increased, then the sensor package must expand in all
directions, because both the sense plates and the torque plates must grow proportionally.
The gap between the package and the proof mass along the acceleration axis must also grow,
since the mass will then move further for a given acceleration.
The positive result from
this increase is that since the mass moves further, the electronics must amplify the charge
proportionally less, resulting in a linear reduction of noise amplitude when varying the proof
mass size.
A sensor design is currently in fabrication which takes advantage of both of these
results. The new sensor will be twice as sensitive as the current design and use amplifiers
with approximately three times less noise than those in the current design.
This should
result in a decrease of the open loop sensor noise to approximately 48 pg/vHz, which seems
reasonable in proportion to the random walk specification.
30
Chapter 3
Compensator Design and
Implementation
In Chapter 2, we modelled the dynamics of the sensor and its associated electronics. In
this chapter, we will develop a compensation technique to estimate the acceleration based
on the sensor model. The structure of the compensation is shown in Figure 3-1: we will
need to compensate for the nonlinearity of the feedback mechanism in the return path while
implementing the controller in the forward path.
a(t)
+
G(s)
P(s)
H(s)
(.)2
Compensator
Figure 3-1: Closed loop block diagram
31
(t)
In Chapter 2, the plant was modelled as the second-order system
P(s) =
s2 + mbs+
(3.1)
m
Then we would like to choose G(s) and H(s) such that &(t) is a good approximation to a(t).
3.1
Compensator criteria
At first look, the design of the compensator blocks seems quite open, but there are a few
conditions which significantly narrow the range of the possible design parameters.
100 Hz bandwidth As the closed-loop bandwidth is usually just below the open loop
transfer function, a design that crosses over just above 100 Hz is desired.
Return path is approximately linear In order for the feedback loop to operate correctly
and C(t) to be an accurate estimate of a(t), we require that the system blocks look
approximately linear. In Chapter 4, we will discuss the options that are available to
us and show that a square root block is the right choice for this application. Thus, we
will choose H(s) a square root block with gain HO.
Proof mass position nulled In order to null the output of the system for DC inputs, we
look at the steady state response to a step input. Using the Final Value Theorem:
AxSS
AX
=
s A (s)A(s)
AI8-*>
G(s)
1 + kG(s)P(s)
2+
32
s+
)
(3.2)
We let G(s) take the general form of a PID controller:
G(s)= -
IS
+kDs+kp
(3.3)
Then Equation 3.2 becomes
A
kDs 4
=3+
+ (kp +
kD
) 3 + (kI
+
kD
S2 ±
...
(3.4)
We see then that the zero steady-state position condition means that both kD and kp
must be zero, i.e. a PID controller must contain only a pure integrator. In a more
general context, the condition that G(s) has more poles than zeros is sufficient to
guarantee zero steady-state position.
> 45% Phase Margin The system must not oscillate excessively. 45% phase margin corresponds to about 18% overshoot in the step response. We have shown that when
G(s) is a pure integrator, all of the previous constraints can be met. An integrator
introduces -9 0 'phase, which leaves us with another 45 0 of phase around 100 Hz to play
with. Higher-order integration meets the zero error to a step constraint, but introduces
another -90*of phase into the system for each integrator, which will make it practically
impossible to realize sufficient phase margins.
If an integrator G(s) = -S is chosen for the forward path gain, and H(s) is a gain
H followed by a square root block, then the open loop transfer function is
s
IS(S2
L(s) = P(s)G(s)H(s) =
s
+ A S + k)
(3.5)
and the closed loop transfer function is
GCo
A(S) =
A
+
s3 +
s2 +
33
ks+ GoPoHo
(3.6)
We can see in Figure 2-4 that at 100 Hz, IP(100j)I e Po - -40dB and LP(100j) ~~
0. Ho is set such that the DC gain of the system is at the desired level. Using these two
parameters, setting L(100j) =1 returns the condition that
Go =
100
(3.7)
Fo Ho
With the return gain nominally set to 1, we get the responses of Figure 3-2(a) for
the closed loop system gain and closed loop sensor noise gain. One can see that the noise is
amplified quite a bit in the signal band, which is not optimal. Depending on the amount of
sensor noise to the other processes corrupting our acceleration estimate, we might want to
reduce this amplification factor. To reduce the noise gain, we can do one of two things:
Increase Ho Increasing the gain of the return path will decrease the amount of sensor noise
at the output but will not increase the signal to noise ratio. This is because increasing
Ho decreases the scale factor of the output proportionally.
Increase P 0 Increasing Po is the more reasonable choice. Basically, this translates into
making the sensor more sensitive (i.e. for a given amount of acceleration, it moves
further). This allows us to reduce the forward gain from the noise input to the output
(Go) while maintaining the same bandwidth.
This may not always be an option,
though, since the sensitivity of the device affects many aspects of its design, including
size, cost, and many other factors beyond the scope of this thesis.
3.2
Implementation Details
3.2.1
Register Width
To be able to distinguish signals in the range of 50g down to 500 Mg, we to represent the
signals in the gate array with at least [log 2
(500-10)]
=
17 bits. Thus, the system parameters
17
must be chosen such that the noise variance at the output of the integrator is less than 2 2- 12
34
Bode Diagram
0-5
-
-10-
-
-15-
-
-
-
-
-20-
-
-
-25
-45 -
-90 -
-135
-
-
-
-18010
tO
Frequency (rad/sec)
10
(a)
Bode Diagram
40
35 30 -
25 -
20
-45
-90
10,
1oo
Frequency (rad/sec)
to
(b)
Figure 3-2: Closed loop responses to (a) entire system (b) sensor noise
A register width of 24 bits was chosen so that the noise at the output due to quantization noise is far below that due to the sensor and analog electronics.
35
3.2.2
Square Root Algorithm
Newton Ralphson Method
An iterative version of the Newton-Raphson method is a common square root implementation. The general Newton-Raphson method begins with an estimate xO of a root of a function
f (x), and a set of successive approximations {xn} is generated by the iterative formula
Xn+1= -Xn -
f(xn)
f '(xn)
(3.8)
In the case where the square root of a is desired, letting the function f(x) = x -- a
results in a root x = ±V/-. Because f'(x) =
Xn+=
,)the
iteration reduces to
Xn -
-
(3.9)
where xn denotes the n-th approximation of the root. This calculation involves the use of a
N-bit multiplier to find a square root of length N, so is more convienient to use in software,
where a multiply instruction is often much less expensive to implement than in hardware.
Direct Method
Reference [7] describes a less gate-expensive class of square root implementations. Referred
to as direct or digit-by-digit methods, they are based on the concept of completing the
square. The fundamental recursion is
Xi = X(i-1) - (2Y(i-1) + yi2-i) yi 2 -' = X0 - Y2
(3.10)
Y =- Y + (i - 1) + yi2-'
(3.11)
where
36
Xi is the ith partial remainder (residual), Xo is the radicand, Y is the ith partially developed
square root, and yj is the ith square root digit.
Based on this result, the iteration of Equation 3.12 can be derived, which is performed with one subtraction and one concatenation.
Xj = XO-1) - (2yjY(-1) + y2)
(3.12)
The iteration first determines the most significant bits of the result and one successive bit is determine for each iteration. Thus, an N-bit square root takes N iterations.
Steps of the Algorithm
Initial step Determine the approximate square root of the first two bits. If the radicand is
A = A1A 2A 3 ... , where A1 is the MSB, then the first bit fo the residual (X 1 ) and the
first square root digit (yi) are determined as in the table below:
A1 A 2
Y1
00
0
00
01
1
00
10
1
01
11
1
10
X
1
Iteration step For successive iterations, the next two most significant bits of the input
operand A are concatenated with the residual and from that is subtracted the approximate square root concatenated with "01". If the residual with the two new bits is
greater than or equal to the approximate square root concatenated with "01", then the
newroot is the old root concatenated with a '1' and the new residual is the remainder
after the subtraction has occurred. If not, the new root is the old root concatenated
37
with a '0' and the new residual is the old residual with the two new bits.
remi
=
cat(X(i_1 ), A 2 (i-1)A(2 i-1))
1,3
to,
-
cat(Y(_1), 01)
(3.13)
if remi ;> 0
if remi < 0
x remi,
Xi
(3.14)
=
cat(X(j-1), A 2 (i-j)A(2 i-1)),
if remi > 0
(3.15)
if remi < 0
End.
Quantization Noise
3.2.3
Since the output of the square root algorithm is quantized to B bits in signed magnitude
representation, it is modeled as an additive white gaussian noise source
2-2
2
-2(B-1).
with variance
The signal is assumed to be sufficiently "busy" such that the errors are well-
distributed across the
3.3
esqt[n]
2B
bins.
Random Walk
Sometimes, the acceleration estimate is integrated to be used as a velocity estimate. Noise
on the acceleration estimate can cause a random walk in the velocity estimate, which corresponds to a growth in the variance of the velocity estimate grows as a function of time. If
the velocity estimate is calculated with an ideal discrete accumulator, and the acceleration
estimate has noise process ea[n], then the error in the velocity estimate will be
n
ev[n] = T
ea[n]
t=O
38
This has a variance of
n-1
01 2[n]
2
rnT Raa[0] + 2T >~
2
(3.16)
izO
If u [n] grows as a function of time, then the velocity estimate is said to have a random
walk.
If ea[n] is assumed to be white with variance or., then the variance of the velocity
estimation error is
2 [n]
= nT 2 0r
and the standard deviation of the velocity error as a function of time is
,[n] = v/Toavt
Thus, to meet the specified o, = 0.03V t
Oa < 0. 0 3 5 m/s
-~ vrh2
(3.17)
, we need
0.035
9.8-/3600T
_Pg
= 85
V'HIzY
This is equivalent to a standard deviation of 8.6 bits if 24-bit registers are being used.
39
Chapter 4
Noise Propagation through
Electrostatic Torquer
In this chapter, it is shown that compensating for the square nonlinearity of the electrostatic
force by applying the square root of the acceleration estimate (with appropriate gain) is
preferable over other methods. If the output of the square root module were applied directly
to the torque plates on the sensor, then the feedback path would simply look like a gain. Since
the square root is much more easily performed digitally, additional processing is required
between the square root module and the application to the sensor.
The effects of noise
generated in between the square root module and the squaring due to the electrostatic force
are explored in this context, and it is shown that white noise generated inside will still be
white when applied to the sensor, but will have a signal-dependent amplitude.
The nonlinearity of the electrostatic force causes a problem for the linear feedback
framework that has been set up for this problem. To deal with this issue, there are basically
two options-linearization and compensation.
40
a(t)
+
P(s)
G(s)
acoqmp Mi
H-H
0 &
Hi(s)
(_)2
Critical area
Figure 4-1: Closed loop block diagram
4.1
Linearization
One solution to this problem is to linearize the nonlinear function about an operating point.
The electrostatic torque relation is rE
would have dTE
kV 2 , so linearizing about a bias voltage V, we
2kVbdV. There is no one operating point that can be chosen such that
the relation can be well enough approximated over the specified range of the sensor, as can
be easily seen in Figure 4-2, where the relation was linearized about Vma/2.
eliminates linearization as an option in this system.
50
,
30
+-D
0
~10
0
0
2
4
6
voltage (V)
8
Figure 4-2: Linearization of Electrostic Force about V
41
=v
2
This fact
4.2
Compensation
The other possibility is to insert a square root block to compensate for the square dependency.
With an ideal square root immediately preceding the application of the voltage to the torque
plates, the effects of this nonlinearity would be eliminated. Unfortunately, this is not possible,
and we must settle for less ideal circumstances.
Because the square root module is only
practical to perform digitally, there must be additional analog and digital electronics between
the square root block and electrostatic torque plates. This less desirable condition must be
explored to see what effects these additional elements have on the overall system performance.
4.3
Effect of intermediate blocks
The intermediate system h(t) is to amplifies x(t) appropriately such that the maximum
value of x(t) corresponds to the maximum torque which may be applied to the sensor (50
g).
It also filters x(t) to prevent the amplifier from slew rate limiting and modulates and
demodules x(t) with square waves for reasons that will be explained later. The transfer
function between the sqrt - I and the (-)2 block cannot be seen as the original time response
squared, because it is inherently not a linear system.
A DC bias is obtained due to the
rectification, and a signal-dependent noise variance is added.
X 2(t)
:
XO
t
+
h(t)
iHt
(_)2
edsdm (t)
Figure 4-3: Return Path Block Diagram
42
y(t) =
2(t)
sq(wht)
Figure 4-4: Modulation, Gain, and Slew Rate Limiting Block h(t)
4.3.1
Effects on Signal
An input x(t) that is band-limited to w; will not be affected by the low-pass characteristic
of h(t) if wx + Wh < 1/r. In that case, the filter h(t) reduces to the gain k, so i(t) is
x(t) modulated by a square wave. The squaring that occurs demodulates the signal, so the
output
2
(t) is simply the original signal corrupted by the even harmonics of the modulation
frequency.
4.3.2
.(t)
=
kx(t)sq(wct)
i2(t)
=
(kx(t)sq(wet)) 2
=
kx(t)
(I
+
(4.1)
E
sin(whnt)
(4.2)
Effects on Noise
If we assume that the square root and square blocks are ideal, then the only noise effects
that are affected by the nonlinearity are the noise sources between the two nonlinear blocks.
22(t) =
x(i) + W(t))2
=x 2 ()
+ 2x(t)w(t) + W2(t)
43
(4.3)
With x(t) known and
edsdm(t)
E[y(t)]
E[x 2 (t) + 2x(t)w(t) + w 2 (t)]
=
or
a white Gaussian noise process w(t), uncorrelated with x(t):
x 2 (t)
+ 2x(t)E[w(t)] + E[w2 (t)]
(4.4)
= E[y2 (t)] - E[y(t)]2
=
E[x 4 (t) + 4x 3 (t)w(t) + 6x 2 (t)W2 (t) + 4x(t )w3 (t)
+w 4 (t)]
-
(x 2 (t) +
2E[x(t)w(t)] + E[w2 (t)]) 2
(4.5)
if w(t) is zero-mean with variance ao,:
E[y(t)]
=
X2 (t) + OW
(4.6)
a2
=
4E[x 3 (t)w(t)J + 6E[x2 (t)w 2 (t)] + 4E[x(t)w 3 (t)]
+E[w'(t)] - 2x 2 (t)O2 - E[w4 ]
(4.7)
If w(t) and x(t) are independent:
o
= 4x 3 (t)E[w(t)] + 6x 2 (t)E[w 2 (t) + 4x(t)E[w3 (t)]
+E[w 4 (t)] - 2x 2 (t)i2j - E[w4]
(4.8)
By introducing the square nonlinearity, the noise at the output of the square block is no
longer white, and now depends not only on the statistics of x(t), but also on the higherorder statistics of w(t). The skewness of w[5], is a measure of symmetry of a distribution,
and is defined to be the third central moment dividing by the cube of the standard deviation
(see reference [5]).
skewness(x)
=
E [(X
t) 3 ]
(4.9)
The skewness of any normally-distributed process is zero, since the normal distribution is symmetric about its mean. When a signal is zero-mean, the skewness reduces to
44
E [x3] /a 3 . Since skewness(w) = 0, then E[w 3 ] = 0.
The fourth-order statistics of a signal are commonly calculated in the form of the
kurtosis, which measures whether a signal is peaked or flat compared to the normal distribution.
kurtosis(x)
-
E
[(X
t)4]
-
(4.10)
The kurtosis of a normal distribution is 3. Since w(t) is a zero-mean process, the
kurtosis reduces to E [x 4] /a 4. Then E[w 4} = 304.
Substituting in the third and fourth
moments of w into Equation 4.8 results in a simple formula for the variance of the output
noise:
o=
4x 2 (t)2 +204
(4.11)
Then if w(t) is a zero-mean AWGN process, then the bias error at the sensor input
is simply the variance of w(t) (cf. Equation 4.4). This makes the bias strongly coupled
with the amount of noise introduced between the between the sqrtj - I and the (-)2 blocks,
most notably the E - A, which is prone to producing tones and other time- and amplitudedependent noise which would affect the bias. Fortunately, the level of the bias is low, as will
be shown in the first-pass design, and whatever dead zone is created by the bias error will
be mitigated by the feedback control system.
When y(t)
>
2,
the variance of the noise added in these blocks should be propor-
tional to the mean of y(t), so the signal to noise ratio should look constant over a wide range
of signal levels, and only rise for the smallest input values.
4.3.3
Noise is filtered before squaring
Now, let's look at the case where the w(t) is filtered white noise. Equations 4.3 through 4.8
will still hold for Cv(t) = w(t) * h(t), since all that was assumed was that w(t) is zero-mean
45
and independent of x(t). Because h(t) is a linear filter, then 6(t) is also zero-mean and
independent of x(t). The skewness and kurtosis of 7i(t) are also the same as in the white
noise case, since the distribution of the noise process remains Gaussian, and therefore has
the same shape and thus the same skewness and kurtosis.
A graphical example of a Matlab simulation demonstrates this fact in Figure 4.3.3.
In this example, the power spectral densities and histograms of the distributions are shown
for (a) a white noise process w[n], (b) w[n] low pass-filtered, and (c) w[n] high pass-filtered.
One can see that although the noise process is filtered, the distribution remains Gaussian,
and thus has zero skewness and kurtosis 3.
White noise: o2 = 0.9994 White noise: skewness = -0.0042, kurtosis = 3.0052
a 0.5
.9000
0
bo
2000
Ednoo
%U
[
0.2 0.4 20.6 0.8
Low pass: or = 0.0326
01
j
-5
0
5
Low pass: skewness = 0.0070, kurtosis = 3.012
1
50
.000
0
-- 50
-- -
,.0
------------- ..........
3000
...... .......
....... .........
900
bO
2100
.............................
%000
m2150
0.2 0.4 P.6 0.8
-e 0 High
pass: o-= 0.9667
50
6'10
00
-5
0
5
High pass: skewness = -0.0061, kurtosis = 3.0034
1
.4000
3000
3-10
$20
"9000
o-40
%000
0)
0.2
0.4
0.6
0.8
1
0
-5
0
Frequency
Figure 4-5: Power Spectral Density and Histograms of Filtered White Noise
46
5
Since the mean and skewness of 'iDare zero and the kurtosis of fJ is equal to that of
w, the mean and variance of the system with input zZ have the same form as for input w.
E[y(t)]
=
02
4.4
x 2 (t)+c,
(4.12)
4X2 (t)or±+26r%
(4.13)
Closed loop response
With the additive noise model, the total noise level at the output of the system is simply
the sum of the closed-loop response of each noise source. The various noise sources and their
respective locations in the control loop are shown in Figure 4-6. The closed loop responses
are shown symbolically below in Figure 4-7, and the relative magnitudes of their variances
will be further explored after completing the first-pass design.
e n]
~
+
+~)H~w
~
Hcz]
+
ms
xf [n]
X. [n]
x[n]
X(t)
--
Hcomp [z]
a!b(t)
-g ()--H(S)
+
HIPf (Z)
+
Hsdm (Z)
edsdm [n]
e,(t)
Figure 4-6: Feedback Loop Block Diagram with Noise Sources
47
-
Ac(s)
Hoj(s)
=
-
GKHpf Hsensor(S)Hcic(S)Hint(S)
Hdc(s)Hint(s)K
Ex
Esdm,
(4.15)
1 + GKHpf Hensor(S)Heic(S)Hint(S)
(s)
GKHsdmDHsense(S)HiP(S)Hic(S)Hint(s)
(S)
(4.14)
(4.16)
1 + GKHpf(S)Hsensor(S)Hcic(S)Hint(S)
Figure 4-7: Closed Loop Signal and Noise Responses
Bode Dagoo
20
-20
0-20
-40-
-135-ISO-
-225
-270
fo,
F-.,o~
10'
(,.dvo2)
(a)
00rj
Fr.q..y (-W-o~)
Ic?
(b)
10-
r
-to-
-201
-46
I
-1351
Icr
10'
(c)
Figure 4-8: Closed loop responses to (a) analog SDM quantization noise (b) digital SDM
quantization noise and (c) sensor and pre-amp noise
48
Chapter 5
Sigma Delta Modulation for A/D and
D/A Conversion
In this chapter, it will be shown that E - A converters are appropriate for use in the HPA
system due to their very high signal to noise ratio for low frequency signals and the linearity
that they allow. We will explore the basic operation of these converters and how they employ
oversampling and noise-shaping to produce these results. The quantization noise added to
the signal by E - A converters will be discussed in the context of this project, and a design
is presented for a E - A digital to analog (D/A) converter.
In this application, we have to rely on very precise, but not very fast signals, as
well as linearity over temperature. Both of these applications strongly point to the use of
a E - A converter with single-bit quantization.
Sigma Delta converters are becoming a
standard method for implementing high resolution A/D and D/A converters in silicon for
many reasons[2]. Among these are the following:
" high resolution quantization is attained with simple circuits
" the circuits are robust to imperfections
" it allows for speed vs. resolution tradeoffs
49
. ease of implementation on a CMOS process
5.1
Sigma Delta Modulation Background
An ideal A/D converter converts a continuous-time signal into a discrete-time signal with
infinite precision, so that x[n] = x(nT), when sampled every T seconds. Because digital
systems do not have infinite precision, the quantized signal i[n] = Q(x[n]) will not generally
equal x[n]. The difference between them is the quantization error ex[n] = i[n]-x[n]. We take
the standard apprioach and model e,[n] as a white, stationary random process, uncorrelated
with x[n] and uniform over the range of values A which it can take. The quantization error
has variance
2
2
_A
or
(5.1)
12
Generally speaking, Sigma Delta converters are defined to be those that employ
oversampling and noise shaping to achieve high resolution. A basic Sigma Delta converter
design is shown in Figure 5-1. The easiest way to understand Sigma Delta converter operation
is in terms of the frequency-domain description of its "linear model", shown in Figure 5-2. In
this model, a nonlinear operation, quantization, is replaced by the addition of a noise signal.
Linear system theory is then invoked to show that the output y[n] is therefore the sum of the
filtered input signal x[n] and the filtered quantization noise e[n]. The two components can
be filtered independently, under the control of the designer by changing the characteristics
of the loop transfer function L(eiw).
R (ew)
STF =
NTF
L (ejw)
(jw)=
.
E()
1
1+L(ew)(5.3)
50
(5.2)
x[n]
+L
(es'')
-
R~n---
+y[n]
Qff-n-Mzier
D/A
Figure 5-1: A 1-bit oversampling converter with noise shaping
x [n]__
L (es'')
+
yn
Figure 5-2: Noise shaping loop with the linear noise model of the quantizer
After the noise shaping stage, the noise pushed out of the signal band is then eliminated and the signal returned to the lower sampling frequency by downsampling r[n].
Table 5.1, taken from [9], shows the theoretical reduction in quantizer bits possible
as a result of noise shaping. For example, if a 4th-order noise shaper was being used, and
we wanted to convert a sample to B bits, then oversampling by a factor of R=4 would allow
us to use a (B-4)-bit quantizer. With R=32, we could use a (B-17)-bit quantizer, etc.
Quantizer order p
0
1
2
3
4
5
4
1.0
2.2
2.9
3.5
4.1
4.6
Oversampling factor R
8
16
32
64
1.5
2.0
2.5
3.0
3.7
5.1
6.6
8.1
5.4
7.9 10.4 12.9
7.0 10.5 14.0 17.5
8.5 13.0 17.5 22.0
10.0 15.5 21.0 26.5
128
3.5
9.6
15.4
21.0
26.5
32.0
Table 5.1: Reduction in quantizer bits as order p of noise shaping
51
E - A Converter Noise
5.2
5.2.1
Quantization Noise
For the same reasons that an analog E - A converter was chosen as the A/D element in this
system, a digital E - A converter was chosen as the D/A element. To be able to convert the
required dynamic range, we need a signal to quantization noise ratio greater than 100 dB in
the signal band. We look to Table 5.1 to see that we need to oversample by at least 32 for
a fourth-order E - A, 64 for third-order, and 256 for second-order modulator.
Also, we have to beware when designing this block that it is in the most sensitive
part of the loop, because any noise that is not filtered out by the analog lowpass filter
following the E - A is amplified and rectified. As was shown in Section 4.3.2, this noise is
amplified based on the current signal level and also generates a small DC bias.
5.2.2
Other noise in the SDM
* Idle tones due to pattern noise Certain types of analog E - A architectures have
been proven to be nontonal [8], but only for DC inputs. Mathematical models often
fail both in the prediction of the location and magnitudes of idle tones. Idle tones are
more likely to occur in digital systems because of the periodicity of discrete processing
of a DC signal 1 Because all signals in a digital system are rational-valued, cycles can
form at the quantizer input that result in tones at the output of the E - A.
The tones that develop are also often correlated with the amplitude of the input signal.
Smaller input signals result in lower-frequency tones. It is only these lower-frequency
tones that concern us in this application, since the signal band is so narrow in com-
parison to the bandwidth of the E - A modulator.
In factor, it will be shown later that because the oversampling ratio is chosen so large,
'[8], page 9.
52
that idle tones play no substantial part in the HPA design.
" Dead zones occur due to low gain, leaky integrators. To not get dead zones, we
need L(ej') to have a DC gain greater than the oversampling ratio R. This can be
easily implemented in a digital E - A converter by choosing a simple accumulator with
transfer function
1
L(67w') =
1,(5.4)
The digital accumulator has no leakage and the model only breaks down upon saturation.
" Quantizer overload This is one of the most serious problems that must be avoided
in the implementation of a digital E - A converter. The quantizer maps an input u to
a quantized value q(u). If u is in the region B = {-A, +A} (where the quantization
levels are ±A/2 and the step size is A), then the error c = q(u) - u is never more than
A/2. Outside B, the error is greater than A/2, and the quantizer is said to overload.
The linear analysis model assumes no overload conditions, and fails if such a condition
does occur, causing a host of nonlinearities and noise generation far above what is
predicted.
2
Due to the complexity of factors and the lack of mathematical tools to predict the
complex noise patterns of E - A modulators, the true performance can only be estimated,
and then rigorous simulation is done to discover any weak points of the design.
5.3
Sigma Delta Analog to Digital Converter
It was calculated above that we need at least 17 bits of resolution to be able to represent all
the signals in the range of the sensor. Also, we would like to make the quantization noise
2[8],
Chapter 2.
53
much less than that of the analog electronics. Then it is desirable to increase the digital bit
width, for which a convenient value of 24 bits was chosen. Table 5.1 shows that with an
oversampling ratio of 128 and a 3rd-order 1-bit E - A converter, it is theoretically possible
to attain adequate noise shaping to accurately quantize to about 22 bits. This would result
in a noise process at the output of the system with power about 60 p1 g/IHz. Because the
input to the A/D converter is modulated by a carrier at fin, the E - A is "tuned" to fM,
such that the noise transfer function looks like a band-reject filter with the stopband at f-.
The design of this E - A modulator is beyond the scope of this thesis. An example noise
transfer function is shown in Figure 5-3.
-85
.~~~~~~~~~~~~
-90
-.
-95
-.
-.
.
~
.
.
.-
. .. . . .
---------------
-a -100
-
-.
c,)
.-
M -105
E
CL-1
a -115
-120
--
-125
. .. .
- -
-130
0
. -- -- - _ --....I.
0.5
1
........ 1.5
-
- - - - -..
. . ..
.
- ....
--..-- 2
2.5
Frequency
.
- ..... ..
3
.--..
--- -
-..
....... - .......
3.5
4
4.5
x 104
Figure 5-3: Noise Transfer Function of a bandpass E - A design tuned to 20kHz
The bandpass E - A converter was not available at the time of testing, so a commercially available part, the Analog Devices AD7720, was used. It is listed as implementing
a 7th-order noise shaping loop with a large bandwidth, but has a higher noise floor than
would be ideal due to circuit nonidealities such as thermal noise in its internal amplifiers.
Due to the unavailability of the exact design of the AD7720, the noise transfer function was
54
estimated and measured, and basically appeared to have a constant -110 dB noise floor over
the signal band of ± 100 Hz around fin, which corresponded well with its datasheet. This
would predict about 158 pig/vHz of noise in the closed loop system.
5.4
Decimation for Oversampling A/D converters
Oversampling A/D converters rely on digital decimation filters to remove out of band noise
so that the unwanted noise about the Nyquist band is not aliased into the baseband by the
downsampling process. In principle, any number of filter designs could be applied to meet
the requirements, but hardware considerations suggest a few architectures that make the
design more practical. For example, some architectures minimize coefficient word lengths,
eliminate the need for a high-speed parallel multiplier, or make the program control simpler.
u[rn]
v[ri]
x(t)--+\] E - A 1Vn01Hipf5(z) --
+
4
+[n]
Figure 5-4: E - A A/D converter system
5.4.1
sincK Filters
One of the simplest and most gate-efficient solutions for the FPGA platform used in this
design is given by the use of sincK filters, also called cascaded integrator comb (CIC) filters
[4]. They can perform large decimations with no multipliers, and are most efficiently implemented by cascading K accumulator stages at the high rate with K differentiators at the
low sample rate. The system response does not allow for a lot of tweaking. The transfer
function of the CIC with respect to the fast sampling clock is
Heic(ei") =G
e)RW)
1-e-jw
(5.5)
where R is the decimation factor and K is the order of the filter. G is the gain of the filter,
and is equal to G = 2-Bmax-Bin, where Bmax is the size in bits of the first register, and Bin
is the size of the input signal in bits.
0
-20
~40
2-60
-80
-100
0
0.17r
0 .2
fr 0.3 7r 0.4 7r 0.5
7r
normalized frequency
Figure 5-5: Frequency response of sinc3 filter
with R=16
IHcic(ejw)
=
G (in9Rw2
sin w/2
(5.6)
Aliasing
Because the sincK transfer function doesn't roll off very quickly, one would expect a large
amount of aliasing when decimating the E - A output because of the significant amount
of out-of-band noise. The key to the operation of the sincK filters are the notches from
the comb filters, which fall exactly at all multiples of the lower frequency. These notches
severely attenuate any noise which would fold back into the frequencies near DC during the
downsampling operation. If the signal is band-limited to a band A around DC, then the
only frequencies of interest are those at
kR
± A, where k = L..R/2. Figures 5-6(a) and 5-
6(b) demonstrate how bandlimited white noise with unity variance would be aliased through
various sincK filters.
56
0
0
K-1
=-50.
........ ....
321
00
'100
250
-150
...... ...........
bO
p200
-350
17r1_
-1000
0
-250
1000
Frequency (Hz)
-200
0
200
Frequency (Hz)
(a)
(b)
Figure 5-6: Aliasing around DC with (a) OSR of 128 and sampling frequency of 5 MHz and
(b) OSR of 32 and sampling frequency of 40 kHz
Multistage Decimation
Due to the fact that sincK filters are very efficient but only prevent aliasing in a very narrow
band around DC, a sincK filter is often used as the first stage in a large downsampling
operation, with discrete IIR or FIR low pass filters as successive stages. This allows the
later filters to be much less expensive without sacrificing signal integrity. This mutlistage
decimation approach is used in the output decimation of the accelerometer, with a sinc 4
filter providing a decimation by 32 and a 64-tap FIR providing the abrupt low-pass filtering
for the final decimation by 4.
5.4.2
Interpolation for Oversampling D/A converters
Oversampling D/A converters require digital data to be interpolated to elevated word rates
before quantization.
Interpolation by L of a signal x[n] with sampling period T consists
of two linear operations: in the first, the x(n) is upsampled by L, resulting in a signal
XL[n] with sampling period '.
XL[n] contains the desired baseband information of x[n] as
well as L - 1 undesirable imaged replications of its spectrum at multiples of 7r/L. XL [n] is
then low pass filtered to eliminate these undesired images, resulting in u[n]. The amount of
57
filtering necessary in the interpolator depends on the frequency band of interest in x[n]. If
the frequency band is far below 1/T, then the analog lowpass filter Hpf5(s) may sufficiently
reduce the imaged spectra without a lot of complexity in the digital interpolator.
u[n]
v[n]
w [n]
Figure 5-7: E - A D/A converter system
There is a duality between interpolation and decimation of signals that suggests
that because sincK decimation filters are efficient implementations for the class of signals
that are typically dealt with in E - A modulation, there should be a transposed filter that
is an efficient implementation for interpolation of these signals. Indeed, sincK interpolation
filters, implemented by cascading K differentiators at the low rate with K integrators at the
high rate, provide some very nice properties for the interpolation: because they require only
accumulators and differentiators, they allow very large interpolation factors with a minimum
of hardware.
In the HPA system, the digital loop runs significantly faster than the frequencies of
interest to allow for efficient demodulation as well as low loop delays. Because of this fact,
a simple linear interpolation can be used to sufficiently reduce the imaged replicas of the
signal. Linear interpolation has a sinc2 response referenced to the high rate. The notches in
this response serve to greatly reduce the narrow-band spectral images around multiples of
7r/L.
5.5
Design of E - A Digital to Analog Converter
The E - A D/A will be implemented in the FPGA. In designing this system, we would like
to have the following parameters:
> 100 dB SQNR at 100 Hz The signal to quantization noise ratio (SQNR) is the ratio
58
of the signal level to the amount of quantization noise measured at the output of the
E - A converter. Typically, since the noise pushed out to higher frequencies, we would
expect that the SQNR is a monotonically decreasing function of frequency.
> 100 Hz bandwidth Because we would like the return path to appear linear in the signal
band (see Section 3.1), the frequency response of the E - A converter should be flat
in this region.
Because we have eliminated the modulation frequency from the signal in the forward
path, upsampling by the same amount in the D/A as in the A/D before quantization will
result in a much larger oversampling ratio. To see this, notice that the A/D converter must
have a bandwidth greater than twice the modulation frequency fin.
It oversamples by a
factor of R, then downsamples to a word rate of 2f m . At the digital output of the system,
there is no modulation frequency to worry about, so the data can be low pass filtered to a
frequency just above 100 Hz. This effectively increases the oversampling ratio of the output
to Rf,
fi>
where
f,
is the cutoff frequency of the analog low pass filter Hpf (s).
Because
100Hz, the effective oversampling ratio of the D/A converter will be very large. For
instance, if R = 128,
fm
= 20kHz, and fl = 400Hz, then the effective oversampling ratio
of the D/A converter could be as large as 6400. Referring to Table 5.1, this will result in a
theoretical SQNR of about 100 dB for a first order E - A converter and about 175 dB for a
second order converter.
For this reason, we will implement a second order E - A D/A converter, which
should provide a sufficently high SQNR such that the level of quantization noise of the D/A
is much lower than the noise introduced by the analog electronics, even with the growth
of the noise due to the square nonlinearity described in Chapter 4.
Second order filters
are the highest order filters which can be guaranteed stable for DC inputs[8]. Higher order
filters can be conditionally so, but many restrictions must be placed on the input signal and
mathematical criteria for designating these conditions are lacking.
59
5.6
Second Order E - A Loop
For the second order loop design, we start with a general form for a unity gain feedback
system based on two integrator stages. A block diagram of this system is shown in Figure
??
±~]+
1
1
+
x[r]
--
b
Q[]
-4[n]
C
Ie[n]
x[n]
a
+
-+
b
1
+
[n)
(b)
Figure 5-8: Torque E - A loop block diagram (a) with quantizer (b) with linear noise model
This system has signal transfer function
STF(z) =
ab
(1-z-1) (1 - z-1 + bc) + ab
(5.7)
and noise transfer function
NTF(z)
Z-1)2
(1- z-1) 2 - ab
60
-Z-1
(1 - z- 1) + bc
(5.8)
As we approach the unit circle (z
-±
1), we see the approximate response near DC
has three zeros. The first is at DC, and the second is determined by the ratio of a/c. Holding
a and b constant and increasing c results in lowering the bandwidth of the STF as well as
suppressing the noise at low frequencies by moving the zero lower. Holding b and c constant
but reducing a will reduce the bandwidth of the STF without changing the NTF.
NTF(z -+ 1)
=
(1
z- 1 ) 2 (I -z-1i
-
(5.9)
With a = 1/4, b = 1/4, c = 256, the STF has a bandwidth of 773Hz and adds
introduces -7.4
0
of phase to the loop at 100Hz. The theoretical SQNR of this design is
approximately 168dB at 1Hz and 148dB at 100Hz. Unfortunately, anything greater than
unity gain in either the inside or outside loop will cause the quantizer to saturate, in which
case the linear noise model breaks down.
With the saturation constraint in mind, we choose a = 2-0, b= 1, and c = 1. This
results in the same STF bandwidth of 773Hz with -7.4of phase at 100Hz. The theoretical
SQNR is 131dB at 1Hz and 81dB at 100Hz. The frequency responses are plotted in Figure
5-9. Then the output noise due to the D/A quantization would be about 64 A pjg/IHz at
the output of the D/A converter, where A is the DC value of the acceleration input in g's.
61
Bode Diagram
0
- 20
-
40 _0
.2
60 - 80 - 00 -..
20
.
45--
tv
-o
---
0
a_
-45
90
-
-
-
100
102
10
103
Frequency (Hz)
Figure 5-9: Bode plot for E - A STF (solid) and NTF (dotted)
62
Chapter 6
Conclusion
6.1
6.1.1
Design Specification Check
Dynamic Range (500 pg to 50 g)
The upper limit of the dynamic range is interpreted for this application to be the maximum
restorative torque that can be applied using the electrostatic feedback mechanism. Because
the FPGA can output signals with levels between OV and 3.3V, the signal was amplified
before being applied to the sensor.
The gain was set such that a 50 g torque could be
applied.
The lower limit of the dynamic range is interpreted to be the RMS value of the
noise on the acceleration estimate over a 1 Hz bandwidth. There are a few types of noise
present in the acceleration output.
Stochastic noise from the A/D and D/A conversions
was characterized in Chapter 5, noise intrinsic to the sensor and charge amplifier in Chapter
2. The harmonic noise due to the modulation and demodulation of the signal is effectively
eliminated during the output decimation. The fundamental and all its multiples are notched
out by the output decimation sinc4 filter, bringing the harmonic distortion to less than -200
dB. The results are summarized in Table 6.1.
63
Noise Source
D/A quantization
A/D quantization
Harmonic distortion
Intrinsic
Noise Power (pig/vHz)
(current) j
(ASIC)
64
13
158
12
~ 0
::0
287
48
Total
509
73
Table 6.1: Summary of noise sources and their output-referenced magnitudes in the closed
loop system under 1 g
6.1.2
Velocity Random Walk (0.035
7)
In Section 3.3, it was shown that, under the assumption that the noise is a white process,
the velocity random walk is minimized when the variance of the noise process is minimized.
Hence, the velocity random walk specification translates to a condition on the noise level
of the acceleration estimate. Specifically, the noise power at the acceleration output must
be less than 85
9
to meet the velocity random walk specification. Because of the high
sensor noise, we were not able to meet this specification in this design iteration, although
the foundation has been set for the ASIC design (see below).
6.1.3
Scale Factor Nonlinearity (0.03% Full Scale)
The nonlinearity of the output was shown in Chapter 2 to be a function of 1. the square
nature of the rebalance force, 2. the torque constant mismatch, and 3. the displacement of
the proof mass from the null position.
The closed-loop design implemented a square root algorithm which compensates for
the square force and reduces the first nonlinearity significantly below the 0.03% full scale
criterion. In fact, it is accurate to within about 0.00002%.
In Chapter 3, the use of a pure integrator as the controller was shown to exactly
null the proof mass position for DC inputs, effectively eliminating all nonlinearity from the
sensor and electronics around for any input within the -50g to 50g valid input range.
64
The dominant source of nonlinearity is then left to the torque constant mismatch,
which is compensated for by high precision premultiplication in the return path of the loop.
The precision of the compensation values is limited only by our ability to measure them. This
eliminates any error due to this source down to the resolution for which we can externally
measure the acceleration input for calibration purposes.
6.2
Implementation Details
The analog circuitry and mechanical systems involved in the HPA system were modelled in
VHDL, and was used as a testbench to simulate the digital logic designs, which were also
implemented in VHDL. The digital electronics were all programmed in a Xilinx XCV200E
FPGA. Each Xilinx slice corresponds to two Combinational Logic Blocks (CLBs), which are
the base design unit of the Virtex Series. Each CLB can hold a small amount of combinational
logic that corresponds to about 260 digital gates.
Table 6.2 shows the sizes of different
components of the design with their slice count, equivalent gate count, and percentage of
the total available resource usage of the FPGA (2352 slices or 306,393 gates).
Most of the individual blocks of the design have been optimized for size. Some of
the elements that allow a smaller design are the following:
" Due to the 1-bit output of the E - A modulator and the linearity of the system blocks,
demodulation could be performed multiplier-free. Single-bit multiplication reduces to
a simple sign changed, which greatly reduces hardware complexity.
" We saw in Chapter 5 that sinCK filters are very efficient for use in large decimation
contexts, and these were used for the bulk of the decimation in the system. The FIR
filter, which was necessary to prevent aliasing at the output, is almost three times
larger than either of the sinc4 filters, even with a much smaller decimation factor.
" The iterative algorithm chosen for the square root implementation is very small compared to the more standard Newton-Ralphson method, which would require a 24 bit
65
multiplier.
If more logic needs to be added to the system, the most obvious savings would
come from eliminating one or more multipliers at the high sampling rate from the system.
The scale factor compensation block could be reduced in size by implementing an iterative
multiplier employing an add-shift iteration that runs for one high-rate cycle once for each bit
of the smaller multiplicand. In this case, both multiplicands are 24 bits wide, so 24 iterations
would be required.
Similarly, because the FIR filter runs at a very slow rate compared to the high clock,
it is possible to implement an iterative add-shift multiplier for this block as well. It would
need to do 16 iterations for each of the 64 taps, for a total of 1024 iterations per low rate
clock cycle. There are a total of 4096 cycles of the highest rate clock per low rate clock cycle,
so this is also doable.
Implementing these two iterative multipliers could reduce the size of the design by
as much as 30%, to approximately 65% of the available space. This wasn't done in the
current design because there was no problem fitting all of the required logic in the FPGA,
but it could be done if a smaller FPGA were desired, for example, or if it was necessary to
add more logic to the current design.
6.3
Actual Data
The system was built and tested, and the results of these tests are shown in Figures 6-1
and 6-2. Figure 6-1 shows the HPA acceleration estimate output when manually turning
the accelerometer from a ig field to a -1g field, and demonstrates the functionality of the
system. At the time of publishing, the test setup was not in place to provide any accurate
accelerations with magnitude greater than 1g or frequencies greater than a few Hertz.
Figure 6-2 zooms in on the tail section of the data to measure the noise power at
the system output. The noise power measured over about 63,000 samples is 476 pg//Hz,
66
Module
Output
deOimtinudecimation
Scale Factor
Compensation
Compensation
Description
Slice
CCount
FIR decimation filter (4 4) (64 taps,
24 bit delay line, 16 bit coefficients)
- sinc 4 filter (4 32)
- 24 bit multiplier
A/D
GEquivalent
Gate
Percent
780
101,610
3%
452
58,2
19%
42
5,8
9
215
28,008
9%
138
17,977
6%
1,3
4i
86
11,203
4%
326
42,468
14%
sinc 4 filter (4128)
Decimation
Compensator
24-bit accumulator
- square root module
Digital to86
Analog
calonconverter
- linear interpolator (T 128)
2nd order E - A modulator
Interfaces
8 bit UART
- Control logic
- 24 bit bus
Demodulator
- 17 bit sine wave demodulation
50
6513
2%
Complete
Everything described above
2259
294,280
96%
System
2
sinc temperature downsampling
- Timing logic
- Top-level glue logic
-
Table 6.2: Summary of Resource Usage
very close to the predicted value for the current design. Because of this accuracy, we are
confident of the analysis and simulation that has been performed.
67
1.5
1
0.5-
0
10
20
- - - -- .. . . .. .
--
-
O 0 - - - -
40
30
50
60
70
Time (s)
Figure 6-1: Accelerometer estimate under 1 g and -1 g fields
6.4
Future Work
Up to this point, the design of the HPA sensor has been quite successful. As described above,
we were not able to meet the velocity random walk specification with the current sensor,
but with a more sensitive sensor and less noisy preamplifier, we can come very close to the
specification. The next stage of the design process will be building an Application Specific
Integrated Circuit (ASIC), which will incorporate the 3rd order bandpass E - A design as
well as the new low-noise sensor.
The noise in the system was dominated by the noise due to the amplification of
the charge output of the sensor.
To reduce this noise, one could make a more sensitive
sensor, which will require less amplification and will thus add less noise to the signal. The
68
200
150
100
. ..
50
N
0
-50
-100
-150
20
40
60
80
100
120
140
160
180
200
time (s)
Figure 6-2: Residual error in bits under 1 g field
modifications listed in Chapter 2 show how the sensor noise can be reduced by a factor of
six.
When this reduction is made, the dominant source of error is the quantization noise
of the E - A D/A converter. Because the D/A quantization noise grows with the magnitude
of the input, the E - A would meet specifications at 0 g, but not at 1 g.
Chapter 5
describes methods of decreasing the E - A quantization noise so that the system also meets
specifications up to 1 g acceleration input. For example, oversampling by a factor of 2 more
than the current design could theoretically decrease the noise in the signal band by a factor
of 5 or more in the current second-order design. This would result in sufficiently low noise
power to meet the aggressive random walk specification.
69
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