AN ABSTRACT OF THE THESIS OF
Philip C. Canfield
for the degree of Doctor of Philosophy in
Electrical and Computer Engineering
Title:
presented on August 2, 1990.
A P-Well GaAs MESFET Technology
/7l1
Abstract approved:.
e"--A
Redacted for Privacy
UdV1U U. AlISLUL
The semiconductor gallium arsenide (GaAs) has many potential
advantages over the more widely used semiconductor silicon (Si).
These include higher low field mobility, semi-insulating substrates,
a direct band-gap, and greater radiation hardness.
All these
advantages offer distinct opportunities for implementation of new
circuit functions or extension of the operating conditions of similar
circuits in silicon based technology.
these advantages has not been realized.
However, full exploitation of
This study examines the
limitations imposed on conventional GaAs metal-semiconductor field
effect transistor (MESFET) technology by deviations of the semiinsulating substrate material from ideal behavior.
The interaction
of the active device with defects in the semi-insulating GaAs
substrate is examined and the resulting deviations in MESFET
performance from ideal behavior are analyzed.
A p-well MESFET technology is successfully implemented which
acts to shield the active device from defects in the substrate.
Improvements in the operating characteristics include elimination of
drain current transients with long time constants, elimination of the
frequency dependence of gds at low frequencies, and the elimination of
sidegating.
These results demonstrate that control of the channel to
substrate junction results in a dramatic improvement in the
functionality of the GaAs MESFET.
The p-well MESFET RF
characteristics are examined for different p-well doping levels.
Performance comparable with the conventional GaAs MESFET technology
is demonstrated.
Results indicate that optimization of the p-well
MESFET doping levels will result in devices with uniform
characteristics from DC to the highest operating frequency.
A P-Well GaAs MESFET Technology
by
Philip C. Canfield
A THESIS
submitted to
Oregon State University
in partial fulfillment of
the requirements for the
degree of
Doctor of Philosophy
Completed August 2, 1990
Commencement June 1991
APPROVED:
A
Redacted for Privacy
Professor of Electrical and Computer Engineering in charge of major
Redacted for Privacy
Head of departmenj
of Electrical and Computer Engineering
Redacted for Privacy
Dean of Gra(
Date thesis is presented
August 2,1990
Typed by the author for
Philip C. Canfield
® Copyright by Philip C. Canfield
August 2, 1990
All Rights Reserved
1
ACKNOWLEDGMENTS
Throughout my graduate studies many individuals at Oregon State
University and in industry have contributed to my work and personal
growth.
Contributors in industry were primarily associated with
TriQuint Semiconductor Inc.
These include Wes Mickanin, Stu Taylor,
Eric Finchem, and Bruce Odikirk who provided many long, engaging, and
Rich
thought provoking discussions about my graduate research.
Koyama has shown a special interest in this work and contributed with
many insightful questions and discussions as well as providing the
opportunity to work two summers at TriQuint.
I especially appreciate
the time and effort Rich committed to serve on my graduate committee,
and his carefully and thoughtful review of this thesis.
Two individuals were especially inspirational early in my
graduate studies and I continue to look up to them both.
Angus
McCamant and Reed Gleason (now with Cascade Microtech) have been
exemplary role models.
They have always shown a keen interest in,
and excitement for my work. They were always eager to offer
assistance when I was experiencing technical difficulties and
provided countless hours of their time to discuss my progress.
In addition, this work would not have been possible without the
generous contribution of TriQuint Semiconductor and Tektronix in
providing the means by which the ideas underlying this work could be
brought to fruition.
Tektronix provided the mask set which was used
to investigate ideas which were developed during the summer of 1987
and TriQuint Semiconductor provided the processing and process design
tools needed to implement the p-well MESFET technology.
In
11
particular the work of Eric Finchem is especially appreciated.
Eric
devoted a significant amount of time selecting the appropriate
implants, guiding the wafers successfully through the fabrication
process, and personally conducting some of the process steps such as
the processing required to make the quarter micron gates on some of
the MESFET test structures.
Tektronix solid state research labs also
provided use of their facilities for deposition and anneal of the pohmic metal used on the test wafers.
I also wish to acknowledge the
support of the National Science foundation.
Various NSF grants have
provided my stipend and travel to several conferences which provided
an immeasurable boost to my professional development.
Other individuals who bear mentioning are Bill Vetanen of
Tektronix (formally of TriQuint) who was always very interested in my
work and helped develop my philosophy of semiconductor processing by
his outstanding example and commitment to excellence.
Norm
Schienberg and especially Bob Bayruns of Anadigics have always shown
a keen interest in this work.
They have provided moral support with
their enthusiastic interest and discussions of my work and have been
long time advocates of a p-well MESFET technology in GaAs.
Noel
Fernandez of Hewlett-Packard helped with some test systems needed for
last minute measurements and Tom Andrade of Gazelle Microcircuits
provided many animated discussions about GaAs technology.
I am deeply indebted to my major professor, Dave Allstot.
has been instrumental in my progress and the quality of my work.
Dave
His
enthusiastic participation and keen interest has been the highlight
of my years in graduate school.
Dave's ability work together with me
111
on this project as a college facilitated the development of my many
weaknesses into strengths.
closest friends.
In addition Dave has become one of my
It has been a rare privilege and honor to work with
a college at this level who shares such a common philosophical
outlook on life.
I also wish to acknowledge the service of Prof. John Wager on my
graduate committee. Many of John's questions have served as
motivation to examine aspects of my work more carefully than I had
The special assistance of Prof. John Owen during a
been.
particularly difficult time in my graduate career is also gratefully
acknowledged.
I want to express my deep gratitude to my family.
inspired and nurtured my love of science.
My mother has
She has contributed
greatly to the fire and enthusiasm I bring to my work.
My father has
shown a great degree of understanding and patience while teaching me
He has provided me ample opportunities to provide for
many things.
myself and thus develop a high degree of self-esteem and confidence
in my life.
His unconditional love and support has been a constant
comfort to me.
My mother-in-law, Qienmei Liu, deserves special
recognition for the care she has provided for my son the last two
years.
Her commitment has made the completion of this thesis
immeasurably easier.
My wife, Lingzhou, whom I met in a Quantum
Mechanics class the first year of graduate school, has been a source
of special comfort.
Her undying support, devotion, dedication, and
love have made my graduate experience rich and fulfilling.
She has
contributed many hours away from own graduate studies in Physics to
iv
assist in the preparation of some of the more tedious aspects of this
document and many of the conference publications which resulted from
this work.
Her triumph and success in life against incredible odds
and seemingly insurmountable obstacles has made any hardship I have
faced seem trivial in comparison.
V
TABLE OF CONTENTS
Page
1.
INTRODUCTION
1
2.
EXPERIMENTAL
10
3.
4.
2.1
Conventional Technology
10
2.2
P-Well Technology
11
2.2.1
Doping Profiles of the P-Well
MESFETs
14
2.2.2
P-Well Test Mask Set
14
2.3
Drain Current Transient Measurements
20
2.4
Frequency Dependent Output Conductance
Measurements
22
2.5
Sidegating Measurements
23
2.6
RF Characterization
26
DRAIN CURRENT TRANSIENTS
27
3.1
Introduction
27
3.2
Measurement of Conventional MESFETs
34
3.3
Analysis
39
3.4
Comparison of Analysis and Measurements
46
3.5
Measurement of Buried-Channel and P-Well
MESFETs
50
3.6 Summary
56
FREQUENCY DEPENDENT OUTPUT CONDUCTANCE
57
4.1
Introduction
57
4.2
Measurement of Conventional MESFETs
60
vi
5.
6.
7.
8.
4.3
Analysis
62
4.4
Measurement of Buried-Channel and P-well
MESFETs
64
4.5
Summary
67
SIDEGATING
68
5.1
Sidegating in Conventional Technology
68
5.2
Measurements of Sidegate Structures with
Floating P-Type Implants
73
5.3
Measurements of Sidegate Structures with
Contact to the P-Type Implants
77
5.4
Summary
82
RF CHARACTERISTICS
83
6.1
Equivalent Circuit Model
83
6.2
S-Parameters
85
6.3
Small-Signal Parameters
89
6.4
fT, f=x, and MAG
94
6.5
Summary
97
LIMITATIONS AND TRADEOFFS
99
99
7.1
Introduction
7.2
Drain Characteristics
101
7.3
Gate Characteristics
106
7.4
Summary
106
CONCLUSIONS
108
BIBLIOGRAPHY
111
vii
APPENDIX
A. Publications
119
A.1
Journal Publications
119
A.2
Conference Publications
121
viii
LIST OF FIGURES
Page
Figure
6
1.1
Cross-sectional view of a conventional
MESFET and the "self -backgating" effect.
2.1
Cross-sectional view of a conventional
ion-implanted GaAs MESFET.
11
2.2
Cross-sectional view of the n-channel
p-well GaAs MESFET.
12
2.3
Doping profiles for the different wafers
fabricated in this study.
13
2.4
Layout of the mask set developed for the
study of the p-well MESFET technology.
15
2.5
An example of the different p-well implant
masks used to study the effect of the gate
contacting the p-well.
16
2.6
Layout of the sidegating test cell showing
the three different sidegate electrodes
available.
18
2.7
Schematic diagram of the measurement system
used to observe the drain current transients.
19
2.8
Illustration of the probe card used for the
drain current transient measurements of GaAs
MESFETs.
21
2.9
Schematic diagram of the measurement system
for characterization of the frequency
22
dependent gds.
2.10
Cross-sectional view of the sidegate test
structure implemented in the conventional
technology.
24
2.11
Cross-sectional view of the sidegate
structure implemented in the p-well
technology.
24
2.12
Schematic representation of the
sidegating measurement system.
25
ix
2.13
Schematic representation of the
measurement configuration used for the RF
characterization of the p-well technology.
26
3.1
Cross-sectional view of the various depletion
regions which can contribute to drain current
transients.
29
3.2
Input drain voltage waveform and corresponding
drain current transient responses due to the
three different regions of Fig. 3.1.
32
3.3
Measured drain current transient response of the
conventional GaAs MESFET. A voltage square wave
between 5.0 V and 1.0 V was applied to the
33
drain.
3.4
VGS = 0.0 V.
Measured drain current transient response of the
A voltage square wave
conventional GaAs MESFET.
between 5.0 V and 1.0 V was applied to the
drain.
34
VGs = 0.0 V.
3.5
Measured drain current transient overshoot for an
abrupt change in the drain voltage from 0.0 V to
5.0 V for a conventional GaAs MESFET. Each curve
represents a different time scale ranging from 10
VGS = 0.0 V.
mSec/Div to 10 nSec/Div.
35
3.6
Measured drain current transient response of the
conventional GaAs MESFET. A voltage square wave
between 5.0 V and 1.0 V was applied to the
drain for three different pulse periods.
36
VGS
= 0.0 V.
3.7
Measured drain current transient undershoot for an
abrupt change in the drain voltage from 5.0 V to
Each curve
1.5 V for a conventional GaAs MESFET.
represents a different time scale ranging from 10
VGS = 0.0 V.
mSec/Div to 10 gSec/Div.
37
3.8
Magnitude of the drain current transient overshoot
for an abrupt increase in Vds from 0.0 V to
38
ads
VGS
0.0 V.
3.9
Charge distribution along a path from the gate
into the substrate of a conventional MESFET. The
shaded regions signify the depletion regions which
change due to the balancing of charge.
41
3.10
Cross-sectional view of a conventional MESFET
showing the path used in Fig. 3.9.
42
x
3.11
Analytical results of drain current transient
undershoot for the conventional MESFET results
of Fig. 3.7.
46
3.12
Time dependence of the log of the magnitude of
current overshoot normalized to t=0 for the
measured current overshoot waveforms of Fig. 3.5.
47
3.13
Time dependence of the capture time constant for
the transient current overshoot of Fig. 3.5.
49
3.14
Measured drain current transient overshoot response
for a 0.0 V to 5.0 V drain voltage step on buriedchannel MESFETs for 1 mSec/Div, 10 ASec/div, and
100 nSec/Div scales. The peak p-type doping behind
the channel is a) 2.0 x 10'6 cm-5, b) 4.0 x 1016 cm-3,
51
c) 8.0 x 1016 cm -5, and d) 16.0 x 10
3.15
cm-3.
Measured drain current transient undershoot response
for a 5.0 V to 1.5 V drain voltage step on buried
channel MESFETs for 1 mSec/Div and 10 ASec/div
The peak p-type doping behind the
scales.
52
channel is a) 2.0 x 10'6 cm- 5, b) 4.0 x 1016 cm-3,
c) 8.0 x 1016 cm-3, and d) 16.0 x 1016 cm-3.
3.16
Measured drain current transient overshoot response
for a 0.0 V to 5.0 V drain voltage step on p-well
MESFETs for 1 mSec/Div, 10 ASec/div, and
The peak p-type doping behind
100 nSec/Div scales.
the channel is a) 2.0 x 10'6 cm-5, b) 4.0 x 1016 cm-3,
54
c) 8.0 x 1016 cm -5, and d) 16.0 x 1016 cm-3.
3.17
Measured drain current transient undershoot response
for a 5.0 V to 1.5 V drain voltage step on p-well
MESFETs for 1 mSec/Div and 10 ASec/div
scales. The peak p-type doping behind the
55
channel is a) 2.0 x 1016 cm-3, b) 4.0 x 1016 cm-3,
c) 8.0 x 101 cm-3, and d) 16.0 x 1016 cm-3.
4.1
High frequency and low frequency small-signal
current for a given applied small-signal vds
59
4.2
Measured frequency dependence of the output
conductance for three different gate voltages.
60
VDS = 2.0 V.
4.3
Measured frequency dependence of the output
conductance for different kips.
4.4
61
VGs = 0.0 V.
Comparison of the frequency dependence of the
output conductance model and measured data for
three different temperatures.
64
xi
4.5
Measured frequency dependence of gds for the
p-well MESFET at three different VGS
The peak p-type doping behind the
VDS = 2.0 V.
channel is a) 2.0 x 1016 cm-3, b) 4.0 x 1016 cm-3,
65
c) 8.0 x 1016 cm-3, and d) 16.0 x 1016 cm-3.
4.6
Measured frequency dependence of gds for the
buried channel MESFET at three different VGS
VDS = 2.0 V. The peak p-type doping behind the
channel is a) 2.0 x 1016 cm-3, b) 4.0 x 1016 cm-3,
c) 8.0 x 1016 cm-3, and d) 16.0 x 1016 cm-3.
66
5.1
Measured sidegating results for the conventional
MESFET structure of Fig. 2.10 at room temperature
without illumination. The drain current is shown
in the upper trace and sidegate current is shown
in the lower trace. Vps = 2.5 V and Ids(VsG =0.0 V)
= 3.0 mA.
69
5.2
Measured drain current sidegating results with
and without illumination for the conventional
MESFET of Fig. 5.1.
70
5.3
Measured threshold voltage shift of a
conventional MESFET for VsG = - 5.0 V.
VGS = 0.0 V and Vps = 2.5 V.
71
5.4
Measured sidegating results of a conventional
MESFET and an n* sidegate electrode surrounded
by a p-type implant for Vps = 2.5 V and
The equivalent peak p-type
Ids (VsG=0.0 V) = 3.0 mA.
doping levels were a) 2.0 x 1016 cm-3,
72
b) 4.0 x 1016 cm-3, c) 8.0 x 1016 cm-3, and
16.0 x 1016 cm-3.
5.5
Measured sidegating results of a buried channel
MESFET and an n' sidegate electrode surrounded
by a p-type implant for Vps = 2.5 V and
The equivalent peak
Ids( VsG=0.0 V) = 3.0 mA.
p-type doping levels were a) 2.0 x 1016 cm-3,
73
b) 4.0 x 1016 cm-3, c) 8.0 x 1016 cm-3, and
16.0 x 1016 cor3.
5.6
Measured sidegating results of a buried channel
MESFET and an n+ sidegate electrode for Vps = 2.5 V
The equivalent peak
and Ids(VsG =0.0 V) = 3.0 mA.
p-type doping levels were a) 2.0 x 1016 cm-3,
b) 4.0 x 1016 cm-3, c) 8.0 x 1016 cm-3, and
16.0 x 1016 cm-3.
74
xii
5.7
Measured sidegating results of a conventional
MESFET and an n+ sidegate electrode in a p-well
for Vin = 2.5 V and Ids(VsG=0.0 V) = 3.0 mA. The
equivalent peak pp -type doping levels were
75
a) 2.0 x 10'6 cm- , b) 4.0 x 1016 cm-3,
c) 8.0 x 1016 cm-3, and 16.0 x 1016 cm-3.
5.8
Measured forward biased p-i-n diode effects for
a p-well MESFET and an e sidegate electrode.
76
5.9
Measured sidegating results of a buried channel
MESFET and an n+ sidegate electrode in a p-well
for Vin = 2.5 V and Ids(VsG=0.0 V) = 3.0 mA. The
equivalent peak pp -type doping levels were
77
a) 2.0 x 106 cm- 3, b) 4.0 x 1016 cm-3,
c) 8.0 x 1016 cm-3, and 16.0 x 1016 cm-3.
5.10
Measured sidegating results of a p-well MESFET
and an n+ sidegate electrode in a p-well
for Vps = 2.5 V and Ids(VsG=0.0 V) = 3.0 mA.
equivalent peak pp -type doping levels were
a) 2.0 x 10'6 cm- , b) 4.0 x 1016 cm-3,
c) 8.0 x 1016 cm-3, and 16.0 x 1016 cm-3.
78
The
5.11
Measured sidegating results for various sidegate
structures with and without illumination.
a) Conventional MESFET and an n+ sidegate
electrode surrounded by a p-type implant,
b) buried channel MESFET and an n* sidegate
electrode surrounded by a p-type implant,
c) conventional MESFET and an n+ sidegate
electrode in a p-type well, d) buried channel
MESFET and an n+ sidegate electrode in a p-type well.
79
5.12
Measured sidegating result for the p-well
MESFET technology with and without illumination.
80
6.1
Cross-sectional view of a p-well MESFET
conceptually illustrating the depletion
regions associated with the pn junctions
and the conductive path to the source of
the p-type region under the channel.
84
6.2
Small-signal equivalent-circuit model used
for the p-well GaAs MESFET.
85
6.3
S21 responses for the p-well MESFETs with
different n-channel and p-well doping levels.
The sweeps are for bias voltages of Vos = 3.0 V
and Vo = 0.0 V.
86
6.4
S22 responses for the p-well MESFET's with
different p-well doping levels. The sweeps
are for bias voltages of VDS = 3.0 V and
87
VGS = 0.0 V.
6.5
CGS and Cgd as a function of p-well doping
levels for bias voltages of VDS = 3.0 V and
88
VGS = 0.0 V.
6.6
Small-signal gm values versus p-well doping
levels at several different VGS bias voltages.
VDS = 3.0 V.
89
6.7
Small-signal Rds values versus p-well doping
levels at several different VGS bias voltages.
90
VDS = 3.0 V.
6.8
Small-signal C, values versus p-well doping
levels at several different VDS bias voltages.
VGS =
6.9
91
0.0 V.
Small-signal Rp values versus p-well doping
levels for bias voltages of VDS = 3.0 V and
92
VGS = 0.0 V.
6.10
1H211 versus frequency for a conventional MESFET
with bias voltages of Vps = 3.0 V and VGS = 0.0 V.
94
6.11
Small-signal fT values versus p-well doping
levels with bias voltages VDS = 3.0 V and
95
VGS =
6.12
0.0 V.
Maximum Available Gain (MAG) values versus
p-well doping levels for bias voltages of
96
VDS = 3.0 V and VGS = 0.0 V.
6.13
Small-signal fmax values versus p-well doping
levels for bias voltages of VDS = 3.0 V and
VGS = 0.0 V.
7.1
Drain I-V characteristics for the p-well
MESFET with the p-well tied to the source
a) and the p-well tied to the drain b).
The maximum VGS = 0.75 V and the step size
97
100
is 0.25 V.
7.2
Subthreshold characteristics for
MESFET with the p-well extending
The
the channel under the gate.
is VDS = 5.0 V and the step size
the p-well
outside
upper curve
is 2.0 V.
101
xiv
7.3
Subthreshold characteristics for the p-well
MESFET with the p-well a) coincident with,
b) pulled in 1/2 micron from, and c) pulled
in one micron from the edge of the channel
The upper curve is
under the gate.
VDS = 5.0 V and the step size is 2.0 V.
103
7.4
Gate I-V characteristics for the
MESFET with the p-well a) pulled
micron from, b) coincident with,
c) pulled in one micron from the
VDS
the channel under the gate.
104
7.5
p-well
out one
and
edge of
= 2.5 V.
Transconductance for the p-well MESFET with
the p-well a) pulled out one micron from,
b) coincident with, and c) pulled in one
micron from the edge of the channel under
the gate. VDS = 2.5 V.
105
XV
LIST OF TABLES
Page
Table
2.1
Implant parameters for the experimental
wafers.
13
2.2
MESFET structure identification for block
A of Fig. 2.4.
17
2.3
Sidegate cell identification for the cells
in block B of Fig. 2.4.
18
6.1
Equivalent-circuit small-signal element
values for the different p-well doping
The values are for MESFETs with
levels.
lAm gate lengths and 300 Am gate widths
and bias voltages of Vos = 3.0 V and VGS = 0.0 V.
93
A P-WELL GaAs MESFET TECHNOLOGY
1.
INTRODUCTION
Interest in the use of gallium arsenide (GaAs) metal
semiconductor field effect transistors (MESFETs) for integrated
circuits (ICs) is based on several potential advantages this
technology offers over silicon technologies.
Among these are higher
low-field electron mobility and peak velocity (high speed), greater
radiation hardness (military and space applications), a direct bandgap (photonic applications), and the availability of semi-insulating
substrates (good isolation and low interconnect and junction
capacitances).
Thus far, GaAs technology has been used successfully
in the implementation of monolithic microwave integrated circuit
(MMIC) applications, is showing increased strength in the area of
high-speed digital applications, and only marginal success in the
area of analog IC's and mixed-mode digital-analog circuits which
require a high degree of precision (8 or more bits).
While the success in the MMIC area has served to maintain a high
level of activity, it has not been sufficient to provide adequate
production volumes for most companies striving to survive
commercially.
The growth in demand for high speed-digital circuits
of medium and large scale integration (MSI and LSI) has resulted in
higher volumes and greater opportunities for many companies to become
profitable.
However, the inability to implement such ICs as
2
operational amplifiers which settle to more than eight bits of
accuracy in less than a second [1], [2] has completely eliminated a
large area of commercial interest for instrument vendors.
Factors limiting the implementation of high-speed precision
analog/digital circuits in GaAs technology are invariably related to
These anomalies are
a large assortment of GaAs device anomalies.
principally due to deviations of the semi-insulating substrates from
ideal behavior.
Included in these anomalies are frequency-dependent
small-signal parameters [1], [3]-[7], pattern and frequency-dependent
propagation delays [8], drain current transients with long time
constants [9]-[14], large absolute and matching tolerances between
devices [15], [16], and sidegating or cross talk between devices
[12], [16]-[20].
To reduce sidegating, large layout spacings have
been used [21], particularly for MESFETs biased at high power levels
as in many microwave applications.
Another aid in reducing
sidegating is the use of an isolation implant [22] or co-implantation
of p-type dopants into the source-drain regions [23].
A p* blocking
electrode [24], [25], and a Schottky shield [26] tied to the most
negative potential has been proposed as well for the reduction in
sidegating.
For analog and digital circuits, frequency-dependent
small-signal parameters result in frequency-dependent gain [1], [27]
and modeling difficulties [1]-[3], [5], [27].
Drain current
transients cause very long settling times in switches and amplifiers
[1], [28] and hysteresis in differential amplifiers and comparators
[2].
Pattern and frequency-dependent propagation delays result in
timing nightmares in digital circuits [8].
An understanding of the
3
properties of the semi-insulating substrate is key to both
understanding the source of these anomalies and to devising
satisfactory solutions to these problems.
GaAs semi-insulating substrates used in industry are almost
exclusively grown by the liquid encapsulated Czochralski (LEC)
technique.
Residual impurities in the melt which are incorporated
into the crystal as it is grown result in lightly doped p-type GaAs
unless steps are taken to compensate the net concentration of
acceptors [29], [30].
The most common residual shallow acceptor is
carbon [31], [32]; however, trace amounts of other elemental donors
and acceptors are also present.
Some of the more common residual
shallow impurities include the shallow donors Si, S, Se, and Te, and
the shallow acceptors Mg, Mn, and Fe [33].
The net effective
concentration of acceptors Mod is on the order of 1015 cm-3, and is
determined by solving the charge balance equation in equilibrium;
(1.1)
Naeff=IiNai-IjNdi.
The sum over i represents all the residual shallow acceptors and the
sum over j accounts for all the residual shallow donors.
In addition
boron and nitrogen incorporated into the melt from the boron nitride
crucible are present.
However, their contribution to the
compensation of the GaAs substrates appears to be of little
consequence in currently available LEC semi-insulting material.
The most common method of compensating the residual shallow
acceptors, which also results in high resistivity material, is to
grow the crystals slightly arsenic-rich [30].
Crystals grown under
these conditions contain a large concentration of native defects
4
which are electrically active.
The most abundant is the deep donor
EL2 which is associated with an arsenic atom sitting on a gallium
site in the crystal lattice [34].
When the concentration of EL2 is
much greater than the concentration of residual acceptors, the
Fermi-level is pinned near the EL2 energy level [35].
Since the
energy level of EL2 in GaAs is near the middle of the band gap, the
resistivity of the resulting material is high (p > 107 Q-cm).
Typical concentrations of EL2 are greater than 1016 cm-3 in GaAs
substrates [32], while the typical net concentration of shallow
acceptors is on the order of 1015 cm-3 [32], [36].
Charge balance
requires that the concentration of ionized deep donors equal Naeff
[37].
This means there are about 1015 cm-3 ionized EL2.
Hence, the
majority of EL2 are filled and electrically neutral which implies
that in equilibrium the Fermi-level is slightly above the EL2 level.
Furthermore, since a relatively large percentage of the EL2 must
change their charge state (- 1015 cm-3) for any significant movement
of the Fermi-level, the Fermi-level is "pinned" near mid-gap.
From a device standpoint, there are two factors of importance to
consider here.
The first is that the concentration of deep levels is
large with a significant fraction of them ionized.
Consequently, the
Fermi level is near the energy level of the trap and any small
movement of the quasi-Fermi levels can result in a significant change
in the number of ionized EL2.
The need to balance this charge,
coupled with the long emission time constants associated with mid-gap
traps, result in a transient time-dependent behavior which can take
seconds to relax to steady state.
When this relaxation process
5
occurs in the vicinity of an active device such as a MESFET, the
time-dependent behavior will be reflected in the operating
characteristics of the MESFET.
The second consideration is related to the transition region
from the active channel (formed by ion-implantation) to the semiinsulating substrate.
This transition region is not abrupt.
It
typically extends about a micron into the substrate while the active
channel is on the order of 0.2 Am thick [38].
Consequently the
channel-substrate potential barrier is effectively graded and
represents a region of varying conductivity.
This facilitates the
ability of the electric fields generated by the drain voltage of a
MESFET, to wrap around the active channel and sweep charge down into
the substrate.
The resulting increase in the quasi-Fermi level can
This charge
change the charge state of deep levels in steady state.
flowing through the substrate under the influence of the drain
electric field is referred to as the sub-threshold current.
The
presence of residual acceptors actually acts to decrease the
magnitude of the sub-threshold current by sharpening the electron
tail and sharpening the barrier [38].
The modification of a MESFET's operating characteristics by the
filling or emptying of traps in the vicinity of the MESFET can be
discussed qualitatively with the aid of Fig. 1.1.
With no electric
field applied the to channel of the MESFET, electrons are
continuously escaping over the potential barrier to the substrate.
These electrons are continually trapped in ionized EL2 sites while
others are emitted from neutral EL2 sites.
In steady-state the
6
Drain
Source
N Channel
Ionized
Neutral
EL2
EL2
Trap
Trap
Depletion
Region
LEC SI GaAs Substrate
Figure 1.1. Cross-sectional view of a conventional MESFET and the
"self-backgating" effect.
concentrations of both trapped and free electrons are adjusted so
that the average number of energetic electrons escaping over the
potential barrier is matched by the average number of electrons
emitted back into the channel.
That is, the capture and emission
rates are equal along the channel-substrate interface.
In steady-
state with a high electric field applied to the channel, both the
rate of injection of electrons over the barrier, and the rate of
emission of electrons back into the channel are increased, but must
still be equal.
7
In a non-steady-state condition, as for example when the
electric field between the drain and source is suddenly increased,
more of the electrons in the channel gain enough kinetic energy to be
scattered over the potential barriers.
Because of the relatively
short capture time constant, these electrons are quickly trapped in
ionized EL2 sites.
With the capture of these electrons the traps
become electrically neutral, making the substrate adjacent to the
channel more negatively charged due to the uncompensated residual
shallow acceptors.
Charge balance is achieved by nearby implanted
shallow donors in the channel, with the accompanying increase of the
depletion width in the channel.
As a result of this pinching off of
the channel, the drain current is decreased.
referred to as "self-backgating" [37].
This effect is commonly
Ultimately the problem lies
with the unconstrained potential of the semi-insulating substrate
which translates into an uncontrolled channel-substrate junction.
In this work a systematic investigation of the interaction
between the changing charge state of the deep-level defects and
operation of the active device is conducted.
Evidence is presented
which supports the contention that an uncontrolled channel-substrate
interface is responsible for the anomalies examined here.
The use of
p-type regions has been reported to help eliminate some of the MESFET
anomalies.
A systematic examination and comparison of the effect of
various p-type layers is conducted and their relative impact on
anomalous behavior is reported.
It is demonstrated that the only
technique which reliably eliminates these anomalous characteristics
8
is control of the channel-substrate junction by the introduction of a
p-well which can be connected to a known potential.
Chapter 2 details the experimental procedure and design used to
study the characteristics of the anomalous behavior in MESFETs.
The
mask set and the various doping profiles used to fabricate the
devices are described.
Chapter 3 examines the nature of the drain current transients.
In addition to the traditional examination of the transient response
to a voltage step on the drain from a high to a low voltage, the
response to a voltage step from a low to a high voltage is examined.
The two responses are quite different and their behavior is shown to
be consistent with modulation of the channel-substrate junction space
charge regions due to filling and emptying of traps in the substrate.
The transient behavior is analyzed using a simple square law
relationship for the drain current and shown to agree with
experimental data.
The effect of p-layers and the p-well are
examined and and the relative impact on the transient response of the
drain current is discussed.
Chapter 4 extends the results of the time-dependent behavior of
the drain current to the frequency-dependent behavior of the output
conductance.
The expression derived for the drain current transients
in chapter 3 is used to derive an expression for the frequencydependent output conductance expression.
This expression is shown to
be in close agreement with experimental results.
The effect of p-
layers and the p-well are examined and and the relative impact on the
output conductance is discussed.
9
Chapter 5 examines sidegating in GaAs MESFETs.
A review of the
effect in conventional devices is presented and the effect of players is examined in detail.
No report of a new technology in GaAs would be complete without
an examination of reporting on its RF performance.
Chapter 6 reports
on the RF performance of the p-well MESFET for different p-well
implant doses.
An equivalent circuit model is implemented using
TOUCHSTONE® (a commercially available software package from EESOF for
RF modeling and measurements) and the FET parameters extracted.
It
is shown that the n-channel p-well MESFET implant parameters can be
optimized to give RF performance which is comparable to MESFETs
fabricated by a conventional technology, while maintaining the
improved immunity to the low-frequency anomalies.
Chapter 7 examines some of the limitations and trade-offs which
arise in the device behavior due to the p-well structure and the ptype implants.
Some of the issues addressed are pertinent to layout
while others address design concerns.
These results are summarized in Chapter 8 and an attempt is made
to place these findings in perspective.
future work are made.
Several recommendations for
10
2.
EXPERIMENTAL
The experimental procedure and design used to evaluate the pwell MESFET technology are described in this chapter.
Both the
conventional and p-well MESFET technologies are presented.
The
implant matrix and the test structures on the mask set used for the
different wafers in this study are shown in detail.
Each of the
measurement facilities and techniques used for the investigation of
the drain current transient response, the small-signal equivalentcircuit output conductance (gds), sidegating, and the RF
characteristics are described.
2.1
Conventional Technology
A cross-sectional view of a conventional MESFET is shown in Fig.
2.1.
Processing of the conventional MESFETs was provided by TriQuint
Semiconductor, Inc. and reflects much of their common processing
methodologies. The n-type channel region and the n' source and drain
contacts are formed by ion-implantation of Si29" into the semiinsulating GaAs substrate.
The implanted donors are activated with
an 800 °C furnace anneal for 30 minutes.
A gate recess is etched to
set the desired saturation current (Id) and pinch-off voltage (Vp).
The one micron gate is non-self-aligned within the three micron
channel length.
The drain and source contacts are made using
Au/Ge/Ni ohmic metal, while Ti/Pd/Au metalization was used for the
gates.
11
SEMIINSULATING GaAs SUBSTRATE
L
Figure 2.1
GaAs MESFET.
2.2
1
Cross-sectional view of a conventional ion-implanted
P-Well Technology
A cross-sectional view of the p-well MESFET is shown in Fig.
2.2.
Processing of the p-well MESFETs was also provided by TriQuint
Semiconductor, and thus the process technology is essentially the
same as the conventional MESFET with additional p-type implants (Be')
and a p-type ohmic contact.
The additional p-type implants are
composed of a bottom p-layer forming the p-well which completely
surrounds the active channel region and the n' source and drain
contact regions
,
a surface p-type implant, and a p' well contact
implant provided by Tektronix solid-state research labs.
The gate is
non-self-aligned with a gate recess to remove the surface p-type
layer under the gate and to adjust Vp and Idss
The well is contacted
12
Well
Drain
Source
PSurface
N Burled
Implant
Channel
LEC SI GaAs Substrate
Figure 2.2
MESFET.
Cross-sectional view of the n-channel p-well GaAs
using a Au/Mn p-ohmic metal on the p' implant.
In normal operation,
the p-well (back-gate) terminal is connected to the source to
guarantee that no pn junction ever becomes forward biased.
By virtue
of the well contact, the n-channel is isolated from the substrate by
a reverse-biased pn junction, and is thus immune to perturbations in
the charge distribution in the substrate and between devices due to
electron capture and emission by defects.
For purposes of comparison MESFETs were also fabricated with out
a p' contact to the p-type well.
These structures are also examined
and will be referred to as buried-channel MESFETs.
13
/-
tr)
I
E
10
1 8
0
.....,
1017
1016
1---
w
z
1
015
11111111 LILLL
0.0
0.2
WILWILLLL1-1
0.4
Implant parameters for the experimental wafers.
Channel Si'29
Surface Beg'
Backside Be9+
Dose
Energy
Dose
Energy
Dose
Energy
1016
1013
(KeV)
1012
(KeV)
1012
(KeV)
CM
CM
3-
1.0
Doping profiles for the different wafers fabricated in
Figure 2.3
this study.
Peak
P-Type
Conc.
0.8
0.6
(microns)
DEPTH
Table 2.1
LU_L
LLI
--2CM
CRIB
0.0
1.20
135
2.0
1.05
165
5.65
20
1.30
125
4.0
1.10
175
5.45
20
2.25
140
8.0
1.20
185
5.45
20
4.25
150
16.0
1.40
200
5.45
20
8.50
155
14
Doping Profiles of the P-Well MESFETs
2.2.1
The dependence of the MESFET characteristics on the p-well
doping level was evaluated from wafers fabricated with peak p-type
dopings of 2.0, 4.0, 8.0, and 16.0 x 1016 cm -3 behind the channel.
Conventional control wafers with no p-type implants were also
The theoretical doping profiles of the
fabricated simultaneously.
p-well MESFETs are illustrated in Fig. 2.3.
These profiles were
generated using TriQuint Semiconductor proprietary software which is
used for process development and has been optimized for TriQuint's
processing capabilities.
To maintain constant Vp and Idss values, the
surface p- and channel n-type implants were both adjusted so that the
effective doping concentration in the channel regions are
approximately equal for all samples.
The implant doses and energies
for the different wafers are given in Table 2.1.
These doping
profiles resulted in depletion-mode MESFETs with Vp = -1.5 V and
Idss 25
2.2.2
200 mA/mm for all wafers.
P-Well Test Mask Set
A special mask set provided by Tektronix was developed to
evaluate the dependence of the MESFET parameters on the presence of
the various p-layers and the effect of tying the p-well to a known
potential.
The mask set is shown in Fig. 2.4 and consists of a large
array of n-channel transistors, a few complementary transistors
including vertical and lateral pnp bipolar transistors and p-channel
MESFETs, special sidegating test cells, analog circuit building
blocks, and analog circuits.
Only the devices used in this study
will be described in detail.
For general DC characterization, drain
15
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vlo
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Figure 2.4
Layout of the mask set developed for the study of the
p-well MESFET technology.
16
P; PLAYERS PULLED OUT 1
Z; PLAYERS PULLED OUT 0 p.m
m
PLAYERS PULLED IN
1
P-WELL
M
CHANNEL
n
n
IMPLANTS
An example of the different p-well implant masks used
Figure 2.5
to study the effect of the gate contacting the p-well.
current transient and output conductance measurements, the block of
devices labeled A (Fig. 2.4) was used.
Within this array are
transistors with no p implants, top or bottom implants only, both top
and bottom implants, and combinations of the above with and without a
p-well contact.
Because the gates are Schottky diodes, when the gate
reverse biases the n-channel, it forward biases the p-well.
In
general, this is an undesirable effect which leads to high gate
leakage currents and parasitic gating of the channel from the
17
Table 2.2
MESFET structure identification for block A of
Fig. 2.4.
Label;
X X XX XX
IL
BM,BZ,BP1
TM,TZ,TP1
P,N2
Q,H,1,2,43
1.
B and T correspond to the backside and surface p-type
implants respectively. M, Z, and P correspond to the
layout of the p-layers in the region of the gate metal
outside the channel as illustrated in Fig. 2.5. These
labels are not present if the corresponding p-type implant
is not present.
2.
P signifies a contact to the p-well and N signifies no
contact.
3.
backside.
These characters represent the gate length in microns; Q
and H are quarter and half respectively.
So in addition to the above combination of devices,
devices with the p-well implants outside the channel in the gate
region, coincident with the gate region, and pulled inside the
channel in the gate region were laid out as illustrated in Fig. 2.5.
The available MESFETs are summarized in Table 2.2.
The sidegate test structures are gathered together in the block
of devices labeled B (Fig. 2.4).
test cells on the mask.
Fig. 2.6.
There are 15 different sidegate
The layout of the sidegate cell is shown in
The test MESFET has a one micron gate length and a fifty
micron gate width.
The individual cells allow testing of sidegate
sensitivity to electrodes on the source and drain sides of the
transistor as well as the edge of the channel.
The different cells
18
BGS5
S; SOURCE
G; GATE
D; DRAIN
BG10; SIDEGATE 1
BG5; SIDEGATE 2
BGS5; SIDEGATE 3
BG5
Layout of the sidegating test cell showing the three
Figure 2.6
different sidegate electrodes available.
Sidegate cell identification for the cells in
block B of Fig. 2.4.
Table 2.3
Label;
1B XTB XTB
Labels for the sidegate electrode.
Labels for the MESFET.
1B
1 micron gate length MESFET for sidegating measurements.
X
X can be N for no contact or P for contact to the p-well
connected to the source.
TB
T and B are the labels for the surface and the backside ptype implants respectively. These labels are only present
if the implant is present.
19
HP 8112A
PULSE GENERATOR
8 pH
_93:00
50 0
9 KO
TRIGGER
TEK 111501
OSCILLOSCOPE
TEK PS5010
DUAL
POWER
SUPPLY
1
0
K
10 n
4.
A
IEEE -488
BUS
10 KO
Roans.
8 pH
QQQ
CONTROLLER
Schematic diagram of the measurement system used to
Figure 2.7
observe the drain current transients.
allowed testing the impact of p-type implants and contacts to the pwell which is illustrated and described in section 2.5.
The cells
were laid out so that the n' sidegate electrode to n' source/drain
spacing would be constant for BG10 and BG5 and the n" sidegate
electrode to n-channel spacing for BGS5.
The different cells are
summarized in Table 2.3.
The group of MESFETs in block C are for the RF characterization.
Included in this array are MESFETs with different source-to-gate and
drain-to-gate spacings as well as quarter, half, and one micron gate
length devices.
Only two of these was examined in this study: the
p-well device and the MESFET with no p-implants on the control wafer,
both with one micron gate lengths and one micron source-to-gate and
20
drain-to-gate spacings.
The placement of the p+ well contact is
different for these structures than the placement shown in Fig. 2.2.
Since the interdigitated gate prevented the placement of the I)*
contact adjacent and parallel to the source contact it was placed at
the ends of the source n+ contacts.
2.3
Drain Current Transient Measurements
A convenient means of detecting, comparing, and analyzing trap-
related effects is to examine the drain current transient responses
of conventional and p-well MESFETs when square wave voltages are
applied to their drains.
The experimental setup used to study drain
current transients is shown in Fig. 2.7.
The drain of the MESFET is
terminated with a 50 ohm resistor to provide impedance matching with
the pulse generator.
The pulse generator was set to a 50 percent
duty cycle to provide a square wave input and deliver independently
adjustable high and low voltages.
The total drain current was
extracted from the voltage across a sense resistor (Rsense) on the
source side of the transistor.
The resistor value used in this study
was 50 ohms, which when taken in parallel with the 50 ohm termination
of the oscilloscope sampling head provided a 25 ohm sense resistor.
The transient waveform was digitized by the oscilloscope and acquired
by a controller over the IEEE-488 interface bus.
With a resistor on the source side of the transistor it is
difficult to maintain a constant VGS while the drain current is
changing.
assembled.
To avoid this problem the gate biasing network was
A dual tracking power supply was used to provide a
voltage to a 10:1 resistive divider.
The 8 a inductors were
21
PROBE CARD
PULSE
GENERATOR
OSCILLOSCOPE
it
BIAS
NETWORK
z
DUAL
POWER
SUPPLY
-gt
Illustration of the probe card used for the drain
Figure 2.8
current transient measurements of GaAs MESFETs.
provided to isolate the power supply from the fast rising and falling
edges of the pulse generator.
The capacitor between the gate and
source of the MESFET is a speed up capacitor which was also needed
for the falling and rising edges of the pulse generator waveforms.
The complete bias network was assembled on a 1 inch square piece of
circuit board and mounted on top of the gate probe to minimize stray
lead inductance.
Fig. 2.8.
The probe card assembly is shown schematically in
This probe and biasing configuration allowed 10 nSec rise
and fall times with no ringing in the test circuit.
22
FUNCTION
GENERATOR
Roans.,
TRIGGER
d
DC
POWER
V
SUPPLY
LOCKIN
F-7-1
'AMPLIFIER
de
A
I
DIGITAL
VOLT
METER
IEEE-488
1\
BUS
IEEE-488 BUS
SYSTEM
CONTROLLER
Schematic diagram of the measurement system for
Figure 2.9
characterization of the frequency dependent gds.
2.4
Frequency-Dependent Output Conductance Measurements
The small-signal output conductance is defined as;
ids
(2.1)
gds =
Vds
VGS
= constant
where ids is the small-signal drain-to-source current and vds is the
small-signal drain-to-source voltage.
The method by which gds is
extracted in this study is illustrated in Fig. 2.9.
A function
generator is used to supply the small-signal voltage (vdd) to the
drain of the MESFET, while the DC offset of the function generator
was used to supply the the DC drain voltage.
The small-signal
23
drain-to-source current is extracted from the small-signal voltage
across Rsense on the drain side of the MESFET.
This small-signal
voltage is measured using a lockin amplifier which was triggered by
the function generator.
The constant VGs was supplied by a DC power
vdd was adjusted until vds=50 mVpd was measured by the lockin
supply.
amplifier for all frequencies.
The data was acquired over the
IEEE-488 interface bus by the controller for several different
frequencies and stored on disk.
2.5
Sidegating Measurements
Sidegating is the decrease in the drain-to-source current of a
MESFET due to a voltage applied to a nearby electrode.
The nearby
electrode can be an n+ contact to an implanted resistor, source/drain
contact of a MESFET, or a piece of interconnect metal which is in
contact with bare semi-insulating GaAs.
A cross-sectional view of
the conventional MESFET sidegate test structure is shown in Fig.
2.10.
It consists of an n +- contact region in semi-insulating GaAs
separated from the source of the transistor by a distance of 10
microns.
The two quantities which will be examined most closely are
the sidegate current (IsG) and the percent decrease in Ids.
All the
measurements are done with the MESFET reverse biased so that with
zero sidegate voltage applied, Ids was 3.0 milliamps.
For the p-well
MESFET the sidegate electrode should simulate the source or drain of
another MESFET which is in a p-well.
The cross sectional view of the
p-well MESFET sidegate structure is shown in Fig. 2.11.
The other
structures listed in Table 2.3 can be obtained by simply removing the
respective implants from Fig. 2.11.
24
SOURCE
SIDEGATE
DRAIN
SEMIINSULATING GaAs SUBSTRATE
Cross-sectional view of the sidegate test structure
Figure 2.10
implemented in the conventional technology.
SIDEGATE
SOURCE
DRAIN
PIBurled
PWell
Channel
PSurface
Implant
SEMIINSULATING GaAs SUBSTRATE
Cross-sectional view of the sidegate structure
Figure 2.11
implemented in the p-well technology.
25
SMU 4
SMU 3
SOURCE
HP 4145B SEMICONDUCTOR
PARAMETER
ANALYZER
SIDEGATE
SMU 1
DRAIN-1
GATE
SMU 2
Figure 2.12
system.
Schematic representation of the sidegating measurement
Sidegating was measured using the experimental setup shown in
Fig. 2.12.
wafer.
A probe station was used for doing the measurements on
An HP4145B Semiconductor Parameter Analyzer was used to
supply the bias voltages and to monitor the currents.
The sidegate
voltage was stepped to the most negative voltage and swept to zero
volts at the slowest sweep rate to minimize the effects of
hysteresis.
The voltage step size was kept very small so that the
sweep would be very slow.
All measurements were done in a closed box
and the influence of illumination was provided with the microscope
light which was focused through the microscope lens onto the sample.
The highest intensity available on the lamp was used.
26
DC SUPPLIES
V ds
gs
1-HP8510
WAFER
1111::11
COPLANAR WAVEGUIDE PROBES
CONTROLLER
Schematic representation of the measurement
Figure 2.13
configuration used for the RF characterization of the p-well
technology.
2.6
RF Characterization
RF evaluation was done using the test setup shown schematically
in Fig. 2.13.
The S-parameters of the test samples were measured on
wafer using an HP8510B network analyzer between 100 MHz and 26.1 GHz
and coplanar waveguide probes from Cascade Microtech.
supplied through bias tees in the network analyzer.
1 Am by 300 Am interdigitated gate MESFETs.
DC biases were
The samples were
The S-parameters were
then transferred to a personal computer for analysis.
A physically
based small-signal equivalent-circuit model was implemented using
TOUCHSTONE®.
The equivalent-circuit parameter values were obtained
by an iterative process in TOUCHSTONE®.
The iteration process
adjusted the element values until the calculated values for the Sparameters of the equivalent-circuit were in good agreement with the
measured S-parameter values.
27
3.
DRAIN CURRENT TRANSIENTS
The influence of deep level traps on the transient behavior of
the drain current of GaAs MESFETs fabricated on semi-insulating
substrates are examined in this chapter.
The drain current
transients are shown to arise from both the capture and emission of
electrons by traps in the substrate near the channel.
The transient
behavior is described analytically using a square law model for the
drain current which includes terms accounting for the modulation of
the channel thickness due to changes in the width of the channelsubstrate junction depletion region.
The drain current transient characteristics suggest that control
of the floating channel-substrate junction is key to eliminating or
reducing this anomalous behavior.
The use of p-type implants to
confine the channel-substrate junction is examined as a potential
technique for accomplishing these goals.
The use of a p-well
technology is shown to eliminate the drain current transients with
long time constants.
3.1
Introduction
Understanding the dynamics of charge capture, as well as
emission of charge by deep levels is crucial to understanding the
transient behavior of GaAs MESFETs.
Since n-channel MESFETs are a
majority carrier device and the substrate is dominated by the large
concentration of EL2, this discussion will be confined to electron
traps.
For an electron trap the emission and capture time constants
are given by [34], [35],
28
ET) / kT
e(Ec
Te
(emission)
(3.1)
(capture)
(3.2)
<v>n Nc ae
1
Tc
<v>n n ac
where, Ec
ET
is the trap energy below the conduction band minimum, k
is Boltzman's constant, T is the absolute temperature, <v>n is the
electron thermal velocity, Nc is the conduction band density of
states, n is the electron concentration, and ae,c is the cross section
for emission and capture, respectfully.
The emission process depends
on the material properties <v>n and Nc and the trap properties
(Ec
ET) and ae.
Therefore, at a given temperature the emission time
constant will be constant for a particular defect.
For emission of
an electron from EL2 at room temperature the time constant is
approximately 17 mSec.
different.
The capture process is considerably
It depends on the material properties through <v>n and n,
and the defect properties through ac.
The dependence of the capture
time constant on n can result in behavior which is difficult to
predict and model since capture can occur in regions of varying
electron concentration.
It is instructive to examine how the drain current responds to
the capture and emission of electrons by traps in different regions
of the MESFET.
The MESFET can be divided into three different
regions illustrated in Fig. 3.1: the gate-channel depletion region
(I), the surface-channel depletion region outside the gate region
(II), and the channel-substrate transition region (III).
The
transient behavior can be described in general terms by careful
29
SOURCE
DRAIN
Cross-sectional view of the various depletion regions
Figure 3.1
which can contribute to drain current transients.
consideration of the response of these three regions and the
subsequent impact on the drain current after an abrupt change in the
drain voltage.
A step in Vds from an initial low voltage to a high
voltage causes the gate depletion region to extend towards the drain.
Subsequently, the subthreshold current flowing through the channel
substrate transition region increases and extends further into the
substrate in response to the electric field.
As traps in region I
emit their electrons due to the expansion of the depletion region,
causing the depletion region to contract, the drain current
30
increases.
The associated time constant is a direct reflection of
the emission time constant of the trap in the gate depletion region.
The transient response of the drain current due to modulation of
the surface space charge region by variations in the potential along
the surface has been examined in the past [14].
It has been
suggested that a finite surface conductivity can lead to time
dependent behavior in GaAs MESFETs [6].
The step from a low to high
voltage on the drain of the MESFET results in surface leakage
currents which can fill some of the surface states with negative
charge, causing the surface depletion region to expand and Ids to
decrease.
As long as the surface conductivity is relatively
constant, the time-dependent behavior will be a reflection of the
distribution in capture cross sections present in the surface states.
For the drain pulse this is dominated by the surface between the gate
and the drain where the largest potential difference exists.
In region III the electric field causes an increased rate of
charge injection into the substrate region, extending the region
through which conduction occurs.
This is represented by an increase
in the electron concentration deep into the substrate.
Capture
occurs in regions where there are ionized defects and an excess of
electrons beyond the steady-state concentration prior to the drain
voltage step.
The excess electron concentration is a smoothly
varying function of depth into the semiconductor.
capture time also varies as a function of position.
Therefore the
Neutralization
of EL2 results in shallow acceptors which are now uncompensated.
To
achieve steady-state operation, this negative charge associated with
31
N.eff must be balanced.
This is achieved by expansion of the
channel-substrate depletion region on the channel side of the
junction.
The electrons which have been swept out of the depletion
region leave behind the ionized shallow donors to balance the
increase in uncompensated shallow acceptors.
The drain current
responds by initially increasing to a high value and then decreasing
as the channel is pinched off due to the expansion of the channelsubstrate depletion region.
The rate at which the depletion region
expands is dependent on the rate of capture, and capture is dependent
on the local concentration of electrons which is position dependent.
Therefore, instead of a single discrete time constant, the time
constant effectively changes with time as the ionized EL2 become
neutral in regions of decreasing electron concentration.
A step from a high to a low voltage on the drain results in
considerably different behavior for all three regions.
In region I
the gate to drain depletion region collapses and the ionized EL2
captures electrons.
Since the electron concentration is so high in
the channel (z1017 cm-3), the capture time constant is much too fast
(z10-12 sec) to observe.
In region II the emission of charge from the
surface states results in the depletion region relaxing, causing Ids
to decay upward after the initial decrease.
The decay is most likely
to be a collection of time constants due to the distribution in
energies of the surface states.
In region III the transient response
is dominated by the emission of charge from EL2.
After the initial
decrease in Ids due the abrupt change in Vds, Ids increases as the
32
INPUT V DS WAVE FORM
REGION I TRANSIENT RESPONSE
REGION II TRANSIENT RESPONSE
REGION III TRANSIENT RESPONSE
Figure 3.2
Input drain voltage waveform and corresponding drain
current transient responses due to the three different regions of
Fig. 3.1.
electrons are emitted.
The decay is therefore dominated by the time
constant of EL2.
The transient responses of the three regions are summarized
schematically in Fig. 3.2.
The response of region I is distinctly
different from that of regions II and III which at least
qualitatively appear to be similar.
Differences are expected though
based on the relative contributions each is expected to make for
current transients resulting from abrupt changes in the drain
voltage.
When the drain is pulsed to a high voltage, region II
contributes to the transient response primarily by increasing Rd, the
33
CONVENTIONAL MESFET TRANSIENTS
TIME (50 mSec/DIV)
Figure 3.3
Measured drain current transient response of the
conventional GaAs MESFET.
A voltage square wave between 5.0 V and
1.0 V was applied to the drain.
VGS = 0.0 V.
parasitic drain-to-gate resistance.
Region III contributes to the
transient response by increasing Rds, the drain-to-source channel
resistance.
Since in saturation Rd, > Rd, trapping in region III is
expected to contribute much more significantly than trapping in
region II.
Also there exists the potential for a much broader spread
in capture time constants in region III than in region II.
distribution in the electron concentration from
The large
approximately 108
cm-3 in the substrate, to 1017 cm-3 in the channel of region III
corresponds to approximately nine orders of magnitude variation in
the capture time constant (10-3 to 10-12 seconds).
34
CONVENTIONAL MESFET TRANSIENTS
6 mA
0)
a
E
0
0
tr)
0
1 mA
TIME (1 mSec/div)
Measured drain current transient response of the
Figure 3.4
conventional GaAs MESFET. A voltage square wave between 5.0 V and
VGS = 0.0 V.
1.0 V was applied to the drain.
3.2
Measurement of Conventional MESFETs
The transient response of the drain current to a square wave
voltage input on the drain terminal with a period of 500 mSec is
shown in Fig. 3.3.
For a voltage step from an initial high value to
a final low value, the drain current decreases to an initial low
value and decays slowly upward to its steady-state value.
This
transient response will be referred to as current undershoot.
The
time required to reach steady-state is on the order of 200 mSec.
35
T=10-8
Q
E
(D
0
T=10-7
...-..-
''...............................,Ibo
T=10
-6
T=10-5
4
T=10
22.6
mA
Time (T Sec/Div)
Figure 3.5
Measured drain current transient overshoot for an
abrupt change in the drain voltage from 0.0 V to 5.0 V for a
conventional GaAs MESFET. Each curve represents a different time
scale ranging from 10 mSec/Div to 10 nSec/Div. VGs = 0.0 V.
However, the drain current response for a low to high voltage step
does not display a transient on this time scale.
When the time scale
is expanded, as shown in Fig. 3.4 a transient is observed for this
drain voltage transition.
As the time scale is expanded further the
transient becomes more dramatic as shown in Fig. 3.5.
The drain
36
CONVENTIONAL MESFET
9.8 mA
LOW
.
,
.
HIGH RESPONSE
.
.
.
.
.
10 mSec
100 ASec
046411t1 tt14W-144401141111
44.01114441114114.01144411
1 p.Sec
cn
8.8 mA
.
.
.
.
.
.
.
.
TIME (100 nSec/Div)
Measured drain current transient response of the
Figure 3.6
conventional GaAs MESFET. A voltage square wave between 5.0 V and
1.0 V was applied to the drain for three different pulse periods.
VGS
0.0 V.
current increases to an initial high value and decays downward to its
steady-state value.
This transient response will be referred to as
current overshoot.
The considerable change in Ids on each scale
indicates there are multiple time constants in the relaxation to
steady-state.
Another feature of the current transients is the dependence of
the decay on the period of the applied square wave as illustrated in
Fig. 3.6.
As the period of the applied signal decreases, the time
37
19
mA
Time (T Sec/Div)
Measured drain current transient undershoot for an
Figure 3.7
abrupt change in the drain voltage from 5.0 V to 1.5 V for a
conventional GaAs MESFET. Each curve represents a different time
scale ranging from 10 mSec/Div to 10 ilSec/Div. VGS = 0.0 V.
constant and the magnitude of the transient overshoot change.
This
behavior arises because of the long time constant associated with
emission.
If the drain voltage switches low and traps do not have
time to emit any electrons before the drain voltage swings high
again, the fixed charge distribution will not have changed.
Therefore, the initial current level will be the same as the final
current level of the previous pulse.
This behavior contributes to
the frequency- and pattern-dependent propagation delays and result in
considerable modeling difficulties.
The drain current transients for the current undershoot are also
shown on an expanded time scale in Fig. 3.7.
Most of the change
takes place on the two longest time scales which is more indicative
of a single time constant.
The changes occurring for much shorter
38
E
0
0
1
2
AV DS
3
4
5
(Volts)
Magnitude of the drain current transient overshoot for
Figure 3.8
an abrupt increase in VdS from 0.0 V to AVd$. VGs = 0.0 V.
times may be the result of another defect level or may be thermal
effects.
Comparing the current transient behavior observed for these
MESFETs with the discussion accompanying Figs. 3.1 and 3.2, it
appears that trapping in region III is dominating the drain current
transient behavior.
This is not surprising since the channel
substrate junction is floating, and is thus susceptible to modulation
by charge accumulation in the substrate.
The lack of any transient
corresponding to region I might be surprising due to the large
concentration of EL2 known to exist in semi-insulating GaAs.
However, there is considerable evidence showing that EL2 is
annihilated in the presence of high electron concentrations during
39
thermal annealing [41], [42].
These conditions are present in the
n-channel regions during the implant activation anneal of an ion
implanted process.
Another result which supports this conclusion is
shown in Fig. 3.8.
This figure shows the magnitude of the current
overshoot for a drain voltage step from zero volts to a high voltage.
As the high value of VdS is increased, AIds increases.
However, no
current overshoot could be detected for drain voltage steps below 0.6
volts.
In this range of voltage steps the MESFET remains in the
linear region of operation and the electric fields are insufficient
to sweep carriers over the channel-substrate barrier and into the
substrate.
Since transients corresponding to region I of Fig. 3.2
could not be detected, these results are direct evidence that EL2 can
be annihilated by common processing steps such as the thermal anneals
used for activating ion-implanted dopant atoms.
3.3
Analysis
The channel substrate interaction can be modeled as a modulation
of the active layer thickness by changes in the depletion layer
thickness of the channel-substrate junction [12].
This interaction
arises due to the capture and emission of electrons by EL2 and other
electrically active defects in the substrate.
For the active layer
thickness and pinch-off voltage of the devices used in this study, a
square law model of Ids is appropriate for analytical purposes.
The
40
square law model most commonly used is the Curtice equation [43]
given by,
VT)2(1 + AVds)tanh(aVds),
Ids = B(Vgs
(3.3)
where, VT is the threshold voltage, A is an empirical parameter
related to the drain conductance, and B can be approximated as
ides/2Kg.
In this expression for B, A is the mobility, Z is the gate
width, es is the dielectric constant, W is the active layer
thickness, and Lg is the gate length.
VT = Vbi
We also have that,
(3.4)
Vpo,
where Vbi is the built-in potential of the Schottky barrier and Vpo is
the pinch-off voltage which is given by,
qNdW2
(3.5)
VP0
2Es
In this analysis Nd is the doping in the active layer which is
assumed to be constant.
B can now be rewritten as;
AZWqNd
(3.6)
B 4L9VP0
and Ids can be rewritten as;
AZWqNd
(Vgs
Ids
Vbi + VP0)2(1 + AVds)tanh(aVds).
(3.7)
4LgVpo
While the assumption that Nd is constant is in reality an over
simplification, it can serve to ease the analysis considerably.
Eventually the transient from of Ids will be expressed in terms of
measurable parameters such as B and VP0 which depend on Nd, thereby
removing the explicit dependence on Nd.
41
GATE
METAL
Old
Waab
ciNa
I774 07. V7774
A Womb
Charge distribution along a path from the gate into
Figure 3.9
the substrate of a conventional MESFET. The shaded regions signify
the depletion regions which change due to the balancing of charge.
The modulation of Ids by changes in the channel-substrate
transition region can be incorporated in Eqn. (3.7) by examining the
charge density in Fig. 3.9.
The figure represents the charge
distribution along the X-X' path of the cross-sectional view of the
MESFET in Fig. 3.10.
In the neutral substrate, the acceptors are
compensated by the ionized deep donors, i.e. Naeff = N. The shaded
region represents the area where the above equation for compensation
is changing i.e. Ncid+ <---> Ndd° by capturing or emitting electrons
depending on how the drain voltage has changed.
Using charge balance
and the notation in Fig. 3.9,
Nd(W
Wh) = Na(Wsub
AWsub).
(3.8)
42
x
x
Cross-sectional view of a conventional MESFET showing
Figure 3.10
the path used in Fig. 3.9.
The amount of change that occurs due to a change in Vds is given by,
NdAW = NaAWsub
(3.9)
where,
AW = WI
Wh.
(3.10)
If we let,
ANdd41° = NaAWsub
(3.11)
be the total number of EL2 per cm2 which emit or capture electrons
43
(i.e. change charge state) then, AW can be expressed as,
ANold+10
AW =
(3.12)
.
Nd
In Eqn. (3.12) ANdcr° is time dependent and is given by,
ANdd+/°(t) = ANdd+/°(03)(1
ANdd+1°(t) = ANddllo (co) e-t/Tc
etire)
(emission)
(3.13a)
(capture)
(3.13b)
where the emission and capture time constants are given by Eqns.
(3.1) and (3.2).
The square law model for the drain current is an
approximation which assumes that current saturation is due to pinch
off of the channel.
The expression for ANdd+/°(t) in Eqn. (3.11) is
consistent with this approximation where X-X' of Fig. 3.10 passes
through the point of pinch off in the channel.
It is a measure of
the sheet concentration of deep donors which change their charge
state along a plane extending along AWsub of Fig. 3.9.
Expressing the effects of capture and emission by traps in terms
of their concentration is not particularly useful for modeling
purposes since these quantities are rarely known with any accuracy.
Furthermore, when the traps are native defects such as EL2, there
always exists the possibility that their concentrations can change
during processing [42].
A more tractable parameter is the channel
thickness which is easier to extract from a simple electrical
measurement of a MESFET.
The change in the channel thickness can now
be rewritten as a single expression for both capture and emission of
44
carriers,
(3.14)
Wc,e(t) = Wh,L ± AWettrc,e
The c, h, and + are for emission, and e, 1, and
are for capture.
These terms are included in the Curtice equation (3.7) by replacing W
with W(t).
Therefore, Ids and Vpo become,
K1
Wc e(t)[Vg +
Ids(t) =
Vp0(t)]2
(3.15)
Vpo(t)
where,
AZqNd
(3.16)
(1 + AVds)tanh(aVds),
xi
4Lg
Vg = Vgs
(3.17)
Vbi,
(3.18)
Vpo(t) = K2 Wc,e(t)2,
and
qNd
(3.19)
K2 =
2es
Expanding Eqn. (3.14) gives,
KiWc,e(t)
(3.20)
[Vg2 + 2VgVpo(t) + Vp0(t)2]
Ids(t) -
VpoM
Replacing V,(t) by Eqn. (3.18) gives,
V g2
Ni
+ 2Vgx214c,e(t) + 22Wo,o(t)3
Ids(t) =
K2
I
.
(3.21)
t'ic,e(t)
Inserting Wc,o(t) of Eqn. (3.14) and separating terms gives an
equation for Ids of the following form;
Ids(t) = Ids(m) ± AIds(t).
(3.22)
45
The components of Ids(t) are given by,
NiWn,L
(3.23)
[Vg + Voh,L]2,
Ids(w)
V
Aids(t) = ic,
f(
)Vg2
Wh,LAWe" t/Tc,e
-F
4-
11
1,1
poh,L
"11,1.
"Awe-tt rc,e
± AWetircie (2Vg + 3V poh,l)
+ 3K2wh,LAw2e-2ttrp,e ± K2Aw3e-3t/rp,e
(3.24)
1,
where,
ciNdwh,i2
V
(3.25)
=
2es
For the depletion mode devices examined in this report Wh,L
AW.
Therefore, the last two terms of Eqn. (3.25) which are higher order
in AW can be ignored.
Furthermore, the first term can be
approximated as,
V92
Wh,LAWCtirc,e
t2
(3.26)
V
Wh,L ± AWE'tiTc,e
VP°v
h,l
h,l
tPrc'e.
AIds(t) now becomes;
AIds(t) = AIds(0)e-tmc,e
(3.27)
,
KiAW
AIds(0) = ±
(3Vpoh,L2 + 2VtVpoh,i
Vg2).
(3.28)
V
Finally, the transient form of Ids can be expressed as,
(3.29)
Ids(t) = Ids(w) ± Aids(0)Cmc,e
The expression in (3.29) is especially convenient for the
characterization of drain current transients because it is expressed
directly in terms of measurable parameters.
For a substrate heavily
46
23
= 10
T = 10-3
T = 10-4
20
19
TIME (T Sec/Dev)
Analytical results of drain current transient
Figure 3.11
undershoot for the conventional MESFET results of Fig. 3.7.
dominated by EL2, the characterization of the emission process is
easily accomplished by measuring AIds(0) and Ids(w).
The time
constant and emission cross section of EL2 are well known and are
easily to verified by measuring the transient at different
temperatures.
The capture process however, presents some
difficulties in that the capture time depends on the concentration of
excess electrons in the vicinity of ionized EL2.
3.4
Comparison of Analysis and Measurement
The analytical expressions for the drain current can be compared
with the experimental results of section 3.2.
The most straight
forward comparison of the analysis and experiment is a comparison of
equation (3.29) to the transient data of Fig. 3.7.
is shown in Fig 3.11.
This comparison
After adjustment of Te of EL2 for self-heating
in the MESFET [5], the Ids curves compare nicely to the curves of Fig.
3.7.
47
0
10-9
1
10-8 10-7 10_6 10-5 10-4 10-3 10-2 10-1
Time (seconds)
Time dependence of the log of the magnitude of current
Figure 3.12
overshoot normalized to t=0 for the measured current overshoot
waveforms of Fig. 3.5.
As mentioned earlier, characterization
of current overshoot is
complicated by the absence of a distinct time constant.
is an equation characteristic of exponential processes.
Eqn. (3.29)
The time
constant can be extracted by manipulation of this equation to give;
t
ti
Tc
9
(3.30)
rlds(t1
In
AIds(ti)
where Tc is just the slope of the line generated from plotting the
denominator of the above equation versus time; ti is some initial
time, and t is some time later.
A plot of the denominator in Eqn.
(3.30) versus time is shown in Fig. 3.12 for the transient overshoot
results of Fig. 3.5.
For an exponential process with a single time
48
constant the curve should be a straight line when the horizontal axis
is linear.
However to fully examine the trends, the horizontal axis
had to be logarithmic. These results demonstrate the absence of a
simple exponential process.
Clearly, if current overshoot and decay are the result of
electron capture in the substrate, a single distinct time constant
would not be expected.
When the drain voltage is stepped from a low
voltage to a high voltage, the electron tail in the channel-substrate
junction shifts into the the substrate.
This shift is in response to
the changing electric field generated by the drain voltage.
The
constant potential lines wrap around the gate depletion region and
the channel-substrate interface, pulling charge into the substrate
along the electric field lines.
in junctions decay exponentially.
In general, carrier concentrations
Likewise this new electron tail
will decay exponentially into the substrate.
Therefore, it is
reasonable to expect the time constant to show a strong dependence on
time in response to the exponential dependence of the electron
concentration on position.
Closer investigation of the time
dependence of Tc can be accomplished by rewriting Eqn. (3.30) as the
simple finite difference equation given below;
ti _1
ti+1
(3.31)
Tci
rds(ti+1)]
AIds(ti.1)
This formulation of Tc relates the capture time to the changes in Ids
created by capture of electrons in specific regions of the electron
49
100
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9 10-8 10-7 10-6 10-8 10-4 10-3 10-2 10-1
Time (seconds)
Figure 3.13
Time dependence of the capture time constant for the
transient current overshoot of Fig. 3.5.
tail as the MESFET reaches steady-state.
The results are shown in
Fig. 3.13 with a least squares fit to the data.
The dotted line
which has been fit to the data results in the following equation;
r(t) = 1.21t°893.
(3.32)
This equation provides a good fit over a range of six orders of
magnitude in time.
The six orders of magnitude change in the time
constant correspond to a six order change in magnitude in electron
concentration which is easily
transition region.
achieved in the channel-substrate
This equation can be used in Eqn. (3.29) to model
the decay of the drain current in response to a drain voltage step
from low to high.
However, for this to be successful, the prefactor
50
to the exponential (AIds(0)) must be modified to represent the amount
of change occurring while this time constant is valid.
3.5
Transient Measurements of Buried-Channel and P-Well MESFETs
The use of p-type implants to control the drain current
transients have met with mixed results [9], [44], [45].
Much of the
difficulty interpreting previously reported results has been due to
the lack of direct comparison with control samples.
Based on the
transient results of the conventional devices, it is reasonable to
postulate that control of the channel-substrate junction should
result in improvements in the transient response of the MESFET.
One
possibility is to leave the p-type region floating as is typically
done and hope that the increased barrier height and abruptness of the
junction will significantly lower the rate of charge injection into
the substrate and subsequent capture and emission [45].
Another
possibility is to enclose the MESFET in a p-type well and confine the
potential of the channel-substrate junction to a known voltage,
thereby isolating the channel of the MESFET from fluctuations in the
charge distribution in the substrate.
The drain current transient response of samples with four
different p-type implants behind the channel were examined and
compared.
The transient response for a low to high voltage step is
shown in Fig. 3.14.
Little improvement is seen in the samples with
the lower p-type doping (2.0 and 4.0 x 1016 crif3 peak p concentration)
behind the channel in comparison to the conventional device.
The two
samples with the higher doping (8.0 and 16.0 x 1016 cm-3 peak p
concentration) behind the channel are significantly different.
The
51
T=I0
-7
-5
T =10
T=10-3
Time (T Sec/Div)
T=10-7
T=10-5
T=10-3
Time (T Sec/Div)
c)
E
op
T=10-7
T=10
T=1
Time (T Sec/Div)
.4(
E
T=10
03
-7
T=10T=10-3
Time (T Sec/Div)
Figure 3.14
Measured drain current transient overshoot response
for a 0.0 V to 5.0 V drain voltage step on buried-channel MESFETs for
1 mSec/Div, 10 ASec/div, and 100 nSec/Div scales.
The peak p-type
doping behind the channel is a) 2.0 x 1016 cm-3, b) 4.0 x 1016 cm- 3, c)
8.0 x 1016 cm -3, and d) 16.0 x 1016 cm-3.
52
a)
T=10-3
../1.......
T:=10-5
Time (T Sec/Div)
b)
T=10-3
T=10-5
Time (T Sec/Div)
Time (T Sec/Div)
Time (T Sec/Div)
Measured drain current transient undershoot response
Figure 3.15
for a 5.0 V to 1.5 V drain voltage step on buried channel MESFETs for
1 mSec/Div and 10 ASec/div scales. The peak p-type doping behind the
channel is a) 2.0 x 1016 cm-3, b) 4.0 x 1016 cm-3, c) 8.0 x 1016 cm-3,
and d) 16.0 x 1016 cm-3.
53
time constant for the decay of the drain current increased
The
dramatically for the buried-channel MESFETs with higher doping.
transient undershoot is shown in Fig. 3.15.
As in the overshoot
case, the two samples with lower p-type dopings behind the channel
For
showed little change when compared to the conventional device.
the two samples with higher doping behind the channel, the magnitude
of the transient increases.
The time constant also changes for these
two samples, becoming faster as the doping is increased.
The drain current transients for the p-well MESFET with the same
doping levels behind the channel have also been investigated.
results of the current overshoot are shown in Fig. 3.16.
The
For the two
samples with the lower peak p-type doping levels behind the channel,
the results are similar to the buried channel structure.
That is
they show little improvement or change when compared to the
conventional MESFET.
The two samples with the higher peak p-type
doping behind the channel are dramatically different.
While the
magnitude of the transients is slightly greater, the current has
essentially decayed to its DC value in under 100 nSec.
The drain
current transient results for a high to low voltage step on the drain
are shown in Fig. 3.17.
The samples with the lower p-type doping
levels showed little change in the response as opposed to the control
samples.
However, the sample with the peak p doping behind the
channel of 8.0 x 1016 cm-3 showed no signs of any transient.
54
T=10
a
E
-7
T=10
-5
03
T=10-3
0
,.....,
Time (T Sec/Div)
E
03
Time
E
T=10
T Sec/Div)
-7
OD
T=10-5
T=10-3
V
Time (T Sec/Div)
T=10
-7
T=10-5
T=10
-3
Time (T Sec/Div)
Measured drain current transient overshoot response
Figure 3.16
for a 0.0 V to 5.0 V drain voltage step on p-well MESFETs for 1
mSec/Div, 10 ASec/div, and 100 nSec/Div scales. The peak p-type
doping behind the channel is a) 2.0 x 1016 cm-3, b) 4.0 x 1016 cm-3, c)
8.0 x 1016 cm-3, and d) 16.0 x 1016 cm-3.
55
.
.
.
.
T=10-3
.
1.---...
T=10-5
.
.
.
.
.
Time (T Sec/Div)
Time (T Sec/Div
Time
T Sec/Div
Time (T Sec/Div)
Measured drain current transient undershoot response
Figure 3.17
for a 5.0 V to 1.5 V drain voltage step on p-well MESFETs for 1
mSec/Div and 10 gSec/div scales. The peak p-type doping behind the
channel is a) 2.0 x 1016 cm-3, b) 4.0 x 1016 cm -5, c) 8.0 x 1016 cm-3,
and d) 16.0 x 1016 cm-3.
56
3.6
Summary
The behavior of the drain current transient response to an
abrupt change in the drain voltage of conventional MESFETs is strong
evidence that this anomalous behavior is the result of charge capture
and emission in the GaAs substrate.
The ability to characterize this
behavior using a square-law relationship for the drain current can be
utilized in modeling these effects, although further parameterization
of the current overshoot behavior must be accomplished.
The concept
of a floating channel-substrate junction modulating the MESFET
current in conventional technology has been demonstrated from these
results.
The p-well MESFET was demonstrated to eliminate the drain
current transients with long time constants and offers hope of a
technology which is better suited for design of precision analog and
digital circuits in GaAs.
Significant reduction in the settling time
of amplifiers and switches, reduction in hysteresis in differential
circuits and comparators and reduction in frequency and pattern
dependent propagation delay times are just some of the potential
benefits possible with these improved device results.
57
4.
FREQUENCY DEPENDENT OUTPUT CONDUCTANCE
The characteristics of the frequency dependent output
conductance are examined in this chapter.
It is shown that gds(f) is
related to the emission time constant of electrons from deep levels
in the substrate near the channel.
Using the expression for drain
current transients in chapter 3, an analytical expression for the
frequency dependent output conductance is derived.
This analytical
expression is compared with experimentally obtained results and shown
to be in good agreement.
The use of p-type implants to control the
frequency dependence of gds is also examined.
The p-well MESFET is
shown to offer the greatest reduction in the frequency dependence of
gds at low frequencies.
4.1
Introduction
The output conductance is the small-signal response of the drain
current to a small-signal voltage applied to the drain of a MESFET.
Ideall y, gds is independent of frequency.
However, in conventional
GaAs MESFET technology gds is frequency dependent.
Studies of the
frequency dependence of gds have primarily focused on equivalent
circuit modeling of the effect [1], [3], [4], [24], and very little
on explaining its physical origins [46], [47].
The frequency
response of gds is characterized by a low value at low frequencies, a
high value at high frequencies, and a transition region which begins
at about 10 Hz at room temperature.
Just as the transient results of
chapter 3 emphasized the deleterious role the floating channelsubstrate junction plays on the time dependent behavior of the
58
MESFET, it is also linked to the frequency dependence of gds at low
frequencies.
Conceptually the frequency dependent behavior of gds can
be understood by carefully considering the interaction of defects in
the substrate with the channel current when a small signal is applied
to the drain.
When the terminal voltages are applied to the transistor, it
will reach steady state operation within a few hundred milliseconds
as illustrated by the transient measurements of section 3.2.
With
the subsequent application of a small-signal voltage to the drain at
a high frequency (f > 1/Te), the changes in Vds will occur too rapidly
for any significant capture or emission to take place as illustrated
by the results of Fig. 3.6.
At a high frequency, the charge
associated with the deep donors is fixed and the small-signal current
is a reflection of this fixed charge distribution.
At low
frequencies, the channel substrate depletion region will respond to
the slowly varying voltage on the drain.
When the small-signal
swings high, the rate of injection into the substrate and subsequent
rate of capture in the substrate increases, resulting in a decrease
of the drain current due to the expanding channel-substrate depletion
region.
When the small-signal voltage swings low the rate of
injection into the substrate and subsequent rate of capture decreases
and the current will increase due to the relatively higher rate of
emission, which decreases the degree to which the channel is pinched
off from the backside.
That is, at low frequencies the traps can
follow the applied signal and the magnitude of the small-signal drain
current will be less than it is at high frequencies.
Since gds is
59
Vds
ds
High frequency and low frequency small-signal current
Figure 4.1
for a given applied small-signal vds.
defined as ids/vds with VGs constant, and the peak-to-peak value of ids
is smaller at low frequencies than at high frequencies we know that
gds at low frequencies is smaller than gds at high frequencies (Fig.
4.1).
It should be emphasized that emission is the rate limiting
process.
As observed from Fig. 3.5, most of the change in Ids occurs
in the first couple of hundred microseconds for a capture process.
Most of the change in Ids of Fig. 3.7. occurs between 100 microseconds
and 100 milliseconds for the emission process.
Before charge can be
captured, there must be ionized deep levels to capture the charge.
If the charge has not had sufficient time to be thermally emitted,
60
15
13
E
11
U)
Vgs(volts)
-o
CD
0 0.75
7Q
A
0
. .1
10
I
.
100
. ....I
1000
0.0
0.5
.
1E4
1E5
FREQUENCY (Hz)
Measured frequency dependence of the output
Figure 4.2
conductance for three different gate voltages. Vps = 2.0 V.
then no change in the charge distribution will occur before the
small-signal swings high again.
4.2
Measurement of Conventional MESFETs
Typical output conductance measurements versus frequency are
shown in Fig. 4.2.
At low frequencies gds is small, increasing
between 10 Hz and 100 Hz and leveling off.
The rise at 10 kHz may be
due to another trap level or may be due to the thermal time constant
of the GaAs.
In Fig. 4.3, gds is shown as a function of frequency
for different lips.
As Vps increases, so does the magnitude of the
change in gds from low to high frequency.
For small Vps, the change
in gds with frequency vanishes which supports the conclusions of the
drain current transient results shown in Fig 3.8 suggesting that
61
2.5
2.0
0.5
10
0
1
10
10
2
3
10
10
4
105
Freq. (ME)
Measured frequency dependence of the output
Figure 4.3
conductance for different Vps. VGs = 0.0 V.
there is no EL2 in the channel.
That is, at low field conditions in
the linear region of operation the small-signal on the drain does not
modulate the charge states of defects in the substrate.
The increase
in gds as Vds increases is due to the increased penetration of the
electrons into the substrate on the drain side of the gate.
This
allows for increased modulation of the channel due to the increased
number of traps which can follow the signal.
62
4.3
Analysis
The agreement of the above discussion with the experimental data
reinforces the conclusion that emission of electrons from EL2 is the
rate limiting process.
Therefore only the emission part of Ids(t)
need be examined in deriving the frequency dependent gds.
Furthermore, from the drain current transient data, a single time
constant is a satisfactory approximation for analytical purposes.
This should allow the use of Eqn. (3.22) to calculate an analytical
expression for gds.
Rewriting Eqn. (3.22) in a more appropriate form
gives,
ic3
Ids (
t )
(1 + AVds)tanh(aVds)
=
V
Pot
x [Wt (V9 + VpoL)2
AWe-ttre(3Vpoh 1.2 + 2VtVp,,,h,1
(4.1)
V92) ]
where,
AZqNd
(4.2)
K3 =
4Lg
The output conductance is defined by,
ales
(4.3)
gds
avos
VGS = const.
Taking the derivative of (4.1) gives,
K3
[Atanh(aVds) + (1 + AVds)asech2(aVas)]
gds(t) =
VPot
x [WL(Vg + VpoL)2 - Awe-tpre(3vpohi2 + 2VtVpoilL
V92)].
Since gds is a small-signal parameter, the time dependence is not
particularly useful.
However, the frequency dependence can be
obtained by taking the Laplace transform of gds(t) in Eqn. (4.4).
(4.4)
63
X3
[Atanh(aVdS) + (1 + AVds)asech2(aVds)]
gds(S)
V
Poi
(WI
X (
+ Vp01)2
S
AW
W)
T. + s
2AW(Vp012
Vg2)
(4.5)
WT. + s
which can be simplified to
+ (Wh/WL)Tes}
1
(4.6)
gds(s) = gds(0)
1 + TeS
S
The term in brackets is the small-signal response, 1/s is the forcing
function, and gds(0) is the low frequency value of gds(s) given by,
X3
(3V92
gds(0) =
2VgVpo1
Vp012)W1
Vpot
(4.7)
x [Atanh(aVds) + (1 + AVds)asech2 (aVds)].
Finally, the small-signal response can be written as;
1 + [gds (m)/gds(0)1Tes
(4.8)
gds(s) = gds(0)
1 + TeS
where gds(m) is identical to gds(0) in Eqn. (4.7) with WI replaced by
Wh.
This form of gds is particularly useful for modeling because it
is expressed in terms of the measurable quantities, gds(m) and gds(0),
and the time constant of EL2 which is well established.
This
equation is identical to a semi-empirical equation derived earlier
[5].
However, here gds(s) is derived from the Curtice model and is
dependent on the common set of modeling parameters B, A, a, and VP0.
Implementation of a physically based model which accounts for the
frequency dependence should therefore be much simpler.
The
robustness is illustrated in Fig. 4.4 which shows Eqn. (4.8) for gds
data at three different temperatures.
64
20
16
275 °K
X
325 °K,,..
.**-'375
° K
I
101
10
2
10
3
10
4
10
5
106.
Freq. (1-1Z)
Comparison of the frequency dependence of the output
Figure 4.4
conductance model and measured data for three different temperatures.
4.4
Measurement of Buried-Channel and P-Well MESFETs
Based on the improvements in transient response observed by use
of the p-well MESFET, similar improvements in gds are expected.
This
is confirmed in Fig. 4.5 which show gds as a function of frequency for
different Vgs.
The two samples with the lower p-type doping behind
the channel continue to show considerable variation with frequency.
The two samples with the higher p-type well doping show that control
of the channel-substrate junction is very effective in eliminating
the frequency dependence of gds at frequencies below 100 kHz.
65
2G
)
15
i
43 0-0
10
0
V gs (..olls)
O 0.75
A
O
10
100
1000
0.0
0.5
1E4
1E5
1E4
1E5
FREQUENCY (Hz)
10
100
1000
FREQUENCY (Hz)
30.0
25.0
20.0
7
15.0
10.0
5.0
0.0
10
100
1000
1E4
1E5
1E4
1E5
FREQUENCY (Hz)
35.0
30.0
E
25.0
20.0
Nr
15.0
10.0
5.0
0.0
100
1COG
FREQUENCY (11Z)
Figure 4.5
Measured frequency dependence of gds for the p-well
MESFET at three different VAS. Vps = 2.0 V. The peak p-type doping
behind the channel is a) 2.0 x 1016 cm-3, b) 4.0 x 1016 cm- 5,
c) 8.0 x
1016 cm-3, and d) 16.0 x 1016 cm-3.
66
E
E
N
Vgs(volts)
ti
O -0.75
0.0
O 0.5
10
1000
100
1E5
1E4
FREQUENCY (Hz)
10
100
1000
1E4
1E5
FREQUENCY (Hz)
100
1000
1E4
1E5
FREQUENCY (Hz)
10.0
d)
8.0
V
9S
(volts)
O -0.75
A
0.0
O 0.5
-6-
0
4,- 6' -6- -45- -A-
-
-It, -46- -6-
4.0
2.0
0.0
10
100
1000
1E4
1E5
IREOUEUCY (Hz)
Figure 4.6
Measured frequency dependence of gds for the buried
channel MESFET at three different VAS.
V
= 2.0 V.
The peak p-type
doping behind the channel is a) 2.0 x 1016 cm-3, b) 4.0 x 1016 cm-3, c)
8.0 x 1016 cm-3, and d) 16.0 x 1016 cm-3.
67
The-buried channel samples on the other hand became much worse
as the doping in the p-type layer is increased as shown in Fig. 4.6.
For the two samples with the highest p-type doping the buried p-layer
simply improves the efficiency of the capacitive coupling between the
drain and the channel.
4.5
Summary
The successful extension of the analysis of the drain current
transients in chapter 3 to the frequency dependence of gds is
convincing evidence that the two phenomena are linked.
Basing the
analysis on modulation of the drain current by varying the charge
states of the deep levels in the substrate further substantiates the
claim that the floating channel-substrate junction is responsible for
this anomalous behavior.
Finally, elimination of the frequency
dependence at low frequencies by controlling the channel-substrate
junction offers the opportunity to develop a technology which is
minimally impacted by this anomalous behavior.
68
SIDEGATING
5.
Chapters 3 and 4 explored many of the adverse consequences of an
uncontrolled channel-substrate junction in GaAs MESFET technology
which arise due to changes in the drain voltage.
This floating
junction can also be influenced by a voltage applied to a nearby
electrode such as the drain or source of a nearby transistor, this
effect is referred to as sidegating or backgating.
The basic
characteristics of sidegating in conventional technology are reviewed
in this chapter.
A substantial decrease in the anomalous behavior of
gds and Ids were demonstrated in chapters 3 and 4 using the p-well
MESFET. In this chapter, the influence of p-type implants on the
sidegating behavior will be examined.
Just as in the case of the
transient and gds behavior, p-type implants have a strong influence on
the sidegating behavior.
The p-well MESFET is shown to offer the
greatest immunity to sidegating.
5.1
Sidegating in Conventional Technology
Sidegating is the result of a loss of isolation between two
devices, which causes the behavior of one device to be modified by
changes in the operating conditions of the other.
In GaAs ICs,
sidegating can occur in MESFETs, implanted resistors, current
limiters and Schottky diodes.
The electrode or device responsible
for causing the loss of isolation and subsequent sidegating can be
any one of the four devices listed above plus metal interconnect
which lies on semi-insulating GaAs.
Sidegating due to interconnect
metal on semi-insulating GaAs can be eliminated by requiring all
69
CONVENTIONAL MESFET SIDEGATING
105
10-6
1
0-7
E
8
10
109
10-10
10
0
SIDEGATE VOLTAGE (1 V/div)
Measured sidegating results for the conventional
Figure 5.1
MESFET structure of Fig. 2.10 at room temperature and without
The drain current is shown in the upper trace and
illumination.
sidegate current is shown in the lower trace. Vin = 2.5 V and
Ids (VGS=°) = 3.0 mA.
interconnect metal to lie on a passivating layer such as silicon
nitride or silicon dioxide.
Since current limiters, implanted
resistors, and Schottky diodes will all be susceptible to the same
sidegating mechanisms as MESFETs, only MESFETs will be examined in
this chapter.
Typical sidegating results are shown for the conventional MESFET
technology in Fig. 5.1.
A MESFET with a 50 gm gate width is first
biased to three milliamps of drain current, followed by the
application of a large negative sidegate voltage which is swept very
70
CONVENTIONAL MESFET SIDEGATING
100
W/0 ILLUMINATION
WITH ILLUMINATION
0
.
.
10
0
SIDEGATE VOLTAGE (1 V/div)
Measured drain current sidegating results with and
Figure 5.2
without illumination for the conventional MESFET of Fig. 5.1.
slowly to zero volts.
The drain current is shown as a percentage of
Ids at a sidegate voltage of 0.0 V on the vertical axis on the left.
The sidegate current is shown on the vertical axis on the right.
The
sidegate voltage which coincides with an abrupt decrease in the drain
current and an abrupt increase in the sidegate current is referred to
as the trap-fill-limit voltage (Vtfl) [48].
The Vtft corresponds to an
applied voltage which results in a rate of injection of carriers into
the substrate which exceeds the rate of emission of these carriers
from the traps in a path between two electrodes.
In this case the
71
CONVENTIONAL MESFET SIDEGATING
0.1
0.08
ca. 0.06
E
0
(f)
0.04
0.02
0.0
-2.5 V
Vcs (0.25 V/div)
0.0 V
Measured threshold voltage shift of a conventional
Figure 5.3
Vps = 2.5 V.
5.0 V.
MESFET for VsG = 0.0 V and VsG =
two electrodes are represented by the sidegate n* electrode and the
channel-substrate junction.
The result is an unpinning of the
Fermi-level and an increase in the conductivity of the material.
The sidegating effect is further aggravated by illumination
which acts to lower the substrate resistivity by generating free
carriers.
Fig. 5.2 shows measured sidegating results with and
without illumination.
With illumination, the loss of isolation
causes the drain current of the given device to decrease with
virtually zero volts applied to the sidegate electrode.
In effect
72
(X
)
(A
)
100.0
1E-05
10.00
(made
/d1v
0+00
Cr
0000
(A )
SE-05
100.0
E.-00
Idly
.
LOG
b)
LOG
a)
I0
1E-12
-10.00
vSG
1.000/div
.000
.0000
( V)
c)
IS(A
1E-12
-30.0C
VSG
1.000/01v
( V)
d)
10
)
)
ecadu
/01v
10.0
/01v
(X )
16G
(A
100.0
AE-05
100.0
E+00
1E-05
10.00
decade
/d1v
10.00
/01v
ecade
/01v
1E-12
-10.00
0000
E+00
/01vr
0000
.0000
vsG
1.000/01v
.0000
( V)
112
-10.00
VSd
1.000/01v
( V)
Measured sidegating results of a conventional MESFET
Figure 5.4
and an n+ sidegate electrode surrounded by a p-type implant for
VDS = 2.5 V and Ids(VsG=0 V) = 3.0 mA. The equivalent peak p-type
doping levels were a) 2.0 x 1016 cm-3, b) 4.0 x 1016 cm-3,
c) 8.0 x 1016 cm-3, and 16.0 x 1016 cill3.
then, the substrate now provides an effective electrical contact
between the back of the channel and the offending sidegate electrode.
In digital circuit applications, the shift in the threshold
voltage due to a sidegate electrode is important [18].
Fig. 5.3
shows the square root of drain current versus Vgs for two different
sidegate voltages.
The threshold voltage shifts 350 mV for a
sidegate voltage of 5.0 V.
Not only does this result in the shifting
of the turn on voltage of a digital gate, but it can cause a dramatic
73
ID
IBG
ID
(A
(X )
IBG
(X )
)
(A I
100.0
1E-05
100.0
E+00
1E-05
10.00
cicada
1Idly
.00
acetic
E+00
Idly
Idly
1.000/d1v
VSG
( V)
I0
I6G
(A)
)
100.0
E+00
10.00°
Idly
VSG
1.000 /div
1.000/d1v
(
V)
MG
ID
(X
(A)
)
1E-05
100.0
E+00
1E-05
'decade
Idly
10.00
Idly
scads
Idly
1E-12
.
.0000
1E-12
-10.00
.0000
-10.00
VSG
.0000
0000
1E-12
.0000
.0000
(X
Idly
-10.00
( V)
.0000
.0000
VSG
1.000/01v
lE-12
-10.00
( V(
Measured sidegating results of a buried channel MESFET
Figure 5.5
and an n+ sidegate electrode surrounded by a p-type implant for
The equivalent peak p-type
2.5 V and Ids(VsG=0 V) = 3.0 mA.
VDS
doping levels were a) 2.0 x 1016 cm-3, b) 4.0 x 1016 cm-3,
c) 8.0 x 1016 cm-3, and 16.0 x 1016 cm-3.
decrease in the speed of a digital circuit due to decreased current
drive capability.
5.2
Measurements of Sidegate Structures with Floating P-Type
Implants
In order evaluate the relative performance of p-type implants
and to optimize their usefulness, sidegate structures with different
combinations of implants were tested.
Results of samples with p-type
implants around the sidegate electrode and no p-type implants around
the MESFET are shown in Fig. 5.4.
The drain current in the sample
74
ID
1SG
ID
(X )
(X
100.0
E+00
1E-05
100.0
E+00
10.00
Idly
cicada
10.00'
/div
Idly
.0000
.0000
1E-12
VSG
ID
(x
1.000 /div
- 10.00
( V)
c)
)
I8 (A
I
100.0
E+00
10.00'
Idly
.0000
.0000
.0000
.0000
1.000/d1v
(A
)
1E-05
decado
/d1v
1E-12
.
VSG
ID (x )
- 10.00
1.000 /div
(
V)
rec
d
1E-00
100.0
E+00
1E-05
decade
/d1v
10.00
Idiv
scads
/d1v
1E-12
VSG
183
b)
)
- 10.00
(
0000
.0000
1E-12
VSG
- 10.00
1.000/d1v
(
Measured sidegating results of a buried channel MESFET
Figure 5.6
and an n+ sidegate electrode for lips = 2.5 V and Ids(VsG=0 V) = 3.0 mA.
The equivalent peak p-type doping levels were a) 2.0 x 101 cm-3, b)
4.0 x 10 16 cm-3, c) 8.0 x 1016 cm- 3, and 16.0 x 1016 cm-3.
with the lightest doping around the sidegate electrode showed
virtually no sidegating immunity.
The three samples with the higher
p-type doping showed no signs of sidegating for sidegate voltages as
high as -10 volts, although the sidegate current steadily increased
as the p-type doping increased.
Similar results have been reported
for sidegate electrodes co-implanted with p-type dopants [23].
The
addition of the p-implants can act to increase the concentration of
ionized deep levels, and consequently the concentration of traps
which act to increase Vtft.
75
:asM )
18G
b)
MI
(A )
100.0
1E-05
100.0
E+00
1E-OS
10.00
dey:te,
10.00
decade
idly
E+00
Idly
.0000
.0000
Idly
1E12
-10.00
1.000/div
VSG
( V)
ID
(X
vSG
18(
c)
)
(A)
100.0
1E-05
10.00
d scads
E+00
/01v
Idly
.0000
.0000
VSG
1.000/01v
1E-12
-10.00
( V)
.0000
.0000
1E-12
-11.00
1.000/01v
(
V)
18G
d)
ID (Si
(A )
1E-05
100.0
E+00
10.00'
/div,
decade
Idly
.0000
.0000
VSG
1E-12
-10.00
1.000/01v
( V)
Measured sidegating results of a conventional MESFET
Figure 5.7
and an n* sidegate electrode in a p-well for Vin = 2.5 V and IdS(VsG =O
V) = 3.0 mA. The equivalent peak p-type doping levels were a) 2.0 x
1016 cm-3, b) 4.0 x 1016 cm-3, c) 8.0 x 1016 cm-3, and 16.0 x 1016 crif3.
The sidegating results for an n+ sidegate electrode and a
buried-channel MESFET are shown in Fig. 5.5.
The sidegating
threshold steadily decreases for this sidegate structure as the
doping in the buried p-type layer behind the channel increases.
The
sharpness of the decrease in Ids also increases with the p-type doping
level indicating that the p-type layer is forming a much more
effective electrical contact between the sidegate electrode and the
channel of the MESFET.
76
IBG
ID
(%
(A
)
iE
E+00 \
decade
/div
4.744/div
1E-11
.0001
VSG
1.000/div
10.00
Measured forward biased p-i-n diode effects for a pFigure 5.8
well MESFET and an n+ sidegate electrode.
The sidegating results for a fully buried-channel technology are
shown in Fig. 5.6.
The sidegate structure consists of combinations
of the previous two examples; a buried channel MESFET and a p-type
implant around the n+ sidegate electrode.
The sidegating results
improve steadily as the p-type doping level increases.
The sample
with the highest level of p-type doping showed only a two percent
decrease in drain current for a sidegate voltage of -10 V with no
noticeable increase in the sidegate current.
77
ID
o)
(X
VSG
1.000/dlY
113G
(A
iE-05
1E00.+00
0
acade
Idly
10.00
Idly
1E-12
-10.00
SSG
(A)
100.0
1E-05
10.00
d scads
E+00
/d1v
Idly
.0000
.0000
VSG
1.000/d1v
(X I
1E-12
-10.00
( V)
I(30
(A
)
iE-05
cicada
/01v
1E-12
.0(1800
VSG
( V)
c)
b)
10
)
/0
1.000 /div
10.00
( V)
d)
(X)
100.0
E+00
10.00'
idly
;decade
/d1y
.0000
.0000
VSG
1.000/d1v
1E-12
-10.00
( V)
Measured sidegating results of a buried channel MESFET
Figure 5.9
and an 6+ sidegate electrode in a p-well for Vps = 2.5 V and
The equivalent peak p-type doping levels were
Ids(Vse0 V) = 3.0 mA.
a) 2.0 x 1016 cm-3, b) 4.0 x 1016 cm-3, c) 8.0 x 1016 cm-3, and
16.0 x 1016 cm-3.
5.3
Measurements of Sidegate Structures with Contact to the P-Type
Implants
The buried-channel MESFETs showed the ability to improve as well
as degrade the sidegating of GaAs MESFET technology.
However,
similar or greater improvements should be observed for the p-well
MESFETs.
The results for a sidegate structure consisting of a
conventional MESFET and an n+ electrode in a p-well are shown in Fig.
5.7.
The results are similar to the results shown in Fig. 5.4 above,
with only the sample with the lowest p-type doping showing any
78
IBG
ID
(X)
(A )
a)
1E-05
100.0
E+00
decade
/div
10.00/dim_
.0000
.0000
ID
.
...._
VSG
(X )
1E-12
10.00
1.000 /div
( V)
IBG
(A )
b)
100.0
E+00
1E-05
10.00/d1v.
.0000
.0000
ID
1E-12
VSG
2.000/div
20.00
( V)
(X )
IBG
(A )
.0000
.0000
1E-12
VSG
2.000/d1v
20.00
( V)
Measured sidegating results of a p-well MESFET and an
Figure 5.10
n+ sidegate electrode in a p-well for Vps = 2.5 V and
The equivalent peak p-type doping levels were
Ias(VsG=0 V) = 3.0 mA.
a) 2.0 x 1016 cm-3, b) 4.0 x 1016 cm-3, c) 8.0 x 1016 cm-3, and
16.0 x 1016 cm-3.
79
18G
a)
IG
(X )
1E-05
100.0
E+00
150
/0
(A
(A
(x
)
1E-05
100.0
E+00
ccade
/01v
1E-12
-20.00
.0033
.0000
2.000/U1v
VSG
180
c)
IO
(X )
.0000
0000
( V:
CA )
1E-12
-10.00
vSG
1U
1.000/01v
(
v)
ISO
d)
(% )
(A ;
100.0
E+00
1E-05 100.0
1E-05
10.00
decade 10.00
/d iv
/d1v
facade
/0 iv
E+00
.0000
.0000
VSG
-- 1E-12
-20.00
2.000/01v
( V)
--
0000
.0000
VSG
1.000/01v
1E-12
-10.00
( V)
Measure sidegating results for various sidegate
Figure 5.11
a) Conventional MESFET and
structures with and without illumination.
an n+ sidegate electrode surrounded by a p-type implant, b) buried
channel MESFET and an n+ sidegate electrode surrounded by a p-type
implant, c) conventional MESFET and an n+ sidegate electrode in a ptype well, d) buried channel MESFET and an n+ sidegate electrode in a
p-type well.
sidegating.
This technique should be more resistant to sidegating
than the structure of Fig. 5.4 since the zero biased pn junction
insures that no electrons are injected into the substrate to fill the
traps.
In the case of the floating pn junction, the junction can
forward bias to supply current to the substrate and fill the traps.
One of the greatest dangers of using p* contacts is the
potential to forward bias p-i-n diodes.
This is illustrated by the
results for a p-well MESFET and an n+ sidegate electrode shown in
80
PWELL MESFET SIDEGATING
g
100
105
80
106
WITH ILLUMINATION
W/0 ILLUMINATION
109
0
10-10
-20
0
SIDEGATE VOLTAGE (2 V/div)
Measured sidegating result for the P-well MESFET
Figure 5.12
technology with and without illumination.
Fig. 5.8.
Such a configuration can be disastrous and should be
avoided at all costs.
The sidegating results for a buried-channel MESFET and an n*
electrode in a p-well are shown in Fig. 5.9.
similar to the results of Fig. 5.6.
These results are very
The sidegate current remains low
for all the samples with higher sidegate thresholds.
The sample with
the highest p-type doping decreased by approximately two percent at
VSG = -10 V.
The sidegating results which represent the complete p-well
technology are shown in Fig. 5.10.
The sample with the lowest p-type
doping level is not shown since it exhibited the forward biased p-i-n
diode behavior which is the result of the p-type doping being to low
81
to from a well defined p-type region around the n+ region.
The
sample with a peak p-type doping of 8.0 x 1016 cm-3 showed no
measurable decrease in the drain voltage.
Even for a sidegate
voltage of -20 V and a 3 Am sidegate electrode to source gap.
The
sample with the highest p-type doping showed what appears to be
punch-through effects.
For the implant doses and the implant species
(Be), this is not surprising.
Be has a much greater implant side-
straggle than Si, and for high concentrations it can diffuse quite
readily.
These conditions may be present for these doping levels
leading to a much narrower effective sidegate-to-source electrode
spacing.
The best results were examined more closely to determine their
resilience to adverse conditions.
The effects of illumination were
shown to adversely effect the sidegating results of conventional
MESFET sidegate structures.
Fig. 5.11 shows the sidegate results for
the samples of some of the previous test structures under
illumination.
The
samples with the conventional MESFET and sidegate
electrode surrounded by a p-type implant showed the greatest immunity
to sidegating.
The sample with the p-well sidegate electrode showed
no change even for a -20 V sidegate bias.
However, such a
configuration my not be practical since care would still have to be
taken to insure that the p+ contact did not form a p-i-n diode with a
nearby n+ contact.
The two samples with the buried-channel MESFET
essentially shorted out when the light was turned on.
The p-layers
behind the channel and the photogenerated carriers allowed the
formation of an efficient backside contact to the channel of the
82
MESFET.
The effectiveness of the p-well technology under
illumination is illustrated in Fig. 5.12.
Even though the sidegate
current increased by two orders of magnitude, the drain current
failed to decrease by any measurable amount.
5.4
Summary
The sidegating behavior of a number of sidegate structures has
been examined to determine the optimum combination of implants.
The
immunity of the p-well MESFET technology to sidegate voltages of -20
V with no decrease in the drain current even under illumination is
further evidence that control of the channel-substrate interface is
of the utmost importance in GaAs technology.
In addition, the hazard
of forward biased p-i-n diodes were illustrated, and degradation of
sidegating in buried-channel MESFET structures was demonstrated.
83
6.
RF CHARACTERISTICS
The RF performance of p-well MESFETs and a suitable small-signal
equivalent circuit model which accounts for the well capacitance and
well contact resistance are examined in this chapter.
The dependence
of the equivalent circuit parameter values, unity current gain (fT),
maximum frequency of oscillation (fmax), and maximum available gain
(MAG) on the p-well doping is examined.
When compared to control
samples with no p-type implants, the p-well devices offer comparable
RF performance.
6.1
Equivalent Circuit Model
The small-signal equivalent-circuit modeling is an extension of
existing, widely-used models with additional elements added to
account for the constrained p-well.
The number of additional
elements was minimized to maintain reasonable accuracy, simplicity,
and direct correspondence between the model and the physical device.
This correspondence is illustrated in the cross-sectional view of the
p-well MESFET shown in Fig. 6.1.
In this cross-sectional view, the
depletion regions between the n +- drain -to -p -well and n-channel-to-p-
well is shown conceptually along with the associated equivalent
circuit elements.
The greatest reduction in the drain current transients,
frequency dispersion in gds, and sidegating are realized when the p-
well is doped sufficiently high so that the p-region under the
channel is never completely depleted.
This corresponds to a
conductive p-type region constrained to the source potential via the
84
PWell
LEC SI GaAs Substrate
Cross-sectional view of a p-well MESFET conceptually
Figure 6.1.
illustrating the depletion regions associated with the pn junctions
and the conductive path to the source of the p-type region under the
channel.
p' contact and which is modeled with the resistor R.
The
capacitances between the p-well and n"-drain and n-type channel
regions are conveniently lumped into a single capacitor Cp.
For the
complete equivalent circuit model (Fig. 6.2), it is shown that C, and
Rp in series form a branch in parallel with the Rd, and Cd, branches
between the drain and source [4].
It is interesting to note that an
RC branch is also commonly used to empirically model the lowfrequency g d, frequency dependence.
The main difference here is that
the RC branch in Fig. 6.2 is also in parallel with Rsc and Rdc, the
parasitic source- and drain-channel resistances.
Another difference
85
Small-signal equivalent-circuit model used for the pFigure 6.2.
well GaAs MESFET.
is that Rp and C, are process dependent because their values are
controlled by implant doses.
In this equivalent circuit model, Rp is
determined by the implant dose and energy while C, is a junction
capacitance which is easily calculated.
By contrast, in modeling the
frequency dependence of gds with an RC branch for a conventional
MESFET, the values of R and C depend on the details of the defect
compensation in the substrate material.
This dependence on substrate
defects makes it difficult to predict the circuit element values
initially, and to account for process variations in their values.
6.2
S-Parameters
This expression for the output impedance of the p-well MESFET is
obtained from the equivalent circuit of Fig. 6.2.
Since
Rds
and Rp
86
P-WELL DOPING DEPENDENCE OF S21
20
0,2,4 X 10
16
cm
-3
1166,
5
16
x
1016
1111
0
10-1
I
C r11
I
3
114
8
x
1016cm
-3
PI
I
100
102
101
FREQUENCY (GHz)
S21 responses for the p-well MESFETs with different nFigure 6.3.
The sweeps are for bias voltages
channel and p-well doping levels.
of Vps = 3.0 V and VGs = 0.0 V.
are much greater than Rs and Rd the output impedance can be
approximated as the series RC branch in parallel with Rds.
This
introduces a pole-zero pair in the frequency response of the output
impedance of the p-well MESFET given by,
1 + sR PC P
Zds S
(6.1)
= Rds
1 + sCp(Rds + Rp)
At low frequencies, the magnitude of Zds = Rds and starts to decrease
at the pole frequency (1/27(Cp(Rds + Rp)).
Zds begins to level off at
the zero frequency, (1/2ffRpCp) and is just the parallel combination of
87
0,2,4 X 10
-3
16
cnn
S22 responses for the p-well MESFET's with different
Figure 6.4.
The sweeps are for bias voltages of %fps = 3.0 V
p-well doping levels.
and VGs = 0.0 V.
Rd, and Rp at high frequencies. In some cases the effect of this
doublet can be observed in the S21 frequency response of the MESFET as
shown in Fig. 6.3.
For the MESFETs with a peak p-well doping of 8.0
and 16.0 x 1016 cm-3, the zero is clearly observable while the pole is
at a lower frequency than could be measured accurately with the
network analyzer.
The effects of Rp and C, are also evident when S22
is plotted on a Smith chart in Fig. 6.4.
As in Fig. 6.3, there is
little effect for peak p-well dopings less than 8.0 x 1016 cm-3.
For
peak p-well dopings of 8.0 and 16.0 x 1016 cm-3 however, there is a
considerable shift in S22 consistent with a decrease in the output
88
0.95
Cgs
0.90
0.85
0.80
0.75
0.10
0
ili
0.05
Cgd
0.00
0
2
4
6
1
I
I
8
10
12
14
16
PEAK PWELL DOPING (1016 cm-3)
C gs and C gd as a function of p-well doping levels for
Figure 6.5.
bias voltages of Vos = 3.0 V and VGs = 0.0 V.
impedance due to the parallel combination of Rds and Rp at high
frequencies.
The magnitudes of Rp and Cp depend primarily on the p-well
doping.
C, is also strongly dependent on the voltage applied to the
drain while the applied voltages have only a minor effect on Rp.
The
p-well doping may also effect the relative magnitudes of some of the
other parameter values.
An evaluation of the equivalent circuit
parameter values provides the information necessary for optimization
of the p-well technology so that both satisfactory high frequency
performance is achieved while maintaining the aforementioned benefits
of junction isolation.
89
100
(1)
E
800
<
0
60
400
0
cn
0
0
A
A
0
0
O
V
V
0
V
V
V
V
V
GS
GS
GS
GS
=0.5 V
=0.0 V
=-0.5 V
=-1.0 V
20
F-
0
0
2
4
6
8
10
12
14
16
PEAK PWELL DOPING (1016 cm-3)
Small-signal gm values versus p-well doping levels at
Figure 6.6.
several different VGs bias voltages. lips = 3.0 V.
Small-Signal Parameters
6.3
High frequency operation is most often characterized by fT, the
frequency of unity-short circuit current gain.
In general, fT can be
expressed in terms of the small-signal parameter values as,
gm
(6.2)
fT
27b.f(Cgs2 + 2CgsCgd)
where, Cgs is the gate-source capacitance, C9d is the gate-drain
feedback capacitance and gm is the small-signal transconductance.
Cgs
and C9d are shown as a function of peak p-well doping in Fig. 6.5.
Because the pn junction capacitances are between the undepleted pwell and the n-channel and n' drain, no significant increase in Cgs or
C9d is observed with doping.
Cgs does increase slightly as the well
90
500
400
A
,O,
A
DI
e--%
C 3000
.....
A
Q
1.0 V
VGS
VAS = -0.5V
3
0
03
Z 200
3
VGS = 0.0 V
VGS = 0.5 V
100
0
'
0
2
I
I
I
I
,
I
4
6
8
10
12
14
16
PEAK PWELL DOPING (1016 cm-3)
Small-signal Rds values versus p-well doping levels at
Figure 6.7.
several different VGs bias voltages. Vps = 3.0 V.
doping increases. However, this is due to the combined effects of
slightly different channel profiles and different amounts of gate
recess used to maintain equal Vp's for the different wafers.
In Fig. 6.6, the RF gm is shown for different gate voltages as a
function of p-well doping.
It is interesting to note that as the p-
well doping increases, gm actually increases slightly.
This
increased gm effect is beneficial to fT by acting to partially counter
the effects of the increasing Cgs.
Another parameter used for
characterizing high frequency operation is fmax
fmax is the frequency
at which the maximum available gain becomes one and therefore, should
have similar dependence on the equivalent-circuit element values.
commonly used expression for MAG is given as [49];
A
91
DRAIN TO PWELL CAPACITANCE
2.5
O
2.0
A
=lV
V DS
2 V
VDS
V
= 3 V
DS
4 V
VDS
4-
1.5
0
1 .0
V
0.5
8
a_
O
V DS
= 5 V
0.0
0
2
4
8
6
10
12
14
16
PEAK PWELL DOPING (1016 cm-3)
Small-signal C. values versus p-well doping levels at
Figure 6.8.
several different Vps bias voftages. VGS = 0.0 V.
1
(fr)2
(6.3)
MAG(f)f
(4/Zds+47rfTCgd)(Rg+Ri+R.+27rfTL.)+4fffTCgdRg
where Zds is the expression given in (6.1) and replaces Rd, in the
usually expression.
For low p-well doping levels, Rds gradually
increases as the p-well doping increases (Fig. 6.7) which is
consistent with the tighter confinement of the channel carriers
provided by the p-well.
The apparent decrease in Rds at a well doping
of 16.0 x 1016 cm-3 is apparently a limitation of the accuracy of the
data.
At this well doping, the pole is at such a low frequency that
92
105
104
a
%Of
0C:
103
102
0
2
4
6
8
10
14
12
16
PEAK PWELL DOPING (1 016 cm-3)
Small-signal Rp values versus p-well doping levels for
Figure 6.9
bias voltages of Vps = 3.0 V and VGs = 0.0 V.
it cannot be resolved using the network analyzer, and consequently
the value of Rds cannot be accurately determined.
The variation of the elements RP and Cp with well doping are
shown in Figs. 6.8 and 6.9. In Fig. 6.8, Cp is shown for different Vps
bias values.
The voltage dependence of the junction capacitance is
visible in the samples with the higher well dopings.
In particular,
the sample with 8.0 x 1016 cm-3 well doping shows a strong voltage
dependence.
For this sample, the depletion region has most likely
reached through the p-well into the undoped substrate.
R
P
in Fig. 6.9 decreases as the well doping increases.
As expected,
The values
for Rp and Cp at the lower dopings should be taken as good
93
Table 6.1 Equivalent-circuit small-signal element values
for the different p-well doping levels. The values are for
MESFETs with lgm gate lengths and 300 gm gate widths and
bias voltages of kips = 3.0 V and VGs = 0.0 V.
EQUIV.
CKT.
PRAM.
PEAK P-WELL DOPING LEVEL ( X 1016 cm-3)
0.0
2.0
4.0
8.0
gm (mS)
57.56
59.45
60.56
63.01
65.93
Tt (pS)
1.64
1.89
1.94
1.62
0.84
Cgs (fF)
772.12
797.45
818.91
871.30
887.28
Cgd (fF)
84.65
81.06
74.84
80.03
76.31
Cds (fF)
83.75
86.25
89.65
99.65
132.29
Cp (fF)
85.66
319.71
377.72
512.30
2356.42
Rd, (0)
280.76
298.64
301.72
190.45
109.92
Rp (0)
11.0
2.66
2.15
0.52
0.22
2.22
1.72
1.52
0.80
Rip (Q)
Rgs (0)
2.55
101
101
100
100
16.0
104
Rsc (Q)
1.16
2.36
2.67
2.94
4.00
Rdc (Q)
0.75
0.63
0.01
1.13
5.19
Rs (Q)
0.01
0.02
0.02
0.03
0.02
Rd (Q)
0.01
0.00
0.05
0.13
0.25
Rg (Q)
0.01
0.01
0.01
0.11
0.01
Ls (pH)
1.25
1.03
0.94
0.96
0.71
Ld (pH)
1.10
1.09
0.97
1.03
0.92
Lg (pH)
26.25
16.06
14.23
18.78
14.85
94
50
40
m
-o
30
....
20
N
=
10
0
109
1010
1011
FREQUENCY (GHz)
1H211 versus frequency for a conventional MESFET with
Figure 6.10.
bias voltages of lips = 3.0 V and VGs = 0.0 V.
approximations which result in a satisfactory fit between the modeled
and measured S-parameters.
However, the trends do indicate the degree
of control over these element values available with this technology.
As
indicated by the equation for MAG, other small-signal parameters are
also important for high frequency performance.
These small-signal
parameter values are summarized in Table 6.1 for the five wafers tested.
6.4
fT, fm, and MAG
The definition of fT given above is just the parameter values which
result in 1H211 = 1 for the equivalent circuit model of the
95
14
13
10
9
2
0
4
6
8
10
12
14
16
PEAK PWELL DOPING (1016 cm-3)
Small-signal fT values versus p-well doping levels for
Figure 6.11.
bias voltages of lips = 3.0 V and VGs = 0.0 V.
MESFET.
However, H21 can be calculated directly from the S-parameters
and fT determined for the frequency at which H21 = 1 as shown in
Fig. 6.10. The slope of the line which has been drawn through H21 is
fixed at 6 dB/octave and fT is determined from frequency at which the
magnitude of H21 = 1.
shown in Fig. 6.11.
The dependence of fT on the well doping is
As expected, based on variations in the small-
signal parameter values, variation in fT is small. In fact, fT
decreases less than 10 percent for the most heavily doped p-well
sample as compared to the control sample.
The maximum available gain of the MESFET was also calculated
from the S-parameters at 10 GHz and is shown in Fig. 6.12 for
96
25
CONTROL WAFER
CD
0
20-
©
o
<
15
1
0
2
I
I
I
I
I
I
4
6
8
10
12
14
16
PEAK PWELL DOPING (1016 cm-3)
Maximum Available Gain (MAG) values versus p-well doping
Figure 6.12.
levels for bias voltages of %fps = 3.0 V and VGS = 0.0 V.
different peak p-well dopings.
A much stronger dependence on the well
doping is apparent for MAG than for fr. This is expected based on the
strong dependence of MAG on the output characteristics of the MESFET.
However, the only sample with a marked decrease in the MAG is the sample
with the highest p-type doping behind the channel as shown in Fig. 6.11.
The sample with a well doping of 8.0 x 1016 cm-3 shows only a small
decrease in MAG.
fmax is the frequency at which MAG becomes one.
extrapolating MAG to the frequency at which MAG = 1.
fr. is obtained by
Since finx is
extracted from MAG it is expected to exhibit much the same dependence on
the p-well doping as MAG.
This is confirmed in Fig. 6.13 which
97
40
.0"
N
0
x
30
4E
20
0
2
4
6
8
10
12
16
14
PEAK PWELL DOPING (1016 cm-3)
Small-signal fr. values versus p-well doping levels for
Figure 6.13.
bias voltages of lips = 3.0 V and VGs = 0.0 V.
shows that the samples with the more heavily doped p-well are adversely
affected.
6.5
Summary
The RF characteristics of a p-well GaAs MESFET technology have been
presented and are shown to be comparable to conventional MESFETs.
In
spite of the heavily doped p-type region behind the channel and the
large increase in capacitances on the drain, there is only minimal
degradation in the performance of the devices.
Furthermore since the
additional pole and zero in the frequency response of the output
characteristics are the result of an implanted pn junction capacitance
98
and a p-region conductance, the positions of the pole and zero can be
set by appropriate modification of the implant parameters.
99
7.
LIMITATIONS AND TRADEOFFS
The results presented thus far offer compelling evidence that
the p-well MESFET technology is superior to the conventional MESFET
technology in many resects.
However, as with many technological
advances there are tradeoffs which must be considered.
In this
chapter some of the tradeoffs mentioned in the previous chapters are
reviewed and some limitations which have not yet been examined are
discussed.
7.1
Introduction
Perhaps the most obvious concern which comes to mind is the
potential for additional capacitance due to the undepleted p-type
well.
As was shown in chapter 6 the well doping can be adjusted to
minimize parasitic capacitances while maintaining electrical control
of the channel-substrate junction.
Further reductions can be
achieved by modifying the drain and source n+ implants.
By lowering
the implant energy, thereby decreasing the implant range and tail, it
should be possible to maintain electrical contact with the channelsubstrate junction for lower peak p-type implant levels than was
possible with the devices fabricated in this work.
Another draw back examined in chapter 5 concerns the need to
avoid independently biased p-type and n-type regions with semiinsulating GaAs in between.
Forward biasing of the resulting p-i-n
diode yields unacceptably large leakage currents.
In addition to these concerns, there are other potential
problems which deserve scrutiny.
The effects examined in this
100
IDS
CmA)
25. 00
2. 500
/div
a)
VOS
. 5000/div
( V)
VOS
. 5000/d i v
( V)
5. 000
IDS
CmA)
25. 00
2. 500
/div
b)
.
0000
5. 000
Drain I-V characteristics for the p-well MESFET with the
Figure 7.1
p-well tied to the source a) and the p-well tied to the drain b).
The maximum VGS = 0.75 V and the step size is 0.25 V.
101
IDS
C A)
1E-01
decade
/d iv
1E-09
-4.800
VGS
.6000/div
0 .6000
C V)
Subthreshold characteristics for the p-well MESFET with
Figure 7.2
The upper
the p-well extending outside the channel under the gate.
curve is lips = 5.0 V and the step size is 2.0 V.
chapter are illustrated with DC data, and include drain I-V as well
as gate I-V and transconductance data.
7.2
Drain Characteristics
Perhaps the most obvious concern with the p-well technology
examined in this study is the need to insure that the drain and
source do not become interchanged.
If the source electrode becomes
more positive than the drain then the drain-p-well pn junction will
forward bias.
This is illustrated in Fig. 7.1 where, Fig. 7.1 a)
shows the normal drain I-V curves and Fig. 7.1 b) shows the result of
switching the drain and source.
For larger drain voltages the
forward biased pn junction current dominates the channel current.
102
For operation in the linear regime and small drain bias in saturation
this isn't a significant problem since the parasitic pn diode current
is negligible compared to the channel current.
Another important consideration is the subthreshold current, or
the channel current when the MESFET is turned off.
The subthreshold
current for one of the p-well MESFET configurations is shown in Fig.
7.2.
This device is completely enclosed in a p-type tub and shows
good subthreshold characteristics with several orders of magnitude of
exponential decay of the drain current before the gate-drain leakage
However, as pointed out in section
current begins to dominate.
2.2.2, the MESFET gate extends beyond the n-channel over the
surrounding GaAs.
For the results of Fig. 7.2, there is gate metal
in contact with both n- and p-type GaAs.
Therefore, when the gate
voltage reverse biases the Schottky to n-channel region it is forward
biasing the p-type region.
This can result in large gate leakage
currents which are discussed in the following section.
One possible
solution is to pull the p-type implant inside the n-type channel
implant as shown in Fig. 2.5.
The subthreshold characteristics are
summarized in Fig. 7.3 for p-type implants coincident with the nchannel and pulled in one micron.
In addition, the RF MESFETs which
had the p-type implants pulled in 1/2 micron and are also shown.
As
the p-well is pulled inside the n-channel along the edges, the
subthreshold characteristics steadily degrade.
This degradation is
simply related to the lack of any p-type implants along the outer
edges of the channel, resulting in portions of the channel with a
more negative pinch-off voltage than the central portion.
103
IDS
( A)
01
1
decode
/d1v
a)
1E-09
- 4. 800
0 .8000
VGS
.8000/d1v
( V)
VGS
.8000/d1v
( V)
VGS
.8000/d1v
( V)
IOS
C
1E-01
decode
/d1v
b)
1E-09
- 4.800
O .8000
IOs
( 111
1E-01
decode
/d1v
c)
1E-09
O .8000
- 4.800
Subthreshold characteristics for the p-well MESFET with
Figure 7.3
the p-well a) coincident with, b) pulled in 1/2 micron from, and c)
pulled in one micron from the edge of the channel under the gate.
The upper curve is Vps = 5.0 V and the step size is 2.0 V.
104
IG
)
1E-02.
decode
/dIv
a)
1E -09-
-9. 900
.0000
VGS
1.100/div
V)
VGS
1.100/dIv
V)
VGS
1.100/dIv
IG
)
1E-02
decode
/dIv
b
1E-09
-9.900
.0000
IG
CA )
1E-02
decode
/div
c)
1E-09
-9.900
.0000
C V)
Gate I-V characteristics for the p-well MESFET with the
Figure 7.4
p-well a) pulled out one micron from, b) coincident with, and c)
pulled in one micron from the edge of the channel under the gate.
VDS = 2.5 V.
105
GM
CMS)
15.00
E*00
1.500
/d1v
a)
0000
-2. 450
VGS
0
.3500/d1v
0
.
VGS
.3500/d1v
C V)
.
7000
C V)
GM
CMS)
15.00
E+00
1.500
/d1v
0000
-2.450
7000
GM
CMS)
15.00
E+00
1.500
/d1v
CJ
0000
-2.450
VGS
0
.3500/d1v
. 7000
V)
Transconductance for the p-well MESFET with the p-well
Figure 7.5
a) pulled out one micron from, b) coincident with, and c) pulled in
Vos = 2.5 V.
one micron from the edge of the channel under the gate.
106
7.3
Gate Characteristics
As mentioned in the previous section, gate metal lying on the
p-type GaAs can result in high leakage currents (Fig. 7.4).
For the
MESFET with the p-type region extending outside the n-channel the
reverse gate leakage is very high.
It should be pointed out that
this is gate-source current via the p-well contact at the source and
not gate-drain current which is very small as illustrated by the good
subthreshold characteristics of Fig. 7.2.
As the p-type material is
pulled inside of the n-channel, the reverse leakage improves
considerably.
One other gate characteristic of importance is the
transconductance which is shown in Fig. 7.5 for the three different
p-well MESFET structures.
The sample with the p-well extending
outside the n-channel has a 'bump' in its shape near VGs=0.0 V.
This
is the result of the forward biased gate to p-type material providing
a small amount of channel modulation through the pn channel-p-well
junction.
When the gate-channel Schottky barrier is reversed biased
the gate-p-well Schottky barrier is forward biased.
This allows the
gate to reverse bias the channel from below the channel.
While most
of this action is shunted by the p-well contact to the source it does
provide some parasitic gating of the p-well MESFET.
As the p-well
implant is pulled inside the channel the effect disappears.
7.4
Summary
In addition to the tradeoffs illustrated in chapter 6 there are
several others that must be considered in the p-well MESFET
technology.
These are primarily associated with the need to prevent
107
the gate Schottky metal from contacting the well.
Pulling the p-well
inside the channel along the edges as illustrated in Fig. 2.5 helps
to reduce high gate leakage currents and parasitic gating of the
channel by the p-well.
However, it leaves a portion of the channel
with a more negative pinch-off voltage which leads to poor
subthreshold characteristics.
108
8. CONCLUSIONS
Various anomalous effects in conventional GaAs MESFETs have been
Failure
shown to arise from the floating channel-substrate junction.
to confine the potential of this junction allows variations in the
charge state of defects in the substrate to modulate the behavior of
the MESFET.
This has been shown to lead to drain current transients
with long time constants, frequency-dependent output conductance, and
sidegating in GaAs MESFETs.
Understanding the mechanisms responsible
for these anomalous effects has motivated the development of a p-well
MESFET technology which electrically confines the channel-substrate
junction potential to the source potential.
The p-well MESFET
eliminates the drain current transients with long time constants and
offers promise of a technology that is better suited for the design
of precision analog and digital circuits in GaAs.
Significant
reduction in the settling time of amplifiers and switches, reduction
in hysteresis in differential circuits and comparators, and reduction
in frequency- and pattern-dependent propagation delay times are just
some of the potential benefits possible with these improved device
characteristics.
That the p-well technology also demonstrated
immunity to sidegate voltages in excess of -20 V with no decrease in
the drain current even under illumination, is further evidence that
control of the channel-substrate interface is of the utmost
importance in GaAs technology.
In spite of the heavily doped p-type region behind the channel
and the large increase in capacitances on the drain, there is only
minimal degradation in the RF performance of the devices.
109
Furthermore, since the additional pole and zero in the frequency
response of the output characteristics are the result of an implanted
pn junction capacitance and a p region conductance, the positions of
the pole and zero can be set by appropriate modification to the
implant parameters.
The results presented in this thesis open up broad avenues of
potential research opportunities.
One of the more obvious would be
the implementation of analog and digital building blocks to begin
quantifying improvements in circuit performance.
The presence of
independent p-type implants and p-ohmics should allow for the
development of a technology with a complementary devices as well.
Complementary devices may be particularly useful in level shifting
applications, replacing large stacks of diodes.
In the general area
of technology development, there are some potential advantages to be
gained from an epitaxial based equivalent to the p-well MESFET.
As
demonstrated in chapter 7, care must be taken to avoid contacting the
p-well with the gate metal.
While this reduces the gate leakage
currents and parasitic gating of the channel by the p-well, this
results in poor pinch-off and subthreshold characteristics due to the
channel n-type implant not being coimplanted with p-type material at
the edges of the channel.
The mask set used for this study is ideal for the investigation
of many device phenomena which might be impacted by the material.
Stress-induced piezoelectric charges, 1/f noise, gate transients,
frequency-dependent transconductance, and low frequency oscillations
110
are all properties which could potentially be impacted by the
presence of p-type implants and bare further scrutiny.
Extension of the device modeling outlined in chapters 3 and 4
could lead to a combined large-signal, small-signal, and DC model
capable of modeling frequency- and pattern-dependent delay times,
provided the transient overshoot term can be better quantified.
111
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APPENDIX
119
A.
PUBLICATIONS
The work contained in this thesis has resulted directly in a
number of publications.
Additionally my graduate studies have
resulted in several publications which are only peripherally related
to the central topic of this thesis; many of them arising from
collaboration with other students and professionals in industry.
They are compiled below for those interested in a full accounting of
my contribution to the general body of GaAs technology knowledge
during my years in graduate school.
A.1
Journal Publications
1.
P. Canfield and L. Forbes, "Gate bias dependent low frequency
oscillations in GaAs MISFETs," IEEE Electron Device Lett., vol.
EDL-6, no. 5, pp. 227-228, May, 1985.
2.
P. Canfield and L. Forbes, "Suppression of drain conductance
transients, drain current oscillations and low-frequency
generation-recombination noise in GaAs FET's using buried
channels," IEEE Trans. on Electron Devices, vol. ED-33, no.
7,
pp. 925-928, July, 1986.
3.
P. Canfield, J. Medinger, and L. Forbes, "Buried channel GaAs
MESFETs with frequency independent output conductance," IEEE
Electron Device Lett., vol. EDL-8, no.3, pp. 88-89, Mar., 1987.
120
4.
P. Canfield and L. Forbes, "Buried channel GaAs MESFETs with
immunity to ionizing optical radiation effects," IEEE Electron
Device Lett., vol. EDL-8, no.3, pp. 113-115, Mar., 1987.
5.
P. Canfield and L. Forbes, "Lateral n-p-n bipolar transistors by
ion-implantation into semi-insulating GaAs," Solid State
Electronics, vol. 31, no. 1, pp. 123-125, Jan., 1988.
6.
H.C. Yang, P.C. Canfield, and D.J. Allstot, "A one transistor
GaAs voltage reference circuit," Electronics Letters, vol. 25,
no. 7, pp. 464-465, 1989.
7.
P.C. Canfield, S.C.F. Lam, and D.J. Allstot, "Modeling of
frequency and temperature effects in GaAs MESFETs," IEEE Journal
of Solid-State Circuits, vol. 25, no. 1, pp. 299-306, Feb.,
1990.
8.
W. MicKanin, P.C. Canfield, E.P. Finchem, and B. Odekirk,
"Transients in GaAs MESFETS: Process, geometry, and material
effects," EURO III-Vs Review, vol. 3, no. 1, pp. 22-25, Feb.,
1990.
9.
P.C. Canfield and D.J. Allstot, "A p-well GaAs MESFET technology
for mixed-mode applications," IEEE Journal of Solid-State
Circuits, accepted for publication, vol. 25, no. 6, Dec. 1990.
10.
L.L. Peng, P.C. Canfield, J.R. Arthur, and D.J. Allstot, "Trap
effects on p-channel GaAs MESFETs: A temperature dependent drain
121
current transient study," Submitted to the IEEE Trans. Electron
Devices.
11.
P.C. Canfield and D.J. Allstot, "A p-well MESFET Technology for
multifunction MMIC's,"
Submitted to the IEEE Trans. Electron
Devices.
12.
P.C. Canfield and D.J. Allstot, "Sidegating in GaAs MESFETS with
p-type implants and its elimination using a p-well technology,"
IEEE Trans. Electron Devices, to be submitted.
13.
P.C. Canfield and D.J. Allstot, "Substrate contribution to drain
current transients and frequency-dependent output conductance on
GaAs MESFETs," IEEE Trans. Electron Devices, to be submitted.
14.
P.C. Canfield and D.J. Allstot, "The impact of p-type implants
on the drain current transients and output conductance in GaAs
MESFETs," IEEE Trans. Electron Devices, to be submitted.
A.2
Conference Publications
1.
L. Forbes, P. Canfield, R. Gleason and A. McCamant, "Lowfrequency noise in GaAs FETs," Proc. 3rd Semi-Insulting III-V
Materials Conf.: Kah-Nee-Ta, D. C. Look and J. S.
Blakemore;
eds., Natwich, UK: Shiva Pub., pp. 392-396, 1984.
2.
L. Forbes, P. Canfield, R. Gleason, and A. McCamant, "Seperation
of generation-recombination noise and 1/f noise components on
GaAs FETs," Abstracts of the 1984 Device Research Conf., IEEE
122
Trans.
Electron Devices, vol. ED-31, no. 12, pp. 1986, Dec.,
1984.
3.
P. Canfield, L. Forbes, R. Gleason, and A. McCamant, "Drain
current transient suppression in buried channel GaAs MESFETs,"
Proc. 4th Semi-Insulating III-V Materials Conf.: Hakone, H.
Kukimoto and S. Miyazawa; eds., Tokyo: Ohmsha, LTD. and
Amsterdam: North-Holland Publ. Co., pp. 573-578, 1986.
4.
P. Canfield, L. Forbes, R. Gleason, and A. McCamant,
"Suppression of deep level trapping related effects in GaAs
MESFETs using a buried channel structure," Abstracts of the 1986
Device Research Conf., IEEE Trans. Electron Devices, vol. ED-33,
no. 11, pp.
5.
1851, Nov., 1986.
L. Forbes and P. Canfield, "Suppression of deep level trapping
related effects in GaAs MESFETs using a buried channel
structure," GaAs REL WORKSHOP abstracts, paper 1-2, 1986.
6.
P.C. Canfield, J. Medinger, D.J. Allstot, L. Forbes, A.J.
McCamant, W.A.
Vetanen, B. Odekirk, E.P. Finchem, and K.R.
Gleason, "High speed quarter micron buried channel MESFETs with
improved output characteristics for analog applications,"
IEEE/Cornell Conference Proceedings, pp. 247-254, 1987.
7.
P. C. Canfield, D. J. Allstot, J. Medinger, L. Forbes, A. J.
McCamant, W. A. Vetanen, B. Odekirk, E.P. Finchem, and K. R.
Gleason, "Buried channel GaAs MESFETs with improved small-signal
123
characteristics," IEEE GaAs IC Symposium Technical Digest, pp.
163-166, 1987.
8.
H.C. Yang, P.C. Canfield, and D.J. Allstot, "GaAs buried channel
MESFET analog integrated circuits," Proc. of the IEEE Inter.
Symp. on Circuits and Systems, pp. 1607-1610, 1988.
9.
E.P. Finchem, W.A. Vetanen, B. Odekirk, and P.C. Canfield,
"Reduction of the backgating effect in GaAs MESFET ICs by charge
trapping at the backgate electrode," IEEE GaAs IC Symposium
Technical Digest, pp. 231-234, 1988.
10.
S.C.F. Lam, P.C. Canfield, A.J. McCamant, and D.J. Allstot,
"Analytical model of GaAs MESFET output conductance," IEEE GaAs
IC Symposium Technical Digest, pp. 203-206, 1988.
11.
D.J. Allstot, P.C. Canfield, P.K. OR, and H.C. Yang, "A GaAs
MESFET voltage reference," IEEE Inter. Electon Device Meeting
Technical Digest, pp. 774-777, 1988.
12.
P.C. Canfield, A.J. McCamant, and D.J. Allstot, "Gate and drain
transient measurements of conventional and buried-channel
MESFETs," Workshop on Instabilities in III-V Devices, Sedona,
Arizona, Ap. 24-26, 1989.
13.
W. Mickanin, P.C. Canfield, E.P. Finchem, and B. Odekirk,
"Frequency-dependent transients in GaAs MESFETS: Process,
geometry, and material effects," IEEE GaAs IC Symposium
Technical Digest, pp. 211-214, 1989.
124
14.
P.C. Canfield and D.J. Allstot, "A P-well GaAs MESFET
technology," IEEE Inter. Solid State Circuits Conf. Technical
Digest, pp. 242-243, 1990.
15.
P.C. Canfield and D.J. Allstot, "The potential of p-well GaAs
MESFET technology for precision integrated circuits," Proc. of
the IEEE Inter. Symp. on Circuits and Systems, pp. 3065-3068,
May, 1990.
16.
P.C. Canfield and D.J. Allstot, "RF Characteristics of p-well
GaAs MESFETs," Proc. of the IEEE MTT-S Inter. Microwave Symp.
Digest, pp. 1077-1080, May, 1990.
17.
P.C. Canfield and D.J. Allstot,
"A p-well GaAs MESFET
technology for precision integrated circuits," Proc. 6th SemiInsulting III-V Materials Conf.: Toronto, accepted for
publication, May, 1990.