@
-.7
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Accepted by................................
MASSACHUSETTS INSTITUTE
OFTECHNOtOGY
JUL

Submitted to the Department of Electrical Engineering and Computer Science on August 30, 2001, in partial fulfillment of the requirements for the degree of
Master of Engineering in Electrical Engineering
Clock distribution across a digital chip raises several serious issues in current and future integrated circuit technology. The distribution of clocks with frequencies in the giga-hertz range is difficult because of interconnect parasitics. Clock skew due to variation sources is becoming difficult to control with traditional balanced distribution networks. Optical interconnects are currently being evaluated as a technique to distribute a clock signal throughout a digital chip. Optics provides the potential for very low skew distribution. This thesis presents a design for an optoelectric clock receiver operating at 1 GHz. The design has been simulated successfully and a full circuit layout has been completed. The impact of variation sources from the input signal, process, and the environment have been evaluated. Process variation is found to contribute most to skew. A strategy has been prepared for testing the fabricated chip. The result is a simulation and layout of a fully functional CMOS optical clock receiver in 0.18pm technology operating at 1 GHz.
Thesis Supervisor: Duane Boning
Title: Associate Professor of Electrical Engineering and Computer Science
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4

These past five years here at MIT have been a very good experience for me. I am very fortunate that it is finally culminating with the completion of this thesis. It has been a long ride though, and as a result, there are several people that I would like to thank for their support.
I would first like to thank my thesis advisor, Professor Duane Boning, for taking me on as a student for such a short time frame. He encouraged me along through continual faith and sound advice. I would have never been able to complete this thesis in eight months without his support.
I would also like to thank Professor Anantha Chandrakasan for referring me to
Professor Boning and for advising me throughout the thesis. Ron Roscoe, thank you for giving me the opportunity to be TA. I have learned many wonderful things from that experience.
Bunnie and Shamik, thank you for your friendship and flawless technical support throughout my MIT experience. They have both pulled me out of countless difficult situations. Special thanks to Bunnie, whose Cadence tutorials cut a month off of my thesis schedule. I would also like to thank Bginzz, Pedro, Bobby, and all my other friends at ZBT for putting up with my complaints and rants of frustration over the years.
I would next like to thank my office colleagues. Mike and I were working on similar thesis projects and compared their difficulty to "trying to teach a monkey how to speak Chinese." Well Mike, the monkey can now say a few words; I leave it up to you to finish the job. Aaron, thank you for your computer and network assistance and for introducing me to the great hot chocolate machine. Joe, Karen,
Vikas, Han, Dave and Brian, thank you for all the interesting conversations and for contributing to an enjoyable work environment.
I would also like to thank my family for their support throughout the years. Mom,
Dad, thank you for shielding me from many problems and allowing me to focus on my interests. Randy, Lyn, Shane, Jimmy, Bernie, Mike, Stephanie, and Laressa, thank
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you for your encouragement and words of wisdom.
This work has been supported in part by MARCO and DARPA under the Interconnect Focus Center program.
6

1 Introduction
1.1 Motivation for On-Chip Opto-Electronic Clock Distribution
1.2 Previous Receiver Designs . . . . . . . . . . . . . . . . . . . .
1.3 Sum m ary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Design Strategy to Minimize Skew and Effects
2.1 Generalized Topology ............... of Variation 23
. . . . . . . . . . . .
23
2.2 Variation vs. Low Skew . . . . . . . . . . . . .
. . . . . . . . . . . .
24
2.3 Design Implications/Challenges . . . . . . . . . . . . . . . . . . . . .
24
2.3.1 Photodetector . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
2.3.2 Transimpedance Amplifier . . . . . . . . . . . . . . . . . . . .
27
2.3.3 Voltage Amplification . . . . . . . . . . . . . . . . . . . . . . .
28
2.4 Receiver Topology Overview . . . . . . . . . . . . . . . . . . . . . . .
29
2.5 Sum m ary . . . . . . . . . . . . . . . . . . . . . 30
3 Circuit Design and Operation
3.1 Operation Amplifier Designs
. .
3.1.1 Two-Stage Opamp.....
3.1.2 Folded Cascode Opamp
3.2 Transimpedance Amplifier . . . . .
3.3 High Bandwidth Voltage Amplifiers
3.3.1 Cascode Architecture . .
3.3.2 Feedback Biasing . . . . . .
7
17
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19
21
31
31
31
33
34
35
36
36

3.4 Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 1
3.5 Linear Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . .
43
3.6 B iasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
3.6.1 Bandgap Reference . . . . . . . . . . . . . . . . . . . . . . . .
44
3.6.2 Current Sources and Voltage References . . . . . . . . . . . .
48
3.6.3 Passive Elements . . . . . . . . . . . . . . . . . . . . . . . . .
49
3.7 Sum m ary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
4 Special Design Considerations and Tradeoffs 51
4.1
4.2
4.3
Power Consumption Analysis
Automatic Gain Control . .
4.3.1 Variable Gain Amplifier
. . . . . . . . . . . . . . . . . . . . .
51
Asymmetric Clipping . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
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54
. . . . . . . . . . . . . . . . . . . . .
54
4.4
4.5
4.6
4.7
4.3.2 Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
Convergence Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
Balanced Switching Thresholds . . . . . . . . . . . . . . . . . . . . .
58
Voltage Reference Comparison Bandgap vs. Self Bias . . . . . . . . 59
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
5 Variation Analysis 61
5.1 Functionality Due to Input Signal Variation . . . . . . . . . . . . . .
61
5.1.1 Input Frequency and Photodiode Capacitance . . . . . . . . .
62
5.1.2 Realistic Photodiode Input Waveform . . . . . . . . . . . . . .
63
5.1.3 Detailed Photodiode Model . . . . . . . . . . . . . . . . . . .
64
5.1.4 Input Signal Intensity . . . . . . . . . . . . . . . . . . . . . .
64
5.2 Process Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66
5.2.1 Channel Length Variation . . . . . . . . . . . . . . . . . . . .
67
5.2.2 Threshold Voltage Variation . . . . . . . . . . . . . . . . . . .
68
5.3 Environmental Variation . . . . . . . . . . . . . . . . . . . . . . . . .
69
5.3.1 Power Supply Variation . . . . . . . . . . . . . . . . . . . . .
69
5.3.2 Temperature Variation . . . . . . . . . . . . . . . . . . . . . .
70
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5.4 Sum m ary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6 Silicon Layout
6.1 Implementation Overview .............
6.2 Cadence Technology Library . . . . . . . . . . . .
6.3 Layout Hierarchy . . . . . . . . . . . . . . . . . .
6.3.1 Folded Cascode Opamp Layout . . . . . .
6.3.2 Two-Stage Opamp Layout . . . . . . . . .
6.3.3 Transimpedance Amplifier Layout . . . . .
6.3.4 High Bandwidth Voltage Amplifier Layout
6.3.5 Output Stage Layout . . . . . . . . . . . .
6.3.6 Linear Voltage Regulator Layout . . . . .
73
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73
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75
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6.3.7 Bandgap Voltage Reference Layout .
. . .
. . . . .
79
6.3.8 Full Layout with Biasing . . . . . . . . . .
6.3.9 Design Verification, Extraction, and Layout Simulation
. . . . .
79
82
7 Testing Strategy
7.1 Functionality and Skew Testing . . . . . . . . . . . . . . . . .
7.2 Circuit Layout Variants . . . . . . . . . . . . . . . . . . . . .
7.2.1 Normal Receiver . . . . . . . . . . . . . . . . . . . . .
7.2.2 Normal Receiver With Isolated Power Supply . . . . .
7.2.3 External Power Supply . . . . . . . . . . . . . . . . . .
7.2.4 External Voltage Reference . . . . . . . . . . . . . . . .
7.2.5 Current Input Signal Injection . . . . . . . . . . . . . .
7.2.6 Voltage Input Signal Injection . . . . . . . . . . . . . .
7.2.7 Photodiode Variants . . . . . . . . . . . . . . . . . . .
7.3 Overall Chip Layout Summary . . . . . . . . . . . . . . . . . .
8 Conclusion
8.1 Evaluation of Variation Performance . . . . . . . . . . . . . . . . . .
8.2 Alternative Techniques Not Used . . . . . . . . . . . . . . . . . . . .
89
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8.2.1 Adaptive Biasing . . . . . . . . . . . . . . . . . . . . . . . . . 90
8.2.2 Amplifying and Hard Limiting . . . . . . . . . . . . . . . . . . 90
8.2.3 Resoanant Tank Amplifiers . . . . . . . . . . . . . . . . . . . . 90
8.2.4 Phase Locked Loops . . . . . . . . . . . . . . . . . . . . . . .
90
8.3 Future Improvements . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.4 Summary of Contributions . . . . . . . . . . . . . . . . . . . . . . . . 91
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1-1 Typical H-Tree Clock Distribution Network [1]
1-2 Global Optical Clock Network . . . . . . . . .
2-1
2-2
2-3
2-4
2-5
Typical Overall Block Diagram .
. . .
Effect of Light Absorbed in Substrate
Traditional Transimpedance Amplifier
Linear Power Supply Regulator .
. . .
Receiver Block Diagram . . . . . . . .
3-1
3-2
Two-Stage Opamp . . . . . . . . .
Folded Cascode Opamp . . . . . . .
. . . . . . . . . . .
. . . . .
32
. . . . . . . . . . .
. . . . .
33
3-3 Transimpedance Amplifier . . . . . . . . . . . . . . . .
. . . . .
35
3-4
3-5
Transimpedance Amplifier Circuit
High Bandwidth Voltage Amplifier . . .
. . . . . . . . . . .
. . . . .
35
. . . . . . . . . . .
. . . . .
36
3-6 Gain Block Representation for High Band width Voltage Aml plifier . .
37
3-7 Gain Block Grouping for High Bandwidth Voltage Amplifier . . . . .
37
3-8
3-9
Feedback Biasing Circuit . . . . . . . . . . . . . . . . . . . . . . . . .
38
Feedback Biasing Loop At DC . . . . . . . . . . . . . . . . . . . . . .
40
3-10 High Frequency Feedback Biasing Loop Model . . . . . . . . . . . . .
40
3-11 High Bandwidth Voltage Amplifier Frequency Response .
. .
. . . . .
42
3-12 Output Stage ..... ..........................
.... .
42
3-13 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
3-14 Bandgap Temperature Independence Example . . . . . . . . . . . . .
45
3-15 Bandgap Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
11
27
29
24
26
30
18
18

3-16 Bandgap Voltage Reference Circuit . . . . . .
3-17 Parasitic PNP Bipolar Transistor . . . . . . .
3-18 Current Source and Voltage Reference Biasing Circuits
3-19 Receiver Block Biasing . . . . . . . . . . . . .
3-20 N-W ell Resistor . . . . . . . . . . . . . . . . .
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47
48
48
. . . . . . .
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4-1 Power Consumption Tree . . . . . . . . . . . . . . . . . . . . . . . . .
52
4-2
4-3
4-4
Block Diagram With AGC . . . . . . . . . . . . . . . . . . . . . . . .
54
Variable Gain Amplifier for AGC . . . . . . . . . . . . . . . . . . . .
55
Peak Detector Circuit . . . . . . . . . . . . .
. . . . . . . . . . . . .
56
4-5 Sample Peak Detector Waveform . . . . . . . . . . . . . . . . . . . .
57
4-6 Balanced and Unbalanced Switching Thresholc d Comparison . . . . . 58
4-7 Self Biasing Voltage Reference . . . . . . . . . . . . . . . . . . . . . .
59
5-7
5-8
5-9
5-1
5-2
100MHz Output Waveform With Input Capacitance Variation . .
Realistic Photodiode Input Waveform . . . . . . . . . . . . . . . .
5-3 Output Waveform Due To Realistic Photodiode Input Waveform .
5-4 Detailed Photodiode Model . . . . . . . . . .
63
64
5-5
5-6
Output Waveform Using Detailed Photodiode Model .
. .
Output Waveform Due to Input Signal Intensity Variation
. . .
. . .
62
63
65
65
5-10
Output Waveform Due To Channel Length Variation .
. .
Output Waveform Due To Threshold Voltage Variation . .
Output Waveform Due To Power Supply Variation . .
. .
Output Waveform Due To Temperature Variation . . . . .
. . .
. . .
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68
70
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71
6-1
6-2
6-3
6-4
6-5
6-6
Guide to Folded Cascode Opamp Layout . . . . . . . . . .
Folded Cascode Opamp Layout . . . . . . . . . . . . . . .
Guide to Two-Stage Opamp Layout . . . . . . . . . . . . .
Two-Stage Opamp Layout . . . . . . . . . . . . . . . . . .
Two-Stage Opamp (within Bandgap Reference) Layout . .
Guide to Transimpedance Amplifier Layout . . . . . . . .
12
75
76
76
77
77
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6-7 Transimpedance Amplifier Layout . . . . . . . . . . . . . . . . . . . . 79
6-8 Voltage Amplification Stage Layout . . . . . . . . . . . . . . . . . . . 80
6-9 Output Stage Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6-10 Linear Voltage Regulator Layout . . . . . . . . . . . . . . . . . . . .
80
6-11 Guide to Bandgap Reference Layout . . . . . . . . . . . . . . . . . .
81
6-12 Bandgap Reference Layout . . . . . . . . . . . . . . . . . . . . . . . . 81
6-13 Guide to Full Receiver Layout . . . . . . . . . . . . . . . . . . . . . . 82
6-14 Full Receiver Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6-15 Layout Extraction Simulation Output Waveform . . . . . . . . . . . . 84
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3.1
3.2
3.3
Opamp Performance Comparison . . . . . . . . . . . . . .
Feedback Biasing Loop Poles . . . . . . . . . . . . . . . . .
Bandgap Variation Analysis . . . . . . . . . . . . . . . . .
4.1 Comparison Between Bandgap and Self Biasing References .
5.1
5.2
5.3
5.4
5.5
Duty Cycle Changes Due to Input Signal Intensity . . . . . . . . . . .
66
Skew Due to Channel Length Variation . . . . . . . . . . . . . . . . .
67
Skew Due to Threshold Voltage Variation . . . . . . . . . . . . . . . .
68
Skew Due to Power Supply Variation . . . . . . . . . . . . . . . . . .
69
Skew Due to Temperature Variation . . . . . . . . . . . . . . . . . . .
70
34
41
48
60
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16

This chapter presents the motivation for on-chip optical clock distribution on a digital chip. Previous receiver designs are analyzed and their limitations are discussed. This thesis attempts to overcome these limitations and create a fully functional optical clock receiver operating at 1GHz.
Optics have been widely used in the telecommunications area to transmit high speed data. This concept can be applied to sending high speed data across a small digital chip. Miller [2] presents a historical summary of the transistion of optics from large scale telecommunications networks to small, on-chip devices. In addition to transmitting data through on-chip optics, this idea can also be applied to on-chip clock distribution.
Clock distribution is becoming a serious issue in modern digital CMOS chips.
Existing schemes for clock distribution such as H-trees and matched delay lines rely on symmetry to achieve minimal skew (difference in signal arrival times) across all leaf nodes on the chip (Figure 1-1). The skew of a clock distribution network is increased in the presence of process and environmental variations. The individual
17

lines themselves are especially prone to metal width variations. Clock buffers are often added to decrease the dependency of skew on individual delay lines. These buffers along with the initial clock driver circuitry at the heart of the distribution network account for a significant percentage of total power dissipation on a digital chip.
41 1-r 1-1-1 1-71 I-rl 1-rE I7-H:
I-r-3: 1-rH
N fl: ;I-: LZ
ITT 17-9:
I-q Flp-a:
Figure 1-1: Typical H-Tree Clock Distribution Network [1]
The fundamental idea of this project is to use light to distribute the clock signal to multiple receivers across the chip (Figure 1-2). Light can be distributed to multiple areas of the chip with very low skew. If this light can be reliably converted to an electrical clock signal, this method could serve as a good replacement for current clock distribution techniques.
Optical Clock Source
Waveguides
Local Electria
Clock Network
Figure 1-2: Global Optical Clock Network
In order for this technique to be useful, a circuit must be constructed to convert the light signal to an electrical clock with minimal skew. The thesis presents a design
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for a circuit that receives a globally distributed optical clock signal through an onchip low skew opto-electrical interface and amplification network. Once the signal is converted to an electrical clock signal, it can be distributed to individual leaf nodes through a local clock distribution network.
This thesis evaluates various aspects of the receiver design. These include circuit issues, design tradeoffs, and receiver susceptibility to variation effects. The receiver is capable of handling a 1GHz clock signal. A previous design [3] has shown that the most significant variations sources are from the power supply ripple and transistor channel length. The proposed design is engineered to yield consistent results in the face of these and other process and environmental variations.
The next part of this chapter will discuss previous work related to optical clock distribution and receivers. Chapter 2 describes the overall strategy of the receiver topology. It also cites specific design choices to reject the effects of variation. Chapter
3 discusses the design and operation of the opto-electrical receiver. All functional blocks in the receiver design will be covered here. Next, Chapter 4 will cover, in detail, the more subtle design issues in the receiver design. Receiver performance with respect to clock skew in the presence of input, environment, and process variation will be evaluated in Chapter 5. The circuit layout and extraction simulation results will be presented in Chapter 6. This thesis does not encompass the fabrication and testing of the receiver. Because of this, Chapter 7 includes a comprehensive testing strategy for the fabricated circuit. Finally, Chapter 8 will discuss overall receiver performance and will present alternative ideas not implemented in this thesis.
To this date, there has been little published research on on-chip optical receivers for the purpose of clock distribution. There are many documented optical receiver design techniques for sensor and telecommunications applications. These techniques have fundamental problems in their immediate relation to the on-chip optical clock application.
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In Alexander's text [4], general high frequency optical receiver designs are presented. Although there are many useful ideas here, the majority of the circuits that are reported cannot be applied to the task of on-chip optical clock distribution. These designs use inductors, BJT's, non silicon photodetectors, and other components that are not available on a standard CMOS digital process. The architecture of these receiver designs are discussed next. However, each has a set of limitations that prevent the design from having useful application to optical clock distribution.
Woodward et al. [5] present a simple single ended solution based on inverters. The transimpedance amplifier is an inverter with a MOSFET used as a feedback resistor.
The voltage amplification stage uses a string of inverters.
Tanabe et al. [6] use a differential structure whose transimpedance amplifier is a common source amplifier. This design differs from the more conventional common source followed by a source follower stage. By doing this, gain is sacrificed while making the circuit more independent to Vth variations.
Ingels et al. [7] return to the inverter based transimpedance amplifier. Its post amplifier consists of a string of inverters whose biasing is set through a complex replica biasing network. This circuit is the basis of Sam's thesis [3].
The receiver designs presented by Woodward [5], Tanabe [6], and Ingels [7] do not consider the effect of variation. Each of their transimpedance amplifiers are based on transistors simulating resistors. This raises the tolerance issue that will be covered in Chapter 2. The voltage amplification stages in these circuits are also highly prone to power supply variation. Because these receivers were not designed specifically for a clock distribution application, skew induced by process or operational variation is not a substantial concern. The designs are just concerned that the absolute speed of the receiver is not adversely affected with variation and do not consider matching signal arrival times. In the case of on-chip optical clock distribution, however, skew is a fundamental concern and the receiver presented in this thesis has been designed with variation in mind.
Two recent publications have examined the feasibility of on-chip optical waveguides rather than focusing on the receiver. Verma et al. [8] attempt to demonstrate
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an integrated, all silicon based, optical interconnect system working in the GHz range.
However, these claims are not supported in the paper. The design is performed using discrete components rather than integrated circuits, consumes high power, and is only shown to work up to 100kHz. Finally, Verma et al. [8] suggests that "the receiver circuit is not expected to cause any problems for the final development of integrated on-chip optical interconnects." The difficulty in achieving robust, high performance optical receivers has been demonstrated by Sam [3].
Mule et al. [9] consider issues in the design of an on-chip optical waveguide network. The system uses a board level vertical cavity surface emitting laser (VCSEL) to feed a clock distribution network. This network is made up of a high fanout, single split junction that connects to an optical waveguide single-split H-tree. Mule demonstrates less than 9ps of maximum skew for a fanout of 256 and a die area of
817mm 2 . The receiver designed in this thesis would perform well at each node of this single-split balanced optical distribution network.
A previous thesis at MIT, written by Shiou Lin Sam [3], seeks to demonstrate a functional optical clock receiver. Sam's design faces a variety of problems. First, Sam uses a TSMC 0.35pu process whose analog properties are very poor at 1GHz. High gains at 1GHz are impossible to attain and are crucial in typical receiver designs. In addition, Sam's design attempts to use silicon PIN diodes as photodetectors. Silicon photodetectors highly attenuate and distort the clock signal in the light to current conversion. The goal of the second generation receiver proposed in this thesis is to overcome many of the limitations identified by Sam's Work.
Optical clock distribution is a possible alternative to traditional balanced electrical distribution networks. To prove the feasibility of an optical network, a receiver must be designed to have low skew at high clock frequencies with minimal variation dependence. The following chapters present the design and analysis of such a design.
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22

Current optical receiver designs share similar functional blocks. However, traditional implementation of the photodetector, transimpedance amplifier, and voltage amplification stage have limitations when applied to optical clock distribution. This chapter will present these limitations along with an overview of the total receiver topology used in this thesis.
The optical clock signal is distributed through the chip to each receiver. The receiver must take the optical signal and convert it into a corresponding CMOS compatible rail to rail voltage signal. A standard receiver topology has three main functional parts, as illustrated in Figure 2-1. First, a photodetector is used to convert light into a current signal. Next, this current must be changed into a voltage through a transimpedance conversion. Lastly, the voltage signal must be amplified to a rail to rail square wave in order to be used in a standard digital system.
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Photodetector
Optical Clock from Waveguide
Transimpedance
Amplifier
Voltage
Amplifier
Full Swing
Clock
Iin
T^^
T_
+ n_
High
Hih+
Gain -Voltage
R
Power Supply
Independent
Gain
Figure 2-1: Typical Overall Block Diagram
The receiver is designed to be part of a global clock distribution network. Because this network distributes a clock signal, skew between receivers must be minimized.
Skew is the time measurement between misaligned clock signals, considered at the output of each copy of the receiver.
One approach to minimizing skew is to accurately predict and reproduce delay in all copies of this circuit. This approach is impossible due to random process and environmental variations across the die. Another approach is to design the circuit to reject most sources of variation. If this is done, skew will remain constant and can be minimized. This is the approach taken in this thesis.
The key issue that significantly constrains the performance of the receiver is the integration with a standard CMOS digital process. The TSMC 0.18,t MOSIS logic process is chosen for the test chip. The receiver must transform an optical clock signal to an electrical equivalent while running side by side with other digital logic. This imposes two key restrictions. First, the photodetector must either be made of silicon
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or be made on a process that can be integrated or bonded to a silicon die. On the electrical side, the maximum speed that the receiver can run at is inherently limited
by the speed of the MOSFETs. For example, a proof of concept for the receiver was first designed using ideal opamps. Replacing these ideal elements with realistic opamps revealed a host of serious issues. These problems are at the beginning of a list of challenges addressed in the receiver design. The photodetector, transimpedance amplifier, and voltage amplifier will now be examined.
The photodetector serves as the interface between the optical and electrical domains.
Photodiodes are used in this application as detectors. On a basic level, a photodiode is a PN junction that is reverse biased and then exposed to light. The reverse bias causes an electric field to form across the depletion region of the diode. Exposure to light will create free electron-hole pairs in the depletion region. These mobile carriers will be swept to the diode contacts by the electric field. The total carrier movement translates to an electrical current.
In the ideal case, a single photon will be enough for a single electron/hole pair to be generated. These mobile carriers should also instantaneously exit the depletion region and contribute to current. This implies that a square wave of light input will result in a square wave of current output. This is not the case in reality.
Photoemitters require a minimum light wavelength to modulate an optical signal at 1GHz. At this given wavelength, silicon has a very low absorbtion coefficient, and a silicon photodiode must be very thick to absorb all exposed light. Because of this transparency effect, silicon's conversion of light to current is very inefficient.
Ideally, all light exposed to the photodiode is absorbed in the depletion region.
However, in any actual implementation of the photodiode, the substrate sits underneath the device. Light shines onto the photodiode, but not all photons are absorbed in the depletion region. A number of them penetrate into the substrate and create electron-hole pairs there (Figure 2-2). Due to the absence of an electric field in the substrate, the carriers take a long time to migrate back up to the depletion region.
25

This results in low frequency gain where a square wave of light is converted into a
highly distorted square wave.
Light From
Waveguide metal I d
Mobile carriers generated in depletion region are swept to contacts by high electric field
Mobile carriers generated in substrate take longer to reach depletion region
0 n well p substate
(biased lower than Vdd) epletion
Figure 2-2: Effect of Light Absorbed in Substrate
Rooman et al. [10] presented a receiver with a novel photodetector based on spatial modulation. The photodetector consists of a row of photodiode strips. Every other photodiode is covered with metal so that it will not be exposed to light. When light shines on this photodetector, some photons are absorbed in the depletion regions of the uncovered photodiodes. The rest penetrates into the substrate and creates mobile carriers there. These slow carriers now have equal probablity of reaching a covered photodiode as an uncovered photodiode. Therefore, the source of distortion will split evenly between the covered and uncovered devices. Each photodiode creates a current which is then converted to a voltage. The difference between the voltages produced will be an undistorted square wave because the distortion is common mode and thus cancels out. The spatial modulation technique was not used in this thesis; instead, our focus is on the receiver circuit.
In the design in this thesis, the test chip will contain both silicon and GaAs photodiodes. The silicon diodes are diffusion to substrate PN junctions. GaAs has a much higher absorption coefficient than silicon. These photodiodes will be fabricated on a separate process and then later bonded to the CMOS chip. Many copies of each type are on the test chip to account for defects and fabrication difficulties.
26

The transimpedance amplifier (TIA) converts current into a proportional voltage.
Intuitively (through Ohm's law) this current to voltage relationship will be highly dependent on a resistance. Therefore, any changes in resistance will alter the transimpedance relationship and will ultimately alter skew.
The most basic of transimpedance amplifiers is a simple resistor. Input current enters and creates a proportional voltage across the resistor. However, to use this voltage, the non-grounded resistor node must be read. This will introduce some degree of resistive loading and will disturb the transimpedance relationship.
Current From
Photodetector
+High
, Gain
AMN\
R
To Voltage
" Amplification
Stage
Figure 2-3: Traditional Transimpedance Amplifier
The method that is most frequently used in building transimpedance amplifiers is based on negative feedback (Figure 2-3). The idea relies on an amplifier with a high negative gain and high input impedance. A feedback resistor connects the input and output nodes. This configuration results in the following transimpedance relationship: .
If the gain (A) of the amplifier is much greater than 1,
'in then V
0
t/In will be equal to Rf. In a MOS implementation, the amplifier gain is based on a gm x
Rjoad product. Therefore, if the transconductance is high and Rload changes, the transimpedance relationship will be preserved.
There are several problems associated with this negative feedback transimpedance conversion approach. The first is that it requires a high amplifier gain at signal frequency (1GHz). Using a 0.18y process, the highest gain that can be attained is about 10. In most cases, higher gain can be achieved by cascading multiple stages.
However, this is impossible here because each stage adds another dominant pole and with it, 900 of negative phase. When a feedback loop is closed around this amplifier,
27

the phase margin will be severely degraded and instability will occur.
Aside from the gain issue, the negative feedback TIA approach has a serious problem because it is still dependent on a distinct resistance. In a CMOS process, resistor values commonly may vary up to 20%. This will result in an unpredictable transimpedance relationship. Also, in order to achieve a high transimpedance gain, a very large resistor must be used. Using a field effect transistor (FET) as a resistor overcomes this last problem.
The receiver design in this thesis uses a transimpedance amplifier that has no feedback. It therefore does not require a single stage high gain amplifier. Furthermore, the TIA relies on a MOSFET small signal output impedance as its principle resistance.
This allows for a large transimpedance gain with less susceptibility to variation than a passive resistor.
An output stage is required in a typical receiver. This stage will, at the very least, be a rail to rail voltage buffer. More often, the stage will also need to provide voltage gain.
Sam [3] uses a topology based on CMOS inverters. Although this method fulfills the above criteria for an output stage, it introduces large skew in the presence of power supply variation. When Vdd changes, the switching thresholds of the inverters also change. Sam found that a 10% variation in power supply caused 100ps of skew over the overall amplifer.
The voltage amplification stage in this thesis is split into two parts. First, high bandwidth cascode amplifiers are used to amplify small voltage signals. The signals are amplified to give ample noise margin in the subsequent inverter amplifier stages.
To account for power supply variation, a linear voltage regulator is constructed to fix Vdd at 1.8V (Figure 2-4). This method requires a separate supply higher than
Vdd and a voltage reference.
Power supply variation skew tests are performed on the inverter with and without power supply regulation. A skew test measures the time difference between the output
28

vddref
0- +
Vdd High (3V)
10nF--
I
Vddreg (1.8V)
Figure 2-4: Linear Power Supply Regulator from a 90% Vdd amplifier and a 110% Vdd amplifier. A normal inverter has 15ps of skew while one with a simple regulated power supply
1 has 2.5ps skew. Power supply regulation therefore provides more than an 80% reduction in skew.
The overall receiver topology can be seen in Figure 2-5. The optical signal is converted to a current through the backbiased photodiode. Since the photodiode is a single element, it is grouped with the next stage. The current is changed to a small voltage through transimpedance conversion.
From this point forward in the circuit, the output voltage from each stage is biased at VDD/
2
.
This ensures proper input signal biasing of the individual stages and helps prevent skew. The method used is feedback biasing, which uses a high gain negative feedback loop to keep a constant DC level while preserving the gain of the amplifier at 1GHz. After the transimpedance conversion, the voltage is amplified through a high bandwidth voltage amplifier with feedback biasing.
Up until this point in the circuit, linear system analysis can be used since the voltage signals are small. Gain and bandwidth are primary concerns in the linear stages. However, this changes when the voltage signal becomes rail to rail after
'Amplifier used in test is a single stage differential pair.
29

passing through the inverter output stage. Now, the system becomes a digital system where fast transition square waves are the primary goal.
Off the signal path are a collection of circuits that support receiver operation.
First, a linear voltage regulator rejects power supply ripple and provides a consistent
Vdd to every other circuit in the receiver. This circuit is critical since the output of every stage is biased at VDD/
2
.
Next, a biasing network provides various voltage references and current sources. The main current reference is constructed with a bandgap reference feeding a MOSFET. Bias stability is a primary concern for maintaining low skew. The bandgap reference proved to be very independent of V 7 h, AL, and temperature variation.
r-------------------------------------------
Linear Voltage
Regulator (Vdd)
Light from
Waveguides
Transimpedance
------------------------------------
High Bandwidth
Figure 2-5: Receiver Block Diagram
A l
~
J Clock
To Local
Distribution
2.5
The challenges of building a high speed optical clock receiver have been discussed in this chapter. Existing architectures of the photodetector, transimpedance amplifier, and voltage amplification stage have limitations that make it difficult to meet the requirements of this application. Instead, a design overview for a new receiver architecture is proposed. The following chapter will detail this receiver's design and operation.
30

A complete design documentation is presented in this chapter. First, the two styles of operational amplifiers (opamps) are discussed. These opamps will be used in the construction of larger functional blocks. Next, the discussion focuses on the three blocks directly in the signal path (transimpedance amplifier, high bandwidth voltage amplification, and output stage). Finally, the linear voltage regulator and the biasing network are described in detail.
The opamps described in this section are needed as building blocks in other sections of the receiver. Six opamps are needed in the complete receiver design. Two main opamp topologies are chosen and each has two variants.
The first opamp topology chosen is the standard two-stage architecture (Figure 3-1).
This opamp consists of a current mirror loaded differential pair followed by an actively loaded common source amplifier. The differential pair bias current is supplied by a current mirror to ensure high common mode rejection.
The two-stage opamp has a system function of H(s) = (
31

Viin-
Vdd
T
Ccomp
Vout
Figure 3-1: Two-Stage Opamp dominant poles. One pole is caused by the high impedance node at the output of the differential pair stage. The second pole is caused by the high load capacitance at the output of the second gain stage. In the frequency domain, each of these poles contributes 900 of negative phase. Because of this, the total phase margin at unity gain crossover is very small. If not corrected, this will contribute to instability when a feedback loop around the opamp is connected.
First, a Miller capacitor is inserted across the gate-drain junction. This has the effect of significantly lowering the dominant pole of the system through the Miller effect while pushing the second pole up in frequecy. However, the addition of this capacitor also brings a right half plane zero into the frequency range of interest. This zero degrades phase margin by providing a magnitude boost while adding negative phase. To compensate for this, a resistor (Rcomp) is added in series with the capacitor
(Ccomp) to move the right half plane zero into the left half plane.
The receiver uses three two-stage opamps. The first two are used in the high bandwidth amplifier stages as voltage buffers. After compensation, these opamps have a gain of 20.8, bandwidth of 12.1MHz, and a phase margin of 90'. This opamp is an ideal choice for a buffer because its unity feedback closed loop response is flat past 1GHz. The last two-stage opamp is used in the bandgap circuit. Its DC characteristics are adjusted to the values relevant to the bandgap reference.
32

The folded cascode opamp (Figure 3-2) is chosen for use in the receiver because it can achieve a higher gain and bandwidth than the two-stage opamp [11]. Its input stage is a differential stage whose current is supplied by a current mirror. The output stage has a cascoded current mirror PMOS structure along with a biased cascode
NMOS structure. The cascode configuration on both sides gives the output node very high output impedance. The input stage is coupled directly into the output stage by steering current to the NMOS transistors.
Vdd
T
Vi0
Vout
Vbias2
Vbiasl
Figure 3-2: Folded Cascode Opamp
The system function for the folded cascode opamp is H(s) =
Apc
There is only one high impedance node in this circuit because all other nodes see 1/gm. It is located at the output node of the opamp and is caused by the high output resistance of the opamp and the load capacitance. The pole dominates the frequency characteristics of the opamp. This gives the amplifier a single dominant pole at the output node.
Using this feature, the folded cascode can be built to have a reasonable gain with high bandwidth. Two of these high bandwidth opamps are used in the high bandwidth amplifier stages. Each has a limited gain of 5.86, but a bandwidth of 192MHz with
900 of phase margin. However, because of the higher order poles and zeros, the poor unity gain closed loop response of this opamp makes it not fit for a unity gain buffer.
An alternative use for the single high impedance output node is to make an opamp
33

with very high gain and phase margin. The linear voltage regulator does not require high bandwidth because it mainly deals with DC signals (Section 3.5). A special folded cascode opamp is designed for this application, featuring a gain of 355, bandwidth of 21.8MHz, and phase margin of 900.
Table 3.1 compares all opamps used in the receiver in terms of gain and bandwidth.
Topology Circuit Used In
Two Stage High BW Amplifier Stage
Two Stage Bandgap Reference
Folded Cascode High BW Amplifier Stage
Folded Cascode Linear Voltage Regulator
Quantity Gain Bandwidth
2
1
20.8 12.1MHz
14.6 10.5MHz
2
1
5.86
355
192MHz
21.8MHz
Table 3.1: Opamp Performance Comparison
As discussed in Section 2.3.2, the transimpedance amplifier of this receiver is not the typical resistor feedback around a high gain amplifier. Instead, the open-loop topology of Figure 3-3 is chosen. Note that the transimpedance amplifier shares the first cascode amplifier with the high bandwidth voltage amplification stage.
Light is converted to current in the photodiode. The photodiode is reverse biased with one end connected to Vdd and the other to a current mirror. The current mirror is constantly biased to the on state using a PMOS device in parallel with the photodiode.
The bias current is 54uA and is purposely kept large compared to the photodiode current so that the output impedance of the diode connected NMOS device remains fairly constant. Therefore, the photodiode current rides on top of a larger DC current.
Current is converted through voltage as it passes through the diode connected
NMOS device. Its effects are amplified further in that the current mirror ratio is 1 to 6. This requires that the DC current be kept at a reasonable size such that the mirrored current in the next stage is not too large. At 1GHz, the transimpedance gain is 1.18kV/A.
The transistor level schematic of the TIA is seen in Figure 3-4.
34

Transimpedance
Input Stage
Vdd
Photodiode
I
First Cascode
Amplifier Stage
V f1: 2.28u10u
Feedback
Biasing
Ve2 mnc2 iO3u/18u mnml luI.18u mnm2
6u/.18u
-L
Figure 3-3: Transimpedance Amplifier
Once the signal is converted to voltage, its peak to peak voltage is only about 17mV.
This voltage must be amplified to the point when normal inverters can take over and rail the signal. Two key architectures are used in this circuit.
Vdd Folded Cascade Opamp
Photodiode
Cascode Two-Stage Opamp Vdd
....-
Low-Pass
Filter
> >
A---------- -
F-gr ---
0
Figure 3-4: Transimpedance Amplifier Circuit
35
---------------

Vdd
The actual voltage amplification is done through the cascode architecture (Figure 3-5).
MOS transistors ni and p1 form a standard common-source voltage amplifier. The lower device, m2, exists to isolate the input node from the output node, thus killing the effect of the Miller capacitance and extending the bandwidth of the amplifier.
The output impedance of the amplifier is also increased by n2, thus raising its gain.
The result is a conventional high gain, high bandwidth voltage amplifier.
The central strategy of this receiver design is to bias the outputs of each amplifier at VDD/2. This reduces skew by standardizing the bias points of each amplifier and preventing clipping before railing the signal at the inverter stages.
The output of the high bandwidth voltage amplifiers is set to VDD/
2 using a feedback biasing technique. This technique is meant to hold a specific DC bias without interfering with the small signal voltage amplification of the cascode stage.
To fully understand the subtleties of feedback biasing, linear analysis must be
36

-A
21
Vin Vout
Figure 3-6: Gain Block Representation for High Bandwidth Voltage Amplifier performed. The full high bandwidth voltage amplifier (cascode stage with feedback biasing) can be modeled with Figure 3-6. In this model the gain blocks A
1
, A
2
, and
A
3 represent the transconductances of various sections of the amplifier (Figure 3-7).
The output resistance block, Rout, is the parallel combination of small signal output resistances:
Rout = ron2||rOPl
-A2
Vbiagut
vinoL
A ,
Figure 3-7: Gain Block Grouping for High Bandwidth Voltage Amplifier
A transfer function for each transconductance gain block must be found. First, the small signal transconductance of the entire amplifier is gmni. Because of the cascode configuration, the dominant pole of A
1 is across gate and source of ni.
37

A
1 gmni
A
2 has a similar transfer function because it relates the change from the feedback biasing loop to the output.
A
2
= mP
(-a2S+1)
Next is the analysis of the feedback biasing loop itself (Figure 3-8). compilation of three smaller transfer functions.
A
3 is the
Vdd
To next stage
0re
+
H4s) R
C R
+
Opamp
H~s)
Figure 3-8: Feedback Biasing Circuit
H
1 is the unity gain closed loop transfer function of the two-stage buffer opamp
(Section 3.1.1). Since it has two stages, there are two dominant poles in the open loop response.
Hl(s) =( s+1)(-r2s+1)
When the loop is closed in unity gain, a single high frequency dominant pole is created.
H (
8
) = (a1+7s+1)(r
2 s+1) (T3s+1)
H
2 is the open loop transfer function of the folded cascode opamp (Section 3.1.2).
This opamp has a single dominant pole around 200MHz.
H
2
(s) = 0s2
38

H
3 is the transfer function of the RC low pass filter. The small output resistance of the two-stage opamp (rots) does not affect the time constant here because the resistors themselves are much larger.
H
3
(s) -
R
1+RCs
R+rots++R
-
R
(R+R+rot)+(R+rots)RCs ~
1
(2+RCs)
A
3
=
H-(s)H
2
H
3 (r
3 s+1)(r
4 s+1)(2+RCs)
Now that all the blocks have been found, feedback analysis can proceed. The feedback biasing circuit must do two things:
" It must bias the DC output voltage at VDD/2.
* It must not interfere with the high freqency voltage amplification of the cascode amplifier.
The following sections will discuss these specific tasks.
Biasing the DC Output Voltage at VDD/ 2
The main feature of feedback biasing is that it allows the output bias point to be accurately set. At DC, the cascode amplifier has no gain. It can therefore be thought of as a constant current source with high output impedance. The rest of the loop can be seen in Figure 3-9. The frequency components of all the blocks are removed because this analysis is at DC. The forward path gain becomes the product of the folded cascode opamp's DC gain, a2, and the non-linear square law component of
p1. The return feedback path gain is simply the resistor divider ratio, 1, because the two-stage opamp is connected as a buffer. The negative feedback forces the output node to be twice Vref. It also forces the gate to source voltage of p1 to accomodate this output voltage given the DC bias current set up by n1. Vref is set to 0.44V to account for the non-infinite forward loop gain. This circuit succeeds in biasing the output voltage of the amplifier at VDD/2.
39

Vref
+ H2 A2 ___OVOUt
Figure 3-9: Feedback Biasing Loop At DC
Non-Interference With High Frequency Voltage Amplification
The initial high frequency gain of the cascode amplifier must be preserved. Figure
3-10 illustrates how feedback biasing affects the high frequency gain.
Vin -A R Vout
Figure 3-10: High Frequency Feedback Biasing Loop Model
At high frequencies, the DC voltage reference is shorted to ground. The overall transfer function from input to output is given by:
=
-A
1
(
1+A
2
A
3
)R
( ) (1+ n
)
Iropi)
Notice the difference between this overall transfer function and that of a normal cascode amplifier. The middle term represents the effect of feedback biasing on the gain of the amplifier. In order for the gain to be unaffected by feedback biasing, the open loop gain term must be much less than unity at the frequencies of interest
(1GHz). Therefore, the feedback biasing open loop response must be designed such that its unity gain crossover occurs before 1GHz.
The other serious design issue is loop stability. The feedback loop must be designed to have a very stable (high phase margin) open loop response. If not, a magnitude spike will develop in the frequency response which will give low frequency gain. If this gain spike is high enough, the transient response will oscillate at the spike's frequency.
40

Pole Frequency Location
27r-2
1
20MHz
1GHz
2
200MHz
1.5MHz
Table 3.2: Feedback Biasing Loop Poles
Stabilizing this feedback loop is very difficult. Table 3.2 shows the frequencies of the amplifier poles. Two main requirements have to be met. First, the open loop frequency response of the feedback biasing has to drop below unity gain before 1GHz.
Second, this unity gain crossover has to occur at a point with enough phase margin or the amplifier will oscillate. To obtain the required phase margin, dominant pole compensation is used. The obvious choice for a dominant pole is the one used to set the low pass filter. Since the next dominant pole in the loop is at 20MHz, the dominant pole needs to be placed below 1.5MHz to maintain stability. However, this pole is set by an RC time constant. It cannot be set arbitrarily low or else the capacitor and resistor sizes will make silicon fabrication impractical. A pair of 100kQ resistors and a 2pF capacitor are used in this design to set the time constant. The result is a feedback biasing circuit that does not interfere with the high gain of the cascode amplifier. Figure 3-11 shows the frequency response of the two high bandwidth voltage amplifiers. Note that the first one is integrated with the transimpedance amplifier
(Section 3.2).
After the signal is amplified to 700mV peak to peak, it is put through a series of inverters (Figure 3-12). This method provides additional amplification to the rails, thus turning the signal into a square wave with fast rise and fall times.
Each inverter is sized such that its switching threshold (VM), is exactly at Vdd/2.
This helps to preserve the duty ratio of the signal. This fact also makes these inverters
41

2nd Voltage Amplifier Output Node
--- - ---------------------100k - --------------------- -------------- -- -
10k
- - -
1st Voltage Amplifier Output Node (TIA)
- - - - - --- - -- - -------- --
- - - - - - - - ------
. . . .
-- --.---.----- ----- ---------------
I
1k
---- - --- ------ ----
Input
Photodlode
Node-
100
--------- ----- ----------------------
------ - -- ------------ ------- -' -----------------
10k10kx1x10xg1g r ----- ------ --- ---- ------------- -- - -r -- ----- I -------- ---1 ---- -- - -- -
l~k ' ' 6kFrequency (log) (H ERTZ)1
1k2
1 p 4i
Figure 3-11: High Bandwidth Voltage Amplifier Frequency Response
100/ U/ u.18
Tu.8 T5/
' ' I u l/1
Vdd u
T u. u 8 18u 8u 7 u/
8
Figure 3-12: Output Stage very sensitive to power supply variation. That is the main
for using the regulated power supply.
The inverter sizes progressively increase as they get closer to the output. This prevents excessive loading from large capacitive loads placed on the output.
The number of these inverters may vary in the actual use of the receiver, and will depend primarily on the local clock distribution network that takes the electrical clock signal from the receiver. The end user can customize the size and number of inverters to a specific application.
42

Power supply regulation is needed to provide a constant Vdd supply to the receiver.
Across a digital chip, the power supply voltage can easily vary by 10% due to IR drops and have significant ripple from the swiching digital logic. A linear voltage regulator topology (Figure 2-4) is chosen because of its simple concept and the availability of a good opamp as presented in Section 3.1.2.
The performance of the voltage regulator is based on four factors. First is the presence of a solid Vdd (1.8V) reference which must remain constant despite the presence of variation. The bandgap reference, discussed later in Section 3.6.1, provides a very solid voltage source from which the VDD reference can be derived.
Once a good reference is obtained, the opamp is the next thing to consider. The regulator topology relies entirely on negative feedback. A single large NMOS device controls the flow of power. It is connected in a follower configuration with a voltage drop between its gate and source. The negative feedback forces the source of the transistor to the reference voltage in order to minimize the error between the two opamp terminals. A customized folded cascode opamp (Section 3.1.2) is constructed for this application. This opamp has a high DC gain with a low bandwidth. Figure
3-13 is a transistor level circuit diagram of the voltage regulator.
Vdd High (3V)
Power FET
Folded Cascade Operrnp-
r -- F
Figure 3-13: Voltage Regulator
43

Because the opamp has a low bandwidth, its gain at signal frequencies (i.e., 1GHz) is very low. To compensate for this, a large decoupling capacitor is needed. The capacitor creates a very low cutoff low pass filter on the regulated voltage node.
However, because the value of the capacitor is so large, it is more feasible to run it off chip instead of trying to fabricate it using silicon.
The largest drawback of this circuit is that it requires a separate VANh power supply. This contributes to added overall power dissipation. The power required by this circuit is equal to the power draw of the opamp (< 1mA) plus the product of the total current draw of the receiver and the voltage difference between
V Ah and
Constraints must be placed on V h for proper functionality. The NMOS power
FET is a maximum sized device so its V"a is minimized. V h must be kept larger than Viat plus VEIjulated or else the power FET will come out of saturation. Vs must also be kept low enough such that the maximum VDS, specified at 1.8V, is not exceeded.
The next step after designing the funtional blocks of the receiver is to construct a stable biasing system. The biasing circuits must provide reliable voltage references and current sources across all variation sources. In a sense, robustness to variation begins with stable biasing. There are three parts to the biasing scheme: the bandgap reference, current sources, and voltage references.
In order to construct the voltage references and current sources of the biasing network, a single, stable current source is needed. Since every other voltage and current used in the receiver is derived from this source, performance will be severely affected if a drastic change occurs with variation. That is why the bandgap topology is chosen; the bandgap method is known to be an effective strategy for designing against tem-
44

perature dependence. The circuit is based on the bandgap of silicon and is designed to output the a constant voltage (1.24V) around a specific temperature (300
0
K).
The bandgap's temperature independence is based on adding two voltages with opposite dependencies on temperature. The voltage drop across the base-emitter (PN) junction of a bipolar transistor has a negative temperature dependence (-2mV/ C).
However, subtracting the base-emitter drops of two bipolar transistors generates a difference that is proportional to absolute temperature (PTAT):
AVBE v th-=7
VBE1 Vth ln
VBE2 Vthln
BE1 VBE2 = Xth ln I
After adding the two voltages, there exists a specific temperature where the two have equal magnitude and opposite sign. At this point, their temperature dependencies cancel each other out and virtual temperature independence is achieved for a wide range of temperatures (Figure 3-14).
Voltage -
Temp Dependence
Scaled Summation
+ Temp Dependence
Temperature Axis
Figure 3-14: Bandgap Temperature Independence Example
Figure 3-15 shows the functional implementation of the bandgap reference. The negative feedback forces the opamp input nodes to be at equal potential, and the ratio of R
1 to R
2 sets the ratio of currents through m, and M
2
. Because of the difference in current, the base-emitter drops of mi and n
2 will not be equal. Their difference
45

(bgp)V
R1 R2
(bgn) .
R3
+b m2
Vbg
Figure 3-15: Bandgap Reference
(PTAT) will be reflected in the voltage drop across R
3
. The PTAT voltage across R3 is summed with the base-emitter drop of m
2 and the collector currents are set such that the desired reference voltage (1.24V) is formed at the output of the opamp.
VBE ~ .75V
VR1 - Vbg -VBE1
=.49V
R3 = Ju
12
= 61kg
R
1
= R3 - 6.kQ
k = 1.24V-J5V = 8.248
R
2
= = 7.OkQ
The transistor level circuit diagram of the bandgap is shown in Figure 3-16. The bipolar PNP transistors are made from parasitic diffusion-well-substrate PNP transistors (Figure 3-17). Although these transistors have very poor current gains
(~ 3), they are adequate for use in this circuit. The opamp has a two-stage architecture and is customized to the appropriate DC levels (Section 3.1.1).
Besides showing independence to temperature variation, the bandgap also rejects the other major variation sources. The voltage reference itself is not based on any
MOSFETS so channel length and threshold voltage variation will only affect the bandgap circuit through the opamp. The same argument applies to power supply
46

Vdd
I~~R1 3k
(bgp) ____,cmmp
(bgn),,R
7.1k
m2
--- Vbg
Figure 3-16: Bandgap Voltage Reference Circuit
E
B
C
C B
PI
J
I
NA] IP+diff
E
N-Well
P-Substrate
B
NI
C
Figure 3-17: Parasitic PNP Bipolar Transistor because the only connection to Vdd comes from the opamp. In addition, the negative feedback of the circuit only requires the gain of the opamp to be large; it need not be constant. Table 3.3 shows how well the bandgap performs with variation of temperature, power supply, channel length, threshold voltage, and resistance. Note that in the resistor test, all three resistors were changed in the same direction; the worst case combination is not represented.
Once the bandgap reference is established, it can be connected across the gate and source of a MOSFET to create the single current source that the rest of the biasing scheme is based on.
47

Variation Source
'Al
V 1 th
VDD
Temperature
Resistance
Variation Change % Output Change
+10% 0.25%
0.27% +10%
+10%
+100%
+10%
1.02%
0.54%
0.016%
Table 3.3: Bandgap Variation Analysis
101d"
Uiu
Vbandgap
10
Vdd
T
"l
2A
0ref2
(1.56V) f b5a
.
ref 1
(.8V)
W4
(li1v) ref5
(.9V) ret6
(N7) b2
1.2u
ref 3
(.44V) breg (1 OOuA)
(200uA) b1f
(200uA) b2t
(1 OOuA) b2f
(200uA)
I Ij" bgl
(1 O0uA)
IO/8
16 u Bu
Figure 3-18: Current Source and Voltage Reference Biasing Circuits
The remaining current sources and voltage references (Figure 3-18) are based on the bandgap reference. Current mirrors reflect and scale the current to provide multiple current sources. The voltage references are created by injecting the reflected current through diode connected MOSFETS. By adjusting the size of these transistors, the
VDS
(equal to VGs) can be changed. The voltage reference is then taken directly from this.
bgl
S
Bandgap Linear Voltage
Regulator (Vdd) b e
Light from
Waveguides *
Transimpedance
Amplifier (TIA)
High Bandwidth
* Voltage Amplifiers
Inverter
[ Amplifiers
To Local
Clock Distribution
Circuit
Figure 3-19: Receiver Block Biasing
48

Figure 3-19 shows where in the receiver the various current sources and voltage references are used. Nodes bgl, b1t, and b2t connect to 100pA current sources for two-stage opamps. Nodes breg, b2t, and b2t connect to 200puA current sources for folded cascode opamps. Finally, the various ref nodes are voltage references used in various parts of the receiver.
The receiver design uses many passive elements in addition to transistors. These resistors and capacitors must be fabricated in silicon along side the active elements.
A total of ten resistors are needed in this receiver. They are made using the resistance of n-well's (Figure 3-20). To implement the very large (100kQ) resistors, multiple smaller resistors are placed in series. Special care must be taken to ensure that the substrate around the well resistor is kept at ground potential. This ensures that the parasitic diode formed by the PN junction remains reverse biased.
Oxide
M I
N+
Oxide
N-Well
Ml
Oxide
P-Substrate
Figure 3-20: N-Well Resistor
Two types of capacitors are used in this design. Smaller capacitances (< 25fF) are obtained with M2-M3 parallel plate capacitors. Any capacitance larger than this is made with a MOS capacitor. Here, the capacitance non-linearly varies with the voltage across the capacitor. In this design, the DC voltage across each MOS capacitor is fixed to a known voltage.
Several decoupling parallel plate and MOS capacitors are included in the layout to reduce power supply noise.
49

This chapter has presented the full design of the optical clock receiver. Individual modules were considered in detail and their interaction with one another was discussed. The next chapter will summarize the more subtle design issues of this project.
50

A variety of additional special issues have been considered during the design process.
Many of them require subtle design decisions that might otherwise be overlooked.
This chapter is dedicated to discussing certain key issues and design tradeoffs.
In Section 4.1, the power dissipation of the receiver is analyzed. Section 4.2, the concerns regarding duty cycle variation due to asymmetric clipping are addressed.
An automatic gain control approach has been developed, and is described in Section
4.3. Convergence related issues are discussed in Section 4.4. The importance of having balancing switching thresholds is emphasized in Section 4.5. Finally, Section
4.6 presents a comparison between the bandgap reference used in this receiver design and an alternative self bias approach.
The receiver consumes a total of 19.27mW of power during steady state operation.
Figure 4-1 explains the power breakdown throughout the individual components.
Power reduction is not a top priorityin this design; rather, functionality at 1GHz and variation independence are the primary goals.
There are two key reasons that this cirucit consumes so much power. First, note
51

Bandgap
Full Optical Clock Receiver
19.27mW
Transimpedance Amplifier'
Cascode Amplifier
-- w/ Input Stage
0.7282mW,
Two Stage Opamp
1.388mW
Folded Cascode Opamp
0.8368mW
Output
Stage
Linear Voltage
Regulator
8.5mW
Biasing Network
4.3136mW
Cascode Amplifier
0.2932mW9 )
Two Stage Opamp
1.388mW;;
Folded Cascode Opamp
0.8368mW
Folded Cascode Opamp,
1.339mW
2PowerFET
7.1724mW
Figure 4-1: Power Consumption Tree that until the output stage, this circuit is fully analog. It contains many linear amplifiers and opamps which dissipate power statically in their biasing currents. The circuit must be mostly analog in order to obtain the transimpedance conversion and high bandwidth voltage amplification functions.
The other major reason that this circuit consumes so much power is the linear voltage regulator. This component gives the receiver full power supply independence but consumes 44% of the total power. The vast majority of this power loss appears across the power FET.
The biasing network consumes 22% of the total power. By monitoring the current through each path of the biasing network, it can be optimized to pull less current and dissipate less power. Also, each opamp has redundant current mirrors in their biasing. This provides modularity but adds extra current paths and therefore more power loss.
The receiver would consume much less power if the voltage regulator was removed.
However, power supply rejection would greatly be affected. Instead, chip area can be traded off with power to reduce consumption. The main power loss is across the power FET and is equal to the voltage difference of the regulated and unregulated supplies times the current draw of the receiver. Thus, the goal should be to reduce the unregulated supply. The unregulated supply has been chosen to have a value of 3V.
52

It needs to be higher than the regulated voltage plus the
VGS drop of the power FET to ensure that the opamp will be able to keep the regulated voltage equal to
VDDref through negative feedback. One possible fix to this problem is to provide a third power supply line with a value in between the unregulated and regulated voltages.
This will be attached to the source of the power FET and will proportionally reduce the power loss. Only the opamp really needs to have a high power supply. Another possible option is to add more power FET's in parallel. This adds more current source capability but more importantly, reduces
VGS in the power FET. Therefore, the unregulated power supply can be reduced and with it, power dissipation is reduced.
One of the largest sources of skew and duty cycle variation is asymmetric clipping in the high bandwidth voltage amplifiers. The core cascode amplifier architecture makes the amplifier saturate on the ground rail before it saturates on the power rail. This is due to the amplifier requiring two VDf' drops from the output node to ground. Once clipped, nonlinearities will be introduced to the signal and will be passed through to later stages. This will ultimately lead to skew and duty cycle variation at the receiver output node.
There are a number of techniques that can be used to prevent asymmetric clipping.
The first was to reduce the number of cascode amplifier stages from three to two.
Once the signal is large enough to pass the inverter thresholds, additional linear amplification is unnecessary. Next, the input signal intensity (Section 5.1.4) must be limited to ensure duty cycle integrity. Finally, automatic gain control can be used to equalize the signal magnitude before passing through the high bandwidth cascode amplifiers. While the ultimate decision is to not include automatic gain control in the present receiver, a design is presented in the next section for potential future use.
53

Automatic gain control was considered in the receiver design. Implementation proved to be difficult so the idea was not used in the final receiver design.
The purpose of the automatic gain control (AGC) stage is to account for amplitude variations. The largest source of amplitude variation comes from the photodiode; however, this stage would also account for gain variations in the cascode stages and prevent asymmetric clipping. Finally, any amplitude variation should be corrected before railing the signal with the inverter amplifiers.
The AGC consists of three parts: the variable gain amplifier (VGA), peak detector, and feedback biased (FBB) load (Figure 4-3). The peak detector stores the peak at the AGC's output. The VGA uses the stored peak value to alter its gain in the input signal. The FBB load, as explained earlier, biases the output signal around a known voltage.
Linear Voltage
Regulator (Vdd)
Light from
Waveguides
Transimpedance
Amplifier (TIA) *
M
Automatic Gain
Control (AGC) gi
High Bandwidth
* i)
Voltage Amplifiers *
Inverter
Amplifiers
Figure 4-2: Block Diagram With AGC
To Local
Clock stribution
The VGA (Figure 4-3) uses a feedback loop to keep the input transistor, mnl, in its linear triode region of operation [12]. The negative feedback attempts to keep the two inputs to the opamp, node a and node c, at the same voltage. The opamp sets the gate voltage of mn2 (node b) such that the
VDS of mnl is fixed to the output voltage of the peak detector.
Assuming now that mnl is kept in its triode region, its drain current and transconductance can be expressed by:
ID (I)AnCox (VGS VTn yV)VDS
54

Vdd mpl
(d)
Vi
(a) mn2
+(b)
--
()Pecak
Detector
Figure 4-3: Variable Gain Amplifier for AGC
9M = VG = (W)[nCoxVDS
Therefore, as long as mnl is kept in its triode region, its transconductance will be proportional to its VDS. Since mn2 acts as a common gate amplifier and has no affect on the ID, the overall gain of the VGA is -gm(ron
2
||rO ).
4.3.2
The peak detector controls the gain of the AGC. An exclusively CMOS topology [13] is chosen to avoid diode non-idealities. If the output voltage amplitude is too high, its sampled peak signal to the VGA must lower. The opposite applies to an output voltage amplitude that is too low. Note the inverse relationship. The output signal is biased at a known positive DC voltage. The peak detector in Figure 4-4 records the low peaks of this signal.
The peak detector stores information of the output signal peak on Cstore. The voltage on Ctoe is buffered once to prevent loading and then again to give the necessary level shift for proper VGA operation.
Figure 4-5 shows the ideal operation of the peak detector. Assume first that the value stored on Ctoe is higher than the lower peak of the output signal, so that the
55

v7
I rj
(C)
Vdd
MP
Catore
T(b)
( o- Vpeak
(a)
I I
~I
L mn1 mn2
Biasing Differential Pair Biasin for ml
Current Mirror Buffer 1 Buffer2 Biasing
Figure 4-4: Peak Detector Circuit voltage at Vi., is higher than the voltage at node d. Node a is at the inverting output of the differential pair. In this case, the differential pair pulls node a down as low as it can go until its current mirror saturates. Because node a is very low, the current mirror in the next stage does not turn on. However, node a also feeds a follower amplifier which biases mpl in the on state. This current leaks down through mn2 and the voltage on Cstore remains unchanged.
Assume now that the voltage at V is lower than the voltage at node d. Then node a will be forced to a high potential, thus turning on the current mirror at mOt and biasing mpl off. The current that flows through mn2 will discharge Ctore to the point where node d is equal to the low peak value. This phase is known as the tracking mode.
After the peak is found, the peak detector remains in the hold mode in which the voltage on Ctore remains relatively unchanged. This voltage can change through leakage discharge or a change in the output voltage amplitude.
56

1Input
0.8 -
0.6 -
0.4 -
0.2 -1
0 L-
-0.2 -
-0.4 -
-0.8 -
0 t
Hold
2
Output Stored Peak
Signal
3
I
Track
I
4 5
Hold
6
-
7
Figure 4-5: Sample Peak Detector Waveform
During the course of this thesis, many Hspice convergence issues were encountered.
Convergence is needed to obtain valid circuit simulation results.
The models used in the receiver simulation are the TSMC 0.18pt analog/mixed signal models. These include complete modeling of parasitic components. Because of their detail, Hspice often does not converge if the models are used at high frequencies
(1GHz). This problem was never fixed; a simple move to the TSMC 0.18[p digital models was made. These models do not include the complex parasitic modeling and converged while maintaining enough accuracy for this thesis.
The other reoccurring issue with convergence is observed when complex feedback loops are used. Techniques such as feedback biasing cause Hspice to lose DC convergence and fail at transient simulation. After researching through the Avant! Hspice
Manual [14], methods for fixing this problem were found. The first and more ideal way is to use initial conditions for any node that might float on startup. The other is to add conductance
0.5uU) and capacitance (~ 1fF) from every node in the circuit to ground. This helps stabilize the circuit during transient simulation. However, this method could cause problems if the conductance and capacitance interferes with normal circuit operation. The final receiver design Hspice simulation uses initial
57

conditions and 1fF of capacitance at all nodes to ground.
Careful sizing of transistors is required to ensure balanced switching thresholds. Balanced switching thresholds are crucial to the design methodology of biasing every amplifier's output at VDD/ 2
.
Figure 4-6 shows a comparison between balanced and unbalanced swithing thresholds. The first example has an input signal biased at 0.9V
and an amplifier with a balanced threshold at 0.9V. The second has the same input signal passing through an amplifier with a switching threshold at 0.8V. The DC voltage difference between the input signal bias and the switching threshold is amplified.
The output signal ceases to be centered at 0.9V.
1.5
-
Amplification of 3 With Balanced Switching Thresholds
-Input
--- Output-
0.5
1
0
0
10 20 30 40 50 60 70 80 90 10 0
Amplification of 3 With Unbalanced Switching Thresholds
1.5 -
1
0.51
10 20 30 40 50 60 70
--
Input
Output
80 90 100
Figure 4-6: Balanced and Unbalanced Switching Threshold Comparison
There are two crucial circuit blocks that require balanced switching thresholds.
In the high bandwidth cascode voltage amplifiers, the sizing of the transistors in the
58

signal path is crucial to keeping them in saturation. This must also be done with each inverter amplifier to ensure equal switching between the PMOS and NMOS devices.
In both these cases, unbalanced switching thresholds result in duty cycle variation and, in extreme cases, a complete loss of functionality. For these reasons, special emphasis is put on the sizing of transistors.
-
One of the keys to variation independence is having a solid central voltage reference
(Section 3.6). Originally, the bandgap circuit used in this thesis was seen as impractical because of the bipolar transistors needed to make it work. Instead, a self biasing circuit (Figure 4-7) was used as the central voltage reference for the receiver.
reset
Vdd High (3V)
30u/.45,u mrb lu/.18u
Vdd
4 3CU.45u
Ibias
30u/.45u
u/ .45u
3k
.4 u
Figure 4-7: Self Biasing Voltage Reference
This circuit relies on current mirror PMOS devices to equalize the current in both legs. The voltage drop across the resistor will be balanced with the gate to source voltage of mrnl. The current flowing through each leg will be that voltage divided by the resistance.
59

This circuit has two stable operating points. One is when the voltage on both sides of the resistor is at ground and there is no drain to source voltage across mpl.
At that point, no current flows through either leg and a useful voltage cannot be extracted. The other operating point occurs when the voltage across the resistor is larger than the threshold voltage of mnl. That voltage can be fed into the gate of another NMOS device to create a useful current reference. To make sure the circuit is in this operating point, mrb and mrc are added as reset devices.
One of the largest advantages of using this circuit is its power supply independence.
If VDD changes, the voltage across the resistor will remain nearly constant because of the high output impedance of the transistors. However, because this circuit relies on matching a VGS with a resistance, it performs poorly when faced with threshold voltage, channel length, and resistance variation.
Variation % Var. Change % Bandgap Change % Self Biasing Change
Al +10% 0.25% 4%
V 1 th
+10% 0.27% 5%
VDD
Temperature
Resistance
+10%
+100%
+10%
1.02%
0.54%
0.016%
0.2%
1%
7%
Table 4.1: Comparison Between Bandgap and Self Biasing References
Table 4.1 compares the performance of the bandgap and self biasing references under variation. The bandgap reference is clearly far superior with respect to all these variations except power supply deviations. This weakness of the bandgap approach is corrected with the addition of the voltage regulator described in Section 3.6.1.
4.7
This chapter has covered the special considerations and decisions that were made in the design of the optical clock receiver. Previous to this, Chapter 3 discussed its full design and operation. Next, in Chapter 5, the performance of the receiver design will be analyzed with respect to variation dependencies.
60

If all process and environmental parameters were kept constant over every receiver in the chip, skew between recovered clock signals would not exist. In reality, however, variation in these parameters creates non-zero skew. Variation analysis for the purposes of this thesis focuses on intra (within) die variation and will not include analysis of the waveguides and photoemitters.
The first section will describe how functionality is affected by realistic input signal changes. Sensitivity analysis has been performed on the receiver circuit. Next, the effects of various process and environmental variation is observed. In each, the effects of perturbing the variation source are compared to a nominal, variation free, output.
The nominal input signal is a 1GHz, 10pA peak-to-peak square wave. The photodiode is modeled as an ideal current source in parallel with a 100fF capacitor. Tests on input frequency, photodiode capacitance, realistic photodiode input waveform, realistic photodiode model, and input signal intensity are performed to analyze the non-idealities of the input waveform and photodiode model to ensure functionality.
61

The first test is to determine if the circuit will still function at lower frequencies and larger photodiode capacitance. The circuit must function at lower frequencies in case the test equipment itself cannot operate at 1GHz. Figure 3-11 shows that in the
100MHz band, the linear portion of the circuit actually has more gain. Therefore, when simulated at 100MHz, the receiver circuit will not only function, but the output waveform will have faster rise and fall times. Running the circuit at a slower clock speed might also be a valid application to reduce power consumption across the total chip.
Also, the full implementation of this circuit must operate with either Si or GaAs photodiodes. The silicon photodiodes have large amounts of capacitance (1pF) associated with them. The input photodiode capacitance is a limiting factor in the speed of the entire receiver design. This capacitance creates a large dominant pole at the front of the receiver, resulting in an immediate reduction in bandwidth. This will ultimately cause the receiver to not function properly at 1GHz.
'
-- ---- ara
1.8706u
1._7_4uThis
100f
1.8708u t1.1
1.871u
-oo----- ~--- --
F------------i
1
8712u
1.87141
(ti) (TIME)
1.8716u i.871ku
'J
1 U72u 1.8722u
1.87241
2.E6u 2.C0tz 2.S1u 2.512u 2.614u 2.C16u 2.618u 2.62u
Tkne (Ib) (TIME)
2.622u 2.62*1 2.62Ev 2.62ku 2.631 2.632u
With Input Capacitance Variation
Figure 5-1: 100MHz Output Waveform
100ff'
The circuit input is successfully capacitance also functions when
(generally simulated achievable with the photodiode capacitance a 100MHz with GaAs input signal photodiodes). is increased to lpF and the assumed
The circuit
(Figure 5-1),
62

El which is a typical capacitance with Si photodiodes.
Section 2.3.1 covered the non-idealities of a real photodiode. Because of the slow carrier low frequency gain, the nominal square wave input current waveform will be distorted to the waveform in Figure 5-2, using the extended equivalent model of
Section 2.3.1.
10 ........... ................ .............. .............. ............. ...........
... ... .
. ................ .......
... .
I~
.............................. .............................. ..............................
0 0.5 1 1.5
Orm (no)
2 2.5
Figure 5-2: Realistic Photodiode Input Waveform
1.57
1.5
0
Nominal
--.-
..... . .
.
..----------.---------------
21672n 216.74n
216.76n 216.78n 216
______________________________
-.-.-.-.- -.--
1 -------n
216.82n 216
84n
216.6n 216.Aln 216.9n 216.92n 216.94n 216.SWn 216.90n 217n
Tlma
(In) (TIME) m
~ ~.. ~ _____ _________________________
....... r --- --------- -
500M
233.2n
. . . i . s . . i . i e . i . a . . 1 . .... 1....... '.
233.4n 233.Gn 233.hn 234n 234.2n 234.4n 234.Sn 234.Sn
Thue (In) (TIME)
235n
.I '' '
235.4n
23 . n 2 ; 236
I
Figure 5-3: Output Waveform Due To Realistic Photodiode Input Waveform
63

When simulated with the more realistic input current waveform at 1GHz, the receiver circuit can still recover a square wave clock (Figure 5-3). The time delay between the waveforms is due to the fact that the realistic current waveform has diminished non-fundamental harmonics. This contributes to non-zero rise and fall times as the input waveform is amplified.
The nominal receiver simulation does not include a complete photodiode. Two additional resistances are added in this section to reveal a more detailed photodiode model (Figure 5-4). The
Rdak resistor appears in parallel with the current source and capacitor. It represents the non-zero dark current that flows when the photodiode is reverse biased in the absence of light. This is represented by a small signal resistance of 100kQ. The Rcontact resistor is represents the series resistance of the n+ and p+ highly doped regions and the resistance of the metal-silicon junctions. This resistor is represented with a 50Q series resistor.
Iphoto
Rcontact
Cdiode Rdark To Receiver
Figure 5-4: Detailed Photodiode Model
Figure 5-5 shows the output waveform that results from the detailed photodiode model. No significant difference is present when this waveform is compared to the nominal output waveform.
Variation is likely to exist in the intensity of the signal that the waveguide feeds to the photodiode. This type of variation is a serious concern for this receiver circuit, as it causes both skew and change in duty cycle (Figure 5-6). Because of the change
64

1
1.2 .
.
.1..
-. ------- --- -- -
.- ..
-. -- ----
-------
---
-- -
----- ---
L .
I
t4------ ------
..-. -
-----
--
- -
..
. .
meas. reme. t r s...tb ad Is d Tab-e- 5.1
of. d a...rate
4...
-------- - - --------. .
.. D -. .....-
-- -----an
T
7 es~scif E.Stl
476.6
47562
~~~~~~~~~~~" ~ ~
400 .
.
7 476.On 47.0n 76 n 2% .7 76.72n476.7'u 7976n 4
~ ~ ~ ~ ~ ~ k (in
.... ..... ... ..
M,6n7S 476.n47.2 765
Figre
2 2 3 25.n 25.
-:OtutWvfrmUigDeald..tdo n
2*'Z
5.21S In 6.n 262n 21.5.n 3.
8.2n
237.* 27.S n27
235.7.2n 237.0 2 7.3n
Th. ((i)
(IME)
217.St oe
88
0 ..............
.
Figure 5: Outut WaveformDe Usin Deptaiged Photodide Modeli
3IA
.'UA jU
I
----- ----
'
----
----.....-..-................... ...........................
I
285 2 n 4766n 4OS.a 28.8,466i A't 2Mb 206
This (151) (TIME) ofle duyndce anccusrtet meurementavform.e antb n Zn 264 0.S 0.u 7 M 207.2 n 20 n5 20Mn 20% 76 2nn94 ae.Ised dslays, the chne inputcyet wshaed the uty w yavefr is dchangsed.Thrar
al .
curen is too. low the linear. amlfir will voltage leel above--- the inverter noise..--------- of-------
6 5- --
T ee-r
----

I7(uA) Duty Cycle % High
3 48%
10
20
30
48%
44%
40
50
40%
37%
34%
Table 5.1: Duty Cycle Changes Due to Input Signal Intensity two reasons for this. The input stage bias current is only 54pA. If the input current becomes too high, it will become a significant fraction of the input current and the small signal approximation will be violated. This will change the operating point and cause non-linearities. To design against this problem, the input stage bias current would need to be increased. However, this will either lead to added power dissipation or lower gain due to the current mirror amplification of the transimpedance amplifier
(Section 2.3.2).
The second reason for the duty cycle change is the cascode architecture of the high bandwidth voltage amplifiers. The cascode architecture allows for asymmetric clipping. This will also contribute to non-linearity before the signal is railed in the inverter output stage.
In the previous section, the effects of realistic operating conditions with relation to input signal and photodiode variation have been discussed. In this section, the two dominant variation sources from the processing of the silicon are analyzed. Because it is difficult to design against these variation sources, they are the dominant sources of skew in this receiver design.
66

The MOSFET channel length is typically the smallest manufactured dimension on the chip. Because of this, it is especially prone to lithography and etch errors during fabrication. In this test, all devices (both PMOS and NMOS) changed together.
Figure 5-7 and Table 5.2 summarize the skew generated from channel length variation.
Note that only positive percentages are tested; simulations for -5% and -10% failed because the models are not defined below the minimum device sizes.
.10% -
68.3
16835n
68At168An
16.5n
6 -8.5
1
TIMe (in) (TIME)
8.5
Xi.5n
168.7n 168.75n 188
6 5 6.n189n
19
11
I
0
---- r
221.2n 2214n 221.6n 221.An 222n 222.2n 222.4i 222.6n 222.
(& ) (TIME) n
2l3n 2232n 223An 223.6 223.Kn 224
........ ..... ....... .....
Figure 5-7: Output Waveform Due To Channel Length Variation
% Variation From Nominal Skew
+5% +20ps
+10% +80ps
Table 5.2: Skew Due to Channel Length Variation
There are two ways to design against channel length variation. The first is to make the performance of the circuit dependent on the ratios of channel lengths instead of their absolute values, to take advantage of beter local matching of channel lengths (compared to global or within chip channel length variation). This is done in areas such as current mirrors. However, this design practice has limited application.
Another approach is to scale the (!) ratio of sensitive transistors. To first order, this
67

should have no effect on normal circuit operation while reducing the sensitivity to channel length variation. This design practice has limitations also in that increasing the ratios adds significant capacitance to adjacent nodes. This leads to a degraded frequency response and in some cases, instability. Both these design methodologies are used as much as possible in the receiver design.
Threshold voltage variation is caused by a variety of factors. The most dominant cause of Vth variation is ion implantation and doping level variation. Figure 5-8 and
Table 5.3 summarize the skew generated from threshold voltage variation.
1.5
1.5
0.
~Nomhinal t-1%
--
-- ----
-
1
.
--
160.7n 16072n 16074. r
160761
------
16078 160 81
- -e (in) (TIME)
160.821
..
160.84n 16086
%e Varation
160.84n 1609 160.92n
-- -- -- -- ---
.
L ---
./
.
1 ..
- - -
__.
- - - -
500M
143.2n 143. 143.6n 143.;n 144n 144.2n 144.4
Tknm
144.6n
(in) (TIME)
144.8n 145n 1452n 145.41 145.6n 145.8n 146n
Figure 5-8: Output Waveform Due To Threshold Voltage Variation
Variation From Nominal Skew
+5%
+10%
-5%
-10%
-20ps
-55ps
+20ps
+70ps
Table 5.3: Skew Due to Threshold Voltage Variation
Overall, this is the most difficult variation source to design against. However, there are methods to somewhat reduce its effect on circuit performance. First, nothing in
68

the circuit should be dependent on a DC VGS drop. This eliminates the use of typical source follower buffers. Next, in common source type amplifiers, the input VGS should be kept much larger than Vth. This will ensure that the transistor is strongly inverted and will reduce the sensitivity to threshold voltage variation. Both of these design methodologies are used, where applicable, in the receiver design, resulting in the sekw results shown in Table 5.3.
After the circuit is fabricated in silicon, its performance is affected by certain environmental factors, particularly power supply and temperature variations. However, additional design techniques are used in the receiver design to minimize skew in their presence.
Across the chip, the power supply can easily vary up to 10% in either direction. Ripple is often caused by switching logic and IR drops can cause DC shifts in VDD. Sam's variation analysis [3] showed that power supply was the largest form of variation for her particular design. The new proposed receiver design uses a linear voltage regulator to control the power supply that the signal path sees (Section 3.5). Table
5.4 shows that the current receiver design performs remarkably well with respect to
VDD variation.
% Variation From Nominal Skew
+5%
+10%
-5%
-10%
-3ps
-20ps
+
0
.5ps
+24ps
Table 5.4: Skew Due to Power Supply Variation
69

H
500M
0
-5%and Nn10%
- ----
------.-------
.. ..
4.3W 24.765n
214.7Tn
214.775n 214.78n 214.785n
214.7;n
214.795n
214.fn
T-mn(in) (T1ME)
214.61n
214.815n 214.J2n
214.025n
214.M3n
214.35n
214. 4 gW
------ ---- ---------
~......................
6.n
19
6.n
1
9An ; lime (in) (TIME)
I
.in 176n 17d.2n 17dAn 17-0A .
.1-7.0...171n
Figure 5-9: Output Waveform Due To Power Supply Variation
It is difficult to predict how much temperature will vary without knowing the surrounding circuitry. Across a chip, hot spots may force certain receivers to perform at temperatures much higher than nominal room temperature. The addition of the bandgap reference significantly reduces ths receiver design sensitivity to temperature.
Table 5.5 demonstrates insensitivity to temperatures up to 200% higher than ambient temperature (25 C
0
).
% Temperature (
0
C) Skew
0 (-100%)
50 (+100%)
75 (+200%)
+
-5ps
18 ps
+36ps
Table 5.5: Skew Due to Temperature Variation
5.4 Summary
The newly proposed receiver design performs well under realistic operating conditions and environmental variation. It is still sensitive to process variations such as channel
70

I III
1 --- --
... 0
T
25 dog Com na -- -- - .- .. -- --- C --- ----------- ----------- - -
.
- -- -
341.765n
341
77n
341.779n
0
341.7k
341.785n
1;7Tkn
341791 341.7991 341.9n
(ibn) (TIME)
341.80R 341.S1n 341.m1n
341.52n 341.825n 341.83n
F
1.5 rr
Yr
50 ----- -----. r.. .............
420.n 40.9 r D:e T.. Tem-ra--
----------------------------- --------...
..
.
:
......
41.C 42hu 22n 422.2n 422.4n 422.91 422.91
Tkm (1n) (TIME)
423n 423.2n 423.n 423XW 43
.I-
Due To Temperature Variation
Figure 5-10: Output Waveform length and threshold voltage; however, these dependencies produce skew within the acceptable limits. The conceptual design of the optical clock receiver has been completed. In the next chapter, the actual layout implementation of the circuit will be discussed.
71

72

This chapter presents an overview of the optical receiver circuit layout in silicon. The process of converting the circuit from netlist to a practical layout will also be covered.
Hierarchical construction and analysis is used to reduce the overall circuit into several managable blocks. Finally, the circuit blocks are pieced together to form the total layout of the circuit. This layout is extracted and simulated to verify functionality.
The inital design and functionality verification is done using Hspice, as described in
Chapters 3 and 4. The layout is constructed in Cadence. Several steps need to be taken to convert the Spice deck into a Cadence layout.
First, a Cadence schematic representation of the receiver circuit is needed. The
Spice netlist must be manually entered into a new schematic view in Cadence. This schematic should then be simulated in the analog environment of Cadence. However, this step was skipped and as a result, simple connectivity problems were later found.
Once the schematic is entered into Cadence, a primitive layout can be generated from the schematic source. This layout contains the transistors and passive devices of proper size and shows connectivity between nodes. The next step is to place and route all elements in the circuit.
After the layout is completed, the design rule checker must be run to catch viola-
73

tions. Next, the layout vs. schematic checker can be run to check node connections.
This last step was skipped also due to problems with certain parameterized transistor definitions. This will be discussed in Section 6.2.
The circuit layout is then extracted with parasitics. The Analog Artist tool is used to generate a partial, but sufficient, netlist, and this netlist is then taken and formatted to be compatible with Hspice. A full Hspice simulation can then be run to verify layout functionality.
The receiver layout complies with the TSMC 0.18p MOSIS design rules. However, the library files obtained from MOSIS for this work were not complete and needed to be altered. The cmospl8 and analoglib (generic analog components) were the main libraries available. The cmospl8 library contained the symbol and simulation information for all devices (active and passive). The layout for each device needed to be copied from the analoglib library and linked to the symbol through a new schematic. After this was done, the device was ready to be used in Cadence.
Two additional modifications have been made to complete the cmospl8 library.
First, the layouts for capacitors and resistors have been altered. The capacitor layout view has been changed into an M2 M3 structure to allow for stacking above active devices and therefore, area reduction. The resistor has been changed from a poly resistor into an N-well resistor to yield larger resistors.
In addition to altering the passive devices, the active devices have also been changed to accommodate transistor fingering. The fingering of MOSFET's is a technique used to break large devices into smaller ones. The smaller devices are placed side by side and share sources and drains in an attempt to reduce parasitic capacitance. However, Cadence will not support a simple placement of transistors directly next to each other. Therefore, a special parameterized layout cell is needed to allow transistor fingering. Fixed finger, four gate, NMOS and PMOS devices have been constructed. Although these devices performed properly after extraction, Cadence
74

still views each as four devices. Because of this, the layout vs. schematic check fails.
Instead of fixing this immediate problem, a simulation of the layout extraction was used to verify circuit connectivity and functionality (Section 6.3.9).
The final addition to the cmospl8 library is a parasitic bipolar PNP transistor.
No layout view exists within either library. A new layout for the PNP has been constructed using the design rules as a guide.
The layout design has been performed in a hierarchical fashion. First, the small opamp blocks are laid out. Next are the larger sub-blocks (transimpedance amplifier, high bandwidth voltage amplifier, output stage, bandgap reference, and linear voltage regulator). Finally, each sub-block is connected globally and the biasing transistors are added.
The folded cascode opamp (Section 3.1.2) layout uses all fingered devices. Its layout is simple and corresponds directly to schematic placement. Figure 6-1 presents a guide to the layout (Figure 6-2).
Biasing Biasing
Ac yve cas ode
Load ni ntiFolded as ode
Fe ces
Figure 6-1: Guide to Folded Cascode Opamp Layout
75

Figure 6-2: Folded Cascode Opamp Layout
Active Load
Stag
Figure 6-3: Guide to Two-Stage Opamp Layout
The two-stage opamp (Section 3.1.1) layout is again very simple and similar to schematic placement. This circuit requires a resistor and capacitor that are constructed next to the active devices (Figure 6-3). Figure 6-4 shows the layout for the two-stage opamp used as buffers in the feedback biasing stages. Figure 6-5 presents the layout for the opamp used in the bandgap reference.
76

Figure 6-4: Two-Stage Opamp Layout
Figure 6-5: Two-Stage Opamp (within Bandgap Reference) Layout
77

The transimpedance amplifier (Section 2.3.2) layout includes the first voltage amplification stage and consists of the input bias transistor, mirror input transistor, cascode amplifier, two-stage opamp buffer, low pass filter, and folded cascode opamp
(Figure 6-6). The low pass filter requires large resistors and capacitors so the layout area is dominated by the passive components. The resistors are laid out adjacent to each other to promote matching. Figure 6-7 shows the complete layout for the transimpedance amplifier.
100k Ohm N-Well Resistor
100k
Ohm N-Well Resistor
2nF MOS Capacitor
TIA
Two-Stage
Opamnp Folded
Cascode o-
Figure 6-6: Guide to Transimpedance Amplifier Layout
As stated earlier, the transimpedance amplifier contains the first voltage amplification stage. Therefore, the second high bandwidth voltage amplifier (Section 3.3) layout, as seen in Figure 6-8 looks almost exactly like the first. The only difference is the lack of input bias and mirrored input device.
The output stage (Section 3.4) is simply a chain of progressively sized inverters. The first four are small enough to construct with single gate devices but the last inverter is large enough to use fingering. The layout for the output stage is seen in Figure 6-9.
78

Figure 6-7: Transimpedance Amplifier Layout
The voltage regulator (Section 3.5) layout, shown in Figure 6-10, is simply an opamp connected to a very large power FET (top-right of the circuit). The FET is fingered but still dominates the area of the sub-circuit. This circuit, with the appropriate biasing transistors, is the only circuit that sees the VDDhigh power line.
The bandgap sub-circuit layout is the most diverse: in addition to using an opamp, it uses three resistors and two parasitic PNP bipolar transistors. The resistors are laid out directly next to each other to promote matching in the face of process variation.
Figure 6-11 presents a guide to the layout (Figure 6-12).
After all the sub-circuit layouts have been constructed, the final layout of the full receiver is completed. Figure 6-13 describes the placement of the sub-circuits. After
79

*fl'~i 1 -
Figure 6-8: Voltage Amplification Stage Layout
.",
Figure 6-9: Output Stage Layout
I
K t", a,:,? -r.62-1 11.jr a."
.............
Figure 6-10: Linear Voltage Regulator Layout
80

.,Mb~I ~* ~ ~
Two-Stage
Opamp
61k Resistor
PNP PNP
Figure 6-11: Guide to Bandgap Reference Layout
X t
t e '.N
---i
Figure 6-12: Bandgap Reference Layout
81

the sub-blocks are laid out, the biasing transistors are added. Each transistor of the biasing network is placed in a row to ensure proper matching. The biasing row is placed in the middle of the full receiver so that certain references have a central distribution point.
Bypass capacitors are added on the power supply and at noise sensitive nodes.
The capacitors are a combination of MOS capacitors and stacked Mi M2 M3 capacitors. They fill the empty space within the layout. Note that the voltage regulator does require an external bypass capacitor on the power supply line.
The final receiver design, without the photodiode, is 205.5pm x 170.0pm or
0.035105mm
2
(Figure 6-14).
Transimpedance
Amplifier
High Bandwidth
Voltage Amplifier
Output
Stage
Biasing Transistors
Voltage
Regulator
Biasing
Bandgap Voltage
Reference
Figure 6-13: Guide to Full Receiver Layout
Once the entire circuit has been laid out, the design rule checker is run. The final design is DRC clean except for one pair of warnings. These warnings apply to the
N-wells of the parasitic PNP bipolar devices. Normally, the N-well is tied to the most positive potential to ensure that the PN junctions formed with the diffusion and substrate do not forward bias. However, the bandgap circuit relies on the PN junction between the emitter and base turning on. Therefore, this feature is desired
82

U[an iiI~Ii.
x
... ... ... ..
.. . . .
.. .. .
C
I
-ramen ..- -.-.--.--.......---
T
---
1r
L.
-
~1 fl~U
I a u
I ... ....
II
N,
A
L
JEA
LMU z
1.
Ir
P'.-..J
r..
--0 -. , . ns t
*
1]
.
*1
Figure 6-14: Full Receiver Layout
83

and the warning is ignored.
Next, the circuit is extracted, including the extraction of parasitic capacitances.
The Analog Artist tool of Cadence is used to generate a netlist from the extracted view. The netlist only contains resistor nodes; it does not contain resistance values.
The resistance values, however, are present in the extracted view. In addition, the bipolar devices are completely absent from the netlist. These problems are the result of an incomplete set of library files. Both the resistor and PNP libraries have been altered during this project because of their lack of cell views. To complete the netlist, these elements are entered in manually, in order to create an accurate netlist.
The netlist is put into Hspice format and simulated. The output waveform that results from the layout extraction simulation is seen in Figure 6-15. In this figure, the waveform is compared to the original Hspice simulation. The overall shape of the extracted waveform matches the Spice simulation but there are minor differences in duty cycle and time delay. These deviations are caused by sizing differences between the original simulation and the layout implementation. Because the two waveforms of Figure 6-15 match, the layout of the optical clock receiver is verified.
1.0
------ f. .---- ------- -- .-
1.4 -- - - ------ - --
Hspice mgaton.
.
- --
Extracton
Sinm aion
--- ---- ---------
Boom --- ,
269.2n 269.4n 269-n 269.in 27 n 270.n 270.n 270.n 270...n 271n 271.2n 271.4n 271.Sn 271. n
272n lime (hin) (TIME)
Figure 6-15: Layout Extraction Simulation Output Waveform
84

This chapter is devoted to the strategy for testing the optical receiver circuit. The actual fabrication and testing of the chip has not been completed as part of this thesis, and is expected to be accomplished in future work in parallel with on-chip optical data receiver research [15]. The testing strategy for the optical clock receiver circuit in this thesis is catered to demonstrating full functionality rather than measuring actual skew.
Special issues must be considered because the circuit receives and processes a clock signal at 1 GHz. A 1 GHz signal is very difficult to measure using conventional methods because of the parasitic capacitance in the pads and probes. Special non-intrusive or ultra-low capacitance equipment can be used to measure the high frequency signal.
This method is very costly and not available for this project. Alternatively, a special circuit can be built to process the receiver output signal. This circuit can be as simple as a frequency divider that outputs a frequency at a lower, more measureable, clock speed. A more sophisticated circuit can be built that actually compares two receiver outputs to determine skew [16]. Such a circuit can then output the skew data at a much slower rate. When adding circuits to the outputs of the receiver, special attention must be taken to ensure that the post-receiver circuits themselves do not
85

add skew.
To test the receiver in this thesis, a simple frequency divider should be built.
After frequency division, a progressively sized inverter chain should be added to drive each pad. These circuits should allow the receiver to be tested with conventional non-specialized equipment.
Skew measurement should be the main focus on the second run of the chip. This chip should contain multiple identical copies of the circuit to test the effects of variation across the chip.
On the current test chip, several replicate copies of the receiver should be used to test functionality. Ideally, each sub-block of the receiver design should be tested to ensure individual functionality. After that, any difficulties can be attributed to biasing or interfacing. Since this approach is not practical, an alternative strategy is to use external stimulus to simulate various sub-blocks of the receiver. The following variants should be used in the final chip layout.
Since the voltage regulator dissipates a lot of power and requires an external bypass capacitor, a single voltage regulator should supply the power supply line to multiple receivers. A pair of receivers should be built to share a single voltage regulator.
One copy of the receiver should have an exclusive voltage regulator. This will reduce loading on the regulator significantly.
86

On one of the variants, the voltage regulator should be entirely removed and an external 1.8V power supply line should power this receiver. This will test for voltage regulator defects.
The bandgap reference should be bypassed and an external 1.243V reference should be added to this variant. This will test for defects in the bandgap reference.
A single receiver should be added with its input node connected to a pad instead of a photodiode. A pulse train of current can be used to test receiver operation. This will test for photodiode defects. However, because of parasitic capacitance in the pad, the speed that the receiver can be tested at will be limited.
Instead of using a current pulse train to test the receiver, a voltage input can be used in place of the photodiode. To enable this feature, however, the input biasing transistor and the first input mirror transistor need to be removed. The voltage should be inserted into the gate of the first cascode input transistor, and it should be a small voltage pulse train with an appropriate DC bias.
Both silicon and GaAs photodiodes will be used in the test chip. Multiple copies of each photodiode-receiver set should be built to account for photodiode defects.
Depending on the space constraints on the chip, one of each photodiode could be used for each of the above variants.
87

As discussed in Section 5.1.1, the circuit should also operate at a clock speed of
100MHz. Therefore, in addition to testing at 1GHz, a 100MHz signal may also be used to verify functionality of the receiver.
The final chip should include as many variants as the chip area permits. Each variant should have a frequency divider and inverter buffer pad driver. If there are more variants than can be supported with pads, an analog multiplexing scheme can be used before the pad drivers. This testing strategy will be capable of demonstrating functionality of the receiver in the fabricated chip.
88

This thesis has presented a design for a fully functional optical clock receiver operating at 1GHz. A layout has been constructed in Cadence and its extraction has been successfully simulated with Hspice. The result is a circuit that converts an optical signal into a rail to rail voltage clock signal. The receiver awaits fabrication.
Sensitivity analysis of receiver variation dependencies reveals that process variations including threshold voltage and channel length have the greatest impact on skew. The receiver performs remarkably well through environmental variations in power supply voltage and temperature. Performance is not affected significantly when non-idealities in the photodiode and input signal are added to the model.
Several ideas were generated during this thesis but were not included because of implementation problems or time constraints. These ideas present alternative approaches that may be used in future designs.
89

This technique uses a floating bias for an NMOS input single stage analog amplifier.
The bias tracks the power supply so that the VGS of the load remains constant.
Ideally, a voltage source would connect the power supply to the load transistor's gate. Instead, a diode with a DC path to ground can be used as a voltage source.
By keeping the load transistor's VGs constant, the gain of the amplifier will become less sensitive to power supply variation. This technique can be used in the voltage amplification stage instead of using feedback biasing (Section 3.3.2).
Another method that was considered for reducing skew was to use a stage with tremendous gain to amplify the small voltage signal off of the transimpedance amplifier. That signal would then be hard limited at the rail voltage. If the input signal were centered around a constant DC voltage, skew would reduce with increasing gain. As long as the gain is large, the actual magnitude of the gain is not of concern.
Many existing discrete optical amplifiers use resonant tanks [4]. This concept can be applied to a single chip design using the spiral coil inductors found on newer processes.
Resonant tanks allow an extension in a normal linear amplifier's bandwidth. This provides higher gain at a higher frequency. However, it is non-trivial to use these amplifiers within a feedback loop as the inductance causes many adverse phase effects.
One of the largest challenges for this design and future optical clock receivers is the high frequency of the signal. As demands for faster and faster clock speed increase, the traditional strategies will fail to provide useful designs. One technique that can be used is to optically distribute a slower multiple of the high speed clock, convert
90

the signal to a rail to rail voltage, and then use a phase lock loop (PLL) to frequency multiply the signal to the desired frequency. In this case, the skew of the receiver will be multiplied and the PLL itself may add skew. However, the bandwidth demands on the receiver will be significantly lower and low skew architectures may be used.
Although this thesis presents a fully functional design, several aspects may be pursued to build on this work.
The receiver was designed using a 0.181L process. A move to a smaller process would increase the speed of operation for the receiver by allowing higher bandwidth amplifiers.
This design was focused on achieving functionality at 1 GHz. Therefore, it may easily be optimized for power consumption and area. Additional work may also be done to decrease its sensitivity to process variation.
Finally, the frequency of the optical distribution network will not be limited by the receiver design; rather it will first be limited by the photodiode. One option is to use special layout techniques such as fingering or spatial modulation [10]. However, these techniques will eventually be limited. Instead, integration of CMOS circuits with alternative materials to silicon need to be investigated in order to achieve a fast photodiode design.
The fundamental goal of this thesis research has been to explore a robust, high performance, standard CMOS circuit design for potential use in on-chip optical clock distribution. The key challenges are high speed and low skew. Previous work by
Sam [3] indicated that process and operating environment variations can induce large skew in a baseline optical receiver design. In this work, we have contributed a new design that features a balanced DC biased signal path using the feedback biasing
91

technique. The design also includes power supply regulation and a variation independent bandgap voltage reference. Given integrated high performance photodiodes
(requiring SiGe or GaAs), the proposed circuit is expected to achieve robust and low skew operation at 1GHz. Future fabrication and testing of the circuit will evaluate this performance. Additional investigation of methods to further reduce the effects of process variation induced skew is also needed to achieve even higher optical clock receiver frequencies.
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[8] A. Verma, A. Chatterjee, and B. Bhuva. All Si-based Optical Interconnect for
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[11] David A. Johns and Ken Martin. Analog Integrated Circuit Design. John Wiley and Sons, 1997.
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[14] Avant! Star-Hspice Manual Index. http://www.ece.orst.edu/~moon/hspice98/.
[15] Michael Mills. An On-Chip Data Transmission Ciruit. Master of Engineering
Thesis Proposal, Massachusetts Institute of Technology, Department of Electrical
Engineering and Computer Science, May 2001.
[16] V. Gutnik and A. Chandrakasan. On-chip Picosecond Time Measurement. Sym-
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[19] Paul R. Gray and Robert G. Meyer. Analysis and Design of Analog Integrated
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