An Evaluation of Indium Antimonide Quantum Well Transistor Technology
By
Jingwei Liu
B. Eng., Electrical Engineering
National University of Singapore, 2005
Submitted to the Department of Materials science and Engineering in partial
fulfillment of the requirements for the
Degree of
Master of Engineering in Materials Science and Engineering
At the
Massachusetts Institute of Technology
MASSACHUSMTS INSTTUTE
OF TECHNOLOGY
September 2006
OCT 0 2 2006
© 2006 Massachusetts Institute of Technology
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The author hereby grants to MIT permission to reproduce
and to distribute publicly paper and electronic copies of this
thesis document in whole or in part in any medium now
known or hereafter created.
Signature of Author:
Department of Materials Science and Engineering
August 11, 2006
Certified by:
rti by:Thomas W . Eagar
Professor of Mat ials Engineerng & Materials Systems
/
Accepted by:/
/
Thesis Supervisor
rSamuel M. Allen
POSCO Professor of Physical Metallurgy
Chair, Departmental Committee for Graduate Students
ARCHIVES
An Evaluation of Indium Antimonide Quantum Well Transistor Technology
By
Jingwei Liu
Submitted to the Department of Materials Science and Engineering
on August 18, 2006 in partial Fulfillment of the
Requirements for the Degree of Master of Engineering in
Materials Science and Engineering
ABSTRACT
Motivated by the super high electron mobility of Indium Antimonide (InSb), researchers
have seen great potential to use this new material in high switching speed and low power
transistors. In Dec, 2005, Intel and its partner, QinetiQ, Ltd, announced 85nm gate length
enhancement and depletion mode InSb quantum well transistors. Such transistors can
operate as high as 305GHz and power consumption is reduced by a factor of 10.
In this thesis, the emerging InSb transistor technology is discussed in details. Given its
superior performance, it may complement silicon transistor to extend Moore's law in the
next decade. The prospect of InSb transistor is also compared with other nanotechnology
transistors, such as carbon nanotube and silicon nanowire. Several potential markets are
figured out, namely, microprocessor, low noise amplifier and millimeter wave device.
Related patents are evaluated. It is found that most of the patents are held by Intel's
partner, QinetiQ Ltd. and thus patents issue would not block the launch of products. A
joint venture or strategy alliance model is proposed to reduce the risk of investment. In
addition, a cost model is presented at the end. It is concluded that cheap silicon substrate
and large enough production scale are two crucial factors for the commercialization
success of InSb transistor technology
Thesis Supervisor: Thomas W. Eagar
Title: Professor of Materials Engineering & Materials Systems
Acknowledgement
I would like to express my great appreciation to Professor Thomas W. Eagar (Supervisor),
Professor Wai Kim Chim (Singapore facilitator) and Dr. Larsson for their unreserved
suggestions and encouragement towards the improvement of the project.
In addition, I would like to thank Professor Eugene Fitzgerald and Dr. Arne
Hessenbruch's help on my project. I benefited a lot from their course 3.207 'Technology
development and evaluation' and other precious advice. Moreover, I would like to give
my appreciation to distinguished guest speakers of course 3.207. It is an eye-opening
experience to attend their speeches and I knew more about technology evaluation. Here I
also want to thank Dr. R. Chau and Dr. Suman Datta from Intel. They gave me precious
guidance in InSb technology application.
This thesis would not have been possible without the support of my family. They are
always there for me when I need them the most. Last but not least, I would like to give
my warmest thanks to the entire faculty of DMSE and anyone who is not mentioned here
but had helped me in one way or another.
Table of Contents
AB STR A C T ........................................................................................................................
2
A cknowledgem ent ......................................................................................................
3
Chapter 1 Introduction ...................................................................................................... 10
1.1 Background and Overview ..........................................................................
10
1.2 Properties of Indium Antimonide ................................................................
12
1.3 Business Plan and Cost Model.................................................
14
1.4 Scope and outline of thesis .....................................................................................
17
Chapter 2 Indium Antimonide Quantum Well Transistor .......................................
19
2.1 Structure of InSb QWFET ............................................................................
19
2.2 Fabrication of InSb QWFET..................................................
21
2.3 M echanism ............................................................................... ........................... 22
2.4 Performance of Transistor................................................. 24
2.4.1 Operating Frequency.................................................
24
2.4.2 Scalability ..................................................................... ............................. 25
2.4.3 Leakage Current and High-K Gate Dielectric .....................................
. 26
2.4.4 Power Consumption and Benchmarking .......................................... ...... 28
2.5 C hallenges............................................................................................................... 30
Chapter 3 Market Analysis and Competing Technology ..................................................
33
3.1 Interaction between Technology and Market .......................................... ...... 33
3.1.1 Technology Push and Market Pull....................................
............ 33
3.1.2 Product Life cycle .............................................................. ........................ 36
3.2 M icroprocessor M arket...........................................................................................
38
3.2.1 M arket summ ary ............................................................... ......................... 38
3.2.3 Players in market: Intel vs. AMD ........................................
.......... 40
3.2.3.1 Manufacturers in market ......................................................
...... 40
3.2.3.2 Current Technology and Competition ..................................... ... 40
3.2.3.3 Lawsuit between Intel and AMD ......................................
........ 44
3.2.3.4 Future of Intel's Strategy against AMD ....................................................
45
3.2.3.5 Other Processor Manufacturers in Market..................................
..... 48
3.2.4 Laptop: the Drive for Future Personal Computer Market................................ 49
3.2.5 Competing technology ......................................................
51
3.3 Low noise amplifier (LNA) market ..........................................
............ 55
3.3.1 Low noise amplifier summary .........................................
............ 55
3.3.2 Satellite Communication Market ........................................
........... 55
3.3.3 Phased Array Radar System...................................................................
56
3.3.4 Cell Phone M arket ............................................................. ........................ 57
3.3.5 Possible Market Demand for InSb LNA................................
......... 58
3.4 Millimeter Wave Circuit Applications.......................................
58
3.5 Competitors for LNA and Millimeter-Wave Circuits.............................
... 60
Chapter 4 Intellectual Property related issues...................................
............. 65
4.1 Patent filing.............................................................................................................
4.2 Patent search ................................................. ....................................................
4.2.1 Carrier extraction .............................................................. .........................
4.2.2 Field Effect Transistor ......................................................
4.2.3 Modulation Doped Field Effect Transistor (MODFET)............................
4.3. Joint Venture .................................................. ..................................................
4.4. Strategic Alliance............................................. ................................................
Chapter 5 Cost M odeling........................................... .............................................
Chapter 6 Conclusion and Future Work ................................................................
Appendix A: Spreadsheet for Cost M odeling ..................................... ....
..........
Appendix B: M arket Share Probabilities ..................................... .....
.............
Appendix C: Decision Tree Analysis .....................................................................
65
67
67
67
68
71
72
75
88
91
95
97
List of Figures
Figure 1: (left) Moore's law. Scaling of transistor size (physical gate length) to sustain
Moore's law, (courtesy of Intel Corp.); (right) InSb band gap versus temperature .......... 10
Figure 2: Total facility cost and normalized facility cost per unit from 1960 to 2010.
(Courtesy of IC know ledge)......................................... .............................................. 14
Figure 3 (left): Structure of InSb QW transistor; (right) Energy band gap versus lattice
constant of different semiconductor materials. InSb has energy band gap of 0.18eV and
lattice constant of 6.48A . ..................................................................................................
19
Figure 4: Schematic of the depletion mode and enhancement mode InSb quantum well
transistors. Transistor on the left is depletion mode, the one on the right is enhancement
m ode' ....................................... ............................. . . . ...... ................ .............. ............ 20
Figure 5: SEM micrograph of a two-finger InSb quantum well transistor with gate-bridge
at the mesa edge. LG=0.2 gm, LDS = 2.Opm........................................
21
Figure 6: Calculated band structure and SchrOdinger-Poisson solution of spatial
redistribution of confined carrier population in various sub-bands in the quantum well for
....
. . . . .... ...... 22
15% and 30% Al percentage barriers 8 .................. .............. . .....
20
Figure 7: (Top left) Hall Mobility data on directly doped and modulation doped 20nm
thick InSb quantum wells with 15% Al in the AlxInl.xSb barrier layer. (Top right) 20 Hall
Mobility data on modulation doped 20nm thick InSb quantum wells with 15%, 20% and
30% Al in the AlxInl.-Sb barrier layer. (Bottom left)' 8 Electron mobility versus sheet
electron density in quantum well. InSb QW has the highest electron mobility among all
the semiconductor materials. (Bottom right)' 8 Electron conductivity versus sheet electron
density in quantum well. Conductivity increases with electron density ........................ 22
Figure 8: (a)ID - VG transfer characteristics of 130nm Lg depletion mode and
enhancement mode InSb QWFETs; (b) Sub-threshold slope as a function of gate length
for depletion and enhancement mode InSb QWFETs; (c) Intrinsic cut-off frequency, fT,
for 85nm gate length depletion and enhancement mode InSb QWFETs at 0.5V Vds.
(from reference 16) ............................................... ..................................................... 25
Figure 9: (a) shows sub threshold slope versus transistor physical gate length; (b) shows
DIBL to gate length Scalability further improves by buffer dopant engineering(from
reference 18) ..................................................................................................................... 26
Figure 10: (left) Transfer characteristics of 85nm LG e-mode QWFET with LsD=0.75tm
(VDs=0.5 and 0.05V)16; (right) schematic of impact ionization18 ............... ........... . . .. ... 26
Figure 11: (left) schematic of InSb QWFET with A120 3 gate dielectric; (right) Room
temperature gate to channel leakage characteristics for ALD A120 3 high-k dielectric and
Al metal gate stack on AllInSb/InSb device layers showing four orders of magnitude
reduction in leakage compared to Schottky metal gate(from reference 18) ............. 28
Figure 12: (left) Room temperature C-V characteristics of AI/Al 20 3/AllnSb/InSb
MOSCAP with surface pre-treatment A; (right) Room temperature C-V characteristics of
Al/A120 3/AlInSb/InSb MOSCAP with surface pre-treatment B. (from reference 16)..... 28
Figure 13: Cut off frequency versus DC power dissipation. InSb e-mode QWFET has 10x
.......... ... .29
power reduction compared to 60nm gate length silicon MOSFET18............
Figure 14: (left) Transistor Gate delay (CV/I) versus gate length for InSb QWFETs at
VDs=0.5V benchmarked against state-of-the-art silicon nMOS transistors; (right)
Transistor Energy-Gate delay product (CV/I) versus gate length for InSb QWFETs at
VDS=0.5V benchmarked against state-of-the art silicon nMOS transistors. ( from
29
reference 16) ..............................................................
innovation.
stimulate
pull
to
push
and
market
Technology
Figure 15: Integrating
.
..
... ............ .........
33
Reprinted from the book "management of technology"25. ...............
Figure 16: Processor power as a function of frequency for two process generations....... 35
. . . . ... ..... 37
.............. .... .....
Figure 17: Product - Market Life Cycle 25 ..................
Figure 18: Worldwide microprocessor market revenue summary and prediction from
39
2005 to 20 15. .............................................................
............ 41
Figure 19: Intel market share by PC type .........................................
...............
........... ...
42
Figure 20: Intel market share by location 31.............
... ............. 43
Figure 21: CPU Manufacturer Summary .....................................
.......... 43
Figure 22: CPU manufacturer Desktop System32 ......................................
........... 44
Figure 23: CPU Manufacturer Portable System 32...............................
Figure 24: Intel Stock Performance from June, 2005-June, 2006 ................................. 47
Figure 25: AMD stock performance from June, 2005 - June, 2006 .............................. 48
Figure 26: global laptop market share (2003). Source: Gartner, IDC .......................... 49
Figure 27: US laptop market share for top companies (Q4 2003). Source: IDC WW
Quarterly PC Tracker, 2004...........................................
..................................
50
Figure 28: (a) Gate delay (intrinsic device speed, CV/I) versus transistor physical gate
length of NMOS devices; (b) Energy-delay product per product width versus transistor
physical gate length of NMOS transistors; (c) Sub threshold slope versus transistor
physical gate length. The planar and nonplanar Si FETs as well as the III-V planar
devices are n-channel transistors, while the CNT FETs are p-channel transistors ......... 53
Figure 29: (a) Gate delay CV/I versus Ion/Ioff. Comparison of 85nm LG InSb QWFETs
and Si MOSFET; (b)Gate delay versus on-to-off state current ratio o/IoIff of Si PMOS
transistors with Lg=60nm and 70nm at Vcc =1.3V, and a CNT PMOS transistor with
....................................... 54
Lg=50nm and V cc =0.3V43 .....................................................
Figure 30: A radar sensor used in 2003-model Mercedes S-class automobiles. The
circuits that transmit and receive millimeter waves are housed beneath the dome-shaped
plastic "radome," which is about 10 cm (4 inches) in diameter. This unit is mounted
. .. . . . . .. . . . .
behind a port5 ..................................
............ 60
Figure 31: Su Perior low-noise performance of NGST InP device to NGST GaAs
counterparts .........
............................................................
63
Figure 32: timeline to obtain a patent .........................................
............... 66
Figure 34: schematic of GaSb/InSb HFET .........................................
........................
70
Figure 35: IC m anufacturing....................................... ............................................... 76
Figure 36: monthly capacity of world top 5 silicon wafer manufacturers ..................... 77
Figure 37: the plot of cost versus production volume given the production capacity 5000
wafers/m onth ..............................................................
82
Figure 38: cost analysis given production volume 4500 wafers/month and production
capacity 5000 w afers/m onth. ....................................................
........................ 83
Figure 39: the plot of cost versus production volume given the production capacity 500
w afers/m onth..................................................................................................................... 83
Figure 40: cost analysis given production volume 450 wafers/month and production
capacity 500 w afers/m onth. ............................................................... .......................... 84
Figure 41: plot of cost versus production volume at different production capacity......... 85
Figure 42: Our Decision Tree Analysis for period. Highlighted in yellow is the best
strategy for Period 1 and in pink is our strategy ......................................
........97
List of Tables
Table 1: Electron mobility of different semiconductor materials at room temperature ... 12
Table 2: classification of product to determine royalty (courtesy of patent caf6) ......... 16
Table 3: Deposition layer variation of InSb transistor18 .................. ............. . . .. . . . . 19
Table 4: Microprocessor Market Summary from 2003-2007 .................................... 38
Table 5: R&D spending and revenue comparison of Intel and AMD fro 2004-2006 ...... 46
Table 6: Calculation of manpower needed in fab 64 .................... ............... . . . . .
81
64
..............
.
.
..
Table 7: Salary of different kinds of manpower in fab ......................
... 81
Table 8: Market share growth rate, market share percentage, and total units projected in
period 1, given low, medium, high scenarios. .......................................
.........95
Table 9: Probabilities of gaining low, medium, or high market share at $250 versus at
$350. Based on a 200M unit/year market ..........................................
........... 95
Table 10: Probabilities of gaining low, medium, or high market share at $250 versus at
$350 in period 2, given low, medium or high market share in period 1. Based on a 200M
unit/year market ................................................................................................................ 95
Table 11: Probability estimates for period two are based on the assumption that there is
high probability that if low market share is gained in the first period, low market share
will again be gained in the second period, if medium market share is gained in the first
period, medium market share will again be gained in the second period, and if high
market share is gained in the first period, there is a high probability high market share
will again be gained in the second period, it is based on a 200M unit/year market ......... 96
Chapter 1 Introduction
1.1 Background and Overview
InSb bandgap versus temperature
Wwxor
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'
S
LAW
warmaneandness
r-
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- 230
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: 220
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o
,200
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i
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:so*
i
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i
1910
1B~tl
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us 180
170
0
50
100
150 200
temperature(K)
250
300
350
Figure 1: (left) Moore's law. Scaling of transistor size (physical gate length) to sustain Moore's law,
(courtesy of Intel Corp.); (right) InSb band gap versus temperature'
The first practical point-contact transistor was developed by William Shockley, John
Bardeen and Walter Brattain in 1947 at Bell Labs. Over the years, transistors have been
divided into two categories: bipolar junction transistors (BJTs) and field effect transistors
(FETs). BJTs have three terminals, which are named emitter, base and collector. Two p-n
junctions exist in BJT. Similar to BJTs, FETs have also three terminals, i.e. source, gate
and drain. The current is conducted in either electron or hole channel. The gate voltage
controls the current.
Bipolar and Metal-Oxide Semiconductor (MOS) technologies have quite different
characteristics. Bipolar devices are faster than MOS devices. However, MOS devices are
cheaper to manufacture, and have lower power consumption and heat generation than
bipolar devices. Therefore, bipolar devices are used when several analog operations are
performed. MOS devices are required when high integration is concerned and digital
operations are performed 2.
The transistor is one of the key components behind practically all modem electronics.
They can be widely used for amplification, switching, signal modulation etc. Although
discrete transistors are still being used, the majority are fabricated into integrated circuits
(IC) along with other components to produce complete circuits.
In 1965, Gordon Moore, who is cofounder of Intel, raised Moore's Law. This law
indicates that the number of transistors on a chip doubles about every 18 months.
Correspondingly, the number of transistors on IC is a rough measure of computer
processing power. It is one of the basic principles behind the semiconductor industry in
the last 40 years and drives the development of transistor technology. In early 2006 Intel
announced their breakthrough of new 45nm silicon technology 3 . Nevertheless, a decade
ago, chips were still built at a 500 nm level. The following question is raised: can the
transistor still shrink in future? Smaller transistors need less operating voltage and
minimum power consumption. Each of these complicates transistor scaling. On April
13th, 2005, Gordon Moore himself stated in an interview that the law may not hold valid
for too long, since transistors may reach the limits of miniaturization at atomic levels. It
is also predicated by Kurzweil that continuation of Moore's law until 2019 will result in
transistor features just a few atoms in width. It becomes necessary to develop new
technology and improve the performance of individual transistors so that Moore's law
can hold true beyond 20204.
1.2 Properties of Indium Antimonide
Based on all these considerations, new materials other than silicon are being explored in
the hope of extending Moore's law. III-V compound semiconductors are one possibility
to complement the silicon transistor in the future. As is seen from table 1, InSb has the
highest electron mobility, which is 50 times higher than silicon and 9 times higher than
GaAs. It also has high electron saturation velocity and low energy band gap.
Table 1: Electron mobility of different semiconductor materials at room temperature5
Si
GaAs In.53Ga.47As
InAs
InSb
Electron
mobility(cm 2V- S'
600
4,600
7,800
1.0
1.2
0.8
3.5
5.0
1.12
1.42
0.72
0.36
0.18
16,000 30,000
Ns=1*10 12//cm2)
Electron Saturation
Velocity(10 7cm/s)
Energy Band
ap(eV)
Actually InSb is not a new material. Investigations of its mechanical and electronic
properties began from the late 1950s. Most of the key parameters had already been
tentatively established in the 1960s and were summarized6- 7. The energy gap is 235 meV
at OK and 172 meV at 300K as is shown in figure 1. In addition, InSb has low
(523C/796K) melting point and is among the most perfect material available
commercially. Defect densities as low as one etch-defined pit in a 75 mm wafer have
been detected by W.F.M. Micklethwaite although higher levels of 10-100 defects/cm 2 are
normally observed 8.
For crystal growth of InSb, hydrogen is chosen as the atmosphere since it is
experimentally proven that hydrogen does reduce floating InOx when InSb melts. The
Czochralski crystal growth method is used for commercial production. Currently 76.3
mm (3 inch) diameter wafers are in routine commercial production with defect density as
low as 10 etchable dislocations/cm 2 . Growth is usually performed with an unfluxed melt
under a pure hydrogen cover gas. This is similar to the growth of silicon and germanium.
Epitaxial growth of InSb has also been reported previously 9' 10,11. It was initially found
difficult to remove the surface oxide prior to epitaxial growth. Atomic hydrogen was then
used to prepare the wafers for very high quality MBE12 . It was also demonstrated that
there was low damage surface cleaning of InSb with atomic hydrogen.
Although InSb has just been considered in making transistors, it has long been an
important infrared material due to its narrow energy gap. InSb can also be used for
remote gas sensing, spectroscopy and magnetic field sensors. A laser diode was also
demonstrated in 199613. The main drawback to the commercial exploitation of InSbbased devices has been the very large intrinsic carrier density, which is a consequence of
its narrow band gap. The variation of intrinsic carrier concentration with temperature also
means InSb is not suitable to environments where temperature can change significantly.
Electron and hole concentration can be controlled using carrier extraction and exclusion
techniques. High quality MBE grown InSb/InAlSb heterostructures can further aid carrier
confinement at room temperature14 15 . Such unique characteristics make InSb a potential
candidate to be used in high-frequency, low-power transistors. Starting from 2003, Intel
and QinetiQ Ltd jointly developed InSb quantum well FET (QWFET). On Dec,
7 th
,
2005,
they announced the 85nm gate length enhancement and depletion mode InSb QWFET.
Such transistors were demonstrated at 305GHz and power consumption is reduced by a
factor of 10 16
1.3 Business Plan and Cost Model
Basically there are three business models that can be considered to generate revenue for
new technology. The first is a product model. This requires vast investment, and a strong
management, technical and legal team. It has the highest risk but also the possibly highest
returns.
1 .20
$10.000
OUO
51 U.
-.-
1 . 00
•$1,000
$100
0.40
$51
o20o
rz.-
1960
1970
1980
Year
1990
2000
2010
14012.3
Figure 2: Total facility cost and normalized facility cost per unit from 1960 to 2010. (Courtesy of IC
knowledge)
Semiconductor fab needs huge investment. Chip manufacturing is a weird industry.
Almost all the cost of producing a chip comes from fixed overhead, especially in the
depreciation of the fab and its equipment. One single stepper to do lithography can cost
millions of dollars. Unlike ship or car, the incremental cost of producing each chip is
almost nothing. The very first chip is extraordinarily expensive. After that, the unit cost
of the next million chips is almost free. The capital cost to build and equip a
semiconductor fab has increased exponentially over time from approximate $6 million in
1970 to in excess of $2 billion for cutting-edge 300mm silicon production. It is
predicated that the cost of a fab will exceed $10 billion by 2007, and may reach $18
billion by 201017.
Correspondingly, cost per chip decreases significantly. Compound
semiconductor products have much less demand compared to silicon chips. In spite of
that, it probably still costs billions of dollars to build an InSb QWFET fab. Given such
strict financial requirements, only giants as Intel, IBM, Taiwan Semiconductor
Manufacturing Corp.(TSMC) etc own and operate their own fabs. A start-up company
has to depend on venture capitals or government grants. It is practically impossible for
them to afford even a normal-sized fab.
There is always another way when stranded. Small technology companies can adopt
intellectual property (IP) model. This is the fab-free style. Companies focus on Research
and Development (R&D) and develop their own technology. Instead of manufacturing by
themselves, such technology can be licensed to other companies with capable production
facilities for a fixed period of time. The owners of the technology will collect certain
royalties annually. Depending on the nature of product, payment of royalties varies as is
seen from table 2. Electronic products can be considered hard goods (product C). 2-10%
based on licensee's total revenue will be a proper percentage for royalties. Actually a lot
of large corporations are also fab-free design houses, such as Xilinx, Agere Systems, Inc.,
Advanced RISC Machines (ARM) Ltd etc. IP model is also a perfect way for university
to commercialize their technology from research. It is estimated there are about 636
companies that have emerged from MIT, including Digital Equipment, Analog Device,
and Lotus Development Corporation.
Table 2: classification of product to determine royalty (courtesy of patent caf6)
Product
Royalty
Software Product 10-40%
Based on
Total Investment
Retail Price or N/A
Wholesale
Hard Goods
0%
Product/Patent
50 cents per
N/A
unit
'A"
Hard Goods
0%
0%
Flat fee of
Product/Patent
'$50,000 @ $
;'B"
10,000 per yr. for
5 years
Hard Goods
roduct/Patent
2-10%
Gross Revenue N/A
or Net Revenue
The last resort is to assign patents. It minimizes the risk but only a fixed amount of
money is collected. This is totally an ownership transfer. All about this technology will
belong to the receiving company. Mark Twain once said, "Prediction is difficult,
especially of the future". It is difficult to estimate how much today's emerging
technology is worth in 10 or 20 years' time. When strain silicon was discovered in 1980s,
few knew how profound it would be. Today it turns to be very important technology in
silicon chip design. Therefore, there is a great risk to underestimate the actual value of
technology when it is still in cradle. Acquisition is similar to assigning patents. It is very
common in pharmaceutical industry. When a potential lucrative drug is approved by US
Food and Drug Administration, the inventor - sometimes small enterprises will be
acquisition targets of giant multinational corporations, e.g. Pfizer, Inc. However, such
practice is less common in semiconductor industry.
1.4 Scope and outline of thesis
In this thesis the InSb QWFET technology will be analyzed in details, including
fabrication, performance, advantages and drawbacks. In addition, extensive market
analysis is presented for possible applications. The potential competitors are also figured
out and compared. Related IP issues are discussed. Cost model is presented at the end of
thesis and possible marketing strategies are recommended according to cost analysis.
Chapter 2 will discuss the structure and fabrication of InSb QWFET. The novel features
of the structures will be presented in details. Following this, performance will be
benchmarked in four different aspects: (1) operating frequency; (2) scalability; (3)
leakage current; (4) power consumption. Pros and cons will be derived from the
benchmarking.
Chapter 3 will give extensive market research on this new product. Battle between Intel
and AMD in microprocessor market will be reviewed. The trend in microprocessor
development will be predicted and InSb QWFET could be important in Intel's strategy.
Further more, the performance of InSb QWFET will be compared with other possible
competitors, i.e. silicon transistor, carbon nanotube (CNT) and silicon nanowire
counterparts. Other markets rather than microprocessors will also be demonstrated.
Chapter 4 will concern about the IP issues. The patents related to InSb transistor
technology will be searched through. Since InSb research could involve a lot of
companies, IP on joint venture and strategy alliance will also be discussed.
Chapter 5 will build a cost model and simulate the fab production processes. Cost based
on both silicon and GaAs substrates will be calculated and presented. Marketing strategy
and future of InSb products will be predicted based on the cost.
Chapter 6 will round up the discussion and conclude on the thesis.
Chapter 2 Indium Antimonide Quantum Well
Transistor
2.1 Structure of InSb QWFET
0
5.5
6.0
6.5
Figure 3 (left): Structure of InSb QW transistor"'; (right) Energy band gap versus lattice constant of
different semiconductor materials. InSb has energy band gap of 0.18eV and lattice constant of
6.48A"9.
Table 3: Deposition layer variation of InSb transistor 8
Layer
Material
Thickness(nm)
Top Barrier
AlxIni.xSb
15-45
Doping
Te
Spacer
AlxInl.xSb
5
Channel
InSb
15-20
Metamorphic Buffer
AlyIn._ySb
3,000
Substrate
GaAs
The structure of Intel's new 85nm gate length transistor is shown in figure 3. As a result
of large lattice mismatch between InSb (6.48 A) and Si (5.43 A), semi-insulating (GaAs)
(5.80 A) is chosen as the substrate instead of Si. The substrate is semi-insulating, so
transistors can be better isolated and parasitic capacitance is reduced. After that a thick
AlxInI.xSb (x in the range 0.15-0.3) buffer layer is deposited to accommodate large lattice
mismatch. Following this, a compressively strained thin InSb layer is grown. This layer is
confined between AlxInl.xSb layer and a Schottky barrier metal gate.
From InSb channel to top, there are a 5nm thick Al0.2In0.8Sb spacer, Te 5-doped donor
layer (doping concentration 1-1.8 x 1012 cm- 2 , W=18000-25000cm 2V 1'S'1), and a 15-45nm
thick AlxInl-xSb top barrier layer. The above layer variation is summarized in table 3. The
top barrier can reduce device leakage and breakdown since it has a relatively high band
gap. This improvement is crucial for the performance of the transistor because InSb has a
very low critical breakdown field (0.04 mV/cm, silicon is 0.3mV/cm). The modulation
doping scheme, with a single Te 8-doped donor layer, is implemented to reduce the
access resistance in enhancement mode device. As is seen from figure 4, an enhancement
mode device also has a deep recess etch in the gate region with an optional etch stop
layer. In contrast, there is only a shallow recess gate in the depletion mode. Due to the
short gate to channel separation, the deep recess gate will exhibit much better subthreshold slope and drain induced barrier lowering (DIBL). The details of performance
will be given in section 2.4.
Figure 4: Schematic of the depletion mode and enhancement mode InSb quantum well transistors.
Transistor on the left is depletion mode, the one on the right is enhancement mode s.
2.2 Fabrication of InSb OWFET
Figure 5: SEM micrograph of a two-finger InSb quantum well transistor with gate-bridge at the
mesa edge. LG=0.2 pm, LDS = 2.0am2°.
To fabricate the device, solid-source molecular beam epitaxy (MBE) is used to grow
different layers on top of the GaAs substrate. A scanning electron microscopy (SEM)
micrograph of InSb transistor is shown in figure 5. The source and drain Ohmic contacts
are defined using optical lithography. Ti/Au layers are then deposited by e-beam
evaporation and lift-off. The Ti/Au Schottky gate metallization is performed using ebeam lithography, e-beam evaporation and lift-off processes. Finally, device isolation is
achieved by wet chemical etching resulting in a gate air bridge at the mesa edge between
the channel and gate feed metal.
2.3 Mechanism
Figure 6: Calculated band structure and Schroidinger-Poisson solution of spatial redistribution of
confined carrier population in various sub-bands in the quantum well for 15% and 30% Al
percentage barriers's.
i
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ELECTRON DENSITY [cm ]
Figure 7: (Top left) 20 Hall Mobility data on directly doped and modulation doped 20nm thick InSb
quantum wells with 15% Al in the Al,Inl,Sb barrier layer. (Top right)20 Hall Mobility data on
modulation doped 20nm thick InSb quantum wells with 15%, 20% and 30% Al in the Al1 Int.,Sb
barrier layer. (Bottom left) n Electron mobility versus sheet electron density in quantum well. InSb
QW has the highest electron mobility among all the semiconductor materials. (Bottom right)'
Electron conductivity versus sheet electron density in quantum well. Conductivity increases with
electron density.
The mechanism of the transistor is based on an InSb quantum well. This well acts as an
electron transport channel. Band gap engineering is used to confine electrons within the
InSb quantum well. AlxInl-.Sb has a higher band gap compared to InSb. In addition, the
InSb layer is only 20nm, which is comparable to the electron de-Broglie wavelength.
Thus, the electron energy is confined and quantized. Since there are few impurities in the
quantum well, electrons have very high mobility. It is also noticed from figure 6 that the
quantum barrier can be changed by varying the Al concentration in the AlxInl.xSb. The
higher the Al concentration is, the higher the barrier is. Therefore, the electron
quantization can be changed.
Hall measurement of electron mobility was performed at room temperature. InSb
quantum well can be doped directly n-type with Te impurities. Electron density is
measured in the range of 0.8-1.2 x 1012cm-2 . Correspondingly, mobility is in the range of
14,000-18,000 cm 2V-'s '." Direct doping can cause impurity scattering and thus reduce
mobility. In contrast, modulation doped structure, with Te 8-doped donor layers, achieves
very high electron mobility of 30,000 cm 2V'ls-1 with n,= 5 x 1011cm-2. As is shown in
figure 7, carrier mobility of modulation doping decreases with carrier density. Such drop
is not due to ionized impurity scattering. According to Schrodinger-Poisson modeling of
carrier distributions, at higher carrier concentration, more carriers start to populate higher
energy sub-bands which spread into the barriers. Consequently it causes lower mobility.
It would give increased mobility if higher conduction band offset barriers are used. The
quantum well mobility increases monotonically with increasing Al percentage. From
figure 7, carrier mobility corresponding to 30% Al percentage barriers exceeds the bulk
InSb mobility. At room temperature InSb QW mobility over 30,000cm 2V'S-' is achieved
with 30% Al barrier at doping concentration n= 1.3 x 1012cm-2 . Figure 7(bottom left) and
(bottom right) compare mobility and conductivity of different III-V compound transistors
and Si MOSFET. The InSb QWFET shows the highest conductivity and lowest carrier
concentration. Considering this, the InSb transistor is attractive for gate capacitance
dominated circuits, and is less suitable for interconnect dominated circuits.
2.4 Performance of Transistor
2.4.1 Operating Frequency
Due to the increased 8-doping level, the enhancement mode devices show higher
performance. The data of figure 8(top left) was obtained from 130 nm LG transistor. It
shows e- and d-mode devices have a threshold voltage, VT, shift of 250mV. From figure
8(top right), the e-mode device has improved VT Roll-off characteristics as well. Thus emode has better short channel effects than the d-mode. Figure 8(bottom left) compares
the intrinsic (de-embedded) cut-off frequency, fT, of 85nm gate length depletion and
enhancement mode devices with a fixed source to drain separation, LSD, of 0.75pm. The
e-mode device has higher operating frequency due to lower access resistance from the
increased 8-doping level. The e-mode switching frequency is as high as 305GHz. Even
for d-mode, the frequency is 256 GHz. It is illustrated in figure 8(bottom right) that the
peak fT decreases monotonically as a function of LSD for both depletion and enhancement
mode devices.
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200
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n
0
0.5
1
1.5
2
2.5
Source Drain Separation, L [urnm]
Figure 8: (a)ID - VG transfer characteristics of 130nm Lg depletion mode and enhancement mode
InSb QWFETs; (b) Sub-threshold slope as a function of gate length for depletion and enhancement
mode InSb QWFETs; (c) Intrinsic cut-off frequency, fT, for 85nm gate length depletion and
enhancement mode InSb QWFETs at 0.5V Vds. (from reference 16)
2.4.2 Scalability
As silicon transistors are scaled down in size, scalability of novel transistors becomes
important. Scalability can be assessed through sub-threshold slope. Lower slope is
desired. As is seen from figure 9(a), the use of e-mode device has already significantly
reduced sub-threshold slope. In transistor fabrication, p-type buffer doping is
implemented. Such doping further reduces the slope. Given all these improvements, InSb
QWFET is more scalable than the advanced Si MOSFET. P-type buffer doping also
reduces DIBL. It is obvious from figure 9(b) InSb QWFET causes less DIBL compared
to Si MOSFET.
300
--
Enhancement mode
0
250
2
0 j
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= 150
..
80
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100
1000
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Gate Length, Letonm]
100
1000
Gate Length, L. [nm]
(a)
(b)
Figure 9: (a) shows sub threshold slope versus transistor physical gate length; (b) shows DIBL to
gate length Scalability further improves by buffer dopant engineering(from reference 18)
2.4.3 Leakage Current and High-K Gate Dielectric
f-
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Figure 10: (left) Transfer characteristics of 85nm
0.05V) 16 ; (right) schematic of impact ionization" s
LG e-mode
QWFET with LsD=0.75pm (VDs=0.5 and
Figure 10(left) shows transfer characteristics of the enhancement mode devices. The off-
state drain leakage current is from either gate leakage through metal-semiconductor (M-S)
Schottky junction or impact ionization in InSb QW. Figure 10(right) explains the
mechanism of impact ionization. The energy from collision can free a valence electron
and causes an electron-hole pair. The added carriers are immediately accelerated by the
electric field in the depletion region. Consequently, they and the original carriers make
additional collisions and create even more carriers. Such leakage from impact ionization
can be reduced through extraction of holes so that a snow-balling creation of carriers is
avoided. Gate leakage from forward-biased Schottky junction can be mitigated through
the insulated gate.
In contrast to silicon, it is difficult to find a high-quality native oxide for III-V
compounds. Intel researchers reported promising high-k dielectric development on
AlInSb/InSb device layers for the first time 16 . The dielectric is A120 3 and is deposited
using a low temperature atomic layer deposition (ALD) process. Figure I1(left) shows
the InSb QWFET with A120 3 gate dielectric. From the experiment results, there are two
surface pre-treatments A and B. Process A oxidizes the AllnSb layer so that indium oxide
is formed on the top, which results in a high density of interface states. Process B has
much reduced oxidation compared to A. From the C-V curves of figure 12, pre-treatment
B achieves less frequency dispersion in the accumulation layer. However, in the inversion
layer, there is still serious frequency dispersion. Basically there are two reasons
accounting for this. One reason is the hole generation in low band gap AllInSb/InSb layers.
The other reason is generation/recombination from surface traps. The high-K/metal gate
stack successfully reduces the leakage current. As is seen from figure 1 (right), the
leakage current is reduced by four orders in magnitude. This is a great performance
improvement, which means less noise during operation and more efficient use of input
power.
-1.0
-0.5
0.0
0.5
1.0
GATE VOLTAGE [VI]
Figure 11: (left) schematic of InSb QWFET with A120 3 gate dielectric; (right) Room temperature
gate to channel leakage characteristics for ALD A120 3 high-k dielectric and Al metal gate stack on
AllnSb/InSb device layers showing four orders of magnitude reduction in leakage compared to
Schottky metal gate(from reference 18).
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8.OE-07
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2.OE-07 -
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-0.5
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Gate Voltage, VG [V]
3.OE-07
2.OE-07
,
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!
I
-0.5
0
0.5
Gate Voltage, VG [V]
Figure 12: (left) Room temperature C-V characteristics of Al/Al2O3/AIInSb/InSb MOSCAP with
surface pre-treatment A; (right) Room temperature C-V characteristics of Al/AI203/AlInSb/InSb
MOSCAP with surface pre-treatment B. (from reference 16).
2.4.4 Power Consumption and Benchmarking
As for power efficiency, the 85nm gate length InSb QW transistor shows more than 10
times lower direct current (DC) power dissipation compared to an advanced Si MOSFET.
This is shown in figure 13. Such a transistor can operate at voltages as low as 0.5V.
_CL503
W 300
% 250
200
150
100
50
10
100
DC Power Dissipation [pW/pm]
1000
Figure 13: Cut off frequency versus DC power dissipation. InSb e-mode QWFET has 10x power
reduction compared to 60nm gate length silicon MOSFET18 .
100.
0o Si M•SI
I 1 E-17
.
E
>
10
U
OSi MOSF
2 1E-18 *Depletioi
* Enhancen
Depletion
1E-19
e Enharce
S
tD
1E-20
o 1E-21
I1E-23
1
100
10
Gate Length,
1000
LG[nm]
1000(
1
10
100
1000
10000
Gate Length LG [nml
Figure 14: (left) Transistor Gate delay (CV/I) versus gate length for InSb QWFETs at VDS=0.5V
benchmarked against state-of-the-art silicon nMOS transistors; (right) Transistor Energy-Gate delay
product (CVII) versus gate length for InSb QWFETs at VDs=0.5V benchmarked against state-of-the
art silicon nMOS transistors. ( from reference 16)
Figure 14 shows the benchmarking of InSb QWFET against historical and future Si
nMOS transistors. For a given physical gate length, the InSb devices offer 2.8x reduction
in gate delay and more than an order of magnitude improvement in the energy-delay
product over Si transistors. That means the InSb QWFET has great potential to operate
fast and power efficient.
2.5 Challenges
In spite of the excellent performance of InSb QWFET, there are still grand technical
challenges ahead. InSb does not form a stable adherent insulating layer. Currently the
surface treatment causes the formation of side-product, indium oxide, which results in
surface Fermi level pinning. The existence of surface traps also accounts for the leakage.
Surface treatment needs to be improved. Maybe better high K-dielectric material can be
pursued. Currently the cutting edge technology for InSb QWFET has a gate length of
85nm. This needs to be further reduced.
In addition, CMOS technology is widely used in integrated circuits. The advantage of the
CMOS technology is that it only uses significant power when its transistors are switching
between on and off states. Therefore, CMOS devices use little power and do not produce
as much heat as other forms of logic. It also allows a high density of logic functions on a
chip. Silicon is the centerpiece of CMOS. Before InSb, a GaAs integrated circuit is
attempted but it failed to demonstrate higher-speed P-channel FETs. It turned out that
GaAs logic circuits have much higher power consumption, which has made them unable
to compete with silicon logic circuits. Until now only electron channeling is
demonstrated in InSb QWFET. Ultra high hole mobility P-channel InSb transistors have
to be fabricated for CMOS. Different from GaAs (hole mobility less than 400 cm 2V-'s),
hole mobility of InSb can be as high as 850 cm 2V-s
1
21,
which is much larger than the
value of silicon (450 cm 2V-1s). Considering this factor, it is possible to fabricate high
speed p-channel transistor in the future.
Another important problem about fabrication is the substrate material. The GaAs
substrate needs to be replaced by silicon substrates so that the cost can be substantially
reduced. Currently 6 inch (150mm) GaAs wafer costs about $300(All the currencies in
this paper are in U.S. dollar) while 12 inch (300mm) silicon wafer costs around $20022. In
late May, 2006, members companies of the international Sematech Manufacturing
Initiative (ISMI) reached consensus to move the semiconductor industry towards 450mm
wafer 23. A Large wafer means more devices can be integrated into one chip. It reduces
the number of components needed. Integrated circuits also tend to be faster and more
energy efficient. Replacement of silicon substrate makes integration easier. InSb QWFET
can be quite well integrated into circuits with other silicon based devices. It widens the
application of InSb devices.
Although high speed and low power consumption are very attractive, InSb devices have
one inevitable shortcoming: critical breakdown field. Breakdown field of InSb is only
103V/cm
21,
which is much less than the value of silicon (3 x 10sV/cm) 24 . It has already
been indicated in section 2.1 that use of higher band gap material AllInSb can increase
breakdown voltage; however, the exact improvement is not disclosed by Intel researchers.
According to Dr. Suman Datta from Intel, InSb devices' are not designed for breakdown
performance. It can be used as low noise amplifier and promising in millimeter wave
applications.
Besides all these technical challenges, cost minimization is a huge task. Take GaAs as
example, which is a relatively mature III-V compound technology compared to InSb.
Given its better electronic property, many people believed the semiconductor industry
will shift from silicon to GaAs in 1980s. During the GaAs craze, Cray Computer
Corporation invested more than 300 million and eventually built one GaAs-based
machine in the early 1990s, the Cray-3. However, the Cray-3 was so costly that Seymour
Cray failed to sell even a single piece. The company filed for bankruptcy in 1995. An
InSb based super computer could be more costly than that and unrealistic. Companies
like Convex computer, now part of Hewlett Packard, and Sequent Computer Systems
only used GaAs in their high-end architectures and they managed to make money. Intel
can adopt a similar strategy, i.e. use the InSb devices in high-end products first, and make
the shift to mainstream products when InSb technology becomes more affordable.
Moreover, government support is very important. The failure of Cray-3 is partly due to
changing political climate (collapse of Warsaw Pact and the end of cold war). GaAs
supercomputer turned to be less attractive for government. It is crucial for Intel to earn
government support and build alliance with other corporations and research institutes.
Chapter 3 Market Analysis and Competing Technology
3.1 Interaction between Technology and Market
3.1.1 Technology Push and Market Pull
The existence of a prospective market is the driver of technology innovation. In many
circumstances, the needs of consumers (in broad definition, it includes individuals,
corporation, government etc) guides the direction of scientific research. In addition to that,
nowadays more and more funding is required for research projects. It is only when
technological developments find a market that scientific research will pay off. In such a
positive circulation, development cost is reimbursed in economic terms and thus further
boosts more technology innovation. According to Tarek Khalil, the so-called technology
push and market pull jointly stimulate innovation. 25 The detailed relationship is depicted
in figure 15.
Opportunities for
Technology Push
*
*
*
*
Scientific discoveries
Applied Knowledge
Recognized needs
Intellectual capital
(Scientists and Engineers)
Market demand
Proliferation of application areas
Recognized needs
Opportunities for increased:
profitability, quality, productivity
* Entrepreneurs
*
*
*
*
Figure 15: Integrating Technology push and market pull to stimulate innovation. Reprinted from the
book "management of technology" 25 .
Such a theory fits InSb transistor technology quite well. It can be analyzed in either way.
Science-Technology Push: Science provides the base for technological development.
Investigation of the InSb compound begins in the late 1950s and most of the data was
collected in the 1960s. Such data shows InSb has the highest mobility among all the
semiconductors. The fabrication of InSb QWFET does not begin from scratch either. The
previous development of InSb detectors and lasers stimulates the growth of InSb
transistor fabrication. In short, scientific advancement 'pushes' the development of InSb
QWFET.
Market Pull: The appearance of InSb transistor is also stimulated by market pull.
Technology is often developed to meet a market demand. This is the most effective way
to connect technology with the market. Power dissipation increasingly limits
microprocessor performance. The power budget for microprocessors is becoming a
design constraint, similar to die area and target frequency.
Supply voltage is also a
problem. It continues to scale down with every new process generation, but at a lower
rate that does not keep up with the increase in the clock frequency and the transistor
count. As is seen from figure 16, processor power increases significantly with operating
frequency.
The power dissipation of an Intel Pentium 4 is almost double the power of Pentium 3. An
improvement to existing technology is urgently required and there is a strong collective
demand for a solution to the power-frequency bottleneck in the market. Architecture
techniques like on-die power management, and circuit methods such as clock gating and
domino to static conversion, are employed to control the power increase of future
microprocessors. Such market pull may provoke major breakthroughs. Most of the
technological developments stimulated by market pull are of an incremental nature. InSb
transistor technology has to be improved gradually. Problems such as silicon substrate
integration, p-channel transistor will be settled in the near future.
Incremental
technological improvements have cumulative effects.
Both mechanisms of push and pull, contribute to stimulating innovation and
technological change. Integrating them accelerates the change. Munro and Noori (1988)
proposed that commitment to technology adoption is dependent on an integrative
approach to technology push and market pull combined with management's attitude
toward technology and the firm's technical financial resources. Management and
financial issues are also critical and they will be discussed in IP and cost model chapters.
Pentlum'4
70
A
0.18um
60
0.18 um
240
P
•
US#
PenIUI!P IN
O.13um
10
0
500
1000
1500
2000
Frequency [MHz]
2500
Figure 16: Processor power as a function of frequency for two process generations26
3.1.2 Product Life cycle
A product undergoes several phases during the market life. The product life cycle is
closely associated to market-growth profile and is shown clearly in figure 17. Phase 'A'
is the R&D phase. A product emerges from a concept. It is then translated into an
engineering design and usually illustrated through engineering drawing. Afterwards a
prototype is developed and tested to make sure that the product specifications are met and
the performance parameters are achieved. In the initial phase, the product is not yet
launched into the market and there is no revenue generated.
Phase 'B' is the product-launching phase, followed by phase 'C', the growth phase,
whose profile depends on the market response to the product. Typically, sales start slow
and then accelerate as the product becomes known and accepted in the market. As the
product is diffused in the market and the market becomes saturated with well-established
mature-technology products. Now the products may be substituted by other new products
and eventually become obsolete. Obsolete products have little or no monetary value. The
product is phased out from the market.
Product-Market life cycle
1
A
A4
r
1
n
S4
S3.5
3
* 2.5
2
'
1.5
E 0.5
0
0
2
4
6
8
10
time(a.u.)
A: Concept Design Prototype
D: Mature Stage
B: Product Launch
E: Substitution Products
C: Product Growth
F: Product Obsolescence
Figure 17: Product - Market Life Cycle 25
In the market analysis of InSb QWFET, currently this technology is undergoing concept
design prototype phase. There are still some technical problems to be solved. In the
product launch phase (around 2015 according to Intel Corp.), it is predicted that some
turbulence will be created in existing systems. New product InSb transistor emerges in
the market and will compete with other product innovations, e.g. carbon nanotube
transistor, and existing silicon based transistors. In phase 'C' (around 2020), InSb
transistors can undergo rapid growth. As the market share of this technology reaches its
peak and starts to decline, a dominant product design emerges and the industry standard
is defined accordingly. In the specific market analysis below, only phase 'A' to phase 'C'
are of our concern.
3.2 Microprocessor Market
3.2.1 Market summary
Table 4: Microprocessor Market Summary from 2003-200727
Year
Revenue(billion U.S. dollar) Growth (%)
2003
27.4
9.7%
2004
30.1
2.3%
2005
30.8
5.5%
2006
32.5
8.5%
2007
35.2
N.A.
From table 4, microprocessor market experiences moderate growth from 2003 to 2007.
Compound Annual growth rate (CAGR) is calculated as 6.46%. CAGR is used to
determine an annual growth rate on an investment whose value has fluctuated widely
from one period to the next 28.
3.2.2 Multi-core Microprocessor Market and future prospect
70,000
700,000
60,000
600,000
50,000
500,000
C
o 40,000
=US$ Mil ions
S-- Thousands of Units
". 30,000
300,000
3
20,000
200,000 -
10,000
100,000
0
0
2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015
Figure 18: Worldwide microprocessor market revenue summary and prediction from 2005 to 201529.
Multiple-core processors are the trend of processor market. Multi-core architecture
requires design engineers to place two or more Intel Pentium processor-based "execution
cores," within a single processor so that it can perform more work within a given clock
cycle. Multi-core architecture has demonstrated enhanced performance, reduced power
consumption and more efficient simultaneous processing of multiple tasks.
The market for multi-core microprocessors is set to explode over the next 10 years. Their
usage rises in products including PCs, servers and video-game consoles, according to
new research from iSuppli Corp's Emerging Technologies service. It is projected that
shipment of multi-core microprocessors most likely will grow to 638 million units by
2015, up from 14.8 million in 2005. Correspondingly, market revenue will expand to
US$64.8 billion, up from US$2.6 billion in 2005. Figure 18 presents iSuppli's forecast
for multi-core microprocessor units shipments and revenue from 2005-2015.
Since multi-core has been almost universally accepted as the optimum design solution for
future microprocessors, it can be safely assumed that the total microprocessor market will
increase to at lease US$70 billion by 2015.
3.2.3 Players in market: Intel vs. AMD
3.2.3.1 Manufacturers in market
Founded in 1964, Intel has long been at the top of the processor world. In fact, they
controlled the high-end and medium-end range of processors. In the 1990s Intel was
ahead of AMD and Cyrix. Because of Intel's control, these two companies were
competing for the low-end market share. With the creation of the PIII (Celeron), Intel
entered the low-end market, which basically knocked Cyrix out of the game. Meanwhile
AMD became focused on making quality processors while delivering them to consumers
at low prices. Adopting such a strategy, AMD slowly built power to compete with the
speed and performance of Intel.
3.2.3.2 Current Technology and Competition
AMD is increasingly out-selling Intel since 200030. Figure 20 shows that the central
processing unit (CPU) market is more and more dominated by Intel and AMD. Other
manufacturers play much less significant roles in market. Generally AMD gained great
growth in market share since 2000 and has maintained such share. In the desktop system,
AMD's performance is stable and has gains almost 30% market share. From figure 23, in
portable system market, Intel is still dominant over AMD, with AMD's share below 20%.
Figure 20 shows that Intel still has relatively lower market share in Latin America and
Europe.
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Figure 19: Intel market share by PC type3
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3.2.3.3 Lawsuit between Intel and AMD
Intel has long been a dominant power in the microprocessor market and has sort of a
monopoly. There have been quarrels between Intel and AMD. According to AMD, Intel
told companies to stop production of AMD motherboards, by threatening to cut off
supply of chips.
In June, 2005, AMD filed an antitrust lawsuit in U.S. District Court in Delaware about
Intel's alleged abuse of its power in at least the previous 5 years. It is said that Intel
pressures customers like Hewlett-Packard, Dell and Gateway to use Intel's chips instead
of AMD's.
Not only in the US, but Japan's regulators ruled against Intel in an antitrust case there in
March 200533. Intel's Japan unit stifled competition by offering rebates to five Japanese
personal computer (PC) makers - Fujitsu, Hitachi, NEC, Sony and Toshiba - which
agreed to buy or to limit their purchase of chips made by AMD and Transmeta34
3.2.3.4 Future of Intel's Strategy against AMD
Both Intel and AMD are public companies. Figure 23 shows the performance of Intel
stock in National Association of Securities Dealers Automated Quotation (NASDAQ)
from June, 2005 to June, 2006. Though stock peaks from Nov, 2005 to Jan, 2006. Intel
has dropped considerably in the past 12 months. In contrast, AMD stock is listed in New
York Stock exchange (NYSE) and performed much better as seen from figure 24. It
shows that investors are more optimistic about prospect of AMD.
Indeed, there are a lot of good news in market for AMD recently. Dell, number 1
computer manufacturer in the world, will adopt AMD processor. Early this year Dell
CEO said AMD's Opteron Dual-Core processors will be offered in Dell's multiprocessor
servers by year's end for the first time. There also have been talks about Dell switching to
AMD processors sometimes in their PC products in the near future, and that could play a
major role in the market share switch.
Currently Intel still has advantages in assets. Market cap is a way to calculate how much
a company is worth. The market cap is the number of outstanding shares (common),
multiplied by the stock price. According to it, Intel is a $128 billion company, while
AMD is a $17 billion company. Intel profit is even larger than AMD's revenue. However,
it is found AMD spent more percentage of revenue in R&D. Given the smaller size of
AMD, it has also more space to grow.
Table 5: R&D spending and revenue comparison of Intel and AMD fro 2004-2006
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Rich Brown, the Senior Associate Editor for CNet.com, has recently done a desktop
rating for Intel and AMD's new dual-core products. In this head-to-head battle, there were
7 different categories to be graded on. These categories were: (1) day-to-day computing,
(2) gaming, (3) multitasking, (4) photo editing, (5) MP3 encoding, (6) video encoding,
and (7) price vs. performance. According to CNet.com, AMD not only beat, but crushed
Intel in all of these areas 35. Though it is just opinion from one computer rating website, it
has to be admitted that Intel faces more severe competition from AMD.
In conclusion Intel has gradually lost the place of sole chip provider for major PC
producers. PC manufacturers, e.g. Dell and HP, face more pressure from competition.
AMD is an alternative option for them to cut cost. It is inevitable. What Intel needs to do
is development of better technology to compete with AMD. More money needs to be
spent on R&D. InSb QWFET can be one weapon for Intel to win the high-end market.
Once InSb QWFET technology becomes mature and price plumbed, it could also be used
in low-end processors.
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3.2.3.5 Other Processor Manufacturers in Market
Besides Intel and AMD, Freescale, Semiconductor, IBM, HP and Sun Microsystems all
have their own processor products, which are mainly used in servers and embedded
systems.
One of the famous non-mainstream processors is PowerPC. It is RISC microprocessor
architecture created by the 1991 Apple-IBM-Motorola alliance, known as AIM.
Originally PowerPC was intended for PC, and gained most success in the PC market in
Apple's Macintosh from 1994-2006. From 2006, Macintosh switches to Intel processors.
IBM focused their PowerPC CPUs towards game machine makers such as Nintendo's
Wii, Sony's PlayStation 3 and Microsoft's Xbox 360.
3.2.4 Laptop: the Drive for Future Personal Computer Market
In past several years' PC market, notebook price fell and technological advancements
narrowed the performance gap between desktop and portable PCs. From Gartner, 2006
PC market will increase 9.8%. Such 9% increase rate will be kept until 2009. Specifically,
portable computer is projected to increases 26% in 2006, and such high growth trend will
continue until 2010. Gartner chip research department vice president Andrew Philips
even predicts that Laptops will replace desktop in future38
In-Stat/MDR reports that portable PCs in 2004 account for a quarter of all PCs shipped,
and that number will increase to close to a third by 2008 as many consumers switch to
laptops.
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Tracker, 2004
From the data of 2003 and 2004 (latest market details not available), HP was the top
global supplier of laptop, with a 16.9% market share, followed closely by Dell (now
replace HP as the global leader), with 16%. Toshiba, which held the No.1 ranking in
laptops from 1994 until 2002, slipped to No. 3, with 12.9%. IBM (now Lenovo) was
fourth, with 8.7%, while Fujitsu and Acer were tied with 6.2% each. Next was NEC, with
4.8%, followed by Sony, with 4.3%.
As a result of the laptop's portable size, it is crucial for it to have lower power
consumption and reduce heat release. Due to the relatively high price of laptops, more
expensive chips can be considered. Therefore, InSb QWFET have bright prospects for
extensive use in laptop microprocessors.
3.2.5 Competing technology
In the early stage of the technology life cycle competition is based on innovation. In this
stage, the technology is still developing and has not been fully accepted. Companies
depend on their innovation to add value to products and services they bring to customers.
The introduced technology helps expand the market size but has not yet demonstrated its
potential for changing the basis of competition. Therefore, in this stage a company must
be able to balance its growth strategies with its marketing strategies. Continuing
innovation is required in addition to market growth. Another important point has to be
mentioned here. At the early stages, competition in innovation and improvement delays
agreement on a standard design. A leader in innovation has the opportunity to set the
standard. A company should strive to be in such a position because once a dominant
design is established in the market by another company, it will be too late for the
company to set a different industry standard based on its own product.
Currently the silicon transistor is still the dominant choice. This technology has been
fully developed for about 40 years. There would not be a new material to replace silicon
in near future and it may never occur. Three different technologies will be compared with
InSb QWFET, i.e. carbon nanotube FET, silicon nanowire FET and advanced planar and
non-planar silicon FET.
A carbon nanotube is essentially a sheet of carbon atoms, which are arranged in hexagons
and curled up into the shape of a tube. It comes in two basic varieties: a single-wall
nanotube, which is a single coil of carbon hexagons; and a multi-wall version, wherein a
single tube is encased in a wider tube. Most of today's research is concentrated on single-
wall tubes. Their size allows them to function as one-dimensional objects. Because onedimensional nanotubes have essentially no height or width, electrons can travel
ballistically inside them. University of Maryland research group reported in 2003
mobility of carbon nanotube is 25% higher than mobility of InSb, and more than 70 times
higher than the mobility of silicon 39 . Multi-wall or single-wall nanotubes can act as the
channel of a FET. However, mass production of nanotubes remains a challenge and is
currently a slow and costly process.
In addition, it is difficult to dope carbon nanotube and categorize them as metallic or
semi-conducting material
40 .
Silicon nanowires, which consist of solid microscopic
strands of self-assembling silicon, are another promising technology. Properties of silicon
are much more controllable. Silicon nanowire can be placed more accurately onto wafer.
Easy doping and integration into conventional electronics make it more attractive.
Jie Xiang et al. of Harvard University reported Ge/Si nanowire high performance FET4 1.
Hole mobility was demonstrated 730 cm2V-'s-1 , which is 10 times higher than that of
silicon p-MOSFET. The device's intrinsic switching delay was comparable to that of
similar length carbon nanotube FET. Silicon nanowire FET also faces problem of scaling
down, fabricating electron channel device rather than holes, creating large-scale
assemblies of the nanowire devices for integrated systems42
Based on review paper of R. Chau et al 43, Different kinds of transistors are benchmarked
in four aspects (1) speed; (2) switching energy; (3) scalability; and (4) off-state leakage.
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NMOS devices; (b) Energy-delay product per product width versus transistor physical gate length of
NMOS transistors; (c) Sub threshold slope versus transistor physical gate length. The planar and
nonplanar Si FETs as well as the III-V planar devices are n-channel transistors, while the CNT FETs
are p-channel transistors.
Gate delay is the parameter used to evaluate the switching speed of transistors. As seen
from figure 28(a), as the gate length decreases, the gate delay decreases nearly linearly.
Among the three different kinds of transistors, Si MOSFET is the slowest; CNTFET is
faster than Si. In contrast, III-V compound semiconductor (including InSb) shows the
fastest switching speed. III-V compound has about 50 times higher channel mobility from
Hall Effect measurement compared to silicon. Since InSb transistors can operate at
voltages as small as 0.5 volts, this will significantly reduce the power needed. Seen from
figure 28(b), energy x delay/ width plot indicates the power dissipation. Once gain, III-V
semiconductors have the best performance.
Moreover, scalability is an important factor to determine whether transistors can be
further reduced in size. The sub-threshold slope against the gate length plot indicates
scalability, as seen from figure 28(c). A lower sub-threshold slope is desired.
This is
measured under high drain bias voltage, VDS=Vcc. All the transistors degrade as gate
length shrinks. Use of non-planar Si FETs, e.g. the Tri-gate transistor, can improve slope
substantially. The sub-threshold slope of a CNTFET is much worse than Si transistors.
That is because a relatively thick gate-oxide is used with metal-drain contacts. Planar IIIV devices degrade due to the relatively large gate to channel separation in these devices.
One of most important technical challenges in CNTFET is to make conventional
implanted or diffused P-N junctions in CNTs. The metal CNT contact currently used
results in degraded sub-threshold slope and ambipolar conduction.
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L=-60nm and 70nm at Vcc=1.3V, and a CNT PMOS transistor with L,=50nm and Vcc =0.3V 43.
Figure 29 shows the gate delay CV/I against leakage current. Generally gate delay
decreases as ION/IoFF deceases. Though smaller delays are achieved, it is at the expense of
increased leakage current. CNTFET has smaller delays as ION/IoFF ratio is less than 100
due to higher electron mobility and lower Vcc. An InSb transistor has a longer range than
CNTFET. Gate delays of 85nm LG InSb QWFETs are less than 70nm and 45 nm LG Si
MOSFET. However, there is problem with InSb QWFET. The gate leakage through the
metal-semiconductor Schottky junction limits the dynamic ION/IOFF range. 85nm LG InSb
QWFETs can only operate below ION/IoFF =1000
3.3 Low noise amplifier (LNA) market
3.3.1 Low noise amplifier summary
Low noise amplifier (LNA) is a special type of electronic amplifier and used in
communication systems to amplify very weak signals captured by an antenna. It is often
located very close to the antenna so that loss in the feedline can be reduced 44.
Noise figure performance has not yet been reported. However, it is likely to be
comparable to InP45. Therefore, InSb transistor technology offers a potential way forward
to realizing Monolithic Microwave IC (MMIC) based LNA. Such application is also
verified by Dr. Datta Suman from Intel InSb QWFET research group. It could be
extensively used in satellite communication, phased array radar system etc.
3.3.2 Satellite Communication Market
Satellite communication systems use FET and MMIC in transmit and receive functions.
The markets include global positioning system (GPS), very small aperture terminals
(VSATs), mobile satellite systems and fixed satellite systems. The ground segments of
these systems need low noise and low power consumption.
Take GPS for example, it is the only fully-functional satellite navigation system. A
constellation of more than two dozen GPS satellites broadcasts precise timing signals by
radio to GPS receivers, allowing them to accurately determine their location.
GPS receivers have similar requirements as mobile communication handsets, with space
and power consumption at a premium. Commercial GPS operates at 1.57 GHz while
more accurate military versions require the use of a secondary frequency at 1.23GHz.
Noise less than 1dB is an essential criterion for high performance GPS receiver.
Once purely for military use, the GPS has spawned a fast-growing consumer industry.
GPS capability is being added to cars, handheld PDAs and even cell phones. More and
more cutting-edge manufacturers - STMicroelectronics, Garmin, Magellan, Trimble,
Lowrance etc, join and develop GPS products. Sales are forecasted to reach $22 billion in
2008, according to ABI, a New York-based technology market research firm46
3.3.3 Phased Array Radar System
In telecommunication, phased array is formed by a group of antennas, in which the
relative phases of the respective signals feeding the antennas are varied. It turns out that
the effective radiation pattern of the array is reinforced in a desired direction and
suppressed in undesired direction 47
Phased-array radar technology has been used by the US army since the 1970s. Raytheon
is a major developer of phased-array radars, including the Ground-Based Radar (GBR)
for the Theater High Altitude Area Defense (THAASD) system, one of the U.S. Army's
Theater Missile Defense programs.
It is now being transformed to civilian aircraft and weather surveillance usage. At the
moment US is undergoing a national transition from existing weather radar systems to a
newer system using multifunction phased array radar48 . Such a system would make future
tropical storm and hurricane prediction more accurate. Along with the transformation
from military technology to civilian technology, phased arrayed radar market becomes
very promising.
3.3.4 Cell Phone Market
InSb LNA could be used in the receiver part of cell phones or base stations. Cell phone
market is well-known for the fast generation change. New models come into and then are
phased out. The market is projected to experience a strong boost of 3G phones. From the
statistics of Nokia, the global 3G phone is approaching 100 million units. 3G phones will
make approximate 40% of the total market by 2009. In addition, the new generation
CDMA phones are also seen to grow about 10-15% a year due to market demand in
China and Latin America. These new generation phones are more compact and powerful,
so stricter power consumption and performance are imposed on design.
Considering cell phone market, the worldwide market has experienced rapid growth since
2000. The number of handsets peaked at 810 million in 2005, which was double the
number in 2000. The total market revenue in 2005 was $115.1 billion, which is also
historical high. Cell phone has already become pervasive in life. Corresponding to that,
the market most probably experiences an overall slow growth until 2009.
3.3.5 Possible Market Demand for InSb LNA
It is very difficult to predict the demand for InSb LNA. In microprocessor market, there
are only two rivals. In LNA markets, almost all the major semiconductor companies have
their own LNA products. Furthermore, a variety of LNAs range in noise, power,
frequency etc. InSb LNA may follow similar track as GaAs replacing Si LNA. Until
today GaAs LNA still has only a small portion in market compared to silicon MESFET.
Total GaAs FET and MMIC demand from LNA reached $46.5 million in 1995 and
$107.4 million in 200049. It can be assumed that initial market share of InSb LNA is
comparable to GaAs LNA as in 1995, i.e. around $50.0 million.
3.4 Millimeter Wave Circuit Applications
The millimeter (mm) - wave region of the electromagnetic spectrum has frequency from
18 to 500GHz. The high frequency of millimeters waves makes them useful for a variety
of applications including large amount of computer data transmission, cellular
communications, video camera (it is now under development by TREX Enterprises in
San Diego, CA 5o) and radar.
One important application is compact radar, which takes advantage of small beam width
of millimeter wave propagation. Beam width is a measure of how a transmitted beam
spreads out as it gets farther from original point. In radar, narrow beam is desired instead
of fanning out. Unfortunately, small beam width requires large antenna sizes. It becomes
difficult to design a good radar set that will fit, for example, inside a cramped airplane
cockpit 51.
In spite of that, the beam width can be made smaller by increasing the operating
frequency for a given antenna. Considering this, compact antenna can be realized if high
frequency millimeter wave communication is utilized. Such millimeter-wave radar has
already been used in military aircraft and vehicle collision avoidance system. In addition
to smaller size, millimeter-wave radar also demonstrates better resolution than
microwave counterparts. It can also penetrate fog, rain, snow during the bad weather.
Millimeter-wave radar can be a great boon to vehicle collision avoidance system. From
mid 1990s a variety of collision warning systems were under development at frequencies
ranging from 10-77 GHz, such as Delphi's forewarn smart cruise control, which uses
concealed millimeter-wave radar sensor behind the front bumper and is currently adopted
in select Cadillacs and Jaguars. Eaton's VORAD (Vehicle On-board RADar) Collision
Warning System was developed mainly for trucks and recreational vehicle. In addition to
US companies, Daimler Benz is the main European centre of research. Figure 30 shows a
radar sensor used in 2003-model Mercedes S-class automobiles. The radar sensor is
linked to electronic control and braking system to maintain a safe distance.
Figure 30: A radar sensor used in 2003-model Mercedes S-class automobiles. The circuits that
transmit and receive millimeter waves are housed beneath the dome-shaped plastic "radome," which
s
is about 10 cm (4 inches) in diameter. This unit is mounted behind a port"
.
3.5 Competitors for LNA and Millimeter-Wave Circuits
Other products for LNA and millimeter-wave circuit applications are mainly based on Si,
GaAs, SiGe, InP or SiC. At the moment the chips based on Si and GaAs prevail in
market. Silicon chips are cheap and related technology has been developed for over 40
years. They can be well integrated into circuits. Nevertheless, Si products are limited by
its own properties, such as a maximum operating frequency of about 2GHz, and less
power efficient.
GaAs chips are replacing a lot of traditional silicon chips in communication field due to
higher effective mobility, lower noise and less power consumption. There are different
kinds of transistors made from GaAs. MESFET is the earliest one and is still the
prevailing GaAs transistor used in industry. It has power level up to 10W with low noise
up to 2GHz. It cannot be used at high frequency and therefore usage is limited in
micrometer-wave
circuits. Heterojunction bipolar transistor (HBT) is the first
commercialized GaAs bipolar transistor. It has low noise at frequencies lower than
100MHz and low linearity as well. High electron mobility transistors (HEMTs) have low
noise at higher frequency (100GHz). HEMT has high gain performance and is the most
efficient GaAs device. Pseudomorphic HEMT (pHEMTs) adopts indium, and can work at
even higher frequencies in millimeter-wave system. GaAs technology is the best
established compound semiconductor technology. Though InSb QWFET can provide
higher operating frequency and less power consumption, the feasibility of InSb MMIC
has not demonstrated yet. InSb QWFET needs time to compete with GaAs chips.
SiGe offers potentially very good RF performance and, most significantly, compatibility
with submicron CMOS, although its power handling capability is limited. SiGe devices
are based on the well-established silicon technology. This is the most important
advantage compared to other III-V compounds. SiGe can be grown on large (8-inch, and
maybe 12-inch), cheap, and robust silicon wafers. SiGe chips can operate at millimeterwave frequency but are not suitable for amplifier beyond 0.5W. SiGe LNA finds
increasing applications in low-power RF transmit-receive section. TEMIC, a subsidiary
of Daimler Benz is the first to market SiGe RF components. Other players include IBM,
Intel, Conexant Systems Inc., Analog Devices, and NEC etc. In March, 2006,
STMicroelectronics introduced first fully integrated low-noise amplifier IC SMA661AS
for GPS applications. SMA661AS uses 70GHz SiGe BiCMOS technology, and achieves
noise figure 1.4dB. It is priced only at US$0.35 in quantities of one million units 52. As
early as 2002, IBM Microelectronics announced SiGe bipolar transistor with a maximum
transistor frequency of 350 GHz, which targeted market in optical networking and
wireless communication
3
Indium Phosphide (InP) HEMT could be widely used in fiber-optic, millimeter-wave and
even wireless communication. InP has high electron mobility (-9x SiGe and 2x GaAs)
and high breakdown voltage (-2xSiGe). It is suitable for LNA with frequencies from
below 1GHz to well above 200GHz. It can also be easily integrated into integrated
circuits (ICs). InP has unique advantage in the fiber-optic arena. It is the only
semiconductor technology that allows photo-detectors and lasers to be integrated on the
same substrate with other analog and mixed signal functionality. In the wireless industry,
InP-based amplifiers provide lower power consumption, high linearity and low
temperature sensitivity. These performances can significantly enhance the battery life and
reception in current handset designs, very similar to InSb QWFET. On the downside, InP
is a relatively new material and therefore large, high quality wafers are not available.
There are only 2 to 4 inch InP wafers in market at present. For example, recently
Northrop Grumman Space Technology (NGST) has steadily transferred its InP HBT
production from 3 to 4 inch substrates 54 . The high cost of InP devices mainly results from
the substrate. If the technology to grow InP wafer improves, price of InP devices would
drop substantially and become competitive to GaAs devices.
Figure 31: Superior low-noise performance of NGST InP device to NGST GaAs counterparts 4 .
To summarize, Si and GaAs devices are still dominant in market, but they have already
shown limitations in one way or another. Novel devices, such as SiGe, InP and InSb, are
promising to take market share away from GaAs counterparts. Both SiGe and InP devices
are relatively easy to integrate into silicon based MMIC compared to InSb chips. As is
known, integration is the key to produce small, low-cost, high-volume electronic products.
Take cell phone for example, high level of integration reduces the number of components
in the product. The integrated circuits also tend to be faster and more energy efficient
than circuits comprising separate components, which are both ideal properties for cell
phones. Regarding performance, both SiGe and InP transistors are capable to work in the
millimeter wave frequency range. IBM's SiGe HBT is demonstrated to work in
frequency as high as 350 GHz, which is comparable to InSb QWFET. InSb devices will
face severe competition from SiGe, InP products in either performance or cost. InSb has
higher electron mobility than any other semiconductor materials. That means it has
potential to achieve higher frequency performance than today's 85 nm technology. InSb
QWFET is still superior to SiGe or InP in power consumption. Initial production cost
most probably will be high and that will erode market share. As is shown in chapter 5
cost model later on, substrate cost is crucial to control the cost. Cheaper silicon substrate
will give InSb products a huge boost in market. Another spin-off of silicon substrate is
easy integration with MMIC. Therefore, the improvement of technology is the key to
success of the InSb transistor.
Chapter 4 Intellectual Property related issues
4.1 Patent filing
The term "Intellectual property" refers to patents, trademarks, copyrights, and trade
secrets or know-how. This is a special classification of intangible property and is unique
because the owner of intellectual property is protected by law from unauthorized
exploitation of it by others. Therefore, it is very important to file patent after a new
technology is developed. The first thing to do for Intel is to file InSb QWFET patent
through American patent office.
The process of obtaining a patent can be very complex and time-consuming. It involves
attorneys and other specialists. American patent law emphasizes the protection of original
inventor. First person to invent is entitled to the patent rather than first person to file as in
other countries. Research will be done to make sure that the proper person gets the patent.
Obtaining a patent involves the following seven general processes (taken from
reference 55):
1. "An application, including a description of the patent and the claims sought, a
drawing(when appropriate), a declaration that the application is the original
inventor, and a filing fee, is made to the Commissioner of Patents and Trademarks.
2. When the application is accepted as being complete, it is assigned to an examiner
who is knowledgeable about the specific technology. Applications are normally
processed in turn.
3. The examiner analyzes the application for compliance with legal requirements
and makes a search through prior U.S. and foreign patents on file, as well as
through technical literature, to see if the invention is both novel and nonobvious.
The examiner reaches a decision as to the patentability of the claimed invention.
4. The application is notified in writing of this decision in an Office Action. It is not
uncommon for some or all of the claims to be initially rejected.
5. The applicant must request a reconsideration in writing, and clearly and
completely explain the basis for his or her belief that the examiner has erred in the
examination.
6. The application is then reconsidered and a second Office Action is issued.
7. If the patent is not granted, the process may go through a third round, after which
the action is usually considered final. "
The timeline to obtain a patent is shown in figure 32. It can cost more than three years
to get the granted patent.
EXA LMINATION
MONTHS 0
12
p
p
p
18
24
ALLOWANCE
36
1ýý
..
0
8 P"
W
W00
-t-_,.--r,
*
W
I YEAR
Figure 32: timeline to obtain a patents
0
aa
"-
0
H
z3
M
P
4.2 Patent search
4.2.1 Carrier extraction
InSb material has high intrinsic carrier concentration (2x10' 6 cm- 3) due to low band gap.
This leads to InSb devices exhibiting high leakage current at or near ambient temperature
of 295K. There have been several patents addressing this problem. US Pat. No. 5382814
by the Secretary of the State for Defense, UK (the predecessor of QinetiQ) discloses a
non-equilibrium metal-insulator-semiconductor field effect transistor (MISFET) using the
phenomena of carrier exclusion and extraction to reduce the intrinsic contribution of the
carrier below the equilibrium level. The latest development of carrier extraction is US Pat.
No.6770902, "charge carrier extracting transistor", which was published on Aug
3 rd
2004, and held by QinetiQ. In its claims, the conducting region consists at least partly of
a quantum well. This transistor contains an excluding junction for inhibiting minority
carrier supply to the quantum well. Moreover, a heterojunction is incorporated between
two semiconductor materials of different band gaps, which are both wider than that of the
quantum well. Such heterojunction is used for carrier exclusion. It includes at least one
junction, which can be biased, to reduce the intrinsic conduction in the quantum well.
QinetiQ also holds the trademark 'EXTRACTIVE' (U.K. community trademark No.
E3195401)5 7 for this technology. Fortunately, as a result of the cooperation between Intel
and QinetiQ, these patents should not block the commercialization of InSb QWFET.
4.2.2 Field Effect Transistor
As is seen from section 4.2.1, most of the patents regarding InSb carrier extraction
technology are held by QinetiQ Ltd, UK. The earliest InSb FET patent, GB.Pat.
No.2346481, was granted to QinetiQ on Aug, 9th , 2000. There are also other similar
patents, e.g. US. Pat. No.6624451. The structure of GB2346481 is different from InSb
QWFET58. It employs base biasing to depress the intrinsic contribution to conduction and
reduce leakage current. It incorporates four successive layers: a p+ InSb base layer, a p+
InAlSb barrier layer, an intrinsic layer and an insulating SiO 2 layer. P+ source and drain
regions are implanted in the intrinsic layer. This patent would not be related to
commercialization of InSb QWFET much. Following this patent, QinetiQ was granted
U.S. Pat. No.2005/019461359 . This FET has a quantum well and a primary conduction
channel. In additional, at least one secondary conduction channel adjacent and in contact
with the primary channel has an effective band gap greater than that of the primary
channel. Higher energy carriers, which might cause impact ionization leading to runaway,
are thus diverted into the secondary channel allowing the device to run faster at increased
voltages and exhibit much greater resistance to runaway. The primary channel is
preferably of low band gap material, including InSb, InAs, InAsySbl-y, and InxGal.xAs etc.
Channel doping is provided in the second channel. This transistor is constructed so that
the holes are confined in a valence band well for removal at the source contact. It also
has a substrate contact for removal of holes. This patent is similar to Intel's 85 nm InSb
QWFET technology.
4.2.3 Modulation Doped Field Effect Transistor (MODFET)
Though most patents are attributed to QinetiQ, there do have some other patents that have
to be considered carefully. In this InSb QWFET, modulation doping is used. A single Te
8-doped donor layer (1-1.8x101 2cm-2) is adopted above the quantum well. An optional
etch-stop layer is employed to deep recess the gate. There are a handful of patents
concerning modulation doping. U.S. Pat. No.6100548 and 5856217 by Nguyen et al
concern group III nitride compounds. U.S. Pat. No.6855963 and 6455871 etc. are
regarding SiGe FET. The most relevant one is U.S. Pat. No.5334865, which was filed on
2 nd,
Aug 1994 by Allied signal Inc (US). Its claims cover a semiconductor device
comprising from bottom to top: a semi-insulating semiconductor substrate, an undoped
semiconductor buffer layer, at least one undoped semiconductor spacer layer, of which at
least one spacer layer has a different composition than buffer layer, and an etch stop layer.
The detailed structure of this MODFET is shown in figure 33.
Figure 33: MODFET structure for threshold control
Nevertheless, this invention aims to improve the threshold voltage control of MODFET
structure. The etch stop layer regards either GaAs layer sandwiched between an undoped
AlGaAs layer and a doped AlGaAs layer, or undoped InGaAs layer sandwiched between
an undoped InP spacer layer and a doped InP layer. InSb QWFET has similar structure as
US. Pat. No.5334865, but there are fundamental differences in layer compositions.
Therefore, MODFET patents would not be a hurdle for commercialization.
4.2.4 GaSb/InSb Complementary Heterojunction Field Effect Transistor (HFET)
TRW Inc filed US Pat. No.6384432 in 2002. This patent is about a complementary
heterojunction field effect transistor (CFET). N-type HFET includes a quantum well,
which is formed from Indium Antimonide (InSb) and acts as conduction channel. The ptype conduction channel is formed through either InSb or GaSb.
From figure 34, the InSb/GaSb quantum well is sandwiched between a buffer (AlSb) and
a barrier layer (AISb). The complementary p-type HFET is formed by p-type doping of a
cap layer, which is formed from GaSb60
("20
IUCTURE
Gab GAP
AtSb BA ER
MSb BUFFER
Figure 34: schematic of GaSb/InSb HFET
In short, as demonstrated through the above sections, most of the patents are held by
Intel's partner QinetiQ Ltd. However, there are some MODFET and HFET related
patents in hands of other companies. Intel may need to do some minor changes in the
structure design in case of the legal disputes. Generally there would not be patents that
provide considerable blocking mechanisms to bringing InSb QWFET to the market.
4.3. Joint Venture
Development of new technology alone can involve billions of dollars. In spite of that,
success of technology is only the first step. Level of acceptance by customers in market is
crucial. Introduction of the new product into market will cost a lot in advertising, building
well-organized sales force etc. Considering the benefits of time-saving, cost-reduction,
and risk minimization, corporate partners are brought together from all over the world as
they expand into new product lines and new global markets. Joint venture partners share
secrets and economic benefits, including the valuable intellectual property of other
partners. InSb technology can be a huge project for any single company. Cooperation
among enterprises and research institutes is necessary. Given the whopping investment
nature of semiconductor industry, partnership and joint venture are very common. Just
look back history of semiconductor industry and take some examples. From 1992 Intel
and Sharp had a 10 - year agreement to co-develop 0.6 and 0.4 micron processes and for
sharp to produce flash chips on a foundry basis. From 1996 NEC and Texas Instrument
(TI) jointly developed combined microprocessor (MPU) - digital signal processing (DSP)
chip. Even in Singapore, there are some joint ventures invested by world-renowned
electronics companies. For example, System on Silicon Manufacturing Co. Pte. Ltd.
(SSMC) is a joint venture of Philips Electronics, Taiwan Semiconductor Manufacturing
Company Ltd (TSMC) and EDB Investment Pte Ltd (EDB - Economic Development
Board of Singapore).
Among all these joint ventures, they can be formed in different models. Some companies
bring manufacturing capabilities to a venture, while other partners bring research
capabilities or marketing know-how. For example, one possible joint venture can be
formed of Intel, QinetiQ and Dell. QinetiQ is the forerunner of InSb technology. It started
to explore InSb device, e.g. InSb detector and laser from mid 1980s. A lot of patents are
held by QinetiQ. Intel is the No. 1 giant in semiconductor industry. Its involvement in
InSb QWFET has substantially accelerated the progress of research. In addition, Intel has
dozens of fabs worldwide, which provides enough capability in manufacturing. Intel also
possesses well-recognized processor trademarks among general consumers. Dell is the
world top PC producer. Over the years, Dell has already become a household name. The
brands of 'Intel' and 'Dell' will altogether infuse consumers with the confidence of new
technology. More importantly, association with such brand names that the targeted PC
market trusts could allow for a higher selling price at retail levels. It correspondingly
translates to a higher wholesale price. Furthermore, Dell owns one of the most successful
PC distribution network required for the new product, which could provide quick market
entry. Very often the first company into the market with a new product can establish a
formidable market share position. Followers, even those possessing improved products,
can have a tough time turning the heads of consumers away from the perceived product
innovator.
4.4. Strategic Alliance
Besides joint venture, strategic alliances have also become popular among many
companies. Some of the reasons are already discussed in joint venture section. Each
partner contributes capital funding, access to the different core competencies of the
alliance partners and therefore risk is minimized. It also accelerates the time needed for
development because of the shared expertise. Alliances are considered to exist when two
companies come together to work on a single project. An alliance is less formal than a
joint venture whereby two companies come together to form a third company.
Strategic alliance is an option for Intel, too. Intel can build alliance with other research
labs or technology companies. Actually Intel and QinetiQ have already built an alliance
through the two year joint research. Nevertheless, it must be mentioned here that strategic
alliances are not to be entered into without careful consideration. They are more complex
business combination than joint venture. Results to date show that few have achieved
their desired goals. Like marriages, the breakup can leave the divorced partners with
strong animosity for each other. Dr. Bob Gussin of Johnson & Johnson (J&J) explained
that both partners need to conduct or have (adopted from reference 55):
* "A clear understanding of the goals to be attained
* A clear strategy for reaching the defined goals
* Milestones by which to judge the progress of the alliance
* Extensive up-front planning
* Defined roles of responsibility for each partner
* Frequent communication between the partners at the operating management level
* Enthusiastic and continuing support from upper management"
Given all these factors, partners must be picked carefully and it is important that both
companies have respect for each other. Personalities and culture become more important
in alliances than in any other type of business combination or operating structure.
The most important reason for alliance failures is a mismatch between the desired
purposes of alliance partners. Unless the alliance involves the core businesses of both
companies, it is likely to fail. The success of InSb technology will mostly depend on how
important InSb on Intel's future technology strategy. Besides QinetiQ, Intel can try to
build alliances with other top universities, e.g. MIT, Stanford etc. Though it is difficult to
make a success, strategic alliance is becoming more and more important. "In the future,
access to patent rights in the form of licenses and cross-licenses will not provide the
broad expertise that companies need. Alliances will need to be formed to help a licensee
practice the patent rights licensed. In the future, where broad and diverse technical
competencies are required, a license to practice the new technology will be only the
beginning. The licensees will need education to allow for successful application of the
technology."(Adopted from reference 55)
Chapter 5 Cost Modeling
Semiconductor has developed for more than 40 years. An almost seamless
supply/demand chain has been formed and well connected. Manufacturing technology of
compound semiconductor falls far behind silicon counterpart. However, the process flow
is more or less the same. There are usually five steps in chip manufacturing, namely, 1.
starting substrate; 2. wafer fabrication; 3. wafer sort/test; 4. assembly and packaging;
5.final testing. The IC manufacturing process adopted from IC knowledge is shown in
figure 35. Giants like Intel, IBM can do all the steps under one roof, and they are known
as independent device manufacturers. Intel processors are designed by Intel engineers,
manufactured on Intel's own fab, and sold under Intel's name. The only part that Intel
outsources is the actual stocking, warehousing, and distribution of its chips. Another
extreme is fabless chip companies like Xilinx. Xilinx designs and sells its own chips but
doesn't actually hold its own fabs. Xilinx rents IBM and other companies' fab to
manufacture chips labeled with Xilinx logo. The third type is foundry. The typical
example is TSMC, which makes chips according to clients' orders and doesn't have its
own chips. In short, most semiconductor companies are involved in only one or two steps
of the pipeline. The trend for electronics giants is to outsource the non-core business, e.g.
packaging and test, to minimize the cost.
1) Starting substrate silicon wafer
(purchased).
2) Wafer fabrication fabricate IC's
on the wafer
3) Wafer
test eý
mark b
Atý
5) Mark & class/final test -
mark and final
test packaged product
4) Packaging -
assemble ICs
into packages
143
Figure 35: IC manufacturing61
Production starts from the substrate. The starting wafers are purchased from wafer
vendors. Currently InSb QWFET is still built on GaAs substrate, but silicon is more
economic and promising in the long run as discussed in previous chapters. In this
modeling, cost based on both silicon and GaAs substrates will be presented and compared.
The big five silicon wafer companies are SEH, SUMCO, Wacker-Siltronic, Komatsu, and
MEMC, which totally amount to 90% of world silicon wafer production 62 . The average
selling price for 200mm silicon wafer is $45 and $200 for 300mm wafer, respectively 63,
but the high grade 300mm wafer can cost thousands of dollars. These companies can be
Intel's silicon wafer source. Figure 36 shows the monthly production capacity of the
world top 5 silicon wafer manufacturers.
200
180
160
140
120
100
80
60,
40
200.
Shin Etsu
Hlandati
SUMCO
WackerSiltronic
(SEH)
MEMC
Kornatsu
Electronic
Materials
Figure 36: monthly capacity of world top 5 silicon wafer manufacturers64
As for semi-insulating (SI) GaAs wafer, it is relatively much smaller market compared to
silicon wafer. Litton Airtron (US), Sumitomo Electric (Japan), M/A-COM (US), Hitachi
Cable (Japan), Freiberger (Germany) jointly dominate world SI GaAs wafer market49.
They can provide GaAs starting wafers for Intel.
Fabrication is the most complex process. For InSb QWFET fabrication, there is growth of
a single metamorphic buffer layer on the substrate. Afterwards other channel and barrier
layers are epitaxially grown. Finally it is A120 3 dielectric layer formation. During the
process flow, there are some procedures repeated, such as coating of photoresist
(lithography), print of the mask on the device(projection) and introduction of impurities
on the open area of the surface (diffusion or ion implantation). At the end of the repeated
processes, the desired circuit structure is reproduced on the wafer. Then the layer is
insulated and electrical connections are formed (metallization). Given the process flow,
MBE and CVD machines are used to grow different layers. Lithography needs accurate
steppers. Both dry and wet etch are required. Various furnaces are used for metal
annealing. Clean equipment and wet benches are purchased for auxiliary usage. The basic
equipment and cost are shown in appendix A. The default values are from SEMTECH.
Chief equipment manufacturers are Applied Materials, Tokyo Electron Limited (TEL),
Nikon, KLA-Tencor, ASM Lithography, Teradyne, Lam Research, Canon etc. Applied
materials of Santa Clara, California, has been the market leader in recent years. The
equipment table in appendix A shows just the minimum outfit required for one streamline
manufacturing. The actual case may need dozens more other equipment.
Considering the tooling cost, it is assumed that mask accounts for the majority of that.
Mask design is usually controlled by a computer, expensive and time consuming. It is
further assumed that totally 100 masks are needed in each streamline production and
purchased from some vendors. Average cost of mask is estimated $10000; life
expectancy is for every 40000 wafers production. In addition to mask, reticle is also
considered important consumable tool. Reticle is sort of negative film, mounted just a
few inches above the wafer and usually made of quartz instead of normal camera film.
Tooling coefficient is set as 1.5 to include other possible tooling.
For a variety of economic reasons, it is important for chip companies to test each chip as
early as possible. The first step in this process is called wafer probing, which is done
immediately after fabrication. The entire wafer is put under a tester. Faulty chips are
quickly marked with a tiny dot of red paint. The machine stepper leaves a bit of space
between each chip as it moves left to right and top to bottom. This blank area allows the
saw to carefully cut in between the chips without damaging them. Chips that have been
cut apart are called die. Natural variations in manufacturing will make some chips work
slightly faster than others. Therefore chips can be classified according to performance
and sold at different prices so that profit is maximized.
After testing, good chips needs to be wrapped up in a package so it can be handled and
shipped without damage. Most chips are housed in plastic packages that look like little
black houses. They are packed clamshell style. First the chip is laid in the lower half of a
plastic package, usually on a spot of glue to hold it; then the upper half of the package is
cemented to the bottom. A hollow cavity in the middle leaves room for the chip and
avoids crushing it. After the chips are packaged, they will be completely tested once
again. Some chips will be overly sensitive to heat and fail during the plastic
encapsulation process so it's important to make one last check to make sure everything's
in order.
Most companies outsource packaging. Companies such as STATS ChipPAC Ltd
(Singapore) provide packaging design, assembly and testing services to customers. An
open market price is used in packaging and testing. It is estimated that packaging costs $2
in material and labor adds another $0.50 of cost. Testing itself adds $1.00 to our cost
(mostly
labor),
and
the
fallout
from
testing
effectively
adds
$10(silicon
substrate)/$15(GaAs substrate) (considering the high cost of InSb QWFET chip) to each
remaining part.
Each of the stages of the manufacturing process has different yields. Yield represents the
percentage of semiconductor devices which are usable in the next stage of manufacturing
process. The wafer fabrication stage has traditionally the lowest yield. When a new fab is
built, all of the chips it produces for the first few weeks will probably be bad. Over time,
the production yield will improve. Usually production yield surpasses 90% only after a
fab has been operating nonstop for more than a year. Contamination in the clean room
can affect yield significantly. Tiny particles of dust in the clean rooms can settle on a
wafer during processing and ruin some of the chips. Imperfections in the processing
chemicals also cause defects, with contaminated water being a major culprit. Exact yield
information of fab is confidential between manufacturers. Yield of 85% to about 97% are
typical for midrange and high-end ICs. Traditionally simple chips have higher yield while
new/complex chips have low yield. In addition, microprocessor wafer has relatively large
die size, which will hurt yield as well. Microprocessors have reached tens of millions of
transistors per die. For example, there are approximately 281 Pentium
4 TM
ICs on a
300mm wafer 65 . It is reported by Northrop Grumman Space technology (NGST) that
their InP HBT production line had 85%-90% device yield 54. Given all these factors, yield
based on silicon substrate is set to 0.85 and yield based on GaAs substrate is 0.80 in cost
model.
Labor cost takes substantial part in fab expenses. Operator, supervisor, manager, engineer
and overhead staff account for most labor in fab. It is assumed that high automation fab is
built. Therefore, less manpower is needed. Based on data from competitive
semiconductor manufacturing (CSM) program of UC Berkeley 64, manpower and salary
can be estimated.
Table 6: Calculation of manpower needed in fab"
High Automation
Level
Fixed
Overhead staff
Manager
Supervisor
Operator
200
12
0.0034
0.0002
472
28
15
Engineer
8
Per wafer
start/month
Total Number
0.0001320
15
19
118
A minimum number of manpower is specified first. The exact number of operator,
supervisor and overhead staff depends on the monthly production volume. Number of
engineers is set to 1/3 of the number of operators. The salary of different manpower is
based on data from SEMTECH and listed in table 7.
Table 7: Salary of different kinds of manpower in fab"
Personnel
Annual Salary
Operator
$60,000.00
Supervisor
$80,000.00
Manager
$125,000.00
Overhead staff
$70,000.00
Engineer
$100,000.00
Labor Cost/month
$3,797,083.33
It takes about 18 months to build and outfit a new fab. World's microprocessor vendors
produce and sell about 10 billion microprocessor chips, only 2% are used in PCs. PC
microprocessors market is about 200 million units per year. Microprocessor chips can be
very profitable (sometimes more than $100 per chip). For a new, high-capability fab,
50000 wafers per month is a good production target. Since compound semiconductor fab
doesn't have so much demand as silicon fab. The smallest scale is set as 100 wafers per
month, medium scale 500 wafers per month, large scale 1000 wafers per month, and
extra large scale 1500 wafers per month.
Based on the cost model, sensitivity analysis is done. In figure 37, production capacity is
5000 wafers/month. Unit variable cost, fixed cost and total cost all decrease with
production volume (PV). As PV increases, manufacturing facilities are better utilized,
and usage of resources is maximized. As is seen from figure 38, variable cost is much
less than fixed cost. Majority of the cost of producing a chip comes from fixed overhead,
especially in the depreciation of the fab and its equipment. The incremental cost of
producing each chip keeps decreasing.
Cost versus production volume
$25,000.00
$20,000.00
--
S$15,000.00
Var. Cost
- Fixed Cost
E $10,000.00
Total cost
$5,000.00
$0.00
0
1000 2000 3000 4000 5000 6000
production volume
Figure 37: the plot of cost versus production volume given the production capacity 5000
wafers/month
rrrnnr
I UU/o
90%
80%
8 wafer cost
7 Labor cost
6 energy cost
70%
60%
50%
40%
30%
o Maintenance cost
o Building Cost
* Tooling Cost
2 Machine Cost
20%
10%
0%
Figure 38: cost analysis given production volume 4500 wafers/month and production capacity 5000
wafers/month.
Cost versus production volume
$80U,UUU.UU
$70,000.00
$60,000.00
* $50,000.00
$40,000.00
i
- Var. Cost
- Fixed Cost
Total cost
$30,000.00
$20,000.00
$10,000.00
$0.00
0
100
200
300
400
500
600
production volume
Figure 39: the plot of cost versus production volume given the production capacity 500 wafers/month
Figure 40: cost analysis given production volume 450 wafers/month and production capacity 500
wafers/month.
Production capacity (PC) is another important factor to influence cost. Generally unit cost
increases with production capacity as is seen from figure 41. Therefore it is better to fully
unitize fab from common sense. However, some capacity margin is usually reserved for
microprocessor fab. Microprocessor chips can be very profitable, but there's a limited
demand for them at any given price. Rather than optimize their fabs to run at 100% of
capacity, microprocessor manufacturers want to ensure they have some excess capacity in
case demand suddenly surges.
Figure 41: plot of cost versus production volume at different production capacity.
From the model, if the plant operates at small scale (100wafers/month) and wafer is
based on GaAs substrate, cost can reach as high as $508 even if it operates at full scale.
Take a more reasonable value. Production volume is set to 450 wafers/month, and
production capacity is 500 wafers/month. Cost is calculated $148. In contrast, if 12 inch
silicon wafer is used, PV=450 wafers/month, PC=500 wafers/month, cost is reduced to
$58. This is significant reduction due to the usage of cheap and large silicon wafer.
However, actual cost can be much higher than what is estimated here. The whole process
flow is simplified a lot as is seen from appendix A. The industrial processing may need
hundreds of steps. According to McKinsey Global report, average Intel microprocessor
price fluctuated between $210 and $230 from 1995 to 199966. In the cost model, two
prices are set for InSb QWFET chip. One price is fixed at $250 to make the product
competitive in market and further gain the foothold in market. Another price is set at
$350 to maximize profit.
The marketing strategy is split into two periods. Period one is from 2006-2010, and
period two is from 2011-2015. As is mentioned in chapter three, Intel plans to launch it
into market after 2015. Even considering the most optimistic scenario, InSb chip will
appear in market only beyond 2010. This 2006-2015 timeline just depicts a pseudo case,
assuming InSb products can be launched immediately. In spite of that, the result can still
be meaningful reference to evaluate potential market and profit.
The details about how decision tree works are shown in Appendix B and C. Basically the
principle behind decision tree is to maximize profits (expected value, i.e. EV). Decision
tree recommends large scale fab and higher price at $350 in period one. However, higher
price may hurt demand badly. To be cautious, only a medium scale fab will be built and
$350 sale price will be charged in the initial stage. Price can be adjusted sometime in
period one depending on the market response. In period two, decision tree recommends
either large scale or very large scale fab and higher price. Such strategies can be adopted
provided period one has seized substantial market share. The expected 10 years profits
for silicon substrate based InSb chips are around $3 billion. Profits for GaAs substrate is
around $600 million due to smaller wafer and high cost
Analysis of cost modeling is so far. Cost is always a headache for new technology.
Manufacturing cost will be driven down only when the technology becomes mature and
large scale production turns feasible. Take silicon technology for example. During its
development, various problems were raised and then settled. More and more companies
joined to explore market. In 1980, the first IBM PC cost US$3000, and was built on
Intel's 8088 processor. Today, with half the price, you can get the latest posh laptop from
store. Similar track can apply to InSb chips and other compound semiconductor
products. .
Chapter 6 Conclusion and Future Work
Silicon transistor has been under scaling for more than 40 years. According to Moore's
Law, the number of transistors on a chip doubles about every 18 months. Today there are
millions of transistors in every single Pentium TM chip. Will Moore's law last for ever? At
least more transistors are still being integrated into single chips. However, due to the
limitation of silicon material, concurrently more cutting-edge technologies, such as strain
silicon and tri-gate transistors, are applied. Another way is to change material. It is tough
task considering silicon technology has already been systematically developed compared
to any other semiconductor materials. In spite of that, new materials are potential to
change the silicon limitation permanently. It is worth trying.
III-V compound material, carbon nanotube and silicon nanowire are on the list. Among
III-V compound materials, InSb has the highest electron mobility and holds the hope for
high speed transistor. Based on quantum theory, carbon nanotube is said to achieve even
higher electron mobility than InSb. However, the growth and fabrication of carbon
nanotube device still lag far behind. Silicon nanowire transistor is a compromise between
carbon nanotube and silicon. Its performance is not as good as carbon nanotube but easier
to fabricate since it is still silicon based material.
QuinetiQ Ltd, UK, is a forerunner in InSb related research. Considering that, Intel had a
two-year jointly research with QuinetiQ on InSb QWFET. Their latest development was
85nm gate length InSb QWFET, which was announced at the International Electron
Devices Meeting (IEDM) Conference in Washington, DC, 2005. Both the enhancement
mode and depletion mode devices were demonstrated for the first time. The e-mode
device can operate at frequency as high as 305 GHz. It can further operate under voltage
as low as 0.5 V and reduce the power consumption with a factor of 10.
InSb QWFET has a lot of unique features in design. It utilizes quantum well to confine
electrons so that high electron transport speed can be achieved. The usage of high
electron barrier material AlInSb further enhances the breakdown performance. P-type
buffer doping reduces DIBL and improves scalability of device. The high dielectric
material A120 3 was first demonstrated to reduce the leakage current.
InSb QWFET has various potential applications. Intel plans to launch it into market after
2015 and complement the prevailing silicon technology. Given excellent noise
performance, InSb QWFET can also be used as low noise amplifier in space
communication facilities. Currently most devices operate at microwave frequency range.
InSb chip can operate well in millimeter wave range. Such uncommon properties make it
ideal for compact radar, video camera etc.
Cost of InSb chips is also examined. This cost model is built on research results of UC.
Berkeley's Competitive Semiconductor Manufacturing (CSM) Program. Two versions
are discussed. One has 12 inch silicon as substrate; the other has 6 inch SI GaAs as
substrate. Demand of InSb products are far below silicon counterparts. InSb chip plant is
relative small, and production capacity ranges only from 100 to 1500 wafers/month.
Given such scenario, labor cost still account for much of the expenditure. In contrast, in
large silicon wafer plant, variable cost is negligible. Most cost comes from equipment
depreciation and maintenance. Another point to notice is that wafer cost is very large
proportion of the total cost. Therefore, replacement of cheap substrate will be crucial to
reduce the total cost.
Nevertheless, there are still severe challenges ahead for InSb QWFET technology.
Substrate is one issue. Currently semi-insulating GaAs substrate is used, which is
expensive and makes it difficult to integrate chip into circuits. Cost and integration are
the key for success of InSb chips. So far there are only electron channel devices. More
research is required to explore ultra-high hole mobility P-channel device for
complementary logic. Although A120 3 has been proved to be effective, high quality highK dielectric materials are still needed to be demonstrated. Similar to silicon, gate length
of InSb transistors has been continuously scaled down to 85nm, which, however, still lags
behind silicon's cutting-edge 45nm technology. Future technology breakthroughs will be
crucial for the success of InSb QWFET.
Appendix A: Spreadsheet for Cost Modeling
Cost Modeling for
InSb QWFET
Please chanpe data only in the cells shaded this color.
Blank 12 inch wafer cost ($)
Number of dies
3500
Line Yield
0.85
Vest cost and test loss/chip ($)
Packaging cost/chip ($)
281
10
2.5
Microprocessor chip needs high quality substrate wafer. 200-mm silicon wafer is about $3100 in 2003. It is estimated that now
300mm (12 inch) wafer should be around 3500.
TM
It is checked that there are approximately 281 Pentium 4 chips in one 300mm silicon wafer. The same
value is adopted here.
New product should have low yield, therefore 0.85 is adopted here.
Test costs about $1-$2 per chip, Chip loss can be high since it is expensive chip. Total cost is
estimated $10.
Package can cost $2, adding another $0.50 for assembly. Data from book "essential guide to
semiconductors".
~... ....
~"~~"""'
Monthly production volume
Facility production capacity
Nvork days/month
No operations
Unplanned Downtime
Maintenance time
Electricity Requirement
Price of Electricity
Energy Adjustment Factor
Annual Energy Consumption
Sapital
Recovery Rate
ccounting Life of Machine
450/month
500/month
30days
hrs/da
1.5y
hrs/da
0.5y
hrs/da
ly
kWh/w
100afer
$0.15/kWh
1.5
kwh/ye
819000ar
10%
10years
Fab usually runs 365 days, and 24 hours per day. Equipment is energy consuming, so it is estimated energy
requirement 100 KWh/wafer. Energy
adjustment factor account for other usage, e.g. water. Fab usually needs to be updated after several years.
Fab machine therefore should have shorter
life time. 10-year isused here.
Ru.ldina
Coo.
Life
(years)
Space Costs
Constru Occupanc Space/pe
rson
y cost
ction
($)
($/yr)
(sq.ft.)
Direct (for manufacturing)
Clean room
25
3500
175
Non-clean room
25
175
50
25
175
50
ndirect
Non-manufacturing
150
Data from UC Berkeley, competitive semiconductor manufacturing (CSM)
program.
Overhea
OperatoSuperv
r
sor _Vanager d staff Engineer
20
12
15
High Automation Level
ixed
er wafer start/month
000
otal Number
0.00012
21
0.0002
201.7
12.1
15
9
51
Itisassumed here a high automation level fab is built. Fixed
umber of man power is the minimum number of people
eeded infab.
The
coefficient of per wafer start/month adjusts the
anpower needed according to monthly production volume.
Number of engineers is set to be 1/3 of number of operators.
Annual
Salary
$60,000.
00
Personnel
Operator
$80,000.
upervisor
00
$125,00
Manager
0.00
$70,000.
Overhead staff
00
$100,00
ngineer
0.00
$1,722,9
1 6.67
labor Cost/month
Data from UC Berkeley, competitive semiconductor manufacturing (CSM)
program.
I
Equipment Set
-··-
-------------~
---
-
Cost per unit of
eauiDment--Space
consumed per
equipment
mm/aintceyr
Cleanroom
non-clean
$mm/Vyr :sq.ft.)
room (sq.ft.)
l
Equipment Type
CMP
CVDI
Smm
$mm $mm
0.3
0.45
latsni
Dry Etchl
Dry._Etch2
0.375
0.375
0.175
Dry Strip
0.15
FumnFastRmp
Furn Nitr
Furn OxAn
Implant
0.15
0.07
0,07
0.15
0.07
0.15
0.45
0.45
0.075
0.07
0.21
Insp PLY
InspVisual
Lithol
Litho2
MBE1
ium
0.21
0.035
480
0.9 0.42
1600
1600
0.35
0.6
2000
0.6
2000
1280
2000
2000
0.28
0.28
0.12 0.056
0.14
0.3
0.3 0.14
Clean
Wet Benchi
Wet Bench2
8.86
6.645
CVD: chemical
vapor
deposition
MBE:
molecular
beam epitaxy
Fum:
Furnace
Implant:
implantati
on
44.3
1120
960
960
960
3200
480
0.75
MBE2
1600
1600
0.175
3.101
;
6760
Data from UC Berkeley, competitive semiconductor manufacturing (CSM)
program.
CMP: chemical mechanical planarization
Litho: lithography
Reject Rate
Dedicated equipment
1.00%
Effective Production Volume
Effective Capacity
3apacity and Volume consistent?
Effective Cycle Time
3atch size
Capacity per stream per month
Run-Time for One Machine (produced)
Run-Time for One Machine (capacity)
Number of Parallel Streams
Average price of mask
Number of masks
Life Exp(wafers)
Other tools coefficient
Tooling Cost per year
16.90hr
40
1491
30.18%
33.53%
1
$10,000
100
40000
2.00
$405,00
0.00
It is assumed 100 masks are used inone streamline process. Life expectancy of mask is every 40000 wafers.
Other tools coefficient account for other
tools and raw material cost, e.g. gases, photoresist, deposition materials.
27040
Main machine cost
Tooling cost
Building cost
Maintenance cost(machine and building)
nergy cost
Labor cost
Total variable cost
Total Fabrication Cost
Total Cost
Cost per die
$59,805
$1,802. ,988.3
41
4 24.58% ,000.0(
$405,0
$75.00 00.00 1.02%
$3,963
,076.0
$35,973
6 10.01% ,000.0(
$733.90
$4,701
,003.1
$870.56
0 11.87%
$18,80
$3,481. 2,067.
$95,77E
,000.0C
$22.75 50.00 0.31%
$20,67
$3,828. 5,000.
70
00 52.21%
$20,79
$3,851. 7,850.
45
$57.86
Total cost includes fabrication cost, raw
wafer cost, testing, and packaging test
Total fabrication cost includes variable cost and fixed cost
Yield is considered in cost per die
·..
·.............
·.
.......
...
... · ....
Step
Clean
MBE-Alylnj.ySb buffer
VIBE-InSb channel
MBE-Alxlnl-xSb spacer
on-implantation
MBE-Allnl.xSb top barrier
Define Holmic contact
etch
E-beam evaporation
Lift off
inneal
CMP
Sum
00 52.52%
$39,59
$7,333. 9,917.
32
50 100.00%
$10,833
.32
Actua
Cl
(hours
1.3(
5.0(
0.5(
0.2C
2.0C
1.2C
1.0(
1.0C
2.0C
0.2C
1.0C
1.5c
16.9C
Appendix B: Market Share Probabilities
Table 8: Market share growth rate, market share percentage, and
given low, medium, high scenarios.
Scenarios
Year
Market share
Market
share
growth rate
2006
NA
1.0%
2007
2%
1.0%
2008
2%
1.0%
Low
2009
2%
1.1%
2010
2%
1.1%
Total
2006
NA
3.0%
2007
5%
3.2%
2008
5%
3.3%
Medium
2009
5%
3.5%
2010
5%
3.6%
Total
2006
NA
5.0%
2007
8%
5.4%
2008
8%
5.8%
2009
8%
6.3%
2010
8%
6.8%
total
total units projected in period 1,
Total units
projected
2,000,000
2,040,000
2,080,800
2,122,416
2,164,864
10,408,080
6,000,000
6,300,000
6,615,000
6,945,750
7,293,038
33,153,788
10,000,000
10,800,000
11,664,000
12,597,120
13,604,890
58,666,010
Table 9: Probabilities of gaining low, medium, or high market share at $250 versus at $350. Based on
a 200M unit/year market.
Period 1
Low(l- 1.1%)
Medium (3.0-3.6%)
High (5.0- 6.8%)
$250
25%
30%
45%
$350
45%
35%
20%
Table 10: Probabilities of gaining low, medium, or high market share at $250 versus at $350 in
period 2, given low, medium or high market share in period 1. Based on a 200M unit/year market
Growth in
low
low
medium
Medium
High
High
period 1
$250
$350
$250
$350
$250
$350
Period 2 low
Medium
high
50%
30%
20%
70%
20%
10%
10%
50%
40%
20%
70%
10%
20%
20%
60%
30%
40%
30%
Table 11: Probability estimates for period two are based on the assumption that there is high
probability that if low market share is gained in the first period, low market share will again be
gained in the second period, if medium market share is gained in the first period, medium market
share will again be gained in the second period, and if high market share is gained in the first period,
there is a high probability high market share will again be gained in the second period. it is based on
a 200M unit/year market.
scenario
Low
Year
Market
share
growth rate
Low demand, period
1
Market
Total
share
units
Medium demand,
period 1
Market Total units
share
High demand,
period 1
Market
Total
share
units
2011
2012
2013
2014
2015
2%
2%
2%
2%
2%
1.1%
1.1%
1.1%
1.2%
1.2%
3.7%
3.8%
3.9%
3.9%
4.0 %
15.5%
15.8%
16.1%
16.4%
16.8%
5%
5%
5%
5%
5%
1.1%
1.2%
1.3%
1.3%
1.4%
8%
8%
8%
8%
8%
1.2%
1.3%
1.4%
1.5%
1.6%
Total
Medium
2011
2012
2013
2014
2015
11,491,362
Total
2011
2012
2013
2014
2015
total
2,208,162
2,252,325
2,297,371
2,343,319
2,390,185
2,273,108
2,386,763
2,506,101
2,631,406
2,762,976
38,712,325
3.8%
4.0%
4.2%
4.4%
4.7%
12,560,354
2,338,053
2,525,098
2,727,106
2,945,274
3,180,896
13,716,427
7,438,898
7,587,676
7,739,430
7,894,218
8,052,103
7,657,689
8,040,574
8,442,603
8,864,733
9,307,969
72,216,400
7.1%
7.5%
7.9%
8.3%
8.7%
42,313,568
3.9%
4.3%
4.6%
5.0%
5.4%
7,876,481
8,506,599
9,187,127
9,922,097
10,715,865
46,208,168
619373
631760
644395
657283
670429
14,285,134
14,999,391
15,749,360
16,536,828
17,363,670
78,934,383
7.3%
7.9%
8.6%
9.3%
10.0%
14,693,281
15,868,743
17,138,243
18,509,302
19,990,046
86,199,615
Appendix C: Decision Tree Analysis
Figure 42: Our Decision Tree Analysis for period. Highlighted in yellow is the best strategy for
Period 1 and in pink is our strategy
Between each price and its three different possible profit outcomes is a line which
represents a probability of that particular profit outcome. Each price has one line which
represents the probability of gaining the profits associated with high market share in
period 1 at that price, one line which represents the probability of gaining medium market
share in period 1 at that price, and one line which represents the probability of gaining
low market share in period 1 at that price. The probabilities of gaining low, medium, and
high market share at a $250 versus at a $350 price can be seen in Appendix B: Table 9.
The percentages represented by low, medium, and high market share can be seen in
Appendix B: Table 10.
The recommendation of what plant size should be built and at what price the product
should be sold is decided by which set of choices would have the highest expected value
(EV). The expected value (for example, EV1) is calculated by summing the following
each of the products of (profit)*(probability of that profit occurring) associated with a
given expected value. For example, in the decision tree on the left, there would be three
products to be summed for each expected value.
The decision tree for the second period is created in the same manner as the decision tree
to the left for the first period. From each profit to the left comes a new decision of
whether to build small, medium, large, or extra large capacity, and from each capacity
option comes the choice of making the price $250 or $350. From each price comes three
profit possibilities, depending on whether low, medium, or high market share is gained in
the second period. The expected values are calculated by summing the products of the
profit at the end of the given scenario times the probability of that profit occurring times
the probability on the branch from the first period from which the second period's
decision had stemmed. Again, each expected value will be summing three products.
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