Outphase Power Amplifiers in OFDM Systems
by
Anh D. Pham
Bachelor of Science in Electrical Engineering and Economics
California Institute of Technology, June 2000
Master of Science in Electrical Engineering and Computer Science
Massachusetts Institute of Technology, June 2002
Submitted to the Department of Electrical Engineering and Computer Science in partial
fulfillment of the requirements for the degree of
Doctor of Philosophy in Electrical Engineering and Computer Science
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
September 2005
 Massachusetts Institute of Technology 2005. All right reserved.
Author_____________________________________________________________________
Department of Electrical Engineering and Computer Science
September 2005
Certified by_________________________________________________________________
Charles G. Sodini
Professor of Electrical Engineering and Computer Science
Thesis Supervisor
Accepted by________________________________________________________________
Arthur C. Smith, Ph.D.
Chairman, Committee on Graduate Students
Department of Electrical Engineering and Computer Science
2
Outphase Power Amplifiers in OFDM Systems
by
Anh D. Pham
Submitted to the Department of electrical Engineering and Computer Science on September
12, 2005 in partial fulfillment of the requirements for the degree of Doctor of Philosophy in
Electrical Engineering and Computer Science
Abstract
A trade-off between linearity and efficiency exists in conventional power amplifiers. The
outphase amplifying concept overcomes this trade-off by enabling the use of high efficiency,
non-linear power amplifiers for linear amplification. An amplitude modulated signal is first
decomposed into two constant amplitude, phase modulated signals that can be amplified
using two high efficiency switching power amplifiers. The two outputs are then recombined
to restore the original amplitude modulated signal. In this manner, an outphase power
amplifier can simultaneously achieve high efficiency and good linearity.
This thesis investigates the capability of the outphase amplifying technique in modern
wireless communication. First, a digital amplitude-to-phase conversion scheme is proposed
to facilitate the outphase decomposition. By taking advantage of the available computational
power in current digital technology, the amplitude-to-phase conversion can be implemented
with both accuracy and efficiency in the digital domain. A proof-of-concept outphase power
amplifier is fabricated using the IBM 7WL SiGe BiCMOS process technology. The test chip
includes two class-E power amplifiers and the first 5.8GHz fully integrated Wilkinson power
combiner. The low-loss integrated combiner allows efficient outphase recombining while
providing the necessary input isolation for a robust outphase power amplifier.
The outphase power amplifier achieves an efficiency of 47% at the maximum output power
of 18.5 dBm. For an input Orthogonal Frequency Division Multiplexing (OFDM) signal of
32 sub-channels of 64-QAM, the adjacent channel power leakage ratio (ACPR) is better than
32dBc. The outphase power amplifier’s error vector magnitude (EVM) is better than -25dB
for up to 20dB of output dynamic range.
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4
To my parents Kim-Anh and Hung,
and my wife Ha.
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Acknowledgements
Many people have contributed to the successful of this project. First and foremost, I would
like to thank Professor Sodini for his unwavering support and caring guidance, especially
during the early months of the project when the proposed solution was both unconventional
and questionable. Ha and I also have the honor of having Charlie and Anne at our wedding.
Next, I would like to thank the committee members, Professor Dawson and Professor
Chandrakasan, for their help and encouragement during the course of the project. Professor
Wornell’s guidance is vital in the theoretical analysis of the outphase concept in OFDM
systems.
Nir built the custom receiver that is instrumental in proving the performance and merit of the
outphase power amplifier. Todd is always available to spot holes in my proofs and help with
any Unix issues. He and John also make sure that I have enough caffeine in the afternoon.
The system experts, Andy, Farinaz, and Everest are helpful and deliberate in our many
discussions. Lunal and Albert industry experience is an excellent resource for everyone in
the office. I would also like to thank all the members of the H. S. Lee and Sodini research
groups for a great office environment and many memorable social events.
Our group administrator Rhonda Maynard does a superb job with all the forms and
scheduling, always with a bright smile.
I am especially grateful for the help of a good friend, Donhee. All the necessary equipments
for chip-on-board setup are available from Donhee’s laboratory at Harvard University.
Finally, my best man Miles, buddies Stuart and the-mad-Hungarian Zoltan deserve special
recognitions for their generous donations to the much needed college fund. It is hard to
imagine not being able to hang out with them as often.
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Contents
Chapter 1
Introduction..................................................................................... 15
1.1
Motivation............................................................................................................... 15
1.2
Literature Reviews on Linearization Techniques ................................................... 16
1.2.1
Polar and Cartesian Feedback Techniques ..................................................... 16
1.2.2
Feedforward Linearization.............................................................................. 18
1.2.3
Predistortion.................................................................................................... 18
1.2.4
Envelope Elimination and Restoration ........................................................... 19
1.2.5
Linear Amplification Using Nonlinear Components (LINC)......................... 20
1.3
Outphase Amplifying.............................................................................................. 20
1.4
Outphase Literature Reviews.................................................................................. 21
1.4.1
Re-combiner Complexity................................................................................ 21
1.4.2
Mismatch Control ........................................................................................... 22
1.4.3
Overall System Efficiency .............................................................................. 22
1.5
Research Contributions........................................................................................... 22
1.6
Thesis Overview ..................................................................................................... 23
Chapter 2
Power Amplifiers Efficiency .......................................................... 25
2.1
Conditions for 100% Efficiency ............................................................................. 25
2.1.1
First Condition: Zero Power Dissipation in the Transistor............................. 26
2.1.2
Second Condition: Fundamental Power Only................................................. 28
2.2
Switching Power Amplifiers with Theoretical 100% Efficiency ........................... 28
2.2.1
Class-E ............................................................................................................ 28
2.2.2
Class-F ............................................................................................................ 31
2.2.3
Other Switching Classes (-F -1, -E/Fx) ............................................................ 32
2.2.4
Switching Power Amplifiers Linearity ........................................................... 33
2.3
Conducting-Mode Power Amplifiers...................................................................... 34
2.3.1
Operating Principle and Efficiency................................................................. 34
2.3.2
Performance Characteristics of Conducting-Mode Power Amplifiers ........... 35
2.4
Summary ................................................................................................................. 37
Orthogonal Frequency Division Multiplexing.............................. 39
Chapter 3
3.1
3.2
OFDM Constructions.............................................................................................. 39
OFDM Peak-to-Average Power Ratios .................................................................. 41
Chapter 4
4.1
Outphase Amplifying – System Analysis...................................... 47
Digital Outphase Conversion.................................................................................. 47
9
4.2
Amplitude Variation Control .................................................................................. 49
4.3
Digital Outphase Conversion in System Simulation .............................................. 52
4.4
Effect of Mismatch ................................................................................................. 54
4.4.1
Error Vector Magnitude.................................................................................. 54
4.4.2
Bit-Error Rate.................................................................................................. 57
4.5
Summary ................................................................................................................. 58
Chapter 5
An Integrated Outphase Power Amplifier .................................... 59
5.1
Class-E Design........................................................................................................ 60
5.1.1
Design Equations and Parameters................................................................... 61
5.1.2
Differential Class-E with Driver Stage ........................................................... 62
5.1.3
Simulation Results .......................................................................................... 65
5.1.4
Corner Simulation........................................................................................... 67
5.2
Power Combiner Design ......................................................................................... 68
5.2.1
Wilkinson Power Combiner............................................................................ 68
5.2.2
Shielded Coplanar Stripline ............................................................................ 70
5.2.3
A Shielded Coplanar Stripline Wilkinson Combiner...................................... 72
5.3
Summary ................................................................................................................. 73
Chapter 6
Experimental Results...................................................................... 75
6.1
Class-E and Power Combiner Measurements......................................................... 75
6.2
Outphase Power Amplifier Efficiency.................................................................... 78
6.3
Overall Outphase Power Amplifier Measurements ................................................ 79
6.3.1
Generating the Outphase Signals .................................................................... 79
6.3.2
Decode the Output Signal for EVM Measurements ....................................... 82
6.3.3
Results............................................................................................................. 84
Chapter 7
7.1
7.2
Conclusion ....................................................................................... 87
Average Efficiency Comparison............................................................................. 88
Future Related Research ......................................................................................... 90
10
List of Figures
Figure 1-1: (a) Cartesian Feedback Loop (b) Polar Feedback Loop ..................................... 17
Figure 1-2: Basic Feedforward Power Amplifier .................................................................. 18
Figure 1-3: Basic Predistortion Block Diagram..................................................................... 19
Figure 1-4: Conceptual Block Diagram of an Envelope Elimination and Restoration PA ... 19
Figure 1-5: LINC Principle Diagram..................................................................................... 20
Figure 2-1: General Power Amplifier Model......................................................................... 25
Figure 2-2: (a) Switching MOS Transistor (b) Small-signal Equivalent Circuit Model ....... 27
Figure 2-3: Simplified Model with Ideal Switch and Parasitic Capacitor ............................. 27
Figure 2-4: Class-E Schematics ............................................................................................. 28
Figure 2-5: Basic Class-E Operation ..................................................................................... 29
Figure 2-6: Class-E Waveforms............................................................................................. 30
Figure 2-7: Class-F Schematics ............................................................................................. 31
Figure 2-8: Class-F (a) and Class-F-1 (b) Waveforms ........................................................... 32
Figure 2-9: Inverse Class-F Schematic .................................................................................. 33
Figure 2-10: Input-to-Output Waveforms of Conducting-Mode Power Amplifiers ............. 34
Figure 2-11: Characteristic Waveforms of a Power Amplifier with Conduction Angle α.... 35
Figure 2-12: Drain Harmonic Currents as a Function of the Conduction Angle................... 37
Figure 3-1: N Parallel Orthogonal Sub-Channels by Using IDFT ........................................ 39
Figure 3-2: OFDM Transmitter Architecture ........................................................................ 40
Figure 3-3: PAPR of Single Channel with Various QAM Levels ......................................... 41
Figure 3-4: Additional PAPR Caused by OFDM .................................................................. 42
Figure 3-5: Amplitude Probability Distribution (128 Sub-Channels OFDM of 256-QAM). 43
Figure 3-6: BER vs. PAPR for Various Clipping Degrees.................................................... 45
Figure 4-1: Outphase Concept with Digital Amplitude-to-Phase Conversion ...................... 47
Figure 4-2: Digital Outphase Conversion .............................................................................. 49
Figure 4-3: Outphase Analog Waveforms Exhibit Significant Amplitude Variation............ 50
Figure 4-4: Signal-space Constellations for QPSK, Offset QPSK and π/4-QPSK................ 51
Figure 4-5: Optimal Outphase Conversion for Amplitude Variation Control....................... 52
Figure 4-6: OFDM Architecture with Outphase Amplifying ................................................ 53
Figure 4-7: Envelope Variation w/ and w/o Optimal Outphase Assignment ........................ 54
Figure 4-8: EVM Definition .................................................................................................. 55
Figure 4-9: Outphase EVM with Gain and Phase Mismatch of α and δº.............................. 56
Figure 4-10: Normalized EVM dues to Mismatch ................................................................ 56
Figure 4-11: BER vs. Voltage Mismatch (OFDM 128 sub-channels of 256-QAM)............. 57
Figure 4-12: BER vs. Phase Mismatch (OFDM 128 sub-channels of 256-QAM)................ 58
Figure 5-1: Die Photo............................................................................................................. 59
Figure 5-2: Test Chip Includes Two Class-E PAs and a Power Combiner ........................... 60
Figure 5-3: Class-E with Ideal Transistor Switch.................................................................. 61
Figure 5-4: Ideal Class-E Waveforms.................................................................................... 61
Figure 5-5: Class-E in Differential Configuration ................................................................. 62
Figure 5-6: (a) Differential Inductor with Center Tab (b) Differential Transformer............ 63
Figure 5-7: Differential Class-E Power Amplifier Using Center-Tapped Inductors............. 64
Figure 5-8: Differential Class-E PA with Driver Stage ......................................................... 65
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Figure 5-9: Switching Transistor Model and Additional Shunt Capacitor CP ....................... 65
Figure 5-10: Simulation Class-E Waveforms (T=1/5.8GHz) ................................................ 66
Figure 5-11: Simulated Efficiency and Output Power vs. Supply Voltage ........................... 67
Figure 5-12: Amplitude Mismatch Due to Process Variation ............................................... 67
Figure 5-13: Wilkinson Power Combiner.............................................................................. 68
Figure 5-14: Analyzing the Wilkinson Combiner in Odd and Even Modes.......................... 69
Figure 5-15: Integrated Circuit Coplanar Stripline................................................................ 71
Figure 5-16: Coplanar Stripline with Floating Metal Shields................................................ 72
Figure 5-17: Effects of Metal Shields.................................................................................... 72
Figure 5-18: Chip Layout of the Coplanar Stripline Wilkinson Combiner ........................... 73
Figure 6-1: Laser Trim Locations and Intermediate Test Points for Individual Block
Measurements ......................................................................................................................... 75
Figure 6-2: Test Board ........................................................................................................... 76
Figure 6-3: Class-E Measured Output Power and Efficiency................................................ 77
Figure 6-4: Measured Wilkinson Combiner S-Parameters.................................................... 77
Figure 6-5: Efficiency Measurement Setup ........................................................................... 78
Figure 6-6: Outphase Power Amplifier Efficiency vs. Pout .................................................... 79
Figure 6-7: Construction of Outphase Signals for OFDM Measurements ............................ 80
Figure 6-8: OFDM Construction Block Diagram inside a Signal Generator ........................ 80
Figure 6-9: Block Diagram for Generating Outphase Signals Procedure.............................. 81
Figure 6-10: Complete Test Setup for Outphase PA Measurements with OFDM Signals ... 83
Figure 6-11: 50Ω Resistor Combiner for Calibration............................................................ 83
Figure 6-12: Gain Adjustment for Compensating Phase Mismatch ...................................... 84
Figure 6-13: Output Power Spectral Density......................................................................... 85
Figure 6-14: 64-QAM Symbols w/o Mismatch ..................................................................... 85
Figure 6-15: 64-QAM Symbols w/ 2% Mismatch................................................................. 85
Figure 6-16: 64-QAM Symbols w/ 5% Mismatch................................................................. 85
Figure 6-17: Measured EVM ................................................................................................. 86
Figure 7-1: (a) Efficiency Comparison .................................................................................. 88
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List of Tables
Table 5-1: Power Amplifier Specification............................................................................. 60
Table 5-2: Summary of Class-E Equations and Waveforms ................................................. 61
Table 7-1: Comparison with Previously Published Results................................................... 87
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Chapter 1
Introduction
The performance of a wireless communication system depends heavily on its power amplifier
(PA). Specifically, the wireless system’s data rate is often determined by the power
amplifier’s linearity. In addition, by usually accounting for more than half of the whole
transceiver power budget, a power amplifier requires not only larger and heavier batteries for
longer communication time, but also bulky heat dissipating panels.
Power amplifiers have been well studied and developed since the early days of vacuum tubes
and continued on throughout the modern era of solid-state transistors. Many classes of
operation have been proposed, and the efficiency-linearity tradeoff has been well understood.
However, most of the early study on power amplifiers has been done at low frequency range,
mostly for audio applications and low-speed data communications, from a few kHz to tens of
MHz. With the explosion of cellular phones and wireless communication networks in the
nineties, there has been a renewed interest in power amplifiers. Modern power amplifier
designers face a much tougher environment. First, the linearity requirement has been
significantly increased to accommodate many new and intricate modulation techniques.
Second, efficiency becomes much more critical with the smaller and lighter trend toward
portable devices.
Fortunately, modern design environment also offers a few advantages. First, advanced
integrated circuit (IC) technologies make it possible for larger and more complex circuits
with better matching control and accurate calibration. Second, designers can now make use
of very powerful digital signal processors with little or tolerable penalty in power
consumption. Taking advantages of these two new capabilities, many complex bias-controls
and feedback techniques have been explored in hope of simultaneously achieving high
efficiency and good linearity in power amplifiers.
1.1 Motivation
A tradeoff between linearity and efficiency exists in conventional power amplifiers.
Conducting class power amplifiers, such as class-A and -AB, offer great linearity but are
very inefficient [1,2]. On the other hand, switching classes, such as class-E and -F, have
excellent efficiency, but are very non-linear [3,4]. Traditionally, non-linear, switching class
15
PAs can only be used in phase or frequency modulated systems, while all amplitude
modulated systems require conducting class PAs with good linearity. Modern wireless
communication systems usually employ intricate modulation schemes, such as OFDM with
multi-channels of Quadrature Amplitude Modulation (QAM), to maximize bandwidth
efficiency. Such modulation often results in amplitude modulated signals with large peak-toaverage power ratio (PAPR) that requires PAs with extremely good linearity. While the
linearity requirement increases, the demand for higher efficiency also exhibits an upward
trend due to the desire for longer battery life and higher data rates. Power amplifier
designers are facing the tremendous challenge to overcome the efficiency-linearity tradeoff.
1.2 Literature Reviews on Linearization Techniques
Linearization techniques can be loosely divided into two sub-categories depending on the
type of power amplifiers they employ. The first linearization category extends the linear
output power range of conventional power amplifiers so that the PA can operate linearly over
a large output range where it is most efficient. The power amplifiers employed by this
category are usually of the conduction classes (-AB, -B, and -C), which already have some
degree of linearity. This category includes, among others, the Polar and Cartesian feedback,
feedforward, and predistortion techniques.
On the other hand, the second category of linearization employs switching power amplifiers
that are highly non-linear, for the inherently higher efficiency, while manipulating the overall
system to achieve the required linearity. This category includes the Envelope Elimination
and Restoration (ERR) technique, and LInear amplification using Nonlinear Components
(LINC).
1.2.1 Polar and Cartesian Feedback Techniques
The Polar and Cartesian feedback techniques are conceptually negative feedback systems
that have been well studied and are popular in the audio and low frequency applications [5].
However, in order to apply negative feedback to an RF transmitter, a high gain and stable
analog feedback loop is needed at the carrier frequency in the gigahertz range for modern
wireless standards. Such a feedback loop is virtually unrealizable in current technologies.
Therefore, an indirect system is employed, where the RF output is down-converted to
baseband. The feedback loop is closed at baseband where error corrections are performed.
In a Cartesian feedback system shown in Figure 1-1(a), the corrections are then performed on
the Cartesian coordinates of the quadrature symbols I and Q. Similarly, corrections are done
on the polar coordinates of amplitude and phase, in the case of Polar feedback as shown in
Figure 1-1(b).
Because of the indirect feedback loop, the Polar and Cartesian feedback techniques are
inherently narrow band and can provide linearization for systems with limited bandwidth (on
the order of a few hundred kilohertz). A major design consideration for the Cartesian
16
feedback is the phase alignment between the up-convert and down-convert mixers [6]. In
addition, the linearity of the overall system depends on the precision of the feedback
corrections as well as the linearity and bandwidth of the down-converters [7]. The most
distinguishing advantage of the Cartesian feedback loop is its resilience against process
variations, temperature fluctuations, as well as the lack of an accurate model for the power
amplifier.
Figure 1-1: (a) Cartesian Feedback Loop (b) Polar Feedback Loop
17
1.2.2 Feedforward Linearization
The basic principle of feedforward linearization [8,9] is shown in the block diagram of
Figure 1-2. This is an open loop, two-amplifier system with a main, non-linear power
amplifier and a smaller auxiliary amplifier. The output of the main amplifier is coupled and
compared to the original input. The difference is amplified using the auxiliary amplifier then
added to the main amplifier output to achieve a linear overall output.
Figure 1-2: Basic Feedforward Power Amplifier
There are several challenges in implementing a feedforward power amplifier. First, the
delays of the two amplifiers have to be replicated precisely in the two signal paths to
maintain the overall signal integrity. This requires accurate models for both main and
auxiliary amplifiers. In addition, in order to add the two amplifiers outputs, a power
combiner is required. Finally, unlike the Cartesian feedback, the feedforward technique is an
open loop setup that makes it vulnerable to environmental changes.
On the other hand, because of the open loop setup, feedforward linearization can operate at a
higher bandwidth. A simulated feedforward system with 7MHz bandwidth has been reported
in [10].
1.2.3 Predistortion
Conceptually, the nonlinear behavior of the power amplifier can be characterized and
preemptively undone by a predistorter inserted right before the power amplifier [11].
However, such a setup is an open loop technique that is highly vulnerable to process
variation, operating temperature, and environment changes. Therefore, predistortion is
usually employed in tandem with feedback loops as described in Figure 1-3. Instead of a
predetermined predistorter, an adaptive version [12] is employed using the two feedback
signals to correct for the power amplifier characterization as well as the overall system signal
integrity. The main difference between the predistortion feedback loop and that of the
Cartesian feedback is that it does not have to operate continuously. The rate of change of the
environment is presumably very slow. Therefore, predistortion does not suffer a bandwidth
limitation. However, it still needs an accurate model of the power amplifier. In addition,
18
circuit complexity could incur significant power overhead that degrades the overall system
efficiency.
A predistortion linearizer has been successfully implemented for class-AB power amplifier
[13].
Figure 1-3: Basic Predistortion Block Diagram
1.2.4 Envelope Elimination and Restoration
Figure 1-4: Conceptual Block Diagram of an Envelope Elimination and Restoration PA
Envelope elimination and restoration, originally proposed by Kahn [14], separates the RF
input signal into phase, using the limiter, and amplitude, using the peak detector as shown in
Figure 1-4. A highly efficient switching power amplifier is then used to amplify the phase
modulated signal. The envelope amplitude information is used to modulate the PA’s power
supply, which restores the amplitude information to the output signal.
The key challenge to the envelope elimination and restoration technique is the
implementation of an efficient and high-bandwidth switching power supply that can
accommodate the signal bandwidth while maintaining respectable overall efficiency. In
addition, phase matching between the two signal paths is critical. A 49% efficiency, 25MHz
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bandwidth power amplifier using envelope elimination and restoration technique has been
reported in [15].
1.2.5 Linear Amplification Using Nonlinear Components (LINC)
Another way to overcome the linearity-efficiency tradeoff is to enable the use of high
efficiency, non-linear power amplifiers for linear systems. This general technique is referred
to as LInear amplification using Nonlinear Components [16]. Figure 1-5 describes the
general principle of LINC. An amplitude modulated signal x(t ) is first decomposed into two
signals s1 (t ) and s2 (t ) that can be amplified using two highly efficient, non-linear power
amplifiers. The PAs’ outputs, y1 (t ) and y2 (t ) , are then recombined to yield y (t ) for
transmission.
Figure 1-5: LINC Principle Diagram
Ideally, to be suitable for linear amplification, the output needs to be a linear scale of the
original input as described in (1-1), where G is the constant gain of the composite power
amplifier.
y (t ) = G ⋅ x(t )
(1-1)
In addition, in order to employ highly efficient, non-linear power amplifiers, the decomposed
signals s1 (t ) and s2 (t ) can not have amplitude modulation. Furthermore, the decomposition
has to be such that its inverse function, which is performed by the re-combiner block, can be
efficiently implemented using analog circuitry.
1.3 Outphase Amplifying
One method of decomposition is the outphase amplifying, which was originally proposed by
Chireix in 1935 [17]. An amplitude modulated signal can be represented as a sum of two
constant amplitude, phase -modulated signals as described in (1-2).
20
Amax
A
cos(ωt + θ + φ ) + max cos(ωt + θ − φ )
2
2
 a (t ) 
 with Amax = max a (t )
φ (t ) = cos −1 
 Amax 
a(t ) cos(ωt + θ ) =
(1-2)
Essentially, the decomposition is the amplitude-to-phase inverse cosine function that results
in two constant amplitude signals that can be amplified using two highly efficient switching
PAs. The re-combiner is simply the addition of the two power amplifiers’ outputs. A valid
amplitude-to-phase inverse cosine conversion can be guaranteed by normalizing the
amplitude to its absolute maximum value Amax .
The outphase amplifying technique can be described in the context of Figure 1-5 as follows,
• Input: x(t ) = a(t ) cos(ωt + θ )
• Decomposition: x(t ) = s1 (t ) + s2 (t )
•
•
•
•

 a(t ) 
Amax

φ (t ) = cos−1
cos(ωt + θ + φ )
 s1 (t ) =
A
2
max



s (t ) = Amax cos(ωt + θ − φ )
Amax = max a(t )
 2
2
Power amplifiers’ gain: G
Intermediate outputs: y1 (t ) = G ⋅ s1 (t ) , y2 (t ) = G ⋅ s2 (t )
Re-combiner: y (t ) = y1 (t ) + y2 (t )
Total output: y(t ) = G ⋅ x(t )
Outphase amplifying is a very simple and elegant technique that allows the use of highly
efficient, non-linear switching power amplifiers in linear systems to simultaneously achieve
good linearity and high efficiency.
1.4 Outphase Literature Reviews
Published literature on the outphase technique has focused mainly on three issues: recombiner complexity, mismatch-control feedback, and overall system efficiency.
1.4.1 Re-combiner Complexity
One way to implement the re-combiner function is the “Chireix combiner”, which uses
simple inductors, capacitors, and transformers that can be easily integrated in today
technology [18,19]. However, the Chireix combiner can only be tuned for a very small range
of outphase angles. With outphase angles outside the tuned range, isolation between the two
21
power amplifiers’ outputs is poor, resulting in significant distortion that degrades the system
linearity. Recall from (1-2) that the outphase angle is a function of the signal amplitude,
small outphase angle range means only systems with a very tight range of amplitude
modulation can employ this particular implementation of the outphase amplifying technique.
It is reported in [20] that the Chireix combiner has a significant nonlinear effect compared to
the hybrid Wilkinson combiner, which offers better isolation across a wide range of
amplitudes, and that linearization is feasible only at the expense of reduced efficiency.
1.4.2 Mismatch Control
A feedback loop and calibration scheme to correct for any gain and phase imbalance among
the two outphase paths are analyzed in [21]. In order to avoid the bandwidth limitation of a
continuous feedback loop, the transmitter is alternating between transmit and correction
modes. In correction mode, a training sequence is used to build a lookup table to provide
gain and phase mismatch corrections during the subsequent transmit mode. Simulation
results are presented for QPSK (Quadrature Phase Shift Keying) and 16-QAM with more
than 40dB improvement in ACPR (from -30dBc to -70dBc). In a similar category, the effect
of quantization error with the hypothesis of a digital implementation of the signal
decomposition is studied in [22]. It is reported that a simulated ACPR of -62dBc can be
obtained for a π/4-shifted DQPSK (Differential Quadrature Phase Shift Keying) system with
9-bits DAC.
1.4.3 Overall System Efficiency
A power recycling technique is proposed in [23] by rectifying the signal and recouping the
energy that is normally dissipated on the combiner due to cancellation of completely out of
phase signal components. The reported experimental results are obtained from a test setup
using a discrete, off-chip hybrid power combiner. Using example modulations of QPSK, 16QAM, and 64-QAM, it is reported that a relative improvement between 33% and 83% on the
average power efficiency is possible.
1.5 Research Contributions
While the basic concept of outphase amplifying is straightforward, challenges exist in
implementation. First, the practical implementation of the outphase amplifying technique
critically depends on the accuracy and efficiency of the amplitude-to-phase conversion.
Implementing the inverse cosine and other trigonometric functions using analog circuitry is
non-trivial and inevitably complex. Second, for a robust outphase amplifier that is suitable
for a wide variety of modulation schemes, complete isolation is needed between the two
power amplifiers’ outputs to prevent them from loading each other. Therefore, hybrid power
combiners, which rely on quarter-wave length transmission lines to provide isolation, are
required in summing the two output ports. For a fully integrated solution, it is very
22
challenging to design efficient and size-constrained power combiners. It could be argued that
the outphase amplifying technique, despite its early introduction in the 1935, never gained
widespread popularity because of these two challenges.
Solving the above two challenges are the main contributions of this thesis to the
understanding and advances of the outphase power amplifying technique. First, an optimal
digital amplitude-to-phase conversion scheme, that takes advantage of the vast computational
power of digital technology, is proposed to achieve the accuracy and efficiency required for
the outphase conversion. Second, an outphase power amplifier with a fully integrated and
low-loss power combiner at 5.8GHz has been successfully fabricated, for the first time. An
experimental verification of the suitability of the outphase concept in modern wireless
systems such as multi-channels OFDM/QAM has been demonstrated. A complete analysis
of the outphase power amplifier efficiency based on signal amplitude distribution is
presented during the evaluation of the outphase technique.
In addition, the effect of mismatch is analyzed and quantified using the general figure of
merit Error Vector Magnitude (EVM), as well as the more system specific bit-error-rate
(BER) in the application of multi-channels OFDM/QAM systems.
The test chip answers the two critical challenges in current power amplifier designs. First, it
shows that the outphase power amplifier simultaneously achieves good linearity and high
efficiency. Second, the fully integrated power combiner combines the output power of two
individual power amplifiers, and effectively doubles the maximum achievable output power
for a given transistors’ breakdown voltage.
1.6 Thesis Overview
For background review, Chapter 2 examines the conditions for 100% efficiency power
amplifiers and concludes that only switching class power amplifiers can offer 100%
efficiency. A brief review of several power amplifier switching classes is then presented as
examples of 100% efficiency power amplifiers. Chapter 2 concludes with a review of
conducting-mode power amplifiers that sacrifice the first condition for 100% efficiency to
achieve some degree of linearity. Next, Chapter 3 explains the construction and
characteristics of OFDM signals. Understanding OFDM construction is relevant in
subsequent system simulation implementation and measurement setups. The chapter also
provides a detailed look into peak-to-average power ratio of OFDM systems as well as more
probable PAPR numbers from a custom simulation of 231 OFDM symbols.
Chapter 4 focuses on the theoretical analysis of the outphase amplifying concept. The digital
amplitude-to-phase conversion is introduced and analyzed here. In addition, an optimal
outphase channel assignment method is also proposed to significantly reduce the outphase
envelope amplitude variations. The digital outphase conversion with optimal channel
assignment is implemented in a custom simulation to characterize the error-mismatch
sensitivity of the outphase concept.
23
The design of a proof-of-concept integrated outphase power amplifier is presented in Chapter
5. First, a differential class-E power amplifier is designed using center-tapped differential
inductors and transformer to minimize the chip area. Second, the first integrated differential
5.8GHz Wilkinson power combiner is presented. The integration is possible by using thin
perpendicular shielding strips of lower level metals to both reduce the combiner’s size as
well as its substrate-coupling loss.
Chapter 6 explains the test setups and measurement procedures to separately characterize the
class-E power amplifier and the Wilkinson combiner. Next the overall outphase power
amplifier performance in OFDM systems is measured to show the outphase amplifying
technique’s capability in modern linearity-demanding modulation systems while at the same
time achieves much better efficiency than conventional linear power amplifiers.
Finally, Chapter 7 summarizes the project results. The proof-of-concept outphase power
amplifier achieves a 47% maximum efficiency with an ACPR of -32dBc for an OFDM signal
with 32 sub-channels of 64-QAM. A comprehensive efficiency and average power
consumption comparison is made among three linear power amplifiers: the outphase, a
conventional class-A, and an adaptive class-A. Among the three, the outphase power
amplifier consumes the least average power in a high linearity requirement system of multichannels OFDM/QAM.
24
Chapter 2
Power Amplifiers Efficiency
This chapter reviews the efficiency of various power amplifier topologies. Instead of the
traditional approach of categorizing power amplifiers into classes of operation then analyzing
each class independently, a general power amplifier model is introduced, from which a
universal efficiency expression is derived. Next, conditions to achieve the theoretical 100%
efficiency are determined. Studying these conditions from a power standpoint, without
specific circuit implementation, provides better intuition for understanding power amplifier
efficiency and linearity tradeoff. Several power amplifier switching classes are then
analyzed as examples of specific implementations of the 100% efficiency conditions.
Finally, the efficiency-linearity tradeoff is demonstrated with several power amplifier
conducting classes where the conditions for 100% efficiency are forgone in exchange for
linearity.
2.1 Conditions for 100% Efficiency
Figure 2-1: General Power Amplifier Model
25
Figure 2-1 shows a typical power amplifier schematic with a common-source transistor
driving the 50 ohms antenna via a passive matching network. The transistor is connected to
the power supply via a Radio Frequency Choke (RFC) to minimize resistive loss while
allowing the drain voltage to swing higher than the supply voltage VDD . The main function
of the matching network is to transform the antenna load into appropriate loading impedance
presented to the transistor, which together with the gate biasing condition, determine the
operational characteristics of the power amplifier.
The transistor is driven with an input power Pin at the gate, while the supply power Psup is
provided via the RFC. Consider the power flow at the drain, the supply power can be
separated into two parts: the power being dissipated on the transistor Pdissipate , and the power
delivered to the matching network Pload ,
Psup = Pdissipate + Pload
(2-1)
Depending on the input drive level and the matching network, Pload generally contains the
fundamental and higher order harmonic components,
Pload = P0 + P1 + P2 + ...
(2-2)
To comply with Federal Communications Commission (FCC) spectral requirements, all the
higher order harmonics are filtered out leaving only the fundamental power, P0 , for
transmission at the antenna. The power amplifier efficiency is defined as the ratio of the
fundamental output power and the supply power.
η=
P0
Psup
(2-3)
From the power expressions in (2-1), (2-2), and (2-3), the efficiency can be rewritten as,
η=
P0
Pdissipate + P0 + P1 + P2 + ...
(2-4)
Clearly, to achieve the maximum 100% efficiency, two conditions have to be met:
Pdissipate = 0 , and P1 = P2 = P3 = L = 0 .
2.1.1 First Condition: Zero Power Dissipation in the Transistor
The first condition, Pdissipate = 0 , requires zero power being dissipated in the transistor.
Theoretically, this condition can be satisfied by operating the transistor as a switch, where
26
there is no overlap between the drain voltage and current, resulting in zero power dissipation
in the transistor. However, in switching condition, there is a non-negligible equivalent drainto-source capacitor whose discharging mechanism could affect the overall efficiency of the
power amplifier.
Figure 2-2: (a) Switching MOS Transistor (b) Small-signal Equivalent Circuit Model
(c) Equivalent Switching MOS Transistor Model
First, the origin of this drain-to-source capacitor is explained in Figure 2-2. A commonsource switching transistor in Figure 2-2(a) has an equivalent small-signal model as shown in
Figure 2-2(b), where the gate is effectively grounded due to the discrete-level nature of the
switching gate input voltage. The result is an equivalent drain-to-source capacitor cds that is
the sum of c gd and cdb . Therefore, a switching MOS transistor can be represented by a
parallel combination of an ideal switch and the equivalent capacitor cds .
Figure 2-3: Simplified Model with Ideal Switch and Parasitic Capacitor
The transistor in the general power amplifier model in Figure 2-1 is replaced with its
equivalent switching model as shown in Figure 2-3. The effect of the drain-to-source
27
capacitor cds can now be analyzed. During the off stage, the switch opens and the capacitor
is charging up. The energy stored on the capacitor is then dissipated by a discharge current
through the switch during the on stage when the switch closes. The discharge current
represents an energy loss and a reduction in overall efficiency. Since the discharge current
occurs once per cycle, the loss increases linearly with the operating frequency. One way to
eliminate this loss mechanism is to drive the drain voltage to zero right before switching on.
That way there is no charge left on the output capacitor that can be discharged through a
closed switch. This technique is generally known as Zero Voltage Switching (ZVS). In
order to have zero power dissipation in the transistor, the zero voltage switching condition
has to be satisfied, in addition to the transistor operating as a lossless switch.
2.1.2 Second Condition: Fundamental Power Only
The second condition, P1 = P2 = P3 = L = 0 means the power delivered to the matching
network contains only the fundamental power P0 . It is important to realize that the voltage
and current at the matching network can have high order harmonics, as long as for each
harmonic other than the fundamental, the corresponding voltage and current do not overlap.
This condition can be satisfied by using appropriate output matching networks. Each
matching network methodology represents a specific class of power amplifiers.
2.2 Switching Power Amplifiers with Theoretical 100% Efficiency
2.2.1 Class-E
Figure 2-4: Class-E Schematics
28
An example of 100% efficiency power amplifiers is the class-E power amplifier that uses a
series resonator LS - C S at the operating frequency as the matching network. The resonator
blocks the DC and higher order harmonics, leaving only the fundamental current into the
matching network. Therefore, regardless of the harmonic content of the drain voltage, the
power delivered to the matching network contains only the fundamental, satisfying the
second condition for 100% efficiency. As for the first condition of zero voltage switching,
class-E power amplifier uses an additional shunt capacitor C P at the drain. The value of this
shunt capacitor, together with the resonator, provides two design parameters that can be used
to set the capacitor (drain) voltage to zero right before switching on to satisfy the ZVS
condition.
In order to analyze the operational waveforms of a class-E power amplifier, the transistor is
replaced with an ideal switch and an output parasitic capacitor cds that is lumped together
with the additional shunt capacitor C P into the total capacitor C1 as shown in Figure 2-5.
Again, the resonator forces its current to be pure sinusoidal. Assume the RFC is large
enough to conduct only a DC supply current, the total current into the switch and shunt
capacitor is an offset sinusoidal,
itotal (θ ) = I dc + I rf sin (θ − θ 0 )
with θ = ωt and θ 0 is the initial phase
(2-5)
Figure 2-5: Basic Class-E Operation
This current is commutated between the switch and the shunt capacitor depending on the
switch’s state. During the on stage, the switch conducts the offset sinusoidal current, and the
capacitor voltage is zero. During the off stage, the capacitor is charging up and its voltage is
the integration of the offset sinusoidal current. Assuming a 50% switching duty cycle, the
relevant currents and voltage are as follows,
29
vd (θ ) =
 I + I rf sin (θ − θ 0 ) 0 < θ ≤ π
isw (θ ) =  dc
0
π < θ ≤ 2π

(2-6)
0
0 <θ ≤π

ic (θ ) = 
 I dc + I rf sin (θ − θ 0 ) π < θ ≤ 2π
(2-7)
θ
0
0 <θ ≤π
1
1 
ic (θ )dθ =

∫
ωC1 0
ωC1  I dc (θ − π ) − I rf [cos(θ − θ 0 ) + cos(θ 0 )] π < θ ≤ 2π
(2-8)
Figure 2-6: Class-E Waveforms
By selecting the appropriate values for the resonator LS - C S and shunt capacitor C P , the
relative phase of the offset sinusoidal current can be adjusted such that the drain voltage is
driven to zero right before switching on, vd (2π ) = 0 . Typical waveforms of a class-E power
amplifier are summarized in Figure 2-6.
30
2.2.2 Class-F
Another example of 100% efficiency is the class-F power amplifier as shown in Figure 2-7.
Here the matching network includes a quarter-wavelength transmission line and a parallel
LP - C P resonant tank, both at the operating frequency. C ac is a large coupling capacitor to
block the DC current from going into the load.
Figure 2-7: Class-F Schematics
Recall that a quarter-wavelength transmission line reciprocates the load impedance, while a
half-wavelength line preserves the load impedance,
Z 02
for l =λ/4
ZL
Z in = Z L for l =λ/2
Z in =
(2-9)
The resonant tank creates a short at all harmonics except the fundamental. For all even
harmonics, the same short is presented to the drain since the transmission line appears as
some integer multiples of a half-wavelength. As a result, the drain voltage does not contain
any even harmonics. Also recall that the square wave contains only odd harmonics; the drain
voltage becomes a square wave. On the other hand, at all odd harmonics other than the
fundamental, the short created by the LP - C P tank is reciprocated into an open because the
transmission line appears as an odd multiple of quarter-wavelengths. The opens at odd
harmonics result in a load current ( iload ) without any odd harmonics except for the
fundamental, which takes the shape of half sinusoidal waveform (recall that the half
31
sinusoidal waveform contains only the fundamental and even harmonics). Therefore, by
limiting the drain voltage to contain only odd harmonics, and the load current to only even
harmonics, class-F power amplifiers guarantee that only the fundamental power is generated
at the matching network, satisfying the aforementioned second condition for 100%
efficiency. Typical class-F waveforms are plotted in Figure 2-8(a).
The drain voltage waveform in Figure 2-8(a) also satisfies the zero voltage switching
condition, where it reaches zero right before switching on. Therefore, class-F power
amplifiers satisfy both conditions for 100% efficiency.
Figure 2-8: Class-F (a) and Class-F-1 (b) Waveforms
2.2.3 Other Switching Classes (-F -1, -E/Fx)
Several other power amplifier classes also offer 100% efficiency. Each uses a different
approach to shape the voltage and current waveforms for maximum efficiency. However, the
same two principle conditions apply: zero voltage switching, and fundamental power only at
the matching network.
The inverse class-F power amplifiers swap the drain voltage and current waveforms
compared to those of the normal class-F [24]. By presenting a short at all odd harmonics
besides the fundamental, and an open at all even harmonics, the inverse class-F has a square
drain current and a half sinusoidal drain voltage as shown in Figure 2-8(b). A typical
implementation of a class-F-1 is shown in Figure 2-9.
32
Figure 2-9: Inverse Class-F Schematic
Yet another example is the class-E/Fx family [25]. Instead of removing all the even
harmonics from the voltage and all odd harmonics from the current as the class-F power
amplifiers, the class- E/Fx power amplifiers retain a few even harmonics in the voltage, and
remove those extra even harmonics in the current to remain satisfying the second 100%
efficiency condition. The advantage of this approach is the ability to control the peak drain
voltage. The more even harmonics being retained in the drain voltage, the lower its peak
voltage gets. The class-E/Fx family becomes very attractive as technology scales with
smaller and smaller breakdown voltage.
Depending on the specific application, each class of switching power amplifiers is more
suitable than the other. The three selecting criteria are the peak value of the drain voltage,
simplicity of implementation, and tuning flexibility. In general, class-E is the simplest to
implement while having the largest peak drain voltage. It is most suitable for low to
moderate output power where the large peak drain voltage can be tolerated. On the other
hand, class-F and inverse class-F are more complicated to implement, but the peak drain
voltage is smaller. The hybrid class-E/Fx family falls in between; both in complexity and
peak drain voltage value.
2.2.4 Switching Power Amplifiers Linearity
From the above efficiency analysis, it is clear that 100% efficiency power amplifier has to be
of the switching type, where there is no voltage and current overlap at the drain. A switching
transistor is unquestionably non-linear from the fact that variations in the input power are not
reproduced at the output in any acceptable form. While the phase of the input signal is
preserved at the output, the amplitude of the output signal is not a function of the input
amplitude, rather it depends on the supply voltage and output matching network. As a result,
conventional switching power amplifiers, without qualification, are not suitable for linear
amplification.
33
In order to achieve linearity, the hard switching condition has to be avoided. Instead,
variations of the input power are reproduced at the output by allowing the input voltage to
modulate the drain current in the “pseudo-linear” transconductance region. That is the basis
for conducting-mode power amplifiers where the switching condition for 100% efficiency is
sacrificed for linearity.
2.3 Conducting-Mode Power Amplifiers
2.3.1 Operating Principle and Efficiency
Figure 2-10: Input-to-Output Waveforms of Conducting-Mode Power Amplifiers
An example of a conducting-mode power amplifier is shown in Figure 2-10. A gate input
voltage within the pseudo-linear transconductance region creates a proportional drain current
at the output. The drain current, in turns, modulates the drain voltage, depending on the load
impedance presented at the drain. A change in the input drive results in a change in the drain
current, and subsequently a proportional change in the output voltage as described by the
three thick arrows in Figure 2-10. Depending on the linearity of the transistor’s
transconductance, a linear relationship between the input and output voltages is achieved.
34
Evaluating the waveforms in Figure 2-10 under the conditions for 100% efficiency developed
in previous sections, several observations can be made.
•
•
•
Drain voltage and current overlap continuously exists in the example waveforms,
resulting in power being continuously dissipated in the transistor. This is a violation
of the first condition for 100% efficiency developed in previous sections.
The amount of overlap, and the energy being dissipated in the transistor, can be
reduced by forcing the drain current to be zero for a portion of each period. This is
accomplished by lowering the initial gate bias voltage, which is the basis for reduced
conduction angle classes of power amplifiers (i.e. -AB, -B, and -C). The power
amplifier efficiency is a function of the gate bias voltage, or conduction angle.
In reduced conduction mode, the drain current is clipped to zero for a portion of each
period, resulting in higher order harmonic content in the drain current. Therefore, in
order to satisfy the second 100% efficiency condition of only fundamental power
delivered into the matching network, all harmonics have to be removed from the drain
voltage. As a result, the drain voltage in conducting-mode power amplifiers is a
usually pure sinusoid at the fundamental frequency.
2.3.2 Performance Characteristics of Conducting-Mode Power
Amplifiers
Figure 2-11: Characteristic Waveforms of a Power Amplifier with Conduction Angle α
The efficiency and linearity performance of conducting-mode power amplifiers can be
quantified by examining the harmonic content of the drain current as a function of the bias
condition. Figure 2-11 shows the general input and output waveforms on a power amplifier
with a conduction angle α. The drain current is a clipped sinusoid, where the clipping occurs
35
when the gate voltage is less than the transistor’s threshold voltage. On the other hand, the
drain voltage is tuned to pure sinusoidal without any clipping to guarantee only the
fundamental power is being delivered to the matching network as discussed in the previous
section.
The conduction angle is used to classify conducting-mode power amplifier. Power
amplifiers operate in class-A have a full conduction angle of 2π. The class-B conduction
angle is π, where the drain current is perfectly half sinusoid. Class-C power amplifiers
conduction angle is less than π.
The drain current in Figure 2-11 can be expressed in terms of the conduction angle as
follows,

 I + (I max − I q )cos θ
id (θ ) =  q

0
α 
α
α
<θ ≤
2
2
otherwise
−
(2-10)
Iq
where cos  =
 2  I max − I q
Replacing the initial drain bias current I q by the conduction angle α ,
α
α
 I max (cos θ − cos(α 2 ))
− <θ ≤

id (θ ) = 
1 − cos(α 2 )
2
2

0
otherwise
(2-11)
From (2-11), the harmonic content of the drain current as well as the power amplifier
efficiency can be calculated as a function of the conduction angle [26]. A plot of the drain
harmonic content versus the conduction angle is shown in Figure 2-12(a), while the
efficiency curve is plotted in Figure 2-12(b).
Several observations can be made from the plot of the drain harmonic currents.
•
•
•
•
As the conduction angle is reduced from 2π, the efficiency increases as expected due
to the reduction in drain voltage and current overlap. This is further evident by the
decrease in the DC supply current.
As the conduction angle is reduced, higher order harmonic currents increase.
A class-A power amplifier has a 2π conduction angle and a maximum efficiency of
50%. For a class-B power amplifier, the conduction angle is π, and its efficiency is
π/4 or 78.5%.
Theoretically, a class-C power amplifier with a zero conduction angle can achieve
100% efficiency. However, this is the detrimental case where the output power is
also reduced to zero as shown by the fundamental and harmonic content of the drain
current.
36
Figure 2-12: Drain Harmonic Currents as a Function of the Conduction Angle
2.4 Summary
This chapter has introduced a power model to facilitate a general power amplifier efficiencylinearity tradeoff analysis. In order to achieve the theoretical 100% efficiency, power
amplifiers have to operate in the switching condition where the relationship between the
output and input amplitudes is highly non-linear. Beside lossless switching operation, the
zero voltage switching condition also has to be satisfied to eliminate energy loss due to
capacitor discharging during on-off transitions. Switching classes are categorized by the
implementation of the output matching network.
37
Conducting class power amplifiers forgo the switching condition to achieve linearity. Power
amplifiers in conducting classes are characterized by their conduction angle, which
determines both the power amplifier linearity and efficiency. A larger conduction angle
corresponds to higher linearity and lower efficiency.
38
Chapter 3
Orthogonal Frequency Division Multiplexing
Orthogonal Frequency Division Multiplexing is a multi-carrier modulation that has been
adopted as the standards for Wireless Local Area Networks, such as the 802.11a in the US
and HIPERLAN/2 in Europe. The basic idea of OFDM is to transmit blocks of symbols in
parallel by employing a number of closely-spaced orthogonal carrier frequencies. The two
most distinct advantages of OFDM are the elimination of elaborate equalization, and the
ability to adapt different sub-carriers to use different modulations depending on the channel
conditions [27,28]. The major drawback for OFDM is the large peak-to-average power ratio
of the transmitting signal, requiring power amplifiers with great linearity over a large
dynamic range of output power, that are often very inefficient.
Because of the general popularity and the high linearity requirement of OFDM, an OFDM
system with multi-channels of 256-QAM will be used throughout this thesis to evaluate the
capability of the outphase concept, and the proof-of-concept outphase power amplifier test
chip. This chapter reviews the basic digital building blocks of an OFDM system. In
addition, the probability distributions of constellation magnitudes for various OFDM systems
are presented from a custom simulation capable of large number of samples for reliable
distributions. The amplitude probability distribution data is important because it represents
more realistic peak-to-average ratios as well as enables a system study into the effect of
clipping on bit-error-rate.
3.1 OFDM Constructions
Figure 3-1: N Parallel Orthogonal Sub-Channels by Using IDFT
39
The basic principle of OFDM is to transmit blocks of symbols in parallel using multiple
orthogonal carrier frequencies. This is accomplished by the Inverse Discrete Fourier
Transform (IDFT) function as shown in Figure 3-1. A group of symbols, one from each
parallel channel, forms the input vector to the IDFT. Recall that the IDFT operates on
frequency-domain input vectors, and outputs time-domain vectors; the IDFT places the
parallel symbols in the appropriate frequency bins. The sub-channels’ orthogonality is
guaranteed by the fact that sinusoidal functions at Fourier harmonic frequencies are
inherently orthogonal†. The parallel time-domain symbols in the IDFT output vector are then
converted to serial for transmitting. Therefore, the transmitting OFDM symbol rate is the
same as that of each individual sub-channel.
A typical OFDM system usually takes the input data in the form of a raw bits stream, maps
them onto appropriate symbols based on the modulation (e.g. QPSK, QAM, …) of each subchannel, then groups them together into parallel sub-channels before using the IDFT to place
them into orthogonal frequency bins. To complete the picture, the serial OFDM symbols are
separated into real and imaginary, or I and Q, quadrature channels before being converted
into analog baseband using two Digtal-to-Analog Converters (DACs). The baseband signals
are then filtered by two reconstruction filters that satisfy the Nyquist condition. Finally, the
quadrature I and Q channels are mixed up to the carrier frequency using appropriate phase
before being amplified for transmission. Figure 3-2 summarizes the typical building blocks
of OFDM transmitter architecture.
Figure 3-2: OFDM Transmitter Architecture
†
Two functions f ( x ) and g ( x ) are orthogonal over the interval (a, b ) when
b
∫ f (x )g (x )dx = 0 .
The
a
orthogonality of two sinusoidal channels with off-set frequencies n∆ω and m∆ω can be proved as follows,
∫ cos(ω
0
+ n∆ω ) cos(ω0 + m∆ω )dω =
T
1
(cos[(n + m )∆ω ] + cos[(n − m )∆ω ])dω = 0
2 T∫
for
T=
2π
∆ω
40
3.2 OFDM Peak-to-Average Power Ratios
In order to find the peak-to-average power ratio of an OFDM system, the PAPR of each
individual channel is required. For a single channel, the PAPR is a function of modulation
type. Figure 3-3 shows the PAPR of a single channel of various levels of QAM.
Figure 3-3: PAPR of Single Channel with Various QAM Levels
For an OFDM system, each symbol from the parallel sub-channels are group together and put
through an IDFT function to achieve OFDM symbols.
An N-point IDFT function is defined as follows,
pn =
1
N
N
∑ am e
2πi ( n −1)( m −1)
N
(3-1)
m =1
Each output OFDM symbol is the vectorial sum of all the parallel sub-channel symbols with
appropriate phase rotation. A peak OFDM amplitude results when all input symbols have
41
maximum amplitude in their respective sub-channel modulation, and perfectly line up in the
summation. In this worse case scenario, the amplitude of the OFDM symbol is N times the
amplitude of the individual sub-channel symbol, with N being the number of parallel subchannels. Therefore, an OFDM system can potentially increase the peak-to-average power
ratio by a factor of N , or 10 log10 ( N ) in dB. A plot of additional PAPR caused by using
multi-channels OFDM is shown in Figure 3-4. For example, an OFDM system of 128 subchannels causes an additional 21dB of PAPR. If each of the 128 sub-channels has
modulation of 256-QAM, then the total PAPR of the system is 25.787dB (21dB plus
4.787dB from Figure 3-3).
Figure 3-4: Additional PAPR Caused by OFDM
However, the above number is the worse case situation. The probability of all the subchannels having peak-amplitude symbols at the same time, and all perfectly lining up is very
slim. For example, the probability of the peak amplitude happens in an OFDM system with
128 sub-channels of 256-QAM is 64 −128 . In order to accommodate this extreme PAPR, the
transmitter has to handle an unreasonably large dynamic range while suffering severe
efficiency penalty for large power amplifier back-off.
For an optimal transmitter performance, a more realistic PAPR number that accounts for
amplitude probability distribution is needed. A custom C-language script is written to find
the amplitude distribution of an OFDM system with multi-channels of QAM. The script
mimics the architecture in Figure 3-2 to construct OFDM symbols. A random generator is
used to generate the input bits stream, which is then mapped onto appropriate QAM symbols
(with 8 bits per symbol for 256-QAM, and 6 bits per symbol for 64-QAM). The QAM
symbols are then put into groups of M-parallel sub-channels. Next, OFDM is applied to the
sub-channels using the M-Point IDFT function. Finally, amplitudes of the output OFDM
42
symbols are then recorded to the appropriate level of the 1024 levels that evenly divide the
OFDM amplitude dynamic range. The script is used to find the amplitude distribution for
four OFDM systems: 128 sub-channels of 256-QAM, 128 sub-channels of 64-QAM, 128
sub-channels of 64-QAM, and 64 sub-channels of 64-QAM. For each system, a set of 2 31 or
more than 2 billion OFDM symbols is used to guarantee reliable distributions. The result
amplitude distributions are plotted in Figure 3-5.
Figure 3-5: Amplitude Probability Distribution (128 Sub-Channels OFDM of 256-QAM)
Several observations can be made from the distribution plots.
•
•
The OFDM amplitudes follow the literature prediction of a Raleigh distribution.
Peak-to-average power ratios for the four systems are:
o PAPR128-channels/256-QAM=14.87dB
o PAPR128-channels/64-QAM=14.37dB
o PAPR64-channels/256-QAM=11.86dB
o PAPR64-channels/64-QAM=11.36dB
43
•
•
•
•
•
Again, it should be emphasized that the above PAPRs are deduced from the set of 2 31
symbols, and are much lower than the worse possible case. However, as mentioned
earlier, the probability of the worse case is extremely rare that could be safely ignored
without affecting the system accuracy. This effect of ignoring the large amplitude
symbols, or clipping, is quantified in terms of bit-error rate in the next section.
As expected, higher number of OFDM sub-channels corresponds to higher PAPR.
For systems with the same number of sub-channels but different QAM levels, there is
little difference in PAPR. That means the total PAPR is dominated by the number of
sub-channels rather than the modulation type of individual sub-channels.
These more realistic PAPRs are much more manageable than the worse case from the
earlier example.
All the distributions have rather long tails at the high amplitude range where the
probabilities are very small.
Since the distribution plot has a rather long tail at the high amplitude range where the
probabilities are very small, the PAPR can be further reduced using clipping. Clipping refers
to the fact that the maximum amplitude can be set at a pre-determined level, where any
symbols with exceeding amplitude are limited or “clipped” to this maximum level.
Obviously, clipping causes errors in transmission. However, clipping can be set such that its
corresponding errors are within a tolerable BER in exchange for a reduction of PAPR.
With the custom C-script, the BER-PAPR trade-off dues to clipping can be easily
determined. The total OFDM symbols used to find the distribution for each system is 2 31 .
Given a tolerable BER , the number of OFDM symbols can be clipped is simply 2 31 ⋅ BER .
Next, OFDM symbols can be discarded starting from the right most amplitude bin of 1024,
and keeping on going until the total of discarded symbols reaches 2 31 ⋅ BER . That is the
maximum level where the amplitude can be clipped. Using this new maximum level, the
new PAPR can be recalculated. Figure 3-6 plots the PAPR versus BER caused by clipping
for the four example OFDM systems. There is little difference between the four systems.
From the results in Figure 3-6, it can be concluded that for a tolerable a BER of 10-5, an
OFDM system with 128 sub-channels of 256-QAM can be clipped to limit its PAPR to less
than 11dB. This represents a tremendous improvement from the worse case number of more
than 25dB that would undoubtedly reduce the power amplifier efficiency from any
acceptable level.
Additional elaborate coding schemes with various levels of complexity can be used to further
reduce the PAPR [29,30].
44
Figure 3-6: BER vs. PAPR for Various Clipping Degrees
45
46
Chapter 4
Outphase Amplifying – System Analysis
The capability of the outphase amplifying concept in modern communication systems
depends on three main parameters: the implementation of the amplitude-to-phase conversion,
the sensitivity of bit-error rate on mismatch among the two outphase paths, and the
implementation of an accurate and low loss power combiner. Traditionally, implementing the
inverse cosine and other trigonometric functions, necessary to carry out the amplitude-tophase conversion, using analog circuits are non trivial and inevitably complex. That is the
main reason for the lack of popularity for the outphase amplifying concept since its invention
in 1935. Instead, this chapter introduces a digital implementation to obtain the required
accuracy and efficiency. In addition, an optimal outphase assignment is proposed to control
the outphase amplitude variations and significantly lower the required power amplifiers’ gain
that can be traded for higher efficiency. Based on the proposed digital conversion, the
relationship between bit error rate and mismatch can be analyzed to establish a figure of
merit in determining the suitability of the outphase concept in modern communication
systems.
4.1 Digital Outphase Conversion
Figure 4-1: Outphase Concept with Digital Amplitude-to-Phase Conversion
47
Figure 4-1 shows the principle diagram for an outphase amplifier with a digital amplitude-tophase conversion, taking advantages of the available computational capability of
contemporary digital technology. Here, the amplitude-to-phase conversion is done in the
digital domain, on the complex series x[n] representing the quadrature time sample instances
of the input signal. The outputs of the conversion box are two series x1 [n] , and x2 [n] that
correspond to the two constant amplitude, phase modulated signals s1 (t ) and s 2 (t ) after the
DACs and Up-Converters. Each of the two constant amplitude outphase signals is then
amplified using two highly efficient class-E switching power amplifiers. The outputs y1 (t )
and y 2 (t ) of the PAs are then combined to restore the original amplitude modulated signal.
In the digital domain, the amplitude-phase conversion box takes the original amplitude
modulated series x[n] as the input, and produces the two outphase series x1 [n] , and x2 [n] .
Figure 4-2 demonstrates the digital outphase conversion using three example constellations:
x[1] , x[2] , and x[3] . Each constellation x[k ] of the original series is represented as a sum of
two outphase constellations, x+φ [k ] and x−φ [k ] , such that all the outphase constellations line
up along the constant amplitude circle. The angle between the two outphase constellations
depends on the amplitude of the original constellation. A constellation with small amplitude
(e.g. x[2] ) corresponds to a large angle between the two outphases ( ∠x+φ [2]x−φ [2] ), while the
constellation with large amplitude (e.g. x[3] ) corresponds to a much smaller outphase angle
( ∠x+φ [3]x−φ [3] ). The outphase constellations are then assigned to the two outphase channels,
represented by the two series x1 [n] , and x2 [n] , with the first channel contains all the x+φ [k ] ,
while the second contains all the x−φ [k ] as shown at the bottom of the conversion box in
Figure 4-2.
The formal mathematical definition of the digital outphase conversion is as follows,
• Input: x[k ] = x[k ] exp( jθ [k ])
• Outphase conversion function: x[k ] = x+φ [k ] + x−φ [k ]

 x[k ]
Amax
exp( j (θ [k ] + φ [k ])) φ [k ] = cos −1 
 x+φ [k ] =
2
 Amax

 x [k ] = Amax exp( j (θ [k ] − φ [k ]))
Amax = max x[n]
 −φ
2
• Outputs: x1 [k ] = x+φ [k ] , and x2 [k ] = x−φ [k ]




48
Figure 4-2: Digital Outphase Conversion
4.2 Amplitude Variation Control
Although each of the outphase series x1 [n] , and x2 [n] contains only constant amplitude
constellations, their corresponding analog signals s1 (t ) and s 2 (t ) do not have constant
envelope amplitude. In Figure 4-3, the solid traces, connecting the outphase constellations
( x1 [1] , x1 [2], x1 [3] ) and ( x2 [1] , x2 [2] , x2 [3] ), represent the continuous-time envelope amplitude
of the two outphase analog signals s1 (t ) and s 2 (t ) . This phenomenon is independent of the
outphase technique, and is also observed in other “constant amplitude” modulation schemes
[31]. For example, the analog waveform of M-ary Phase Shift Keying (PSK) modulation
exhibits significant envelope variation despite the fact that all M-ary PSK constellations are
on a constant amplitude circle. The envelope variation is most severe when there is a
transition through zero, which occurs when the relative phase between two sequential
symbols is 180º.
49
Figure 4-3: Outphase Analog Waveforms Exhibit Significant Amplitude Variation
Despite Constant Amplitude Constellations
In the example of Figure 4-3, the transition angle between x2 [1] and x2 [2] is close to 180º,
results in significant envelope variation during transition between the two constellations.
When the two outphase signals s1 (t ) and s 2 (t ) have very large envelope variation, the two
switching power amplifiers need to have very large gain. Large power amplifier gain is
undesirable for it tends to make the power amplifier unstable as well as inefficient.
Instability comes from parasitic couplings that could inadvertently create positive feedback
in a large gain system. In addition, unreasonably large gain requires additional amplifier
stages that consume more power and degrade the PA’s overall efficiency. The envelope
variation can be controlled by limiting the transition angles between two sequential symbols.
For example, in Offset-QPSK and π/4-QPSK, only the transitions with angles not exceeding
90º and 135º, respectively, are allowed as compared to the non-offset QPSK where 180º
transition angles are possible as shown in Figure 4-4.
50
Figure 4-4: Signal-space Constellations for QPSK, Offset QPSK and π/4-QPSK
For the outphase technique, the fact that the outphase channel assignment is not unique offers
a simple method to control envelope variation of the outphase signals. For each constellation
x[k ] , there are two ways to assign outphase channels: the “forward-angle” x+φ [k ] to the first
channel x1 [n] , the “reverse-angle” x−φ [k ] to the second channel x2 [n], or vice versa. This
additional degree of freedom can be exploited to limit the transition angles and control the
envelope variation. For each outphase pair x+φ [k ] and x−φ [k ] , the channel assignment that
results in smaller transition angles is selected. Obviously, memory of the two previous
constellations x1 [k − 1] and x2 [k − 1] is needed to calculate the possible transition angles.
Following is the selection procedure,
•
•
•
Let x+φ [k ] and x−φ [k ] be the current outphase constellations that need to be assigned.
Let x1 [k − 1] and x2 [k − 1] be the previous constellations of the two outphase channels.
Calculate the two possible transition angle pairs:
ƒ If x+φ [k ] is assigned to x1 [k ] and x−φ [k ] to x2 [k ] then,
a1 = ∠x1 [k − 1]x+φ [k ] and a2 = ∠x2 [k − 1]x−φ [k ] ( 0 ≤ a1 , a 2 ≤ π )
ƒ
•
If x+φ [k ] is assigned to x2 [k ] and x−φ [k ] to x1 [k ] then,
( b1 = ∠x1 [k − 1]x−φ [k ] and b2 = ∠x2 [k − 1]x+φ [k ] ( 0 ≤ b1 , b2 ≤ π )
Eliminate the pair that has the largest transition angle among the four possible angles:
ƒ If max (a1 , a2 ) > max(b1 , b2 ) then assign x+φ [k ] to x2 [k ] and x−φ [k ] to x1 [k ]
ƒ
Otherwise, assign x+φ [k ] to x1 [k ] and x−φ [k ] to x2 [k ]
Looking back to the examples in Figure 4-3, all the x+φ [k ] are assigned to the first channel
and all the x−φ [k ] to the second channel. The result is a close to 180º transition angle
between x2 [1] and x2 [2] , causing significant envelope amplitude variation. Instead, based on
the comparison among possible transition angles, x+φ [2] is assigned to the first channel and
x−φ [2] to the second channel. The improvement is tremendous with a smaller transition
angle between x2 [1] and x2 [2] , and a much more tolerable amplitude variation in both
outphase channels as shown in Figure 4-5.
51
Figure 4-5: Optimal Outphase Conversion for Amplitude Variation Control
by Swapping Channel Assignment between x+φ 2 and x−φ 2
[]
[]
4.3 Digital Outphase Conversion in System Simulation
The custom C-script used to find the OFDM amplitude distributions in Chapter 3 is expanded
to carry out the digital outphase conversion with optimal outphase assignment to verify the
amplitude variation improvement. In order to construct the outphase signals, the script
follows the digital block diagram of an OFDM transmitter using the outphase amplifying
technique that employs a digital outphase conversion as shown in Figure 4-6. The
construction can be divided into three stages. The first stage is simply the script written
earlier to construct OFDM symbols from the input bits stream as implemented in Chapter 3.
The output of this stage is a series of OFDM symbols x[n] . In the second stage, the outphase
conversion with optimal assignment is implemented following the procedures described in
sections 4.1 and 4.2. Stage two outputs are the two digital outphase series x1 [n] and x2 [n] .
In stage three, the digital outphases are converted into analog, using first-order-hold DACs.
Next, ideal raised cosine filters, which satisfy Nyquist condition, are used to filter and limit
the bandwidth of the outphase baseband signals. Finally, the baseband signals are mixed up
to carrier frequency to achieve the two outphase signals s1 (t ) and s 2 (t ) , that are the inputs of
the two class-E power amplifiers.
52
Figure 4-6: OFDM Architecture with Outphase Amplifying
Top Row: Conventional OFDM Digital Building Block
Bottom Row: Outphase Power Amplifier with Digital Outphase Conversion
For comparison, the envelope amplitudes of the outphase signals are recorded in Figure 4-7
for two cases: one with the optimal outphase assignment included, the other without. Again,
the solid traces represent the continuous-time envelope amplitude of the two outphase analog
signals s1 (t ) and s 2 (t ) . The collection of original OFDM symbols is plotted in the far left.
As discussed in the previous section, small envelope amplitudes require larger power
amplifier’s gain that would be both unstable and inefficient. The optimal outphase
assignment eliminates undesirable small envelope amplitude.
53
I1
I1
Q1
Original OFDM Symbols
I
Q
Outph ase Envelope Amplitude
(non-optimal)
I2
Q1
Outphase Envelope Amplitude
(optimal outphase assignment)
I2
Q2
Q2
Figure 4-7: Envelope Variation w/ and w/o Optimal Outphase Assignment
(The variation is within 4dB when the optimal assignment procedure is included)
4.4 Effect of Mismatch
4.4.1 Error Vector Magnitude
In order to exactly recover the original signal, the two outphase paths, from the outphase
conversion function in the digital domain, all the way to the final power combiner, have to be
perfectly matched. Any gain and phase mismatch will cause the actual constellation to be
shifted from the original point. For a given gain and phase mismatch, it is straightforward to
calculate the degree to which the constellations are being shifted. A common figure of merit
is Error Vector Magnitude, which can be used to quantify the error caused by mismatch
among the outphase paths.
EVM is defined as the vector from the ideal error-free constellation to the actual transmitting
constellation caused by mismatch errors. From Figure 4-8,
r
EVM = e
(4-1)
54
Figure 4-8: EVM Definition
Sometime, EVM is normalized to the magnitude of the ideal error-free constellation to
remove the effect of the channel gain. In that case,
EVM nom
r
e
= r
r
(4-2)
Assuming that there is a gain mismatch of α, and a phase mismatch of δ° between the two
outphase paths as shown in Figure 4-9. The mismatch causes the outphase constellation x−φ
r
to shift by an error vector e to x−φerr . After recombining, the original constellation x is also
shifted by the same error vector. The error vector is a function of the mismatch and the
nominal gain of the outphase channels as shown in (4-3).
r G ⋅ Amax
2
EVM = e =
1 + (1 + α ) − 2(1 + α ) cos(δ )
2
(4-3)
It is important to recognize that for a given mismatch, the error vector magnitude is constant
for all constellations. To remove the effect of the channel gain, EVM is normalized to the
r
error-free magnitude r , where
r
r = G ⋅ Amax cos(φ )
where is φ the outphase angle
(4-4)
Therefore,
r
2
e
1 + (1 + α ) − 2(1 + α ) cos(δ )
EVM nom = r =
r
2 cos(φ )
where is φ the outphase angle
(4-5)
55
Figure 4-9: Outphase EVM with Gain and Phase Mismatch of α and δº
In addition to gain and phase mismatch, the normalized EVM is also a function of the
outphase angle φ , or the constellation amplitude. Recall the outphase decomposition
described from previous section that constellations with large amplitude correspond to
smaller outphase angle, and therefore, smaller EVM for a given mismatch. A plot of EVM
versus normalized constellation amplitude is shown in Figure 4-10. For comparison, TDSCDMA standard using QPSK modulation requires an EVM of -10dB or better [32], while
802.11 g/a) requires an EVM of -30dB.
Figure 4-10: Normalized EVM dues to Mismatch
56
4.4.2 Bit-Error Rate
In the previous section, the error vector, which represents the displacement of the OFDM
symbol, was determined and plotted as a function of gain and phase mismatch. It was
concluded that the raw EVM (non-normalized) is independent of the system modulation.
This section goes a step further to determine the bit-error rate caused by gain and phase
mismatch among the outphase path. Unlike the case with EVM, the mismatch-displaced
OFDM symbols have to be converted back to individual channel modulation symbols in
order to determine BER. As a result, the effect of mismatch on BER is modulation-specific.
In other words, BER is also a function of the modulation types of each parallel sub-channel,
besides the gain and phase mismatch.
The C-script is expanded yet again to include a built-in mismatch between the two class-E
PAs and the functionality of an OFDM receiver, where the output signal of the outphase
power amplifier is down-converted, digitized, and decoded into parallel sub-channel symbols
and finally into bits stream. The received bits are then compared to the original transmitted
bits to determine BER.
Figure 4-11: BER vs. Voltage Mismatch (OFDM 128 sub-channels of 256-QAM)
The simulation is done for an OFDM system with 128 sub-channels of 256-QAM with a total
of 2 31 symbols or 2 39 bits since each 256-QAM symbol has 8 bits. The results are plotted in
Figure 4-11 and Figure 4-12 for BER versus voltage (linear gain) and phase mismatch. With
current integrated technology, the voltage and phase mismatch of less than 2% and 6º are
achievable which will put the BER caused by mismatch of less than 10-4.
57
Figure 4-12: BER vs. Phase Mismatch (OFDM 128 sub-channels of 256-QAM)
4.5 Summary
This chapter has introduced an accurate and efficient digital amplitude-to-phase outphase
conversion to facilitate the outphase amplifying concept. In addition, an optimal outphase
assignment procedure has been proposed to control the two outphase signal envelope
amplitude variations and relax the gain requirement for the two switching power amplifiers.
A custom C script system simulator verifies the amplitude-variation reduction results.
The theoretical analysis and system simulation on the effect of gain and phase mismatch
among the two outphase signal paths were also presented. The effect of mismatch has been
quantified using both the general EVM figure of merit and the more system specific BER.
Simulation results show that the BER caused by a linear gain mismatch of 2% and a phase
mismatch of 7º is less than 10-4 for an OFDM system with 128 sub-channels of 256-QAM.
In general, the effect of mismatch among the two outphase paths is manageable and
comparable to other wireless communication standards.
58
Chapter 5
An Integrated Outphase Power Amplifier
Figure 5-1: Die Photo
An integrated outphase power amplifier was fabricated in the IBM 7WL SiGe BiCMOS
process to verify the outphase concept. Only MOS transistors were used on the test chip
which includes two identical class-E power amplifiers and the first fully integrated power
combiner at 5.8GHz. They are described in Figure 5-2. During testing, all the outphase
signal conversion and construction are done off-chip, using available measurement
equipment.
59
Figure 5-2: Test Chip Includes Two Class-E PAs and a Power Combiner
For compatibility and testing purposes, the outphase power amplifier specification is based
on the Wireless Gigabit Local Area Network (WiGLAN) project [33], which is the parent
project of this thesis. The WiGLAN uses the Industrial, Scientific, and Medical (ISM) band
at 5.8GHz, which is reserved by the FCC for indoor wireless communication with a
maximum transmitting power of 100mW.
One main obstacle in the design of a fully integrated CMOS power amplifier is the low draingate, drain-source, and drain-substrate breakdown voltages of the transistor. The low
breakdown voltage limits the achievable maximum output power. In order to maximize the
achievable output power, the power amplifier is designed to allow the drain voltage to reach
its maximum level without damaging the transistor. In a class-E power amplifier design, the
maximum drain voltage is a function of the supply voltage. Therefore, there is no
specification for supply voltage; rather it is determined from the class-E waveforms and the
process technology’s breakdown voltage.
Table 5-1: Power Amplifier Specification
Maximum Output Power
P0 max
20
dBm
Center Frequency
Nominal Gain
Supply Voltage
Maximum Drain Voltage (Thick Oxide FET)
f0
G
VDD
VBR
5.8
15
TBD
3.6
GHz
dB
V
V
5.1 Class-E Design
Among the high efficiency switching power amplifier classes, the simplicity of class-E
output matching network makes it the best candidate for a fully integrated outphase power
amplifier. In addition, because of the moderate required output power (20dBm total, or
17dBm for each class-E PA), the potential drawback of a class-E large peak drain voltage can
60
be easily accommodated. The class-E operation principle is discussed in Chapter 2. Its
voltage and current waveforms are summarized in Table 5-2.
The following design values can be determined from the above specification: the optimal
load RL , the shunt capacitor CP , the series resonator LsCs , the size of the switching
transistor (by determining its drain current), and the supply voltage VDD .
Table 5-2: Summary of Class-E Equations and Waveforms
Figure 5-3: Class-E with Ideal Transistor Switch
itotal (θ ) = I dc + I rf sin (θ − θ 0 )
with θ = ωt and θ 0 is the initial phase
 I + I rf sin (θ − θ 0 ) 0 < θ ≤ π
isw (θ ) =  dc
0
π < θ ≤ 2π

0
0 <θ ≤π

ic (θ ) = 
 I dc + I rf sin (θ − θ 0 ) π < θ ≤ 2π
vd (θ ) =
θ
1
ic (θ )dθ
ωC1 ∫0
Figure 5-4: Ideal Class-E Waveforms
5.1.1 Design Equations and Parameters
Recall that class-E employs ZVS, where the capacitor (drain) voltage is driven to zero right
before the transistor is switched on. In addition, the capacitor current also returns to zero
before the transistor is switched on. Therefore,
vd (2π ) =
πI dc − 2 I rf cos(θ 0 )
=0
ωC1
(5-1)
61
ic (2π ) = I dc + I rf sin (2π − θ0 ) = 0
(5-2)
In addition, there are two conditions on the drain voltage: its average is the supply voltage,
and its peak value is less than the process technology’s breakdown voltage.
2π
VDD = ∫ vd (θ )dθ
(5-3)
VBR = max[vd (θ )]
(5-4)
0
Another design equation comes from the power from the DC source, which is the same as the
maximum output power for an ideal 100% class-E efficiency.
Pdc = VDD I dc = P0 max
(5-5)
Given the maximum output power P0 max and the breakdown voltage VBR , the five design
parameters ( I dc , I rf , θ 0 , VDD , C1 ) can be determined from the above five equations ((5-1) to
(5-5)). From these five parameters, all the values necessary for the design of a class-E power
amplifier can be calculated.
5.1.2 Differential Class-E with Driver Stage
Figure 5-5: Class-E in Differential Configuration
62
In process technologies where a backside ground plane with via access is not available, bondwires are used for ground connections. However, bond-wires usually have undesirably large
inductors that could take up precious voltage headroom. For the class-E design, a differential
configuration is used to take advantage of the virtual grounds and avoid the large groundwire inductors that could degrade the voltage headroom and overall efficiency. As described
in Figure 5-5, due to the virtual grounds created by the differential configuration, the two CP
capacitors can be combined and replaced by a single capacitor connecting the two transistors’
drains. Similarly, the two LD inductors can be combined into one differential center-tapped
inductor as shown in Figure 5-6(a), where the AC ground center tab can be connected
directly to the supply voltage. The most benefit perhaps comes from combining the two gate
inductors LG. In order to resonate out the gate capacitance, a shunt inductor with low-loss
and low-impedance ground connection is needed. Combining the two gate inductors
provides the ground connection needed while reducing the inductors die area by half. The
differential inductors are modeled and designed using Sonnet Suites 8.0, a high frequency
electromagnetic simulator. By using the top thick metal layer for the windings and metal
shields on M1 (the first metal layer), inductors with quality factors between 18 and 25,
depending on the size and inductance, can be designed.
Figure 5-6: (a) Differential Inductor with Center Tab (b) Differential Transformer
63
A schematic of the differential class-E power amplifier using center-tapped inductors is
shown in Figure 5-7.
Figure 5-7: Differential Class-E Power Amplifier Using Center-Tapped Inductors
In order to achieve the required gain, a driver stage is added to achieve the required gain.
Again the differential configuration is used with connections to bias and supply voltages via
center tabs of differential inductors. Again, the center-tapped differential inductor LG _ OUT is
used to resonate out the gate capacitance of the output transistors while providing the bias
voltage via its center tab. Inter-stage matching is accomplished by the driver inductor
LD _ DRV and capacitors C IM , which also double as DC blocks between the two stages.
Finally, the driver stage’s gate inductor LG _ DRV is realized as part of the input transformer
that provides input matching as well as single-to-differential converter. The transformer
layout is shown in Figure 5-6(b). The complete schematic of the design is given in Figure
5-8.
64
The designed class-E is fully integrated except for the 12Ω output load. Normally, additional
transformation is needed to convert the optimal 12Ω load to the typical 50Ω antenna load.
However, since the outputs of the class-E power amplifiers are connected to the power
combiner, the impedance matching will be addressed later during the power combiner design.
Figure 5-8: Differential Class-E PA with Driver Stage
5.1.3 Simulation Results
Figure 5-9: Switching Transistor Model and Additional Shunt Capacitor CP
A class-E power amplifier with the above design values is simulated using Cadence’s
Spectre. Before examining the simulation waveforms, it is important to recognize that the
drain current actually consists of two elements as shown in Figure 5-9: the switch current isw ,
which is zero during the OFF stage, and the parasitic capacitor current icds , which is zero
65
during the ON stage. Therefore, comparing to the theoretical currents from Figure 5-4, the
simulated drain current in Figure 5-10 resembles the switch current during the ON stage.
Figure 5-10: Simulation Class-E Waveforms (T=1/5.8GHz)
During the OFF stage, the drain current is the parasitic capacitor current icds , which is
proportional to the total capacitor current ic plotted in Figure 5-4. This is further verified by
the fact that the capacitor (drain) voltage peaks when the capacitor current crosses zero
during the transition from charging to discharging. During switching on, the transistor goes
from saturation into triode, causing a shift the in the drain current as indicated in Figure 5-4.
In addition, the drain voltage is not completely zero during the ON stage, due to the fact that
the transistor has a small parasitic “on” resistance.
The plots of the overall efficiency and output power versus the supply voltage VDD are shown
in Figure 5-11. At the nominal supply voltage of 1.3V, the power amplifier outputs 15.5dBm
at 63.7% efficiency.
66
Figure 5-11: Simulated Efficiency and Output Power vs. Supply Voltage
5.1.4 Corner Simulation
Figure 5-12: Amplitude Mismatch Due to Process Variation
of the IBM 7WL SiGe BiCMOS Process
67
A corner simulation is done to estimate the amplitude mismatch caused by process variation.
Results in Figure 5-12, show that for a threshold voltage and velocity saturation variation
within ±1σ, the amplitude mismatch is less than 5%. Amplitude mismatch due to transistor
width and length variation is minimal. It should be mention that these are wafer variations.
For ICs within a wafer, the process variation is expected much smaller.
In addition, the tolerance for top layer metal, where the power combiner is incorporated, is
less than 0.86µm. With the (60µm x 2800µm) quarter-wavelength section of the power
combiner, the process variation for the power combiner is on the order of 1%, which also has
minimal effect on mismatch. Therefore, most of the mismatch is expected to come from the
transistor process variation.
5.2 Power Combiner Design
5.2.1 Wilkinson Power Combiner
Figure 5-13: Wilkinson Power Combiner
As discussed earlier, in order for the outphase technique to operate over an extended range of
amplitude modulations, good isolation is needed between the two class-E power amplifier
outputs. The isolation requirement limits the choices to hybrid power combiners, such as the
Wilkinson combiner or branch-line combiner. Hybrid combiners rely on quarter-wavelength
transmission lines to achieve input isolation. Among hybrid combiners, the Wilkinson,
shown in Figure 5-13, has two advantages. First, it has only two quarter-wavelength
sections, compared to others with four or more sections. Second, the Wilkinson is also
capable of impedance transformation that comes in handy in stepping the 50Ω antenna load
to the optimal 12 Ω load required by the class-E PA designed in the previous section.
68
Figure 5-14: Analyzing the Wilkinson Combiner in Odd and Even Modes
The Wilkinson can be analyzed in even and odd modes using a line of symmetry as shown in
Figure 5-14.
•
•
In the odd mode, all the points along the symmetrical line are virtual ground. The
half circuit consists of a quarter-wavelength section with the output grounded, and the
input connected to the half resistor R 2 to ground. The quarter-wavelength
transmission line converts the short at the output to an open at the input. Therefore,
the total impedance presented at the input is simply the half resistor R 2 . All the
odd-mode input power is dissipated across this resistor.
R
o
o
= 0 and Z IN
=
VOUT
2
In the even mode, all the points along the symmetrical line are open. Imagine the
output resistor Z OUT as two parallel resistors of 2Z OUT each. Then the half circuit
consists of a quarter-wavelength section with a 2Z OUT resistor at the output, and the
input with a floating (open) resistor R . The quarter-wavelength transmission line
converts the 2Z OUT resistor at the output to an impedance of Z L2 2Z OUT , which is the
impedance presented at the input. The input to output voltage equation is given by
transmission line theory.
2Z
Z L2
e
e
VOUT
= − j OUT VINe and Z IN
=
ZL
2Z OUT
From the above odd-even Wilkinson combiner analysis, several conclusions can be made:
69
•
o
e
Isolation between the two input ports can be achieved if Z IN
= Z IN
. In other words,
the impedance looking into one input is always the same, regardless of what happens
at the other input port. Therefore, the design equations for the Wilkinson are as
follows,
Z L = 2 Z IN Z OUT
and
R = 2Z IN
(5-6)
The above equations also imply the impedance transformation capability of the
Wilkinson combiner by appropriately sizing the internal resistor and the characteristic
impedance of the quarter-wavelength sections.
•
The “in-phase” parts of the two inputs add up to the output‡, while the “out-of-phase”
parts appear and are dissipated across the combiner’s resistor.
VOUT = j (VIN 1 + VIN 2 )
Z OUT
2 Z IN
and VR = VIN 1 − VIN 2
(5-7)
The power conservation can be used as a sanity check:
•
Input power: PIN = PIN 1 + PIN 2
VIN2 1 VIN2 2
=
+
Z IN Z IN
V 2 (V − V )
Combiner’s resistor power: PR = R = IN 1 IN 2
R
2Z IN
Z OUT
(VIN1 + VIN 2 )2
2
2
(
VOUT 2Z IN
VIN 1 + VIN 2 )
Output power: POUT =
=
=
Z OUT
Z OUT
2Z IN
2
•
•
•
Power conservation: POUT
VIN2 1 VIN2 2
+ PR =
+
is indeed equal to the input power PIN
Z IN Z IN
5.2.2 Shielded Coplanar Stripline
Since the output of the two class-E power amplifiers are differential, the Wilkinson combiner
is constructed using coplanar striplines that consist of two parallel and closely spaced metal
lines as shown in Figure 5-15. For a fully integrated approach, the combiner has to be small
and low-loss§.
‡
The signal at the combiner’s output is in fact shifted 90º from the “in-phase” inputs. However, this is not an
issue since all signals are shifted by 90º. Therefore, there is no change in the relative phase.
§
It is important to distinguish this energy loss, which is caused by parasitic resistance and various couplings, to
the energy dissipated on the combiner’s resistor as discussed in the previous section. The stripline loss is a
70
The size of the combiner is determined by the wavelength, which is a function of the
frequency and the phase velocity, which in turn is a function of the dielectric material.
λ=
vp
f
where v p is the phase velocity, and f is the frequency
(5-8)
For silicon-based integrated circuits, v p = 87 ⋅ 106 m / sec . Therefore, at the center frequency
of 5.8GHz, the length of a quarter-wavelength section is λ 4 = 3.75mm . The phase velocity
is sometimes expressed in terms of the self-inductance between the two conductors of the
coplanar striplines, and the shunt capacitor due to the close proximity of the two conductors
[34].
1
LC
where L and C are the striplines’ inductor and capacitor per unit length
vp =
(5-9)
Figure 5-15: Integrated Circuit Coplanar Stripline
As indicated by the two coupling capacitors in the cross-section picture of Figure 5-15, the
electric field around the coplanar striplines couples to the substrate. Since the silicon
substrate is lossy, the striplines lose considerable power due to substrate coupling.
One way to reduce both the size and loss of the coplanar striplines is the use of floating metal
shields as shown in Figure 5-16. Long perpendicular floating strips of lower metals can be
inserted along the length of the striplines. For example, the SiGe 7WL has 7 metal layers,
from top to bottom: AM, E1, M5, M4, M3, M2, and M1. First, the coplanar striplines are
placed on the top AM metal. Minimum width E1 shielding strips are then placed at
minimum spacing, perpendicular to the striplines. This process is repeated for other metal
layers (M5, M4, …), where the shielding strips in adjacent metal layers are interleaved for
function of the environment that could be controlled by different layout techniques. On the other hand, the
energy loss on the resistor is a function of the input signals that can only be changed by coding and modulation.
71
better shielding as shown in the x-direction cross-section picture of Figure 5-16. In order to
minimize induced currents caused by the AC currents on the coplanar striplines on the top
metal, minimum width shield lines are used.
Figure 5-16: Coplanar Stripline with Floating Metal Shields
The shield has two effects. First, it prevents the electric field of the coplanar striplines from
coupling to the lossy substrate, significantly limits the loss of the striplines. Second, in
preventing the electric field from coupling to the substrate, the electric flux from the two
conductors of the striplines that normally go into the substrate is now redirected to between
the conductors as shown in Figure 5-17. The effect is an increase in effective capacitance
between the two conductors of the striplines. Recall from (5-8) and (5-9) that the phase
velocity and wavelength are inversely proportional to the square root of the unit length
capacitor. The result is a shorter wavelength, or smaller coplanar striplines. Using this
shielding technique, an improvement of up to 2x in effective quality factor Q, and 2x in size
reduction have been reported [35,36].
Figure 5-17: Effects of Metal Shields
5.2.3 A Shielded Coplanar Stripline Wilkinson Combiner
72
For the outphase power amplifier, the load at the power combiner’s output is the 50Ω
antenna, while the combiner inputs have to present the 12Ω optimal load required by the two
class-E PA. Therefore, the design parameters for the Wilkinson combiner are,
Z OUT = 50Ω and Z IN = 12Ω
(5-10)
The cross-input resistor and the characteristic impedance of the quarter-wavelength sections
can be calculated using (5-6),
Z L = 34.64Ω and
R = 24Ω
(5-11)
Again, the Sonnet Suit 8.0 software is used to design the Wilkinson combiner with above
parameters. In order to minimize the die area, the two quarter-wavelength coplanar striplines
are wrapped around the chip edge as shown in Figure 5-18. Using the metal shield
technique, the quarter-wavelength of the coplanar stripline is found to be 2.8mm, or 25%
shorter than the 3.75mm of an unshielded line. An input isolation of 35dB is achieved at the
center frequency of 5.8GHz, while the throughput response is around -4dB, which is
equivalent to 1dB loss from input to output (a Wilkinson combiner with loss-less striplines
has -3dB throughput response). Sonnet simulation also shows that the magnetic and electric
fields do not extend more than 100µm inside the combiner loop, where the two class-E
power amplifiers are placed.
Figure 5-18: Chip Layout of the Coplanar Stripline Wilkinson Combiner
5.3 Summary
This chapter presented the design and fabrication of a test chip consisting of two identical
class-E power amplifiers and the first fully integrated Wilkinson power combiner. The classE power amplifiers use differential configuration with center-tapped inductors and
transformer to take advantage of differential-mode virtual grounds. Simulation results show
73
each class-E power amplifier has an output power of 17.5dBm with 64% efficiency at the
nominal operating supply voltage of 1.3V. The integrated Wilkinson power combiner is
realizable with special metal shields to minimize loss as well as chip area. Using the
designed power combiner, excellent input isolation of -35dB is achieved while the input-tooutput insertion loss is within 1dB.
74
Chapter 6
Experimental Results
The measurement required to verify the theoretical analysis is, in itself, a deliberate and
challenging process. First, individual blocks, namely the class-E power amplifier and the
Wilkinson combiner, are measured and characterized for comparison to the respective
simulation results. Second, in terms of conventional power amplifier measurements, an
output spectral density plot is needed to verify the outphase power amplifier linearity and
FCC spectral compliance. Finally, since the outphase amplifying technique requires the
amplitude-to-phase decomposition and recombination, a mismatch-error sensitivity
measurement is needed to verify the accuracy of the outphase power amplifier. For all
measurements, the test chip is mounted and wire-bonded directly onto a printed circuit board
(PCB). Because of the fully differential design, the outphase power amplifier is robust
against ground and supply wirebond inductance. For differential signal output ports,
variation in wirebond lengths can be compensated using external tuning capacitors.
6.1 Class-E and Power Combiner Measurements
Figure 6-1: Laser Trim Locations and Intermediate Test Points for Individual Block Measurements
75
First, recall that the test chip consists of two identical class-E power amplifiers, and a
Wilkinson combiner, all of which are fully differential. The two class-E inputs also include
single-to-differential transformers enabling single-ended input signals. Intermediate test
points between the class-E and the combiner are also incorporated for individual blocks
testing purpose.
In order to isolate and test the class-E power amplifier by itself, laser trims are used to cut the
wires connecting the class-E output and intermediate test point to the combiner as shown in
Figure 6-1. In this case, the intermediate ports need to provide the 12Ω differential load to
the class-E output. Since all available equipment is single-ended, transformers similar to the
ones at the inputs are used to convert and transform the 50Ω single-ended equipment load to
the12Ω differential load required by the class-E. These transformers are fabricated on PCB.
The transformer layout also includes tuning features to compensate for variation of wirebond
lengths on the differential ports.
Similarly, to isolate and test the Wilkinson combiner by itself, traces between the class-E
outputs and combiner’s inputs are cut. Since the combiner’s inputs are also 12Ω differential
impedance, the same PCB transformers used for the class-E outputs can convert the 12Ω
differential impedance to single-ended 50Ω inputs. A photo of the PCB is shown in Figure
6-2.
INPUT1
Intermediate
Transformer
OU TPUT
Output
Transformer
Inte rme diate
Tra nsfor mer
INPUT2
Figure 6-2: Test Board
Since the output power of a switching class power amplifier is a function of the supply
voltage. The output power and efficiency of the class-E power amplifiers are measured for
different values of the supply voltage as shown in Figure 6-3.
76
Figure 6-3: Class-E Measured Output Power and Efficiency
The measured S-parameters of the Wilkinson combiner are plotted in Figure 6-4. The
measurements show good agreement with the Sonnet EM simulation. The measured input
isolation is better than 30dB.
Figure 6-4: Measured Wilkinson Combiner S-Parameters
77
6.2 Outphase Power Amplifier Efficiency
Using the outphase technique, each of the two class-E power amplifiers generates a constant
output power into the two input ports of the combiner. The output power of the combiner
depends on the relative phase between the two outphase signals. The “in-phase” components
are added to the combiner output port while the “out-of-phase” components are dissipated
across the combiner’s resistor. When the relative phase is zero, all the class-E output power
is added to the combiner’s output with no power being dissipated on the combiner’s resistor.
Otherwise, depending on the relative phase, a fraction of the class-E output power appears at
the combiner output, and the rest is dissipated across the combiner’s resistor. Therefore, the
outphase power amplifier achieves the best efficiency at the maximum output power. At
lower output power, the efficiency decreases. This behavior is inevitable in an amplitude
modulated system where the output power fluctuates within the output dynamic range.
The outphase power amplifier efficiency across the power range is measured using the test
setup described in Figure 6-5. The single-tone 5.8GHz output of the signal generator is first
duplicated using a power splitter. One of the power splitter’s output is connected directly to
the first input of the outphase PA, while the other is connected to the second input via a
variable phase-shifter. The phase-shifter is used to adjust the relative phase between the two
input signals, and thus changing the output power of the outphase power amplifier.
Figure 6-5: Efficiency Measurement Setup
For this measurement, the exact value of the relative phase is not required. For every single
setting of the phase-shifter, the output power is recorded; and the efficiency is determined as
the ratio of the output power to the total DC supply power.
η=
POUT
Pclass − E1 + Pclass − E 2
(6-1)
78
The efficiency versus output power of the outphase power amplifier is obtained by sweeping
the phase-shifter setting. The result plotted in Figure 6-6 shows a maximum efficiency of
47% at 18.5dBm output power.
Figure 6-6: Outphase Power Amplifier Efficiency vs. Pout
6.3 Overall Outphase Power Amplifier Measurements
6.3.1 Generating the Outphase Signals
Since the test chip only consists of the two class-E power amplifiers and combiner, in order
to measure the outphase power amplifier overall performance in a multi-channel OFDM
system, the digital outphase conversion has to be implemented and the two outphase signals
s1 (t ) and s 2 (t ) have to be provided as inputs to the test chip. Realizing that each of the two
outphases s1 (t ) and s 2 (t ) is also an OFDM signal, two vector signal generators with OFDM
capability can be used to construct the required outphase signals. The trick here is to supply
the signal generators with the right input sequences so that they produce the correct outphase
signals s1 (t ) and s 2 (t ) . In addition, since the two outphase signals are generated separately
using two signal generators, precise synchronization is required to ensure the correct timing
between the two outphase signals. The digital outphase conversion and all necessary digital
signal processing can be implemented in Matlab. Two available vector signal generators are
Agilent models E8267C and E4438C.
79
Figure 6-7: Construction of Outphase Signals for OFDM Measurements
Before a procedure to generate the outphase signals can be devised, it is important to
understand the functionality and capability of the vector signal generators. Both available
signal generators have built-in baseband generators capable of multi-channels OFDM with
custom I-Q modulations. In order to generate OFDM signals, the signal generators require
an input vector of sub-channels modulation symbols. Functionally inside the signal
generator, the input vector is fed to an IDFT block to put the sub-channels modulation
symbols into frequency bins, resulting in an OFDM symbols vector. A parallel-to-serial
converter is used to convert the parallel symbols in the OFDM vector into serial OFDM
symbols, which are then converted and filtered into baseband signals before being mixed up
to the selected RF (carrier) frequency. A functionality block diagram of the signal generator
is shown in Figure 6-8. The key point here is the fact that the signal generator requires inputs
of sub-channel modulation symbols to construct the OFDM signal. The signal generator
does not directly take OFDM symbol inputs.
Figure 6-8: OFDM Construction Block Diagram inside a Signal Generator
80
Because of equipment constraint, the outphase power amplifier is tested using an OFDM
system of 32 sub-channels of 64-QAM. The test signal is provided in a sub-channels
modulation vector form, with each vector contains 32 parallel 64-QAM symbols. Following
is the procedure to generate the outphase signals using Matlab and two vector signal
generators.
Using Matlab, the IDFT function is performed on the input vector a[n] to obtain the OFDM
vector x[n] . In terms of the outphase concept, these OFDM symbols represent the original
amplitude modulated signal. The outphase amplitude-to-phase conversion is carried out
next, converting x[n] into the two equivalent digital outphase vectors x1[n] , and x2[n] . Each
of the two outphase vectors contains digital OFDM symbols that can not be fed directly to
the vector signal generators. Therefore, using the Fast Fourier Transform (FFT) function,
x1[n] , and x2[n] are converted back to sub-channels modulation symbols (vectors a1[n] and
a2[n] ), which are the correct inputs required by the signal generators as shown in Figure 6-9.
Obviously, the two vectors a1[n] and a2[n] , in general, have arbitrary I-Q modulation, as
opposed to the original input vector a[n] which has the standard 64-QAM. Therefore, the
available custom I-Q modulation feature of the vector signal generators is extremely useful.
Figure 6-9: Block Diagram for Generating Outphase Signals Procedure
The two vectors a1[n] and a2[n] are then programmed as inputs into the two signal
generators to generate the desired outphase signals s1 (t ) and s 2 (t ) . In order to synchronize
the two outphase signals, two built-in frequency reference lines are used. First, a 10MHz
frequency from the “RF Sync Out” of the first signal generator is connected to the “RF Sync
81
In” of the second generator to synchronize the RF (carrier) frequency. Similarly, the 1MHz
“Symbol Sync Out” from one is fed to the “Symbol Sync In” of the other to align the symbol
timing between the two outphase signals.
6.3.2 Decode the Output Signal for EVM Measurements
Since EVM represents the error vector from the ideal error-free symbol to the actual symbol
being transmitted, EVM measurements require the knowledge of the actual symbols being
transmitted by the outphase power amplifier. Therefore, the output signal of the outphase
power amplifier has to be down-converted, and digitized to achieve the actual transmitted
OFDM symbols. Also, the OFDM symbols can be converted further to each sub-channel
modulation symbols. This function can be achieved using a Vector Network Analyzer
(VNA) with appropriate frequency and modulation capabilities. However, a VNA with the
outphase power amplifier specifications is not available to this project. Instead, a custombuilt receiver, dubbed the WiGLAN receiver, that can receive the same type of multichannels OFDM signals as the output signals of the outphase PA, is accessible. The
WiGLAN receiver detects the OFDM signal, down-converts, and digitizes the equivalent
baseband signal. The captured digital data is then transferred to a computer for processing.
The receiver is part of a parallel project carried out by Nir Matalon [37].
The WiGLAN receiver (and a lot of Matlab data processing) is used to determined the actual
transmitting symbols from the outphase power amplifier’s output. The complete test setup,
shown in Figure 6-10, includes two vector signal generators (Agilent E8267C and E4438C)
supplying the outphase input signals to the outphase power amplifier test chip. The outphase
PA’s output is connected to the WiGLAN receiver via a 20dB attenuator. A laptop computer
handles all the data captured by the receiver and carries out all necessary Matlab codes.
82
To Computer
USB Port
To R eceiver
Symbol
Sync
10MHz
RF Sync
From SigGen2
(E4438C)
From SigGen1
(E8267C)
Figure 6-10: Complete Test Setup for Outphase PA Measurements with OFDM Signals
Figure 6-11: 50Ω Resistor Combiner for Calibration
The measurement setup is first calibrated using a resistor combiner (Agilent Power Divider
11636B). Replacing the outphase power amplifier, the two outphase signals from the signal
generators are fed into two ports of the resistor combiner, the third port is the output port,
which is then connected to the receiver. The resistor combiner is close to an error-free
combiner, which allows the receiver to be calibrated. By comparing the receiving symbols to
the known transmitting sequence, a calibration matrix can be built to remove the receiver
non-idealities during outphase PA measurements.
83
6.3.3 Results
Once the receiver calibration matrix is obtained, the outphase power amplifier test chip
replaces the resistor combiner for the overall system measurements. Recall from Chapter 2
that the amplitude of the output signal of a class-E power amplifier is a function of its supply
voltage VDD . Therefore, the supply voltage, which is separate between the two integrated
class-E PAs, can be adjusted to control the amplitude mismatch between the two outphase
paths. On the other hand, there is no direct way to adjust the phase mismatch. However, the
phase mismatch can be quantified in terms of amplitude mismatch.
Figure 6-12: Gain Adjustment for Compensating Phase Mismatch
Figure 6-12 illustrates an example of a phase mismatch δφ , which causes the outphase
constellation x−φ to be shifted to x−φerr . In order to get back the correct original constellation
x , the gain of the two outphase channels can be adjusted from x+φ to x+φadj , and from x−φerr
to x−φadj , respectively. A mathematical calculation of the exact gain adjustment can be found
in Appendix A. Therefore, adjusting the supply voltages on both of the class-E PAs is an
indirect way to control the phase mismatch.
Back to the overall outphase PA measurement, the supply voltage on one of the class-E is
adjusted for the “best-looking” received QAM diagram from the WiGLAN receiver. Bestlooking means the most concentrated clusters of received QAM symbols. The voltage
adjustment is not too far off, with VDD = 1.295V results in the least scattered QAM diagram
in Figure 6-14 (with the supply voltage of the other class-E PA set at the designed nominal
84
value VDD = 1.3V ). The corresponding spectral density of the output signal is shown in
Figure 6-13.
Figure 6-13: Output Power Spectral Density
Figure 6-14: 64-QAM Symbols w/o Mismatch
Figure 6-15: 64-QAM Symbols w/ 2% Mismatch
Figure 6-16: 64-QAM Symbols w/ 5% Mismatch
85
Next, the supply voltage is adjusted for different mismatches. Figure 6-15 shows the QAM
diagram with a voltage mismatch of 2% ( VDD = 1.275V ), while Figure 6-16 corresponds to a
5% mismatch ( VDD = 1.235V ).
Finally, the received OFDM symbols are compared to the “error-free” symbols to obtain the
error-vector-magnitude. The measured EVM for three different mismatch levels are plotted
in Figure 6-17 together with the simulated EVM. The measured EVM for 1% mismatch is
right on top the simulated curve.
15
Normalized EVM (dB)
3% V DD Mismatch
-0
5% V DD Mismatc h
-15
5% Simulation
1% V DD Mismatch
-30
1% Simulation
-45
-40
-30
-20
-10
0
Normalized Amplitude (dB)
Figure 6-17: Measured EVM
86
Chapter 7
Conclusion
The outphase amplifying technique’s place in modern wireless communication has been
proven in this investigation. The outphase power amplifier achieves a 47% maximum
efficiency under a high linearity OFDM signal with 32 sub-channels of 64-QAM . The two
performance-deciding elements of the outphase concept are the outphase decomposition and
the output combiner. By taking advantage of the advanced digital technology, the outphase
amplitude-to-phase conversion can be implemented digitally with both accuracy and
efficiency. The freedom in assigning the outphase channels is also utilized to control the
amplitude variation in the outphase signals and further improve the switching power
amplifiers efficiency. By carefully designing the Wilkinson power combiner using coplanar
striplines with metal shielding, a first 5.8GHz fully integrated differential Wilkinson
combiner is realized. The low-loss integrated combiner allows efficient outphase
recombining while providing the necessary input isolation for a robust outphase power
amplifier.
Measurement results from the outphase power amplifier test chip confirms that the outphase
technique is suitable for wireless systems with high linearity requirement. The outphase test
chip is capable of amplifying OFDM signals with multi QAM sub-channels. The outphase
power amplifier’s EVM due to mismatch is better than -25dB for a 20dB output dynamic
range. In a multi-channels OFDM/QAM system, this EVM is equivalent to a BER of less
than 10-4.
Table show a quick comparison of the outphase maximum efficiency to recent published
results. The outphase PA achieves a superior maximum efficiency due to its use of high
efficiency, switching class-E power amplifiers.
Table 7-1: Comparison with Previously Published Results
[38]
[39]
[40]
[41]
This work
Technology
CMOS
SiGe BiCMOS
InGaP/GaAs
Si-HBT
SiGe BiCMOS
Standard
WCDMA
WCDMA
802.11a/b/g
802.11g
OFDM/QAM
Pout(dBm)
26
26
26
22
22
η
22 %
27 %
28 %
32 %
47 %
Special Technique
2-PA system (high & low power)
Predistortion
Outphase
87
7.1 Average Efficiency Comparison
Since the outphase power amplifier efficiency decreases as the output power is reduced, an
average efficiency comparison is carried out for a complete efficiency evaluation of the
outphase power amplifier. Figure 7-1(a) plots the efficiency profiles across the output power
range of three power amplifiers: an outphase, a conventional class-A, and an adaptive classA. All three power amplifiers offer excellent efficiency. The adaptive class-A power
amplifier operates in the class-A full-conduction mode with an adaptive biasing scheme that
adjusts the bias current based on the input level to improve efficiency at lower output power
range [42].
Figure 7-1: (a) Efficiency Comparison
(b) System Specific Power Distributions vs. Output Power for Average Power Consumption Comparison
88
Several observations can be made:
•
•
•
The maximum efficiency of the outphase power amplifier is much better than the
other two power amplifiers due to the fact that the outphase PA is composed of two
high efficiency class-E power amplifiers.
Compared to the conventional class-A, the outphase power amplifier is more efficient
at all power levels.
Compared to the adaptive class-A, the outphase power amplifier has better efficiency
when the output power is 13dBm or higher. In other words, in a wireless system
where the PAPR of 7dB or less, the outphase power amplifier is, on average, more
efficient than the adaptive class-A PA.
Instead of comparing efficiency, a better figure of merit would be the average DC power
consumption. For this comparison, the probability distribution of the output power is needed.
Using the simulation results earlier in Chapter 3, the output power distribution is plotted in
Figure 7-1(b) **, and aligned to the power levels of the efficiency plot. For a fair comparison,
the maximum output power is held constant for the three power amplifier at 100mW or
20dBm.
•
Since the two class-E power amplifiers power consumption is constant regardless of
the overall output level, the total power consumption of the outphase power amplifier
is constant and measured at,
Pdc outphase = 212mW
•
Because of its fixed biasing, the conventional class-A power amplifier consumes the
same amount of DC supply power regardless of the output levels. With an efficiency
of 31% at 100mW output power, the DC power is,
Pdc class − A =
•
(7-1)
POUT max
η max
= 320mW
(7-2)
Since the adaptive class-A power amplifier adapts the bias (or DC power
consumption) based on the power level, an output power distribution is needed to
calculate the average DC power consumption. Using these power distribution, the
average power consumption is determined as,
Pdc adaptive − A = 275mW for OFDM with 128 sub-channels
Pdc adaptive − A = 260mW for OFDM with 64 sub-channels
(7-3)
**
Notice that the distribution is plotted versus the output power in dB, as opposed to the linear output voltage
which results in a Raleigh distribution in Figure 3-5 of Chapter 3.
89
7.2 Future Related Research
Two additional features remain desirable to fully realize the potential of the outphase
amplifying concept. First, an auto calibration loop to correct for any phase and gain
mismatch between the two outphase paths can be added to further improve the outphase
power amplifier capability. Second, for wireless systems with large PAPR, the power being
dissipated on the combiner’s resistor is significant that can significantly degrade the average
efficiency. The power dissipation issue can be alleviated by reducing the PAPR through
coding, or replacing the combiner’s resistor with a power recycling block to recoup the
“wasted” energy.
Additionally, the outphase amplifying technique could lend itself in a new transmitter
architecture. Since the two outphase signals are constant amplitude, phase modulated, the
quadrature I-Q baseband building block can be eliminated all together. Instead, the carrier
frequency Voltage Control Oscillator (VCO) can be phase-modulated directly to produce the
two outphase signals.
90
Appendix A – Phase Mismatch Compensation
Ideally, the two outphase channels are perfectly matched, where
A
A
y1 (t ) = max cos(ωt + θ + φ ) and y 2 (t ) = max cos(ωt + θ − φ )
2
2
 a 

with φ = cos −1 
 Amax 
such that y1 (t ) + y 2 (t ) = a cos(ωt + θ )
For a phase mismatch of δφ , the two outphase channels are
A
A
y1 (t ) = max cos(ωt + θ + φ + δφ ) and y 2 (t ) = max cos(ωt + θ − φ )
2
2
Since there is no direct phase mismatch control, the supply voltages of each class-E PA can
be adjusted to compensate for the mismatch. The amplitude of each outphase signal can be
controlled by adjusting the supply voltages. Let G1 and G2 be the amplitude scaling factors
of the two outphase signals,
A
A
y1 (t ) = G1 max cos(ωt + θ + φ + δφ ) and y 2 (t ) = G2 max cos(ωt + θ − φ )
2
2
To compensate for the phase mismatch, we need to find G1 and G2 such that
y1 (t ) + y 2 (t ) = a cos(ωt + θ ) or
A
A
G1 max cos(ωt + θ + φ + δφ ) + G2 max cos(ωt + θ − φ ) = a cos(ωt + θ )
2
2
Expanding the left side,
A
G1 max [cos(ωt + θ ) cos(φ + δφ ) − sin (ωt + θ )sin (φ + δφ )] +
2
= a cos(ωt + θ )
Amax
[cos(ωt + θ )cos φ + sin (ωt + θ )sin φ ]
G2
2
Or collecting the cos(ωt + θ ) and sin (ωt + θ ) terms,
Amax
 Amax

G1 2 cos(φ + δφ ) + G2 2 cos φ  cos(ωt + θ ) +


= a cos(ωt + θ )
Amax
 Amax

G2 2 sin φ − G1 2 sin (φ + δφ ) sin (ωt + θ )


Equating the two sides,
Amax
 Amax

G1 2 cos(φ + δφ ) + G2 2 cos φ  = a


Amax
 Amax

G1 2 sin (φ + δφ ) − G2 2 sin φ  = 0


91
 a
Recall that φ = cos −1 
 Amax

 , solving the two equations for G1 and G2 ,

sin 2φ
G1 =
sin (2φ + δφ )
2 sin (φ + δφ ) cos φ
G2 =
sin (2φ + δφ )
For sanity check, G1 = G2 = 1 as expected when δφ = 0 .
92
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