An Ultra Low Power ADC for Wireless
Micro-Sensor Applications
by
Naveen Verma
B.A.Sc., Electrical Engineering and Computer Engineering, University
of British Columbia
Submitted to the Department of Electrical Engineering and Computer
Science
in partial fulfillment of the requirements for the degree of
Master of Science in Electrical Engineering and Computer Scienco
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
June 2005
© 2005 Massachusetts Institute of Technology. All rights reserved.
......
A uthor ..........................
Department of Electrical Engineering and Computer Science
May 16, 2005
C ertified by ....................
................ .....................
Anantha P. Chandrakasan
Professor of Electrical Engineering
Thesis Supervisor
Accepted by.....
..........
Arthur C. Smith
Chairman, Departmental Committee on Graduate Students
MASSACHUSETTS INS
OF TECHNOOGY
E
BARKER
MAR 0 3 2006
LIBRARIES
2
An Ultra Low Power ADC for Wireless Micro-Sensor
Applications
by
Naveen Verma
Submitted to the Department of Electrical Engineering and Computer Science
on May 16, 2005, in partial fulfillment of the
requirements for the degree of
Master of Science in Electrical Engineering and Computer Science
Abstract
Autonomous micro-sensor nodes rely on low-power circuits to enable energy harvesting as a means of sustaining long-term, maintenance free operation. This work
pursues the design of an ultra low-power analog-to-digital converter (ADC) whose
sampling rate and resolution can be scaled to dynamically recover power savings.
The proposed ADC has a sampling rate of 0-100 kS/s and a resolution of either
12 or 8 bits. The design is based on the successive approximation register architecture (SAR), which is suitable for scaleable, micro-power operation. Specifically, the
number of active blocks has been minimized to allow efficient power-gating, which, inturn, has been leveraged to implement scalability features. Several new techniques to
improve the efficiency of the ADC have been developed and employed. Analog offset
calibration in the regenerative latch is used, to improve the power-delay product of
the comparator; pre-amplifier cascade optimization is performed with consideration to
thermal noise limitations; weak-inversion biasing is employed in the active amplifiers;
passive switch-capacitors are used to generate the auto-zero reference voltage such
the CMRR of the ADC is maximized; integrated capacitors are laid-out in a new
common-centroid arrangement that minimizes edge effects; finally, the sub-DAC's
transmission gain is adjusted to reduce non-linearities caused by the attenuating effects of parasitics.
The ADC has been fabricated in a 0.18pLm CMOS technology. All circuits are
powered using a IV supply, though bootstrapping is used internally. At a resolution
of 12-bits, and a sampling rate of 100 kS/s, the power consumption of the entire
ADC core is 26pW. The SNDR of the converter with a 48 kHz input tone is 65dB
(10.55 ENOB) and the SFDR is 71dB. The power consumption decreases linearly
with sampling rate, and is measured to be approximately 200nW at 500 S/s.
Thesis Supervisor: Anantha P. Chandrakasan
Title: Professor of Electrical Engineering
3
4
Acknowledgements
This thesis has been a major accomplishment. It is not, however, my accomplishment
alone. The immense support and friendship I've received from so many over the course
of my degree and education so far, is perhaps the aspect most worth remembering.
Let me start by thanking them here.
Firstly, I must express my gratitude to my advisor and role model, Professor
Anantha Chandrakasan. Anantha forces me to do my best; how is it that I can spend
months analyzing a problem, and the first time I present it to him, I get a question
I hadn't even thought of? But, most importantly, I thank Anantha for giving me
something to strive towards.
Of course, non-technically, the biggest impact in my life is courtesy of my mom and
dad. Saying thank you to you guys is too trivial and inconsequential for everything
you have done and meant. I only hope that you know, as you always do, how much
your support means to me on a daily basis.
My sisters, Angelee and Serena, have played a very important role, not only in
my life, but specifically in the completion of this thesis. Thank you, both, for making
it such a high priority to keep in tact my ability to write prose. Of course, your
encouragement has meant even more.
Engineering education, a microcosm of life, is an arduous process. I've gotten
support, all the way, from my good friend, Sean. Neither of us quite fits into the EE
scene, but we get each other through it, and, at the end of it, we have a good laugh.
There is a group of masters who took it personally to make sure I understood
what engineering really is: a tall order, considering, at the time, I barely understood
V=IR. Thank you Dr. Lawrence, Dr. Jaeger, Dr. Pulfrey, and Dr. Salcudean.
Here at MIT, I wish to thank everyone from Ananthagroup.
I'm lucky to be
associated with such a bright group, that continually inspires me to be more creative.
Finally, I would like to acknowledge National Semiconductor for providing fabrication services for the prototype chip, as well as their development help and CAD
support.
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Contents
1
Introduction
1.1
1.2
2
3
19
Requirement Specifications . . . . . . . . . . . . . . . . . . . . . . . .
20
1.1.1
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
1.1.2
Sampling Rate
. . . . . . . . . . . . . . . . . . . . . . . . . .
21
1.1.3
Scalability . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
1.1.4
Input Interface
. . . . . . . . . . . . . . . . . . . . . . . . . .
22
Architecture Selection
. . . . . . . . . . . . . . . . . . . . . . . . . .
22
25
Precision Limitations
2.1
Low Overdrive of MOS Switches . . . . . . . . . . . . . . . . . . . . .
25
2.2
Charge Injection Errors . . . . . . . . . . . . . . . . . . . . . . . . . .
26
2.3
Mismatch of Passive Elements . . . . . . . . . . . . . . . . . . . . . .
27
2.4
Mismatch of Active Elements
. . . . . . . . . . . . . . . . . . . . . .
27
2.5
Device Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
2.6
Threshold Voltage Hysteresis . . . . . . . . . . . . . . . . . . . . . . .
30
2.7
Other Error Sources
. . . . . . . . . . . . . . . . . . . . . . . . . . .
31
2.8
Summary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
Successive Approximation Conversion
33
3.1
Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
3.2
Differential Successive Approximation ADC
. . . . . . . . . . . . . .
35
3.3
Analysis of Error Sources . . . . . . . . . . . . . . . . . . . . . . . . .
37
3.3.1
39
Capacitor Mismatch
. . . . . . . . . . . . . . . . . . . . . . .
7
3.4
4
DAC Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . .
39
3.3.3
Reference Voltage Error
. . . . . . . . . . . . . . . . . . . . .
41
3.3.4
Comparator Offset
. . . . . . . . . . . . . . . . . . . . . . . .
41
3.3.5
Sampling Switch Non-Linearity
3.3.6
Comparator Thermal Noise
Summary
. . . . . . . . . . . . . . . . .
42
. . . . . . . . . . . . . . . . . . .
42
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
Architecture Design and Theory
45
4.1
Global Architecture and Concepts . . . . . . . . . . . . . . . . . . . .
45
4.1.1
Conversion Plan . . . . . . . . . . . . . . . . . . . . . . . . . .
45
4.1.2
Sample Rate Scaling . . . . . . . . . . . . . . . . . . . . . . .
47
4.1.3
Resolution Modes . . . . . . . . . . . . . . . . . . . . . . . . .
50
4.1.4
Self-Timed Bit Cycling . . . . . . . . . . . . . . . . . . . . . .
51
4.2
4.3
5
3.3.2
Block Architecture
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
4.2.1
Comparator Architecture . . . . . . . . . . . . . . . . . . . . .
54
4.2.2
DAC Architecture . . . . . . . . . . . . . . . . . . . . . . . . .
65
4.2.3
SAR Architecture . . . . . . . . . . . . . . . . . . . . . . . . .
72
Summary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Circuit Design
5.1
5.2
73
75
DAC Circuit Design
. . . . . . . . . . . . . . . . . . . . . . . . . . .
75
5.1.1
Switch Network . . . . . . . . . . . . . . . . . . . . . . . . . .
76
5.1.2
Capacitor array . . . . . . . . . . . . . . . . . . . . . . . . . .
83
Comparator Circuit Design . . . . . . . . . . . . . . . . . . . . . . . .
91
5.2.1
Preamplifers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
92
5.2.2
Offset-Calibrating Latch . . . . . . . . . . . . . . . . . . . . .
96
5.2.3
Latch Level Restorer
. . . . . . . . . . . . . . . . . . . . . . .
106
5.3
SAR Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . .
107
5.4
Clock Manager
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
111
5.5
Charge Pump and Voltage Multiplier . . . . . . . . . . . . . . . . . .
112
8
6
7
115
Testing and Characterization
6.1
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
115
6.2
Characterization
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
118
6.2.1
Static Linearity . . . . . . . . . . . . . . . . . . . . . . . . . .
118
6.2.2
Dynamic Noise and Linearity
. . . . . . . . . . . . . . . . . .
120
6.3
Power Consumption
. . . . . . . . . . . . . . . . . . . . . . . . . . .
124
6.4
Comparision Study . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
6.5
Summary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
128
Discussions and Future Work
129
7.1
Effects of Applied optimizations . . . . . . . . . . . . . . . . . . . . .
130
7.2
Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
131
7.2.1
Digital Optimization . . . . . . . . . . . . . . . . . . . . . . .
132
7.2.2
Programmable On-Chip Post-Filtering
. . . . . . . . . . . . .
132
7.2.3
Resolution Scalable DAC . . . . . . . . . . . . . . . . . . . . .
132
7.2.4
Active Input Switch
. . . . . . . . . . . . . . . . . . . . . . .
132
135
A ADC Fundamentals
Linear Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . .
135
A.1.1
Ideal ADC Model . . . . . . . . . . . . . . . . . . . . . . . . .
136
A.1.2
Quantization Noise . . . . . . . . . . . . . . . . . . . . . . . .
136
A.2 Non-Ideal ADC Model . . . . . . . . . . . . . . . . . . . . . . . . . .
137
A.2.1
Effective Resolution . . . . . . . . . . . . . . . . . . . . . . . .
138
A.2.2
Random Noise in SAR ADCs
. . . . . . . . . . . . . . . . . .
138
. . . . . . . . . . . . . . . . . . . . . . .
139
A.1
A.3
Performance Normalization
A.3.1
Sampling Rate
. . . . . . . . . . . . . . . . . . . . . . . . . .
139
A.3.2
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
140
A.3.3
Figure of Merit . . . . . . . . . . . . . . . . . . . . . . . . . .
141
9
List of Figures
1-1
Existing designs in a power-input frequency space (data courtesy B.
G insburg, M IT).
1-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
Existing designs in a power-resolution space (data courtesy B. Gins-
burg, M IT ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
2-1
Effective resistance of a CMOS Transmission Gate.
. . . . . . . . . .
26
2-2
Origin of charge injection error in a sampling circuit.
. . . . . . . . .
26
2-3
Gain compression of a low voltage amplifier. . . . . . . . . . . . . . .
28
3-1
Logical block diagram of a successive approximation register ADC.
.
34
3-2
SAR sampling phase. . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
3-3
SAR bit cycling of MSB. . . . . . . . . . . . . . . . . . . . . . . . . .
36
3-4
Fully Differential DAC during sampling.
37
3-5
Errors in 3 bit ADC transfer characteristics:
error (c)Gain error (d)Linearity error [22].
3-6
. . . . . . . . . . . . . . . .
(a)Ideal case (b)Offset
. . . . . . . . . . . . . . .
38
Effect of capacitor array top-plate parasitics (a)During sampling (b)During
bit-cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
3-7
Effect of errors in Vregp. . . . . . . . . . . . . . . . . . . . . . . . . .
41
3-8
Equivalent sample-and-hold circuit. . . . . . . . . . . . . . . . . . . .
42
4-1
Block diagram of the final ADC. . . . . . . . . . . . . . . . . . . . . .
46
4-2
Final ADC conversion plan for (a)12-bit mode (b) 8-bit mode. ....
47
4-3
Waveforms showing power-gating control . . . . . . . . . . . . . . . .
50
4-4
Waveforms showing standard bit-cycling signals. . . . . . . . . . . . .
52
11
4-5
Waveforms showing self-timed bit-cycling signals.
. . . . . . . . . . .
53
4-6
Delay for amplifiers with various output resistances. . . . . . . . . . .
56
4-7
Comparator gain structures (a)Linear amplifier cascade (b)Regenerative
am plifier.
4-8
4-9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
Power-delay (normalized to CL) versus total gain for linear and regenerative am plifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
Auto-zeroed multi-stage preamplifiers.
60
. . . . . . . . . . . . . . . . .
4-10 Amplifier network (a)During auto-zeroing (b)During bit-cycling. .
.
61
. . . . . . . .
63
4-12 Effect of changing GM at constant amplifier power-delay. . . . . . . .
64
4-13 Architecture of final comparator.
. . . . . . . . . . . . . . . . . . . .
65
4-14 Architecture of final DAC. . . . . . . . . . . . . . . . . . . . . . . . .
66
4-15 Typical main-DAC/sub-DAC implementations . . . . . . . . . . . . .
68
4-16 Fully passive main-DAC and sub-DAC. . . . . . . . . . . . . . . . . .
68
4-17 Thevenin equivalent circuit for analyzing passive sub-DAC. . . . . . .
69
4-18 Differential-mode offset due to varying auto-zeroing voltage.
. . . . .
70
. . . . . . . . . . . . .
71
4-11 Normalized total power-delay of auto-zeroed amplifier.
4-19 Common-mode independent charge sampling.
.
4-20 Passive auto-zero reference voltage generation using capacitor arrays.
5-1
71
Implementation of switch sets in switch matrices (a)MSB switch set for
positive array (b)Bits 10-0 switch set for positive array (c)MSB switch
set for negative array (d)Bits 10-0 switch set for negative array.
. . .
76
5-2
DAC network (a)During purging (b)During sampling. . . . . . . . . .
77
5-3
Distribution of injection error determined by poorly matched top-plate
parasitic capacitances.
5-4
. . . . . . . . . . . . . . . . . . . . . . . . . .
78
Qualification of BCYCLEN and BCYCLEN signals with delayed
sam pling signals.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
79
5-5
Equivalent Resistance of input switch with respect to input voltage. .
80
5-6
Parasitic PN-junction on top-plate. . . . . . . . . . . . . . . . . . . .
81
12
5-7
Waveforms showing the origin of a transient spike during MSB bitcycling.
5-8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
83
Zoom-in of DAC differential output voltage as it recovers from a neg. . . . . . . . . . . . . . .
84
Implementation of purging switches . . . . . . . . . . . . . . . . . . .
85
5-10 Capacitor mismatch leading to largest DNL. . . . . . . . . . . . . . .
85
5-11 Effect of parasitic capacitance on sub-DAC top-plate. . . . . . . . . .
86
ative spike to the correct positive voltage.
5-9
5-12 Errors in ADC transfer characteristic due to compression in sub-DAC
interpolation.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
5-13 INL due to 200fF parasitic capacitance on top-plate of sub-DAC. . . .
88
5-14 INL after adjustment of coupling capacitance Cc. . . . . . . . . . . .
88
5-15 INL, after Cc adjustment, resulting from errors in estimation of parasitic capacitance.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
89
5-16 Capacitor array layout (a)Conventional common-centroid (b)Equaledge ratio common-centroid. . . . . . . . . . . . . . . . . . . . . . . .
90
5-17 Bottom-plate to top-plate and dummy array coupling in poly-poly capacitor arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
5-18 Implementation of auto-zeroing switches (a)First and second stage of
12-bit cascade (b)Last stage (only stage for 8-bit path). . . . . . . . .
91
5-19 Pream plifier circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
92
5-20 DAC and preamplifier waveforms during overdrive recovery . . . . . .
94
5-21 Change in cascade time-constant with respect to fractional changes in
Gm .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-22 Preamplifier biasing source.
96
. . . . . . . . . . . . . . . . . . . . . . .
97
. . . . . . .
98
5-24 Offset compensating latch during auto-zeroing. . . . . . . . . . . . . .
99
5-25 Block diagram of latch calibrating circuit . . . . . . . . . . . . . . . .
100
5-26 Latch voltage-follower calibration circuit. . . . . . . . . . . . . . . . .
100
5-23 Simplified schematic of complete offset-calibrating latch.
5-27 Latch voltage-follower equivalent circuit during first half of auto-zeroing
phase. .......
..
...................................
13
101
5-28 Latch circuit waveforms during the auto-zeroing phase. . . . . . . . .
102
5-29 Offset compensating latch during reset-resolve phase. . . . . . . . . .
103
5-30 Latch circuit waveforms during the reset-resolve phase. . . . . . . . .
104
5-31 Replica biasing circuit for latch. . . . . . . . . . . . . . . . . ... . . . .
105
5-32 Gain and phase of filtered and unfiltered auto-zeroing calibration circuit. 107
5-33 Latch level restoring circuit. . . . . . . . . . . . . . . . . . . . . . . .
108
5-34 Latch level restorer waveforms.
. . . . . . . . . . . . . . . . . . . . .
108
5-35 SAR state machine circuit. . . . . . . . . . . . . . . . . . . . . . . . .
109
5-36 Metastability recovery circuits (a)Metastability detector (b)Metastbility
reset.........
.....................................
110
5-37 Circuitry supporting resolution scaling. SLEEP signal is used to enforce power-gating.
. . . . . . . . . . . . . . . . . . . . . . . . . . . .111
5-38 Internal clock gating circuitry. . . . . . . . . . . . . . . . . . . . . . .111
5-39 Charge pump circuit to generate voltages beyond VDD -...........
5-40 NMOS Dickson voltage multiplier [39].
.112
. . . . . . . . . . . . . . . . . 113
5-41 Voltage muliplier simulation. . . . . . . . . . . . . . . . . . . . . . . .
113
6-1
Micrograph of fabricated test chip.
116
6-2
Micrograph of full ADC with offset calibrating latch.
6-3
ADC Test setup.
. . . . . . . . . . . . . . . . . . .
. . . . . . . . .
116
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
117
6-4
ADC Test PCB photograph. . . . . . . . . . . . . . . . . . . . . . . .
118
6-5
Code density histogram of ADC in 12 bit mode. . . . . . . . . . . . .
119
6-6
DNL and INL of ADC in 12 bit mode.
. . . . . . . . . . . . . . . . .
120
6-7
Code density histogram of ADC in 8 bit mode . . . . . . . . . . . . .
121
6-8
DNL and INL of ADC in 8 bit mode. . . . . . . . . . . . . . . . . . .
121
6-9
ENOB versus input frequency for the ADC in 12 bit mode and 8 bit
m ode.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
122
6-10 FFT of ADC output with 47.3kHz input tone. . . . . . . . . . . . . .
123
6-11 ADC power consumption with respect to sampling rate. . . . . . . . .
124
14
6-12 Figure-of-merit of this ADC compared with previous implementations
(data courtesy B. Ginsburg, MIT).
. . . . . . . . . . . . . . . . . . .
126
6-13 Power consumption of SAR ADCs with respect to input frequency
(data courtesy B. Ginsburg, MIT).
. . . . . . . . . . . . . . . . . . .
127
6-14 Power consumption of SAR ADCs with respect to resolution (data
A-1
courtesy B. Ginsburg, MIT). . . . . . . . . . . . . . . . . . . . . . . .
127
. . . . . . . . . . . . . . . . . . . . . . . . .
136
Ideal model of an ADC.
15
List of Tables
6.1
Simulated and measured power consumption of ADC blocks. . . . . .
125
6.2
ADC performance summary. . . . . . . . . . . . . . . . . . . . . . . .
128
17
18
Chapter 1
Introduction
Wireless sensor networks have received a lot of attention recently by various sectors of
the research community. Although protocols and requirement specifications are still
being defined at the communication, network architecture, node architecture, and
circuit levels, design constraints and applications are already emerging. The vision of
a micro-sensor network includes dense, intelligent nodes that are energy-autonomous
and that operate and are deployed in an ad-hoc manner. Such networks have diverse
applications ranging from military surveillance, reconnaissance, and damage assessment to environmental forest fire detection [1] and industrial process monitoring.
The design of micro-sensor node hardware is constrained by several factors, many
of which can be derived from collective considerations of the target applications. To be
energy-autonomous, nodes must be powered entirely by an energy harvesting source.
This places demanding, low-energy requirements on the constituent circuits. Ad-hoc
deployment and operation requires that nodes be fault tolerant and able to adapt to
unpredictable environments and network characteristics. Finally, high density and
ubiquity places a cost constraint on nodes, reducing their acceptable price per unit
to a few cents.
Fundamentally, the architecture of an intelligent sensor network node must consist
of an analog-to-digital conversion front-end (ADC), a digital signal processor (DSP),
and a short range radio. Additionally, a power subsystem, which might be a simple
as an energy scavenger regulator or as sophisticated as a dynamic voltage scaling DC-
19
DC converter, is a highly desirable peripheral [2][3]. This document will focus on the
development of an ultra low power ADC suitable for sensor network nodes. Although
design specifications and optimizations will be undertaken with this application in
mind, the circuit techniques developed, and indeed the final ADC, will be useful for
a variety of low power systems.
The remainder of this chapter discusses the preliminary considerations associated
with ADC design. Namely, Section 1.1 examines the target application and derives
the performance requirements.
Additionally, features beneficial, but not limited,
to sensor applications are specified here. Section 1.2 surveys existing designs as a
means of identifying ADC architectures that would be appropriate for this, low-power,
implementation.
1.1
Requirement Specifications
Within the vast application space encompassed by wireless sensor networks, acoustic
monitoring of a battle field environment is an example that requires a sophisticated
sensor node and, in particular, a non-trivial ADC. Consequently, it is a good vehicle
for developing a system of general value. The performance requirements and features specified in the following subsections have largely been derived by anticipating
possible functions and algorithms the sensor nodes might perform. In an effort to
maintain broad usefulness, aggressive requirements, that also provide some academic
gratification, have been specified.
1.1.1
Resolution
In the case of an acoustic sensor front-end, the microphone, preamplifier (if it is
present), and ADC all impose noise and distortion on the system. The microphone,
can have a dynamic range in excess of 100dB [4][5]. The preamplifier, at the cost of
power consumption, may be designed for virtually any dynamic range desired. In this
case, the ADC limits the dynamic range of the front-end. As explained in Appendix
A, all ADCs introduce quantization noise, limiting the sensor system's ability to
20
detect minute signals.
The magnitude of acoustic activity is measured by sound-level or sound pressure
level (SPL). The SPL associated with a quiet field is approximately 30dB, while that
associated with a large (military) vehicle, one meter away, is approximately 100dB.
Consequently, 70dB, which corresponds to just under 12 bits of quantization noise, is
an upper limit of the dynamic range required of the ADC. Accordingly, in this design,
a 12 bit ADC is pursued.
1.1.2
Sampling Rate
Although the acoustic frequency band extends to 20kHz, military interest of the
spectrum in a battle field is far more limited.
Vehicular and personnel acoustic
activity is typically within the kilo-Hertz range. As a result, a Nyquist rate converter
with a sampling rate as low as 2-3kS/s may be sufficient. However, to avoid in-band
signal-to-noise degradation due to aliasing, this imposes stringent requirements on the
pre-filters. Specifically, very high-order anti-aliasing filters are required. Typically
these are achieved through active circuits that may consume more power than the
entire ADC. To allow exploration of a variety of anti-aliasing options, this ADC will
be designed to have a sampling rate of 100kS/s.
Of course oversampling, in this
manner, would require post-ADC digital decimation filtering.
1.1.3
Scalability
As mentioned previously, low-power operation is a paramount design objective for
sensor subsystems.
Since sensor nodes are reactive, and the ADC is the front-end
unit in the detection path, conventional sleep-active state manipulations are of limited
use. In particular, some form of ADC is responsible for detecting an event of interest
and, accordingly, generating a wake-up signal. Of course, the level of sophistication
required in that initial detection depends on the application, and may be met by a
simple threshold detector. In any case, the ADC must remain "on" in some capacity.
Where the power source is erratic and unpredictable, such as the case of an energy
21
scavenger, it is beneficial to scale the power consumption in response to the dynamically varying constraints. The two main dimensions, along which an ADC may be
scaled in order to recover power savings are sampling-rate and resolution.
In the
extreme, the power consumption of the ADC should be vanishingly small. Highly reconfigurable solutions have been demonstrated [6] [7]. The characteristic of scalability
is itself a feature that can impose considerable overhead, in the form of the reconfiguration logic/fabric as well as adaptive biasing circuitry. It is essential, therefore,
to limit the performance space based on need, but also, based on ease of implementation. It, of course, follows that facilitating scalability should be considered early
on, at the architecture selection phase. Precise specification of the scalability feature
of this ADC will be deferred until the treatment of architecture and implementation
issues.
1.1.4
Input Interface
As discussed in Section 3.2, a differential ADC architecture is highly beneficial for
robustness.
This may, however, increase system complexity, as it requires a fully
differential input signal path. Since the power consumption of the sensor system is
liable to increase with the added complexity, this ADC will be designed to support
single-ended inputs, though some degradation in precision is expected in this case.
1.2
Architecture Selection
Architecture selection can begin with regards to the resolution, input bandwidth,
and scalability requirements specified above.
Since low-power operation is critical
in this design, architecture selection will be driven by an examination of the power
consumption of previous ADCs. Figure 1-1 plots the power consumption of existing designs against the maximum input frequency they can digitize. As shown, in
the 1OOkS/s space, successive approximation register (SAR) ADCs and oversampling,
delta-sigma ADCs achieve the lowest power. Pipelined and flash converters populate
the high-speed, higher-power regime. Similarly, Figure 1-2 plots the power consump-
22
tion of existing designs against their resolution. Here, very low-power SAR converters
are prominent at the 8 bit level. However, at the 12 bit level, the lowest power designs demonstrated are delta-sigma converters, though a couple of SAR converts also
achieve reasonably low-power.
Power VS Input Frequency
A
10
0X
10 -2
10
-1
0
10~10'
0
1-5
0
106
O
*
Flash
o SAR
-O
x
Pipelined
10
102
104
10
108
Input Frequency (Hz)
Figure 1-1: Existing designs in a power-input frequency space (data courtesy B.
Ginsburg, MIT).
With respect to the desired speed and resolution, SAR and oversampling ADC
architectures are the primary candidates for this design.
Delta-sigma modulation
greatly eases the implementation requirements of analog blocks, and, for preserving
accuracy, places an increased emphasis on digital circuits. This is amenable to modern
technology scaling trends, and, as a result, efficient, low-voltage designs have been
demonstrated in advanced technologies [8][9].
Delta-sigma converters benefit from
the additional advantage that they fundamentally rely on oversampling, easing antialiasing requirements.
Nonetheless, among the designs plotted in Figure 1-1 and
Figure 1-2, the lowest power are SAR converters, achieving power levels of submicro23
Power VS Resolution
Aj
Xp
10
A AA
A&
10-2
A
A
10
*
0
10
0
A
A
A
A
A
AA
10-5 -
Flash
SAR
0
x Pipelined
A Al
*
8
10-6
10-7
A
0~
6
8
10
12
14
16
Resolution (Bits)
Figure 1-2: Existing designs in a power-resolution space (data courtesy B. Ginsburg,
MIT).
Watts and micro-Watts [10][11].
This design will leverage the SAR architecture,
which is suitable for micro-power operation, and apply new techniques to efficiently
increase resolution capabilities to the 12 bit level.
24
Chapter 2
Precision Limitations
Having identified the precision requirements for this ADC, we can begin to identify
limitations in the implementation technology that must be addressed. This section
surveys practicalities in circuits and devices that are relevant to the development of
medium and high resolution ADCs.
Often, these limitations will be overcome by
appropriate circuit techniques, layout, and device sizing. Corresponding details are
provided in Chapter 5.
2.1
Low Overdrive of MOS Switches
The availability of ideal switches is extremely beneficial in analog circuit design.
In this ADC, switches are used to control signal flow, enable charge redistribution
on capacitors, and short nodes to ensure voltage equivalence.
functions as a nearly ideal switch. At low gate overdrives (IcVGS
The MOS transistor
- VTN,P
I), it provides
very high "off" resistance, and at high gate overdrive, it provides relatively low "on"
resistance.
In low-voltage analog circuit design, however, reduced headroom limits the gate
overdrive that can be applied. The effective resistance of a MOS transistor in deep
triode is given by Equation 2.1.
1
(2.1)
Reff,N,P
AN,PCOX(1
25
IGS
- VT N,P
Here, PN,P is the device mobility, Cox is the oxide capacitance, and
(1)are the device
dimensions. The resulting range of voltages effectively passed by an NMOS is between
0 and
VDD-VTN;
VDD.
The resistance of a CMOS transmission gate, such as the one shown in Figure
the corresponding range for a PMOS is between VDD-IVTPI and
2-1, is the parallel combination, Reff,N
Reff,P-
In the limit, when VDD < VTN
+ IVTPI, a CMOS transmission gate approaches the "off" state for voltages near
mid-supply, regardless of gate voltage.
VIN
R'L-RN-f
Reff,N__
|0
Cefp
VOUTtefP
Figure 2-1: Effective resistance of a CMOS Transmission Gate.
At low overdrive voltages, where the CMOS transmission gate resistance is high,
we are faced with increased settling times due to the resulting RC time constant.
Additionally, as this resistance becomes more dominate, its nonlinear nature (through
the dependence on IVGS
2.2
-
VTN,PI) becomes highly significant.
Charge Injection Errors
An additional limitation associated with MOS switches is the error in voltage observed
on high-impedance nodes immediately following sampling.
Consider the sampling
circuit shown in Figure 2-2.
VSAMP
vF
2 r
Rs
TI
CGSD-L
COL
Cs
CGSD
'COL
VOUr
Cu
Figure 2-2: Origin of charge injection error in a sampling circuit.
26
As VSAMP is reduced following sampling, the channel charge established in the
NMOS escapes through its source and drain. The resulting voltage error depends
on the interaction of the load impedances, CH, CS, and RS, with the MOS intrinsic
capacitance, CGS,D, and extrinsic capacitance, COL. In strong inversion, the intrinsic
capacitance is fixed at approximately
4
[12). In weak inversion, the intrinsic capac-
itance is nonlinear and vanishes exponentially [13]. In both cases, circuit simulators,
such as SPICE, represent charge injection behavior inaccurately.
2.3
Mismatch of Passive Elements
Among the errors in an ADC's transfer characteristic, linearity errors are most difficult
to correct. In a SAR ADC, the dominate source of nonlinearity is element mismatch
in the feedback DAC (as explained in Section 3.3). To minimize this, highly linear and
well matched passive elements are employed. Integrated poly-poly capacitors exhibit
superior matching characteristics and are extremely stable, having low voltage and
temperate coefficients (10-100 ppm/V and 20-30 ppm/SC respectively).
Although
native, untrimmed matching of +0.01% (suitable for up to 14 bits of precision) is
achievable, this depends on proper sizing and layout techniques.
2.4
Mismatch of Active Elements
Geometric tolerances as well as process dependant effects including diffusion, etch,
thermal, and stress gradients all contribute to mismatch in MOS transistors. This
mismatch results in variation that can be referenced to the physical MOS parameters
VTO, -y (the body-effect coefficient), /t, Cox, W, and L [14]. All of these variations,
except those associated with the one-dimensional quantities W and L, can be convolved with a double box function, defining the geometry of the devices, to quantify
the overall variation. One dimensional analysis can be applied to W and L.
If the proper layout practices of common-centroid arrangement and tight proximity are applied to matched devices, the residual spatial variations will have short
27
correlation distances with respect to the device dimensions and can be treated as
random "white noise". In this case, the short range mismatch parameter associated
with VTO dominates and can be used to estimate statistical variation between devices.
At the circuit level, mismatch between devices manifests itself as an offset voltage
which can be referred to the input of amplifiers. In a SAR ADC, offsets affecting the
comparator result in overall offset of the ADC transfer characteristic. Though this can
be calibrated using external hardware [15] or software [16], circuit support for offset
cancellation can also be employed (as explained in Section 4.2). Note, comparator
offset depends on temperature and is typically not static. This is particularly true in
low-voltage implementations where the active amplifiers operate in weak inversion.
An additional consequence of device mismatch is the resulting degradation in amplifier gain. Consider the simple amplifier in Figure 2-3. Assuming weak inversion
operation of all devices, the available linear output range with a 1V VDD is approximately 700mV. Outside this range, all devices are no longer in saturation, and severe
gain compression occurs. For devices with an intrinsic gain (gmro) of 20, the linear
gain of the amplifier is approximately 10
(gm,N(roN 11
ro,P) where
gm,N
gm,P in
weak inversion). The resulting input linear range is only 70mV. Any input referred
offset of the same order will cause degradation in the amplifier's gain. Consequently,
device offset must be considered when designing gain stages.
1V
>10mV
0-]
>10mV
>10mV
Figure 2-3: Gain compression of a low voltage amplifier.
28
2.5
Device Noise
Noise is fundamental to circuits and cannot be avoided. Nonetheless, managing noise
is critical particularly in the case of low-power, precision systems. Low-power implies
either low voltage or low current. In both cases, the ability to derive signal power is
reduced, and the limiting effect of noise power on achievable dynamic range is more
significant.
The noise inherent to electrical conduction, which comes about due to the discrete
nature of charge, is known as shot noise. Assuming the arrival of charge carriers (i.e.
electrons) is governed by Poisson statistics, and by treating their arrival as an impulse
of current (causing a step change in charge), the variance in current, in a bandwidth
Af, is given by the well known relationship of Equation 2.2[17].
2
= 2qISIGAf
(2-2)
The signal power can be represented by ISIG and the noise power can be represented
by a-.
Accordingly the signal-to-noise ratio (SNR), can be represented by Equation
2.3.
ISIG
_
ISIG
2qAf
12-
The important result of this relationship is that, SNR can be increased either by
increasing the signal (resulting in increased power consumption) or by reducing the
bandwidth.
If this analysis is approached from a thermal noise point of view, an
identical relationship is observed [18].
In a SAR ADC, this noise limits precision in at least three places. During initial
sampling of the input signal (Section 5.1.2), we are limited by CSAMP noise due to
the sampling switch, where CSAMP is the sampling capacitor. During auto-zeroing
(Section 4.2.1), we are limited by BC
Uk
noise due to the active amplifier, where
B is an implementation dependant parameter set by the amplifier and CAZERO is
the auto-zeroing capacitor. Finally, during bit cycling, we are limited by noise in the
29
comparator (Section 5.2.1) which originates in the preamplifiers and latch. This last
case can be extremely difficult to quantify, as comparator decisions do not depend on
the average power of the input signal. Instead, a transient analysis that considers the
time varying nature of the latching circuit must be applied.
Since the arrival of electrons is treated as an impulse of current, the shot or
thermal noise considered above has constant power over a broadband of frequencies.
As a result, it is called "white noise".
An additional type of noise, not inherent
to conduction, but prominent in MOS devices, nonetheless, is -, or flicker, noise.
Surface effects at the channel's silicon-oxide interface result in extraneous energy
states (or "traps") for the carriers. Flicker noise is highest at low frequencies. Its
power increases with device current (in a linear or quadratic manner depending on the
degree of inversion) and decreases with channel area. Flicker noise affects comparator
decisions if it is not cancelled appropriately.
2.6
Threshold Voltage Hysteresis
In a MOS device, inversion occurs as a result of energy band bending of the silicon
in the channel region. This is induced by the electric field originating at the gate. At
the on-set of strong-inversion, the concentration of channel forming carriers increases
quickly with increasing gate voltage. Consequently, the strengthening electric field
terminates at the silicon-oxide interface, and the additional voltage drop appears
across the oxide. The ensuing reduction of oxide energy bands results in low-energy
traps that can be filled by carriers via tunneling mechanisms [19].
Subsequently, when the gate voltage is reduced, carriers can take tens of milliseconds to leave the oxide traps and re-enter the silicon. The presence of the carriers in
the oxide long after the stress voltage is removed leads to threshold voltage hysteresis in devices. This behavior is only observed for positive stress voltages and, as a
result, affects differential inputs asymmetrically. The net effect manifests itself as a
hysteresis in amplifier offset voltage.
Threshold voltage hysteresis, on the order of millivolts, has been observed [19].
30
The effects are far less pronounced in PMOS devices than NMOS devices, and can
be managed further by minimizing signal induced band bending.
2.7
Other Error Sources
In addtion to the error sources mentioned above, power supply noise and substrate
noise can have a considerable effect on the precision of the ADC. Both of these noise
sources may be correlated with signal transitions in the circuits. Particularly in the
case where large swing digital signals couple to the sensitive analog blocks, like the
comparator preamplifiers and latch, the ADC output can be subject to periodic error.
For instance, since transitions in the SAR state machine occur in a regular fashion,
spurious noise, associated with some fraction of the clock frequency, might degrade
the ADC's precision.
Lastly, kickback noise from the comparator, which comes about when the outputs
start regenerating, is not particularly limiting in a SAR ADC. In a flash converter this
noise appears at the inputs, which couple to other comparators through the resistive
string. In the SAR ADC, only one critical decision is made at any time, and the
comparator is reset between decisions, negating previous kickback effects.
2.8
Summary
Details of how each of limitations above are managed are provided in the following
chapters.
Generally, both architecture and circuit techniques have been applied.
For instance, low switch overdrive is overcome, in some cases, by bootstrapping,
and, in other cases, by applying an architecture that avoids analog switches in the
critical signal path. Similarly, charge injection errors are minimized through the use
of counter-phased dummy switches as well as switching sequences that direct channel
charge onto the appropriate nodes.
Mismatch in passive and active elements are
managed through proper sizing. Additionally, amplifier offset cancellation techniques
are used. Finally device noise is limited in preamplifiers though gain, bandwidth, and
31
biasing considerations.
32
Chapter 3
Successive Approximation
Conversion
This chapter will describe the structure and operation of successive approximation
(SAR) analog-to-digital converters.
In Section 3.1, the basic operation of a SAR
ADC will be considered. In Section 3.2, an enhancement to the architecture, enabling
robust, differential operation, will be presented. Finally, in Section 3.3 constituent
blocks of the SAR ADC will be analyzed for their contributions to errors in the overall
conversion process.
3.1
Basic Operation
Successive approximation register (SAR) ADCs are very popular for medium and
high resolution applications. They achieve reasonably quick conversion times since
they are based on an efficient convergence algorithm. A logical block diagram of a
SAR converter is shown in Figure 3-1 below. Here the main blocks are a digital finite
state machine (itself called a successive approximation register), a digital-to-analog
converter (DAC), a sample-and-hold (S/H), and a comparator.
The input signal offsets the DAC's output value, and the finite state machine SAR
applies a binary search algorithm to the DAC to arrive at a digital representation of
the analog input. In practice, the sample-and-hold is often combined with the DAC,
33
DAC
+
+
VIN
Comparator
S/H
Clock
Figure 3-1: Logical block diagram of a successive approximation register ADC.
and the entire structure is implemented using binary-weighted switch capacitors.
Here, details of the conversion process for an N bit SAR ADC are described conceptually [20]. Operation, in the case of the practical implementation, employs additional
enhancements. Basically, conversion requires two phases: sampling, during which the
input voltage is stored, and bit-cycling, during which bits of the corresponding digital
code are successively resolved. In particular, the digital code corresponds to where
the analog input voltage lies within a range defined by the reference voltages,
and Vref,p.
Vref,N
As shown in Figure 3-2, the input voltage is initially sampled onto the
bottom plates of the DAC capacitor array. The resulting charge on the top plate of
the capacitor array, QTOP, is equal to -(VIN
- VrefN)2NCo.
Next, bit-cycling starts by resolving the MSB. First, the bottom plate of the largest
capacitor (2N-
1
C)
is connected to the positive reference voltage,
Vref,P,
while the
bottom plates of the remaining capacitors in the array are connected to the negative
reference voltage,
Vref,N,
as shown in Figure 3-3. The resulting structure forms a
capacitor divider with equal capacitance from the output to Vref,p and
Vef,N-
If we
neglect the charge initially sampled on the top-plate, the output node will settle to
2refP
refN.
Instead, the sampled charge superimposes a voltage on the top node,
22
and the resulting output is
VrefN.e, -
1
following charge conservation analysis.
34
IN + Vref,N. This can be verified by the
Sample
QTOP=-(VN-VrefN)2NCo
STOP
2
VrefN
VrefN
20o
S1
SN-1
+
SRES
so
VVref
VIN
To SAR
Co
O
N
SIN
Ve
VVrefN
Figure 3-2: SAR sampling phase.
QTOP =
-(VIN
-
Vref,N)22NCON
(VOUT
-
Vre)NCo
fN)N1CO
+
(3.1)
VOUT
T
=
Vref,P + Vref,N
2
-VIN
(3.2)
-± Vref,N
From this, we can see that for VIN equal to the mid-scale voltage
VrefP+Vref,N
,VOUT
2
equals Vref,N, which is the comparator transition point. If the comparator resolves
to "1", VIN is greater than the input mid-scale; if it resolves to "0", VIN is less than
the input mid-scale. In the former case, the MSB capacitor bottom plate remains
at Vref,p during subsequent bit-cycling. In the ladder case, the MSB capacitor is
connected to Vref,N. The remaining bits are resolved in a similar manner, and the
digital output code corresponds to the successive comparator decisions.
3.2
Differential Successive Approximation ADC
The ADC discussed in Section 3.1 is not practical for medium or high resolution
conversion. Specifically, it suffers from a high sensitivity to power supply noise. For
instance, a 12 bit ADC, depending on Vref,p and Vref,N, will have an LSB voltage less
35
Bit Cycle
QTOp=-(VIN-VrefN)2NCo
STOP
20Co
Vref,N
2
To SAR
CO
S-
Vrefp
VIN-N SIN
Vrf,
Vref,N
Figure 3-3: SAR bit cycling of MSB.
than 1mV. Supply noise will be attenuated through the capacitor divider and appear
at the comparator input, degrading the resolvable signal. To mitigate this effect,
a fully differential architecture can be employed.
Figure 3-4 shows the resulting
structure.
Here, VCM is the common-mode voltage of the input signal. It ensures that equal
and opposite charge is stored on each of the capacitor arrays. This, in turn, guarantees
that the common-mode voltage of the DAC's output, during bit-cycling, does not
change from conversion-to-conversion, regardless of the input common-mode voltage.
ADC errors due to varying input common-mode are considered further in Section
4.2.2.
In addition to improved power supply noise rejection, this approach has several
other advantages. Firstly, the differential nature provides first-order cancellation of
linear voltage coefficients in the DAC capacitors [21].
Non-zero capacitor voltage
coefficients result in linearity errors, and as a result, the differential ADC improves
linearity. Second, the thermal noise limited dynamic range of the entire ADC is
doubled. This can be seen by considering that the input range has been extended
from (Vref,P
-
Vref,N) to
-(Vref,P
-
Vref,N).
As a result the LSB voltage doubles,
and the required minimum resolvable signal is larger. Note, however, if the ADC is
36
VIN+
Vref,N
2N-1C
+ _F
eVrefP
VrefN
VIN-
Figure 3-4: Fully Differential DAC during sampling.
quantization noise limited, instead of thermal noise limited, the differential structure
provides no improvement in dynamic range. Additionally, even in the thermal noise
limited case, the extension in dynamic range comes at the cost of an increase in power
consumption, since two capacitor arrays must be charged. The power increase in the
DAC is, however, offset somewhat by a power decrease in the thermal noise limited
comparator stages.
3.3
Analysis of Error Sources
Any deviation from the ideal ADC transfer characteristic represents errors in the
analog-to-digital conversion process. Figure 3-5 below enumerates static errors commonly observed in ADCs with respect to the ideal characteristics of a single-ended
converter. A differential converter may be considered by means of a straight forward
extension.
37
Any shift in the transfer curve is called offset error and results in a reduced
conversion range. For instance, in Figure 3-5b, even if the input signal is shifted, the
first
-q16
of the analog input range is not properly converted, saturating the digital
output at the lowest code. As shown in Figure 3-5c, equal deviations (from K/) in
the width of code transition voltages results in gain error. Finally, as shown in Figure
3-5d, unequal deviations in the width of code transition voltages results in linearity
errors.
Digital
Code
Digital
Code
111 -
111 -
110
110-
101
101-
100
100-
011
011 -
010
010-
y Ideal
Actual
-.
-
,v.
001
--doo
0001
/
(a)
... '.
Digital
Code
ref
-
Digital
Code
111 -
*Ideal
110101-
VI/Vref
%
(b)
Actual
111 -
%/4
Ideal
Actual
110-
-
-'
./
101-
100-
100-
011-
011-
010-
010-
001-
001-
000
000
ref
(c)
-
-j....
-y.
I
//
r-
'
%/
3/
1
VI/Vref
(d)
Figure 3-5: Errors in 3 bit ADC transfer characteristics: (a)Ideal case (b)Offset error
(c)Gain error (d)Linearity error [22].
38
In addition to the static errors considered in Figure 3-5, dynamic errors also influence the performance of ADCs. Non-linearities, for instance, may be dependant on
the frequency of the input signal. Additionally, thermal noise in the converter is most
clearly observed through dynamic analysis since static analysis typically applies averaging which attenuates zero-mean, random noise. Methods for precisely quantifying
and correcting ADC errors are described in [22]. Among these, linearity errors are
the most difficult to correct through post processing, and as a result, represent the
most serious non-idealities in an ADC. The remainder of this subsection will examine
the major sources of errors in a SAR ADC and how these manifest themselves with
respect to the static and dynamic characteristics of the converter.
3.3.1
Capacitor Mismatch
From the discussions in Section 3.1 it is clear that the DAC generates output voltages
by means of capacitive voltage division. It follows, then, that ratiometric matching,
and not absolute matching, of the capacitive elements is required. Since output values
of the capacitor divider define the transition voltages, capacitor mismatch results in
inconsistent deviations in the transition voltages, leading to linearity errors. This is
a primary source of nonlinearity in the SAR converter.
3.3.2
DAC Parasitics
During both sampling and bit-cycling the bottom-plates of all elements in the capacitor array are driven to either VIN, Vref,p, or Vref,N. The parasitics on the bottom
plates are also driven to the corresponding voltage without affecting the sampled
charge. Consequently, bottom-plate parasitic capacitance does not introduce errors.
The top-plate of the capacitor array is a high impedance node during bit cycling
and, as a result, the distribution of sampled charge is affected by associated parasitic capacitance. To understand this, consider the single-ended capacitor array of
Figure 3-6a. The first thing to note is that, during sampling, the top-plate, and
its parasitic capacitance, is charged to
Vref,N
39
which is precisely the voltage towards
which the DAC output converges during critical comparator decisions. This implies
that, during bit-cycling, when the capacitor array is switched so as to output VrefN,
the top-plate parasitic will hold exactly as much charge as it did during sampling.
The remaining charge on the top-plate, which corresponds to the sampled voltage,
will be appropriately distributed between the elements of the capacitor array. When
the capacitor array is switched so as to output anything other than Vref,N, the result can be analyzed through the Thevenin circuit equivalent shown in Figure 3-6b.
Here, the output voltage is attenuated through the capacitor divider composed of the
DAC capacitor array,
2 NC,
and the parasitic capacitance Cp. As a result, of this
attenuation, the comparator must be able to resolve smaller signals.
Vref,N
S
2CO
o
p
.---
VIN
(a)
Vref p
Z bi2'Co
Thevenin
N
Equivalent
2 N Cp
VDAC,actual
2
-0
N-1
VDAC,ideal
i--O
.'P
L,
Vref,N
(b)
Figure 3-6: Effect of capacitor array top-plate parasitics (a)During sampling
(b)During bit-cycling.
40
3.3.3
Reference Voltage Error
While parasitic capacitance on the top-plate causes attenuation of the DAC output
around the comparator trip point
(Vref,N),
staic reference voltage error on Vref,p
causes attenuation (or amplification) with respect to ground. Namely, the DAC output voltage, referenced to
Vef,N,
is attenuated (or amplified). The resulting equiv-
alent circuit is shown in Figure 3-7.
referenced to
Vef,N,
Here,
VDAC,ideal
is the DAC output voltage
rather than ground, and G represents the attenuation (or am-
plification) as a result of
Vef,p
errors. The overall effect is a systematic compression
(or expansion) of transition voltage widths leading to gain error in the ADC transfer
characteristic. Static errors on
Vref,N
have a similar effect of compressing (or expand-
ing) the DAC output voltage range, and also result in ADC gain error; in this case,
the comparator input common-mode voltage is also shifted.
GVDAC,ideadbN-1,
-.. ,
0
Vref,N +
Vref,N
>
Figure 3-7: Effect of errors in Vref,p.
From the argument above, it follows that non-static noise on the reference voltages
can be highly problematic in the ADC. It is essential, therefore that the reference be
properly de-coupled from other signals or power supplies.
3.3.4
Comparator Offset
Figure 3-1 illustrates how the DAC output voltage is offset by the analog input signal
before being resolved by the comparator. Comparator offset can be modeled as an
additional summing operation with a static error signal at the comparator input. This
can be combined with the ADC input signal, showing, explicitly, that comparator
offset has the effect of adding offset to the entire ADC.
41
3.3.5
Sampling Switch Non-Linearity
Since sample-and-hold (S/H) is the first operation and is applied directly to the input,
any non-linearities in the S/H circuit contribute to overall ADC linearity errors. In
SAR ADCs, sampling maybe a passive operation that occurs through MOS switches
onto the capacitor array, as shown previously in Figure 3-2 and Figure 3-4. The
capacitor array is typically quite linear. The sampling switches, however, are quite
non-linear having an effective resistance dependant on the input signal voltage. This
is not problematic at low frequencies, since the sampled voltage will track the input
voltage, provided sufficient settling time.
At high frequencies, however, the S/H
circuit can be viewed as the voltage divider shown in Figure 3-8, where the sampled
voltage is set by the non-linear MOS sampling resistance and the impedance of the
capacitor array.
R(VIN)
VS/H
VIN
ZArray
l/MWCArray
Figure 3-8: Equivalent sample-and-hold circuit.
Here, the sampled voltage, VS/H, and the input voltage, VIN, have the non-linear
relationship, described in Equation 3.3, where R is a function of VIN.
1
VS1H
=
VIN
1(3.3)
1
+ JWCArrayR
While the error in magnitude observed due to this non-linearity might be small, the
error in phase can be quite large, significantly contributing to distortion.
3.3.6
Comparator Thermal Noise
In medium and high resolution SAR converters, the comparator must resolve signals
of only tens or hundreds of micro-volts. Transient noise during the course of comparator settling, degrades the SNR of the ADC. Further, although SNR is effective
42
for characterizing noise power in the ADC, it does not fully elucidate the effect noise
has on the resulting output code. In a SAR ADC, the code histogram resulting from
noise can have a non-monotonic decay pattern from the mean code [23] as it depends
on the joint probabilities of how individual bits are resolved (this is considered further in Appendix A). As a result, the effect of noise on the resulting output code, in
addition to the dynamic range, should be considered.
3.4
Summary
All of the error sources mentioned in this chapter can lead to significant degradation
in ADC performance. Consequently, they are addressed in the implementation of
this design. For instance, although the reference voltage is provided from off-chip,
it is heavily de-coupled on-chip to minimize transient errors. Comparator offset is
cancelled using auto-zeroing and latch calibration. Input switches are bootstrapped
to reduce the effect of their non-linear behavior. Finally, thermal noise is limited to
an acceptable level in the comparator preamplifiers through gain, bandwidth, and
biasing considerations.
43
44
Chapter 4
Architecture Design and Theory
This chapter discusses the system architecture of the implemented ADC. A high-level
description of the converter is provided in Section 4.1 with the purpose of explaining
global features affecting the conversion process and its control mechanisms. Block
level architectures are considered in Section 4.2 along with analysis supporting the
applied optimizations.
Implementation details, pertaining to design tradeoffs and
circuit techniques, are presented in Chapter 5.
4.1
Global Architecture and Concepts
Figure 4-1 shows a block diagram of the final ADC. Most of the blocks were introduced
in Chapter 3. Here, however, the DAC has been separated into two sub-blocks: a
main-DAC and a sub-DAC. The precise effect of this structure will be considered in
Section 4.2.2. An additional block, the clock manager, is used to implement scalability
in sampling rate, as described in Section 4.1.2.
4.1.1
Conversion Plan
In the most straightforward case, a SAR conversion cycle consists of one phase of
input sampling, typically combined with offset calibration (auto-zeroing), followed by
one phase of bit-cycling for each bit that must be resolved. This implies that for a
45
Sub DAC
7
V,, Main DAC
VIN+
Vref N
VIN-*
Comparator
SAR
VreVref,N
Clock
Manager,
CLK
Figure 4-1: Block diagram of the final ADC.
12-bit converter, at least 13 clock cycles are required; for an 8-bit converter, at least
9 clock cycles are required. The conversion plans for the 12-bit and 8-bit modes of
this ADC are presented in Figure 4-2.
Here, the conversion plan includes several phases in addition to those described
above. Specifically, a phase has been added to purge the capacitor arrays; the sampling and auto-zeroing phases have been separated; and an extra half-clock cycle has
been devoted to resolving the MSB. Clock cycles have been allocated to resolving
the remaining bits in a standard manner. The purpose of the purge phase, as well
as the rationale behind separating offset calibration and sampling, is explained in
Section 4.2.2. Details pertaining to the auto-zeroing phase are provided in Section
4.2.1. Finally, the extra time spent resolving the MSB is justified in Section 4.1.4.
In any case, a 17 clock cycle conversion period (in the case of the 12 bit mode) im46
4.,2
17 clock cycles
Clockn---~-~I
llFL
2
d-
a, A 1jI
EBit-Cycle
--
L
(10:0)
(a)
12 clock cycles
Clock
2
aN
CU
0
Bit-Cycle (6:0)
E
U
CO
421
(b)
Figure 4-2: Final ADC conversion plan for (a)12-bit mode (b) 8-bit mode.
plies a clock frequency of 1.7MHz to achieve a conversion rate of 1OOkS/s. This ADC
will be designed to operate at a clock frequency of 2MHz, such that the maximum
conversion rate is slightly higher that 1OOkS/s.
4.1.2
Sample Rate Scaling
Section 1.1.3 examined the value of scaling the performance of the ADC to recover
power savings in response to dynamically varying energy and performance constraints.
Assuming a constant supply voltage, the power consumption of both digital circuits
and analog circuits is directly proportional to their operating speed.
In the case of digital circuits, this can be seen in Equation 4.1, which expressed
47
the power consumption for digital transitions (0 -+ 1).
Here, a is the switching
activity factor, CL is the load capacitance, VDD is the supply voltage, fcIk is the
clock frequency, and d is the duty cycle (i.e.
processing) [24].
ratio of time the circuit is actively
Often, d is combined with a and may be considered a specific
parameter associated with switching activity.
Pdi = aCLVDDfclkd
(4.1)
Additional forms of power consumption, namely direct-path power and leakage power,
are also present. However, these typically represent a smaller portion of the total
power consumption. In the case of analog circuits, we can consider, as an example,
a simple single stage amplifier. Here, the required gain, A, and bandwidth, f-dB,
are given by the following expressions, where GM is the amplifier's transconductance,
and Rut is the amplifier's output resistance.
A = GMRUt
1
f-3B =
1
27r Rout CL
(4.2)
(4.3)
For a simple differential pair implementation, the amplifier's GM coincides with the
transconductance of the input devices, gm, and can be expressed in terms of the bias
current, 'bias (note, this relationship is true in the weak-inversion regime [18] where
efficiency is highest).
gM = Ibiasq
nkT
Panaq
nkTVDD
Combining these results, the power consumption can be expressed as in Equation 4.5,
where its proportional dependence on signal frequency is shown.
2
7TnkTVDDCLAf-3dB
Pana =
q
(4.5)
.5
Fundamentally, this result suggests that a linear power relationship is achievable
with respect to processing frequency. With consideration to Equation 4.1, this rela48
tionship occurs explicitly in digital circuits through
fclk,
the clock frequency, and d,
the duty-cycle ratio. In analog circuits, however, some flexibility exists in how this
relationship can be leveraged. In a sampled system, which performs analog processing in the discrete-time domain, reduced signal frequency implies a reduced sampling
rate requirement. With reduced sampling rate, the settling time of the analog circuits
can be increased to allow lower power operation. This may be achieved, as suggested
by Equation 4.2 and Equation 4.4, by increasing Rt
and decreasing GM. Such an
approach, however, would require dynamic adjustment of bias currents, which can
be difficult to implement, particularly over a large range [7]. A more straightforward
strategy is to apply power-gating to the analog circuits, such that they process at
a constant rate, and then shut-off to enable scalability in performance and power
consumption.
One of the main advantages of the SAR architecture, for low-power implementations, is its limited number of constituent active components.
Specifically, the
comparator is the only active analog circuitry. The SAR (finite-state machine) is
a digital block, and the DAC is based on the passive charge redistribution process
(Section 3.1). Consequently, the SAR ADC architecture provides the opportunity for
very efficient power-gating; static bias currents in the comparator, as well as digital
clocking circuitry, can be shut off between conversions, minimizing power consumption to leakage levels. During this process, the only overhead is
CL VD
energy of
charging and discharging load capacitors.
The waveforms in Figure 4-3 show how power-gating is controlled in this design.
Here, CNVRT is the input control signal to initiate a conversion, DOUT is the 12bit digital output code, and SLEEP is an internal control signal used to shut-off
the clock and active circuits between conversions. Figure 4-3 shows the case where
the sampling rate has been scaled to half the maximum rate. Chapter 5 explains
how sleep modes are implemented at the circuit level, such that only leakage power
is consumed during the sleep phases.
49
CLK
CNVRT
DOUT
Data Valid
Data Valid
SLEEP
Sleep
Active Conversion
Sleep
Active Converion
Figure 4-3: Waveforms showing power-gating control
4.1.3
Resolution Modes
Along with sampling rate, Section 1.1.3 identified resolution as a performance dimension along which scalability can be implemented to achieve dynamic power savings.
The inherent relationship between power consumption and resolution can be derived
by considering analog and digital circuits separately.
Resolution is a measure of the loss in precision, due to noise, imposed by a processing block. Dynamic range is defined as the ratio of maximum signal power to minimum signal power when the SNR has degraded to unity. Note that the signal power,
at unity SNR, is equal to the accumulated power of all noise sources.
add quantization noise.
All ADCs
However, their ability to resolve a higher number of bits
is ultimately limited by intrinsic device noise. To characterize the power-resolution
relationship in analog circuits, the effect of thermal noise, on limiting dynamic range,
can, once again, be analyzed for a simple one stage amplifier. Equation 4.6 relates
dynamic range, DR,to the power of a full-swing sine wave,
2
V
2
^ m, and the noise power,
22
vno-
DR=
The value of v2 is given by -/,
V2
Amp
2vno
(4.6)
where y is the equivalent number of noise sources
in the amplifier and CL is the load capacitance.
Then, by applying Equation 4.2,
Equation 4.4, and Equation 4.3, we get the following expression.
DR ~~
VmpPanaq
47rn(kT) 2 AVDDf- 3dB
This results shows that power consumption in analog circuits is directly proportional
50
to dynamic range.
Extrapolating to ADCs, where dynamic range is exponentially
related to resolution (namely 2 N, where N is the number of bits), power consumption
can be expected to vary exponentially with the number of bits to be resolved.
This result, however, is not true in the case of digital circuits. The power consumption of digital circuits is simply linearly related to the number of bits.
This
can be seen, for example, in an adder circuit, where a 16-bit version requires twice
the number of full-adder cells as an 8-bit version (assuming the critical path is not
affected).
Since ADCs are, generally speaking, mixed signal systems, the resulting powerresolution relationship expected in a scalable ADC, lies in between that for digital and
analog circuits. A bias towards one or the other will depend on the exact distribution
of power consumption between digital and analog blocks. The situation is complicated, however, by the ability to implement the feature of scalability. Although, in
analog circuits, we expect exponential power savings with dynamically reduced resolution, in reality, this is limited by circuit practicalities, as described later in this
chapter.
In order to reconcile the difficulties associated with implementing power-resolution
scaling, in this design, two discrete resolution modes have been chosen: a 12-bit mode,
and an 8-bit mode. A feature of the SAR conversion algorithm, which resolves bits
successively, starting with the MSB, is that the conversion process can be stopped
at any point during bit-cycling, once the digital code has been determined to the desired resolution. Of course, this, alone, yields only linear power savings. In order to
scale resolution more efficiently, the analog blocks, namely the comparator and DAC,
should be retuned appropriately. Mechanisms to perform this adaptation in the comparator are described in Section 4.2.1. The difficulties associated with implementing
scalability in the DAC are presented in Section 4.2.2.
4.1.4
Self-Timed Bit Cycling
The most straight forward signaling to control bit-cycling in a SAR ADC is shown
in Figure 4-4. Here, the SAR finite state machine generates the appropriate digital
51
control for the DAC at the start of the clock cycle
(tek_
after the rising edge). During
the first half of the clock period, the DAC and comparator preamplifiers (if present)
settle to their correct values. Then, the comparator latch is triggered at the falling
/edge of the clock. Subsequently, the comparator decision is used by the SAR logic to
derive the next digital control for the DAC. In this scheme the preamplifier settling
time,
(plus the SAR clock-Q time,
tsettle,PAMP,
tck-q)
must be less than half the clock
cycle.
CLOCK
tck-q
SAR
DAC
PRE-AMP
\ seftle,PAMP
LATCH
T
+-tiatch
Figure 4-4: Waveforms showing standard bit-cycling signals.
Alternatively, a self-timed scheme was suggested in [25], where the DAC and comparator preamplifiers borrow time from the latch, to ease their settling requirements.
The signals associated with this scheme are shown in Figure 4-5. Here, the latch is
once again triggered by the falling clock edge. However, now, following the latch resolution time,
tlatch,
the SAR immediately derives the next digital control word for the
DAC. Subsequently, the DAC and preamplifiers start settling to their respective values while the clock is still low. As a result, the preamplifier settling time,
can be longer by
t
+
tck-q - tiatch - togic,
where
tdlk
tsettle,PAMP,
is the clock period. Specifically,
if the preamplifiers dominate the bit-cycling time (i.e. the logic and latch delays are
small), their settling time can be nearly doubled, reducing their power consumption
by a factor of two.
52
CLOCK
-tiogic
SAR
tsettle,DAC
DAC
PR E-AMP
tsettePAMP
LATCH
-+ +tlatch
Figure 4-5: Waveforms showing self-timed bit-cycling signals.
Since the successive approximation algorithm works by dividing the conversion
range in half during each phase of bit-cycling, the possible input swing to the comparator decreases by a factor of two each time. During the first few MSBs, however,
large voltage swings are possible.
The worst case sequence for the comparator to
resolve involves a large input during one cycle, followed by a very small signal, of
the opposite sign, during the next cycle. This condition is known as the overdrive
case and is treated quantitatively in Section 5.2.1.
The latch resolution time will,
generally speaking, be dependant on the magnitude of the input signal. During overdrive conditions,
tiatch
will be very short during the first phase due to the large input.
Subsequently, the preamplifiers will benefit from a lot of extra settling time, which
they will need, as the weak input they are subsequently driven with limits the recovery time. In this manner, self-timed bit-cycling is particularly suitable for the SAR
algorithm.
The resolution process associated with each bit, except the MSB, has the opportunity to borrow time from the previous latching phase. Although, the MSB decision
is not subject to overdrive, a condition nearly as limiting can be imposed by the
preceding sampling phase. The corresponding details are described in Section 5.1.1.
To ensure that the ADC timing is not limited by this effect, an extra half cycle has
53
been devoted to the MSB decision.
4.2
Block Architecture
This section describes block level optimizations that have been implemented in this
ADC in order to improve efficiency and facilitate scalability. Architectural concepts
are presented here, and implementation details are provided in Chapter 5.
4.2.1
Comparator Architecture
The comparator is responsible for resolving the sign of its input and generating a
full-swing digital output based on its decision. An ideal comparator will be able to
generate a decision despite an arbitrarily small input. In this sense, comparators must
have nearly infinite gain. Fortunately, their non-linear and open-loop nature implies
that cascading techniques and positive feedback can be used to increase efficiency
without suffering instability.
The next few subsections present optimizations and design approaches employed
in the comparator. Specifically, trade-offs associated with linear and regenerative
amplifier design, amplifier cascade optimization, auto-zeroing coordination, and performance scaling will be considered.
Gain Optimization
As mentioned, the open-loop nature of comparators presents the opportunity for employing cascaded amplifiers and positive feedback in order to achieve very high gain.
The advantage of cascaded amplifiers is based, fundamentally, on the principle that
the total gain is the product of the individual stages, while the time-constant is the
sum of the individual stages. As a result, the constant gain-bandwidth constraint associated with a single stage amplifier is overcome. Positive feedback provides an even
more efficient means of achieving high gain, since the signal continuously regenerates
itself. This leads to a time-varying behavior, where the gain increases exponentially
with respect to time.
54
To compare the efficiency of various amplification strategies, transconductor based
gain blocks may be considered. For a given tranconductance and load capacitance,
transconductance amplifiers, which have infinite output impedance, achieve a required
output swing faster than voltage amplifiers, which have finite output impedance. This
is shown in Figure 4-6, where the output voltage, normalized to the product of the
), is plotted with respect to time, normalized to the
input voltage and Gm (i.e.
GVou
load capacitance (i.e.
Here, the transconductor acts as an integrator, exhibiting
i-).
a voltage ramp at the output. The voltage amplifiers, having R"'t equal to 30 and 15
respectively, are subject to RC settling at their outputs. Assuming an output swing
of 10 is required, the transconductor provides the least delay of the three options.
Since, in the most efficient operating regime (i.e. weak inversion), amplifier GM is
proportional to current, this plot shows that high-gain stages achieve a better powerdelay product than low-gain stages.
Despite improved efficiency, high-gain stages
suffer from several practical effects. These are considered later in this section.
An analytical comparison of multi-stage and regenerative amplification was pursued in [26] where cascaded transconductors were assumed. Figure 4-7 illustrates the
structures compared. In the case of the cascaded linear stages of Figure 4-7a, it was
shown that the delay,
tdly,
to achieve a total gain of Atot is given by Equation 4.8,
where GM is the transconductance of each stage, CL is the load capacitance of each
stage, and N is the total number of stages.
0
tdly,lin =
m(At tNL!)
GM
(4.8)
Then, multiplying by NGM gives an expression for the total power-delay product
of the cascade. The delay associated with a regenerative amplifier was shown to be
given by Equation 4.9.
tdly,reg
=
CL
Gm
lrt(Atot)
(4.9)
Similarly, multiplying by GM (since only one transconductor is required) expresses
the power-delay product of the regenerative stage. The results corresponding to the
power-delay for a regenerative amplifier, as well as a 5-stage and 3-stage cascade, are
55
Output Voltage VS Time
20
out
-
18
.R
16
4
=15
/
14
0~10
0
6
4
2
0
I
5
10
15
20
25
30
35
t/CL
Figure 4-6: Delay for amplifiers with various output resistances.
plotted in Figure 4-8. Here, it is shown that regenerative stages possess a superior
power-delay figure of merit compared with linear stages.
The difficulty with regenerative amplifiers is that they typically suffer from large
input-referred offset. Typically offsets on the order of 50-100mV can be expected
[27]. Accordingly, a common approach, is to use, less-efficient, offset-cancelled linear
stages to achieve a signal swing larger than the offset floor of the regenerative latch,
and then use the latch to generate full-rail, digital outputs.
In this ADC, however, analog calibration will be applied to the regenerative latch
to minimize its offset, thereby easing the gain requirements of the linear stages. Latch
offset calibration has been explored previously [26][28], however, structures suitable
for multi-step converters, such as SAR ADCs, have not been demonstrated.
The
primary challenge associated with multi-step converters is that the opportunity to
calibrate does not occur prior to every decision. Calibration involves storing offset
56
cL
CLCL!
LL
Gm
fGm
L-
ICL
CL
Gm
L
(a)
Gm
(b)
Figure 4-7: Comparator gain structures (a)Linear amplifier cascade (b)Regenerative
amplifier.
voltages on capacitors. However, latches typically need to be reset following every
decision.
During this process, the stored offsets are lost and must be regenerated
by means of calibration. Since calibration requires application of a reference signal
at the input, it is not a viable option during bit-cycling.
Specifically, in a low-
power, low-voltage design, the reference signal is difficult to generate, and difficult to
apply, as analog switches, having a degraded gate-overdrive, should be avoided in the
signal path. The circuit implementing latch calibration suitable for this SAR ADC is
presented in Section 5.2.2.
57
Power-Delay VS Total Gain
120
Rgnrtv
5-stage
-''' 3-stage
-
-
100
-
80
-
-.
0
60
E
0Y)
-lop
-5
40
-
- .. .
20
-- -'--
-
-
-
-
-
-***
f'L
100
10
102
103
104
Figure 4-8: Power-delay (normalized to CL) versus total gain for linear and regenerative amplifiers.
Preamplifier Chain Optimization
Although regenerative amplifiers are most efficient from a power-delay point of view,
achieving complete offset cancellation is difficult. Several techniques exist, however,
to fully correct offsets in linear stages. Consequently, the common approach, of using
linear stages preceding the regenerative stage, has been employed in this design. As
suggested above, linear stages may be cascaded to improve their efficiency.
Although it was shown that a desired output swing could be achieved fastest with
high-gain or transconductance amplifiers, these require input offset cancellation techniques for auto-zeroing. As mentioned later, implementing this type offset cancellation effectively is difficult. Low-gain amplifiers do not suffer from the same effect, and
consequently are used in this design. Specifically, a stage-gain of 3-4 is most practical
to implement. Roughly speaking, amplifying 12-bit LSB voltages (58
100p V) to levels
reasonable for calibrated latch offsets (~
5mV), requires a cascaded gain between 30
and 60. This implies that three stages of preamplifiers should be used.
Auto-Zeroing Optimization
To fully correct for static (and low-frequency) errors in linear preamplifiers, techniques
such as auto-zeroing and chopper-stabilization [29] may be employed. Chopper stabilization relies on modulating the input signal to a higher frequency, amplifying it
in a low-noise frequency band, and then modulating it back to baseband.
In low
power implementations [30], modulation, at the input and output, is performed using
passive, commutating switches. In the case of a SAR ADC, where the comparator
is driven by a charge redistribution DAC, injection errors imposed by such switches
on the critical nodes is prohibitive. Alternatively, auto-zeroing relies on sampling the
amplifier offset, and noise, and subtracting this from subsequent outputs.
Three common approaches to auto-zeroing are input offset storage (IOS), output
offset storage (OOS), and auxiliary offset compensation [29]. Both IOS and auxiliary
offset compensation involve sensing and storing the input referred offset, by means of
feedback. For these techniques to be effective, high gain amplifiers are required, as the
offset is attenuated by the factor of 1+Ao, where A 0 is the gain of the stage. Typically,
the required gain for sufficient offset compensation is only achieved by cascoding or
gain boosting techniques.
Neither of these is amenable to low-voltage, low-power
designs. Further, in IOS, charge injection errors, from auto-zeroing switches, appear
at the amplifier input, and, as a result, get amplified by A 0 when reflected to the
output.
Output offset storage, however, does not require high gain amplifiers to achieve
nearly perfect offset compensation and is not as sensitive to charge injection errors.
Consequently, multi-stage, output offset compensation is employed in this ADC. The
resulting structure is shown in Figure 4-9.
Here, the charge on the auto-zeroing
coupling capacitors is initially purged. This occurs at the start of the conversion
as mentioned in Section 4.1.1. Then, the DAC generates a reference signal of zero
differential amplitude (this is discussed in Section 4.2.2), and, simultaneously, the
59
three auto-zeroing switches are closed. The output-referred offset of each stage is
stored on the auto-zeroing capacitors for 11 clock cycles. Then, the first auto-zeroing
switch is opened, and the second stage is given another half clock cycle to cancel the
ensuing charge injection error. This procedure is repeated in the next stage, such
that the entire cascade is subject only to the charge injection error of switch AZ3,
which is small when reflected back to the input [22].
PRG
>
PRG
F
I
AZ3
AZ2
AZ
PRG
PRG
Clock
PRG
L.
PRG
.J
PRG
AZ1
AZ2
AZ3
Figure 4-9: Auto-zeroed multi-stage preamplifiers.
Typically, auto-zeroing is performed during sampling. However, in this design,
the two operations are separated (as explained in Section 4.1.1 and rationalized in
Section 4.2.2). Consequently, the auto-zeroing time is not constrained by the settling requirements of the sample-and-hold and can be optimized. The optimal time,
determined to be 1- clock cycles in this design, can be estimated by considering
the relative thermal noise contributions during auto-zeroing and bit-cycling. Figure
4-10 shows the networks relevant to noise analysis during the two phases, where it
has been assumed that the load imposed by the subsequent amplifier stage is small.
Here, the total capacitance seen during each phase should be optimized for minimum
overall power-delay in the amplifier. Specifically, since the amplifier must settle only
60
once during auto-zeroing, but, once for every bit during bit-cycling, it is beneficial to
decrease the noise contribution during auto-zeroing at the cost of increased settling
time.
CL
CLI
AZ
AZ
(b)
(a)
Figure 4-10: Amplifier network (a)During auto-zeroing (b)During bit-cycling.
During bit-cycling, comparator decisions are subject to the noise sampled during
auto-zeroing (on the CAZ capacitors), as well as the time-varying noise of the amplifier,
which is always present. If the amplifier implementation is set (i.e. its gm, Rout, and
equivalent number of noise sources does not change between auto-zeroing and bitcycling), the total noise variance,
Vo,toit,
is given by Equation 4.10, where CL is the
load capacitance during bit-cycling, CAZ,tot is the total load capacitance during autozeroing (CAZ + CL), and a is an implementation-dependant constant.
a
2
ono,tot =
CL
_+
a
CAZ,tot
(4.10)
Normalizing this expression, such that the desired noise variance is equal to a, allows
CL to be expressed in terms of CAz,tot.
CL
=
CAZ,tot
CAz,tot -
(4.11)
1
The overall power-delay of the amplifier can be expressed as the sum of the GM-r
products over the entire conversion.
For a 12-bit ADC, this is given by Equation
4.12, where 12 clock cycles are required for bit-cycling, and the number of clock
61
cycles for auto-zeroing, K, must be determined for minimum power-delay. Note, it
is assumed that neither GM, the amplifier transconductance, nor Rut, the output
impedance, change during the conversion.
K+12
GMTi = KGMRoutCAZ,tot + 12GMRoutCL
(4.12)
In the case that equally complete settling is desired during auto-zeroing and bitcycling, the ratio of CL to CAZ,tot is given by Equation 4.13, where the settling time
during bit-cycling is set to 1 clock cycle.
1
K
-
Tbit-cycle
RoutCL
CL
Tazero
RoutCAz,tot
CAz,tot
(4.13)
Now, using Equation 4.11 and Equation 4.13, CL and CAZ,tot can be expressed as
follows.
K±+1
CL = K
K
(4.14)
CAz,tot = K + 1
(4.15)
Finally, normalizing the expression for power-delay (Equation 4.12) by GMRout gives
Equation 4.16.
E K+12 T -
K(K + 1) +
R,,t
12
K+ I
K
(4.16)
This function is plotted in Figure 4-11, where it is shown that minimum power-delay
occurs for K ~~1.6. Based on this result 11 clock cycles have been used for autozeroing the amplifiers, and the load capacitances have been set appropriately. Recall,
however, to improve the cancellation of charge injection errors, an additional clock
cycle is used so that the auto-zeroing of each stage is extended with respect to the
preceding stage.
Resolution and Sample Rate Scaling
As described in Section 4.1.2, linear power savings, with respect to reduced sampling
rate, is straight forward to achieve.
In this design, sample rate scaling has been
62
Power-Delay VS Auto-Zero Clock Cycles
28
27.527p-426.5
<
26
p 25.5_ 2524.52423.5
1
1.5
2
2.5
Auto-Zero Clock Cycles
3
Figure 4-11: Normalized total power-delay of auto-zeroed amplifier.
implemented by power gating the preamplifiers and latch. This is controlled by the
SLEEP signal, shown previously in Figure 4-3.
Scaling the ADC's resolution means less overall gain is required, as the LSB voltage
in 8 bit mode is 16 times larger than that in 12 bit mode. While the regenerative
amplifier does not provide linear gain, and is therefore unaffected by this result, the
preamplifiers can benefit from the reduced requirement. However, if the same threestage cascade is used, the power will only be reduced by a factor of 163. As mentioned
in Section 5.2.1, the original preamplifier cascade is limited by the thermal noise
performance requirement of the 12 bit converter.
However, the reduced resolution
greatly relaxes the capacitive load requirement of the first stage. Specifically, if the
gain of each preamplifier in the three stage cascade is 4, the first two stages, providing
a combined gain of 16, are not required. The power-delay product of the last stage,
which is not thermal noise limited, coincides precisely with that achievable for an 8
bit converter.
The Gm sets the power, and the Rt
capacitance, which depends on parasitics, is fixed).
63
sets the delay (since the load
If the power consumption and speed of the ADC is dominated by the preamplifier performance, adjusting these parameters proportionally would only change the
maximum speed of the converter, and not its energy per conversion.
This can be
seen in Figure 4-12, where the effect of doubling GM, and accordingly halving R0 ,, is
shown. Here, the power consumption doubles during the active conversion. However,
the settling time, and therefore the clock period, is reduced by half. The net result
is that the conversion completes in half the time, and the preamplifier shuts-off for
the remainder of the sampling period. As a result, the average power consumed is
unchanged.
Clock
tsette=NT=NRoUTCL
PAMP
2
Clock
L_
I
Cq4
o
t'see=NT'=NR'OUTCL
=NROUTCL/2
PAMP
Figure 4-12: Effect of changing Gm at constant amplifier power-delay.
Of course, in reality, the relative power consumption depends on the portion of the
total clock period consumed by preamplifier settling, and the portion of total power
consumed in the preamplifiers. Nonetheless, to ease the implementation of the 8 bit
mode, a single stage, identical to the last stage of the 12 bit cascade, can be used,
and the clock rate can be set appropriately. As mentioned before, analog switches
should not be used in the signal path as they are limited by low gate-overdrive in this
low-voltage design. So, to avoid multiplexing the input signal of the third stage, an
entirely separate preamplifier path is used. The final comparator structure is shown
in Figure 4-13 below. The power gating switches are used to enforce sample-rate
scaling, as well as resolution scaling, by shutting-off the inactive preamplifier path.
64
NSLP12
NSLP12
NSLP12
NSLP12
PRRP
PRG
PRG
Ao=GmIRoUTI
AZ3
AZ2
AZ1
Ao=GM2RouT2
PRG
Ao=Gm3RouT3
NSLP8B
NSLP8B
PR
7AZ3
PR
Ao=Gm3RouT3
Figure 4-13: Architecture of final comparator.
4.2.2
DAC Architecture
The DAC is responsible for generating analog outputs at precisely the code transition voltages of the ADC. Figure 4-14 shows its complete architecture.
Positive
and negative outputs are generated using two sets of capacitor arrays that are coupled, through the top-plate sampling switch, only during sampling and auto-zeroing.
During bit-cycling, the charge redistribution process is controlled by switches, in the
positive and negative switch matrices, which drive the bottom-plates of the capacitors
to the appropriate voltages. As shown, this ADC employs a fully differential DAC.
Although the increased robustness is not crucial in 8 bit mode, and, as result, the
extra overhead may be avoided, such configurability is not easily achieved in practice.
In particular, switching from a differential DAC to a single-ended one would require
shorting the top-plate of the positive array to Vef,p. However, now, the DAC outputs
will swing around Vre,,p, which may be as high as VDD. Consequently, charge loss
65
from the critical node can occur through the top-plate sampling switch. Although this
can be avoided, through proper bootstrapping, it results in a less desirable structure,
which could degrade the ADC precision in 12 bit mode.
Vref.P
Vref.N
VIN+
AZERO AZEROSwitch
Matrix
SAMPLE
(Positive)
BCYCL(11:0)--/-+
12
-6
E2 x6
0_T
I
VOUT-
Top-plate Sampling switch
VOUT+
It
CC.
x6
Ma nDAC
-
1
-
-
Su DAC
6
12
BCYCL(11:0)--\-c
SAMPLE
AZERO
D1
TI'
SAMPLE 6
A ZERO
C,
7is
x6
000
T
T
AC
-
ManDAC
Swtc
,
Matrix
itive)
VINV
Vref,
Vref,N
Figure 4-14: Architecture of final DAC.
In a charge redistribution DAC, the ability to generate transition voltages accurately depends on the matching between constituent capacitive elements. In addition
66
to proper matching, a number of other considerations are critical during DAC design.
For instance, in Section 1.1.4, the ability to convert both single-ended and differential
signals was an identified requirement. Since, internally, this ADC uses a differential
architecture, proper support of single-ended inputs can be interpreted as a commonmode signal rejection requirement. The associated high-level implementation details
are presented in following subsections.
Sub-DAC
One of the limitations associated with medium and high resolution capacitive DACs
is the binary relationship between elements. Specifically, in the case of a 12-bit converter, the largest capacitor is 2048 times bigger than the smallest capacitor. This
binary relationship can be broken by using a sub-DAC [31][32]. Two structures, implementing M + N bit DACs, are shown in Figure 4-15. The basic principle here
involves using the main-DAC to precisely generate transition voltages corresponding
to the N most significant bits of the digital input code, and then interpolating between these using the M bit sub-DAC. The structure in Figure 4-15a uses capacitive
charge redistribution to implement the interpolation, while that in Figure 4-15b uses
a resistive string. Although the resistive implementation is inherently monotonic, it
draws static current, and therefore has not been used in this low-power design.
A major drawback of the structure shown in Figure 4-15a is that it requires an
active, unity-gain buffer to drive the bottom plate of a main-DAC unit-capacitor. An
alternative, fully passive implementation is shown in Figure 4-16 [33]. To analyze this
structure, notice that the total capacitance of the main-DAC is ( 2 N
-
1)CO. Also, the
capacitance looking into the series combination of the coupling capacitor, Cc, and
the sub-DAC, is equal to Co. However, unlike before, the bottom plate of the subDAC is involved in sampling the input. As a result, the main-DAC generates the MSB
transition voltages by treating the series combination of the coupling capacitor and the
sub-DAC as a single unit capacitor. To see how sub-DAC interpolation is performed,
consider the Thevenin equivalent circuit shown in Figure 4-17. Here, voltages derived
by the unloaded sub-DAC effect the output through the same capacitive divider
67
2N-ICO
C
"'0
C
2
4
2N "0
0
VIN
V~f N
Vref N
- -Co
CO
Vref p
VIN
2 C0
Co
CO 0
Co-
Vref p
Vf
Vf N
N
(a)
(b)
Figure 4-15: Typical main-DAC/sub-DAC implementations.
(with ratio
1)
as the previous implementations, thus
2 M+N
transition voltages are
generated.
Vref,N-->
C
--
M
Vref,P
VIN
VrefN
2lm1Co
.- .
2Co
Co
Co
V/N
Vref,N
Figure 4-16: Fully passive main-DAC and sub-DAC.
Co essentially sets the transmission gain from the sub-DAC to the main-DAC such
that proper interpolation is performed.
Unlike the main-DAC, however, parasitic
68
Vref p
N-1
i
(2N
C
-
Thevenin
M-1
I
,
Z b2'C
1WI
~A
1
VrefN
Cc
qi-i'Co Equivalent
C
bi2=Co
)CO N-I
C0
Vref,P
.
2v
c
(2"-)CO
Co - Zqi2
I
Vref,N
VrefN
2mCo
+
VrefN
Figure 4-17: Thevenin equivalent circuit for analyzing passive sub-DAC.
capacitance on the top-plate of the sub-DAC causes linearity errors. Details of how
these errors originate, and the technique used to manage them, is described in Section
5.1.
Common-Mode Rejection
Device mismatch in comparator preamplifiers leads to unbalanced currents in the two
branches of the differential pair. Consequently, the gm's of the input devices are not
equal. Then, due to the finite output resistance of the tail current source, commonmode input signals can lead to differential output voltages.
Low-voltage designs,
such as this one, are particularly susceptible to this effect since the reduced headroom
leaves little margin for ensuring the tail device remains in deep saturation. Figure 4-18
demonstrates this in the case of 3o- mismatch applied to the preamplifiers discussed
in Section 5.2.1. Here, the voltage at which the amplifier is auto-zeroed is varied,
while the common-mode voltage, during active operation (i.e. bit-cycling), is fixed
at 500mV. Although, perfect offset compensation is assumed, as shown, differentialmode offsets in the millivolts are observed even if the auto-zeroing voltage deviates by
only 1OOmV. To avoid this, it is critical that the the preamplifiers be auto-zeroed with
the appropriate reference signal. Specifically, the reference signal should be equal to
the common-mode voltage seen during bit-cycling. Additionally, the DAC's output
common-mode voltage should be well controlled to remain within the range amenable
to the preamplifiers.
69
Input Referred Offset VS Auto-Zeroing Common-Mode
5
E
co
.
4 - ....0..
1.
... . .
.
1...............
0.3
0.35
-
. . -..
...
0.4
0.45
0.5
0.55
0.6
0.65
Auto-zeroing Common-Mode Voltage (V)
0.7
Figure 4-18: Differential-mode offset due to varying auto-zeroing voltage.
As mentioned, proper conversion of single-ended inputs requires the ADC to have
good common-mode rejection.
By ensuring that the differential capacitor arrays
sample equal and opposite charge, the comparator will not be subject to the varying
common-mode of the input [21].
Additionally, the DAC outputs will be centered
around vref,P+vef,N , which, by design, is desirable for the comparator preamplifiers.
This can be seen in Figure 4-19, where the charge sampled on the top-plate is independent of the common-mode voltage, VCM. The only difference between this sampling
network and that in Figure 3-4, is that no bias is actively applied to the top-plates
of the arrays. If no charge is initially present on the capacitors, and the arrays are
well matched, the top-plates will passively settle to the input common-mode voltage.
One advantage of the purge phase, at the start of the conversion (Section 4.1.1), is
that it eliminates the need for active VCM generation.
Typically, auto-zeroing is performed during the sampling phase, using the topplate voltage as the reference. However, as shown above, during sampling, the topplate tracks the varying input common-mode voltage.
70
Further, the outputs of the
+
1
N-
C
C
.
NCoV 1N
+
2
+
VCM
VIN
Q = 2NCoVN12
C
Figure 4-19: Common-mode independent charge sampling.
DAC during bit-cycling will not be centered around this voltage. Consequently, the
top-plate voltage during sampling is not an appropriate auto-zeroing reference. This
problem was solved in [25] by multiplexing a separately generated reference to the
preamplifier inputs. In addition to imposing charge injection errors, this approach
is not desirable in this low-voltage design, because it requires analog switches in the
signal path. As a result, a separate phase has been devoted to auto-zeroing so that
the capacitor arrays can generate an appropriate reference passively.
In order to do this, the capacitor arrays are initially purged to remove any residual
charge.
Then, they are switched in a manner similar to MSB bit-cycling, which
generates a transition voltage at mid-scale. To guarantee that the preamplifier inputs
are zeroed, the top-plate sampling switch remains closed during this process. Note,
this switch may experience low-overdrive, so it is bootstrapped, as described in Section
5.1. The resulting structure is shown in Figure 4-20.
Vref P
Vref P
2-1C'
2N-1Co
(LSB Cap's)
I
(LSB Cap'si
2Co
Vref N
Vref N
Figure 4-20: Passive auto-zero reference voltage generation using capacitor arrays.
71
Resolution and Sample Rate Scaling
Since the DAC is fully passive, no special support is required to implement scalability
in sampling rate. The array will only consume power when switched by a new digital
input code.
Ideally, scaling the ADC's resolution from 12 bits to 8 bits would allow removal
of the 2 MSB capacitors in the main-DAC and the sub-DAC such that they don't
participate in sampling or bit cycling. In practice, this is quite difficult to do. One
option would be to disconnect the unused capacitors from the top-plate so that they
are completely decoupled from the active array. This requires analog switches between critical nodes, and is, therefore, not straight forward. The use of bootstrapped
switches, to resolve this problem, is considered in Section 7.2. Another option would
be to disconnect the bottom plates of the MSB capacitors so that they do not impose
any charge loading on the active arrays. Despite disconnecting their bottom-plates,
however, the MSB capacitors continue to load the remaining arrays, as bottom-plate
parasitic capacitances cause coupling to ground.
Bottom plate parasitics are pro-
portional the size of the active capacitance, and consequently, in the case of MSB
capacitors, are quite large.
Due to these practical limitations, no special technique has been used to facilitate
power scaling in the DAC with respect to reduced resolution. In 8-bit mode, the last
4 capacitors in the sub-DAC are simply not bit-cycled.
4.2.3
SAR Architecture
The SAR state machine is the digital block responsible for controlling the conversion
process. Due to the self timed nature of this design, as well as its use of clock gating
during sleep modes, asynchronous techniques are used extensively. During bit-cycling,
successive resolution-of bits is triggered by completed comparator decisions. There is
the possibility, however, that the latch does not resolve, remaining in a metastable
state indefinitely. This could stall the entire bit-cycling process if it is not properly
detected. Section 5.3 describes how latch metastability is sensed, and the manner in
72
which the SAR state machine recovers from this condition.
4.3
Summary
A number of optimizations are applied to the global architecture of the ADC, as
well as to specific blocks, in order to enable a low-power, scaleable design. Samplerate scaling is achieved through clock-gating, in digital circuits, and power-gating in
analog circuits. Resolution scaling is achieved by activating a comparator path that
provides the appropriate gain, bandwidth, and noise characteristics for the required
precision. The efficiency of the bit-cycling process is improved by using a self-timed
scheme that relaxes the settling time requirements of the DAC and preamplifiers.
At the block level, a low-offset regenerative latch improves comparator performance
by reducing the gain requirements of the less efficient linear amplifiers. Further, the
common-mode rejection of the ADC is enhanced through proper sampling, as well as
de-coupling the sampling and auto-zeroing phases. This allows an appropriate autozeroing reference to be generated passively using the charge redistribution DAC while
avoiding analog switches in the signal path. Finally, since auto-zeroing is de-coupled
from sampling, it has been optimized with consideration to the preamplifier noise
contributions during the conversion phases.
73
Chapter 5
Circuit Design
This chapter describes the circuit-level implementation of the ADC blocks. To achieve
low-power operation the entire ADC has been designed to operate from a
IV
VDD.
Both the digital state machine and charge redistribution DAC benefit from the reduced supply due to their quadratic power dependence on VDD. Analog blocks, however, only benefit in the case of non-noise limited stages. To maximize the noiselimited SNR, Vref,p has been designed to be as high as VDD, though it can be reduced
slightly to meet the requirements of different applications. Similarly, VrefN is intended
to be as low as OV (ground). These values allow a differential input signal swing of
iV, and a single-ended input signal swing of IV. Further, in the differential case,
it is assumed that the nominal common-mode voltage of the input is 500mV. Subsequent sections use these parameters to rationalize, and develop, the implemented
circuit strategies.
5.1
DAC Circuit Design
Architectural issues pertaining to the DAC were discussed in Chapter 4. Here, implementation details will be presented through consideration of the two main substructures: the first is the switch network, consisting of the switch matrices, as well as the
sampling and purging switches; the second is the capacitor arrays of the differential
main-DACs and sub-DACs.
75
5.1.1
Switch Network
The DAC switch matrices consist of sets of switches, connected to the bottom plates
of each capacitor.
These switches control the charge redistribution and sampling
processes. Figure 5-1 shows their actual implementation. The PRG, AZERO, and
SMPL (SMPL) signals enforce the corresponding phases of the conversion cycle.
The Cx (Cx) signals control successive bit-cycling for the 12 bits (or 8 bits), and
the BCYCLEN (BCYCLEN) signals are qualifiers to globally enable bit-cycling.
Their full significance is described later in this section.
~AIN+
V22 V
()
BTMPLT (1-0)+
BTMPLT_11+
Vre, N
Vref,N
(a)
(b)
BTMPLT_11-
BTMPL T(1-0)-
AIN-
~e
0
(1
T
0
Vr
60
C/
VrefP~ Vref N
0
Vref N
60M
'r-
Vr,P
AIN_
r
Vref,P
Vref N
(d)
Figure 5-1: Implementation of switch sets in switch matrices (a)MSB switch set for
positive array (b)Bits 10-0 switch set for positive array (c)MSB switch set for negative
array (d)Bits 10-0 switch set for negative array.
The switch sets associated with the positive and negative arrays have inverted
76
functionality during the bit-cycling phase (i.e.
the bottom-plate
Vref,N
and
Vref,P
connections are reversed), as shown. Further, during auto-zeroing, the capacitor arrays are switched in a manner similar to MSB bit-cycling, where the largest capacitor
in the positive (negative) array is connected to
capacitors are connected to
Vref,N (Vref,P).
Vref,P (Vref,N),
and the remaining
As a result, the switch sets associated
with the MSB capacitors are slightly different than those for the other capacitors.
The purge phase is shown in Figure 5-2a. Here, the bottom-plates of all capacitors are driven to
Vref,N
(which is nominally ground), and the purging switches are
closed across the top and bottom plates. Following this, during the auto-zeroing and
sampling phases, the top-plate sampling switch shorts the top-plates of the positive
and negative arrays, equalizing any residual charge injection mismatch from the purging switches. The sampling phase is shown in Figure 5-2b. Physically, the top-plate
switch is implemented as a single NMOS device. Both during auto-zeroing and sampling, it can be subject to low gate-overdrive, as its source and drain are at a voltage
near mid-rail. As a result, its gate is bootstrapped using the charge-pump described
in Section 5.5. The input switch, which is implemented as the CMOS transmission
gate shown in Figure 5-1, can also be subject to low overdrive for input voltages near
mid-rail. Consequently, the NMOS is bootstrapped in a similar manner.
Input
switch
VIN.
Vrf N
VrefN
VrefN
(IV to 0%)
Purging
switch
Top-plate
switch
0.5V
Top-plate
switch
Purging
switch
VrefN
Vref,N
VreftN
Input
Switch
VIN-
(OV to IV)
(b)
(a)
Figure 5-2: DAC network (a)During purging (b)During sampling.
Proper control of the top-plate sampling switch is critical to the precision of the
sample-and-hold operation. If correct timing is not ensured, excessive injection er-
77
rors, and even loss of sampled charge can occur. Specifically, following the sampling
phase, the top-plate sampling switch must turn off before the input switches turn off,
and before the VrefP and
Vref,N
switches turn on to bit-cycle the MSB. Since these
operations all occur, nominally, during the same phase, special circuitry is required
to enforce their sequence.
When it turns off, the top-plate sampling switch imposes charge injection. This
directly affects the sampled value and introduces error if there is any mismatch between the charge injected on the positive and negative arrays. The precise proportion
with which channel charge leaves the source and drain depends on the interaction
between the device's capacitances with the load impedances on either side. To minimize residual mismatch, the impedance on either side of the sampling switch should
be well matched.
If the bottom-plate input switches turn off before the top-plate
sampling switch, the capacitor arrays appear as a large impedance in parallel with
main-DAC's top-plate parasitic capacitance.
As a result, injection charge from the
top-plate sampling switch will depend on the, relatively small, and poorly controlled
parasitic capacitance, as shown in Figure 5-3.
By ensuring that the bottom-plate
input switches turn off after the top-plate sampling switch, the injected charge can
be directed to the large, well-matched capacitor arrays. Consequently, the SMPL
and SMPL signals driving the input switches are delayed using a series of weak inverters. The matching of the loads is further improved through input switch sizing
as discussed later.
No current
path
No current
path
TCP
CPT
Figure 5-3: Distribution of injection error determined by poorly matched top-plate
parasitic capacitances.
At the start of bit cycling, the charge redistribution process begins when the
78
bottom plates of the capacitor arrays are driven to Vrefp or
Vref,N.
At this time,
differential outputs are generated by the DAC. Consequently, it is critical that the
top-plate sampling switch be closed, or charge will be exchanged between the positive
and negative arrays, corrupting the input sample.
Since the input switches and
the sampling switch are overdriven by relatively slow charge-pumps (described in
Section 5.5), their turn-off time is difficult to predict.
To ensure proper timing,
the BCYCLEN and BCYCLEN signals are qualified, as shown in Figure 5-4, by
buffered versions of the bootstrapped sample signals. This guarantees that bit-cycling
will not begin until the sampling switch is completely off.
BCYCL
BCYCLEN
SMPL_DLY----
SMPLDYBCYCLEN
Figure 5-4: Qualification of BCYCLEN and BCYCLEN signals with delayed sampling signals.
Input Switches
As mentioned, the NMOS of each input switch in the switch matrices is overdriven
to ensure the resistance of the CMOS transmission gate is not excessive. Specifically,
sufficient settling time must be ensured, during the sampling phase, for analog inputs
near mid-rail. The time-constant associated with the sample-and-hold can be estimated by considering the half circuit consisting of one CMOS input sampling switch,
one of the differential capacitor arrays, and half of the top-plate sampling switch.
For the used geometries, the worst case resistance of each input switch is 6.5kQ,
while, at the expected common-voltage (500mV), the resistance of the top-plate sampling switch is 4.6kQ. Although, each capacitor in the array has an associated timeconstant, a conservative analysis assumes that the entire array (which imposes a load
of 7pF) is charged by a single input switch. This results in a time-constant,
Tsmgp,
of
approximately 62ns. For 12 bit accuracy, a settling of at least 9 time-constants is re-
79
quired. Consequently, 1-1 clock cycles of a 2MHz clock are sufficient for the sampling
period. The entire array, with distributed time-constants, was simulated to confirm
this result.
In addition to settling time considerations, symmetry in the input switches is
critical to minimizing charge injection errors.
As mentioned above, keeping these
switches "on" helps match the load impedance on either side of the top-plate sampling
switch.
This matching is further preserved by sizing the PMOS, and overdriven
NMOS, such that the non-linear resistance of the input transmission gate is symmetric
about the input common-mode voltage. The equivalent resistance is shown in Figure
5-5, for the used geometries and gate voltages; the typical process corner has been used
for this simulation. Here, the difference in resistance is less than 300Q (approximately
10%) for differential input voltages centered around 500mV.
Input Switch Resistance VS Input Voltage
4000
3500-
3000 .0
(n 2500 -
-
2000-
15001
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Input Voltage (V)
Figure 5-5: Equivalent Resistance of input switch with respect to input voltage.
Finally, the input switches introduce non-linearity to the sample-and-hold process
due to their dependence on input voltage. The effect they have on degrading SNDR
depends on their precise voltage dependence. This is considered further in Chapter
80
6.
Reference Switches
The source-drain regions of the top-plate sampling switch, which is implemented using
an NMOS device, introduce parasitic PN-junctions on the critical top-plate nodes, as
shown in Figure 5-6.
VIN-
N+
VrN
Vre P
Vep
VreN
0-
Co
Co
Co
Co
Figure 5-6: Parasitic PN-junction on top-plate.
During sampling, a voltage is generated across the array capacitors. Subsequently,
after the sampling switch is opened, the impedance on the top-plate node is high,
and the bottom plate is driven to Vref,N or Vref,p. As a result, top-plate voltages
beyond the rails are possible.
Specifically, when the MSB is bit-cycled, following
the sampling phase, the voltage on one of the top-plate nodes can undershoot below
ground, forward-biasing a PN-junction. As a result, top-plate charge can be lost,
corrupting the sampled input. To avoid this, the PMOS devices, which connect the
capacitor bottom-plates to Vref,p, have been sized much stronger than the NMOS
devices, which connect the bottom-plates to Vref,N. As a result, the top-plate voltage
never undershoots below ground, and no charge is lost.
A drawback to this approach is that the DAC outputs can spike in the wrong
direction during MSB bit-cycling before settling to the correct value. As shown in
Figure 5-6, all capacitors in the negative array (right hand side), except the largest
one, connect to Vrej,p, whereas in the positive array (left hand side), only the largest
81
capacitor connects to Vef,p. Due to the strong PMOS devices used to make the Vref,p
connections, the top-plate of the negative array initially approaches Vej,p faster than
the top-plate of the positive array, even if a negative input voltage is sampled. This
transient impulse is shown in Figure 5-7 below.
Here, during the sampling phase
a voltage near 1LSB is applied to the array. Then, at the start of MSB bit-cycling
(BCYCL1 1), the DAC's negative output (VoUT_)
is observed at the differential outputs
( 3 ,d
rises sharply, and a negative pulse
plot). Figure 5-8 shows the slow settling
during this period as the weak NMOS device, which is connected to Vef,N, finally redistributes the charge, generating an output with the correct sign. Due to bandwidth
limitations, the impulse seen here is smeared out in time through the comparator's
preamplifier chain. As a result, the comparator is subject to a near overdrive condition. Since self-timed bit-cycling (explained in Section 4.1.4) leverages latch time
borrowing, which benefits all bits except the MSB, an extra half clock cycle is given
to MSB bit-cycling so that it does not limit the ADC's performance.
Purging Switches
The purging switches short the common top-plate node to the six, separate bottomplate nodes of each capacitor array. Their implementation is shown in Figure 5-9
below. Here, a half-sized dummy switch, MN2, is used to minimize charge injection
error. It turns off slightly after the main switch so that its injected charge is not lost,
through the switches, to the bottom plate. Although, it is not strictly required, this
device does help control the common-mode output voltage of the DAC, by reducing
extraneous top-plate charge. In the structure shown, there is a single NMOS associated with the top-plate, MN1, and one for each of the bottom plates, MN3 - MN8.
This arrangement minimizes the top-plate parasitics during the conversion process,
by decoupling MN3 - MN8 from the top-plate when MN1 turns off.
82
Conversion Phase
- - -'-'-----'--
-
SAMPLE
BCYCL_11
-'
00.5 0
- -
0 -
- - - - - 4.2
4
4.4
5.2
5
4.8
4.6
DAC Ouput Voltages
1
S--
CD
I
VOUT+
'
I
OUT-
05
0
4.2
4
4.8
4.6
4.4
DAC Differential Output Voltage (VOUT+
5
-
5.2
VOUT)
0.5
CD
0) 0
-II
-
0
-0.5
4.2
4
4.4
4.6
4.8
5
5.2
Time (g s)
Figure 5-7: Waveforms showing the origin of a transient spike during MSB bit-cycling.
5.1.2
Capacitor array
As mentioned in Section 3.3, mismatch in the capacitor array is the dominant source of
low-frequency non-linearity in the ADC. Since this ADC does not employ capacitor
calibration [34], the elements must be sized and laid-out appropriately to manage
mismatch.
Additionally, during the sampling process, thermal noise can limit the
SNR of the ADC.
During the sampling phase, the sub-DAC appears as a unit element. The total
capacitance seen by the input, is the series combination of two arrays, each having
a total value of 26Co, where Co is the unit capacitance. The resulting sampled noise
83
DAC Differential Output Voltage (VOUT+ - VOUT-)
1
0.8 0.610.4
E
0.2
0
CZ
0
-0.2
-0.4
-0.6 F
-0.8
-1
4.5
4.55
4.6
4.65
4.7
Time (p. s)
Figure 5-8: Zoom-in of DAC differential output voltage as it recovers from a negative
spike to the correct positive voltage.
power is given by Equation 5.1.
2
Vno,smpl
_kT
32Co
(5.1)
This relation suggests that, with a signal of 1V amplitude, a sampling-noise limited
SNR of 74dB (12 bits) is achievable with a unit capacitance of 6.5fF. The analysis
below shows that capacitor sizing is instead limited by matching requirements.
Poly-poly capacitors have been used for the DAC arrays due to their superior
matching characteristics and stability. To determine the sizing required for sufficient
linearity, consider the static transfer characteristic of the ADC. DNL is a measure of
the deviation of code transition voltages from the ideal LSB voltage (after correcting
for gain error). In the case of a 12 bit SAR ADC, the transition voltage associated
with digital code 2047 is derived by the voltage divider shown in Figure 5-10a, where
84
TPPLT
MN2
(Half-size
dummy switch)
MNI
DDi~2 r~-
0011-
itI
rI-I
1
I-O
k
0~
k
t-
U-
-J
Figure 5-9: Implementation of purging switches.
the MSB capacitor and one unit capacitor are connected to
Vref,N,
and the remaining
capacitors are connected to Ve,,p. The next transition voltage, associated with digital code 2048, is derived by the voltage divider shown in Figure 5-10b, where all the
switchable capacitors are reversed. The worst mismatch scenario is where the MSB
capacitor has a positive or negative error bias with respect to the remaining capacitors. Applying these considerations to the matching characteristics of the technology
(provided by the vendor), a unit capacitance of 100fF was determined to be sufficient.
Vref P
2N-2CO
. .
2-1c0±0
.
T
-C:
2C0
Vref P
C0O
-2
T
2N2 OT
**
.
2C 0
oT
COT COT
C0
Vref,N
Vref,N
Code 2047
(a)
Code 2048
(b)
C0
Figure 5-10: Capacitor mismatch leading to largest DNL.
In addition to sizing, proper layout techniques are essential to ensuring the best
matching of capacitive elements. Common-centroid arrangement has been used to
85
minimize the effects of linear process gradients, and dummy devices have been employed to ensure all elements are subject to similar etching environments. Further, a
metal, electrostatic shield is used above the poly-poly capacitors to isolate their topplate from the bottom plate routing wires [35]. Coupling between the top-plate node,
which is common to all capacitors in the array, and individual bottom plate wires
adds to the net capacitance of the associated elements. If this is not well controlled,
it can be a significant source of element mismatch. Note, the solid metal shield does
increase the parasitic capacitance to ground associated with the top-plate. However,
this does not affect the linearity of the ADC, at least in the case of the main-DAC.
Parasitics associated with the top-plate of the sub-DAC are discussed below.
Sub-DAC Transmission Compensation
Parasitic capacitance on the top-plate of the sub-DAC leads to linearity errors in the
ADC. This can be seen in Figure 5-11, where the Thevenin equivalent of the DAC
network is considered. As mentioned in Section 4.2.2, voltages generated by the subDAC,
VubDAC,
are reflected to the output through the capacitive division between the
net unit capacitor, Co, and the total main-DAC capacitance, ( 2 N _ 1)CO. In this way,
the sub-DAC interpolates between transition voltages generated by the main-DAC
array.
Vref p
VreP
1
i0
N
1) CO
(2
Cc
C0
The venin
M-1
q2'C0 Equivalent
M
AI
b,2'C 0 1
Vref,N
I2.o
(2N-1)C
0
VmainDAC
-1
CC
2 MC
CP'
VsubDAC
-LT jgo-
VrLfN
Figure 5-11: Effect of parasitic capacitance on sub-DAC top-plate.
However, as shown in Figure 5-11, parasitic capacitance on the top-plate of the
sub-DAC, has the effect of attenuating the sub-DAC output through the resulting
parasitic capacitor divider (formed by 2 mCO and Cp). The sub-DAC is, thus, subject
86
to gain error, which manifests itself as a constant compression in code transitions
within the interpolation range.
However, this appears as non-constant deviations
at the main-DAC transistion voltages, and thus contributes non-linearity. A sample
transfer charcteristic, with a 2 bit sub-DAC, is shown in Figure 5-12 below.
-
......
-
MainDAC transitions
Ideal subDAC transitions
Compressed subDAC
transitions
Max. INL-+
-
Figure 5-12: Errors in ADC transfer characteristic due to compression in sub-DAC
interpolation.
In this design, the resulting non-linearity has been minimized by adjusting the
transmission gain of the sub-DAC, which is set by the coupling capacitor, Cc. By
increasing Cc, the effective weight of the sub-DAC interpolation increases, compensating for the attenuating effects of the parasitic capacitance. The top-plate parasitics
were estimated to be approximately 200fF based on RC extraction of the layout. A
zoom-in of the resulting INL for the first 320 codes of this 12 bit converter, with no
adjustment to Cc, is plotted in Figure 5-13. Here, as expected, a saw-tooth pattern
is observed with a period equal to the sub-DAC interpolation range (i.e. 26). The
worst case INL is -1.9LSB.
Figure 5-14 shows the maximum INL expected for various values of Cc.
The
uncompensated value is 101.59fF. However, as shown, INL is minimized for a Cc of
104.76fF. The value used in this ADC was set accordingly. Note, adjusting Cc in this
manner introduces gain error since the mainDAC no-longer sees a unit capacitance
looking into the coupling capacitor. Figure 5-14 shows INL after proper gain-error
correction.
Since the method used here requires estimating the total parasitic capacitance on
87
INL VS Code
0
-0.5
Cl)
-1
z
-1.5
-2
0
50
100
150 Code 200
250
300
Figure 5-13: INL due to 200fF parasitic capacitance on top-plate of sub-DAC.
INL with subDAC Parasitics VS Coupling Capacitance
41
1
-
1
_1
106
108
110
3
Cl)
2
-J
z
1
E
E
0
-J
X -1
-2
-o30
100
102
104
Coupling Capacitance (fF)
Figure 5-14: INL after adjustment of coupling capacitance Cc.
the top-plate of the sub-DAC, it is worth evaluating the sensitivity of the INL to that
parameter.
Figure 5-15 shows, the resulting maximum INL if the actual parasitic
capacitance differs by 100fF (50%) in either direction. In this range, a maximum INL
of less than 0.8LSB is observed, so, some error in the estimated parasitic capacitance
can be tolerated.
88
INL with predicted subDAC Parasitics VS Actual parasitics
1
M 0.5C,)
z
E
0
-
E
-0.5
-1
100
150
200
250
Parasitc Capacitance Capacitance (f F)
300
Figure 5-15: INL, after Cc adjustment, resulting from errors in estimation of parasitic
capacitance.
Edge Effect Minimization
As mentioned, an array of dummy capacitors are used around the active elements to
ensure a uniform etch environment. The top and bottom plates of the dummy elements are grounded. A conventional layout of this sort would look like the array shown
in Figure 5-16a [27][35]. Here, the array has a total of six binary weighted capacitors,
Co
-
C 5 (where C 5 = 2 5CO), in an interleaved and common-centroid arrangement.
However, the conventional common-centroid array suffers from non-linearities due
to the parasitic coupling between the bottom-plates of the poly-poly capacitors and
the top-plates of neighboring elements. This is shown in Figure 5-17, where CP 1 to Cp3
all cause coupling to the common top-plate of the array, increasing the net capacitance
of the actual element. CP4 , however, causes coupling to the top-plate of a grounded
dummy device, and does not effect the net capacitance of the element. Thus, since
active elements on the outside edge of the array do not experience the additional,
parasitic increase in their capacitance, they are subject to a source of mismatch.
Figure 5-16b shows our layout approach which was used in this design. It attempts
to equalize the ratio of outside edges to capacitance for the largest capacitors. It is
89
Dlimnty A ray
D mrhy A ray:
C5
04
C5
C4 :
C5
C4
C5 :
,
4
1
d52
---- q3
02
1
0
1
2
Ci
C3J
[iC
. ..
1C11C4Cd
I li
5
05
04
05 1
1:
Dummoy Array:
j
iC5 :
IC4
C4
C5
_5
Dumm y Array
(a)
(b)
Figure 5-16: Capacitor array layout (a)Conventional common-centroid (b)Equal-edge
ratio common-centroid.
critical to focus on the largest capacitors, since their errors have the most impact on
the linearity of the ADC. In this case, C5, C4 , and C3 are subject to 18, 10, and 4
outside edges, respectively; the ratios of
1, and
7 outside edges to capacitance are 18,
32' 16'
. The corresponding ratios in the conventional case
(24, 4,
32t16d
and 1)
are not as well
8
matched.
Dummy
Elements~Gun
.P
.
.
--
Ground
r-Top-Plate
Active
Elements
Figure 5-17: Bottom-plate to top-plate and dummy array coupling in poly-poly capacitor arrays.
90
5.2
Comparator Circuit Design
The comparator auto-zeroing strategy was introduced in Section 4.2.1. As shown in
Figure 5-18a, the first two stages of the 12-bit preamplifier cascade are auto-zeroed
at a high impedance node. By design, the optimal input, and output, common-mode
voltages are equal to mid-rail. Consequently, instead of active biasing, an initial phase
to purge the charge on the capacitors is all that is required. Note, however, sufficient
settling, requires that the auto-zeroing switches, which are implemented using NMOS
devices, be overdriven using the charge-pump circuit. The final preamplifier, stage,
which drives the latch, must have an output common-mode voltage slightly less than
mid-rail. Consequently, it is auto-zeroed at the required bias voltage, as shown in
Figure 5-18b. Generation of this bias point is considered in Section 5.2.2. Here, the
auto-zeroing switch is delayed with respect to the biasing switches to equalize their
charge injection error. Additionally, half-sized dummy switches not shown are used.
PRG
PRG
IVCMLe!!h
I
-r
-7_
PRG
PRG
VOUr-
VIN+
V"N+
A
JAZEROAZERO
J
VOUT+
V/&.'
PRG
-EROVou-r-
(boosted and
delayed)
AF
VIN-
FAZERO
AZEROA
> VOUT+
---
PRG
AZEROj
71
-7-
FAZERO
VCMW~th
PRG
PRG
(b)
(a)
Figure 5-18: Implementation of auto-zeroing switches (a)First and second stage of
12-bit cascade (b)Last stage (only stage for 8-bit path).
The remainder of this section discusses the design details associated with the
preamplifiers and offset calibrating latch.
91
5.2.1
Preamplifers
The preamplifier circuit is shown in Figure 5-19. This topology allows for a compact
layout compared to a resistively loaded differential amplifier, and it achieves a good
balance of offset and gain characteristics. Specifically, the VGS of the diode connected
loads limits the output swing, easing overdrive recovery. Despite the reduced output
range, however, offsets (due to 3- device mismatch) do not degrade the gain severely,
as in the case of a current source loaded differential amplifier.
VDD
SLEEP
P3
MP1
MP2
DVOUT+
VOUT-VIN+ =_
SLEEP
MN4
MN2
MN1
VtaiioJ
MN3
VIN-
SLEEP]
MN5
Figure 5-19: Preamplifier circuit.
In Figure 5-19, the input devices, MN1-2, are biased in weak-inversion to maximize
gm at the given current level. The load devices are biased in strong-inversion such
that the gain of the stage is between 3 and 4. The devices MP3 and MN4-5 facilitate
sample-rate scaling, by performing power gating, such that the preamplifiers shut off
between conversions. Additional design details are considered below.
Noise Considerations
The preamplifiers are central to determining the actual precision achieved by the
ADC. Excessive flicker and thermal noise can exceed the quantization noise, limiting
the overall dynamic range. Auto-zeroing acts as a high-pass filter [29], and is effective
at managing flicker noise.
Here, design constraints imposed by thermal noise are
92
considered.
The noise contributions of the diode connected loads, MP1-2, appear directly at
the outputs, and are attenuated by the square of the amplifier's gain, when input
referred. To simplify this analysis, the total noise will be estimated by considering
the weak-inversion input devices, MN1-2. Their combined input referred noise power
is given by Equation 5.2.
v2
= 2
(f2nkT
(5.2)
gml,2
The integrated noise depends on the amplifier's bandwidth, which is set by the output
resistance, Rose, and load capacitance, CL1. Alternatively, Rest can be expressed in
terms of the amplifier's gain, A0 , giving the following expression.
V2. -ni
nkT
AOCLl
(5.3)
From Equation 5.3, the load capacitance required to achieve 74dB of SNR (i.e. 12
bits), is 104fF. The actual value used in this design has been set more conservatively
to account for the accumulation of other errors.
Settling Time
The time-constant associated with the first preamplifier is set by its R,t and the load
capacitance, CL1, determined from the noise analysis above. Since subsequent stages
are not noise limited, their load capacitance is determined by the fixed parasitics
associated with their outputs. Accordingly, RC extraction of the layout provides a
reasonable estimate for these output capacitance, CL2 and CL3, associated with each
of the next two stages. The output resistance of the amplifiers is, then, constrained
by the settling-time required of the cascade.
Specifically, the overdrive case, where the preamplifiers are driven strongly in one
direction, and then weakly in the other direction is considered. The corresponding
waveforms are shown in Figure 5-20.
Although the full-rail swing of VDD is not
possible due to saturation in the amplifier, it can be used to analyze the worst-case
overdrive, where the output of the cascade must recover from +1V. Assuming a
93
subsequent output swing of 5mV is required to ensure the latch resolves correctly, the
settling requirements of the cascade can be derived. If each of the three preamplifiers
has a gain of 3, a -L-2
input voltage (-240pV) will ultimately settle to -6.75mV at
the output. The number of time-constants, N, required to exceed the required 5mV
swing is given by Equation 5.4.
: AC a
Pre-amp output
DAC output
IV
OV -- mlf
------to---- c
t
-240piV
u
-5 V
p
fl------o
-6.75mV
during-bit-
Figure 5-20: DAC and preamplifier waveforms during overdrive recovery.
N =-ln
1 -
1.00675)
=.0
-6.35
(5.4)
The preamplifiers are allowed to consume most of the clock period during bitcycling, since the digital logic and DAC impose very little delay and settling time.
As mentioned in Section 4.1.4, the latch resolves quickly during overdrive conditions,
allowing the preamplifiers to borrow a significant amount of time to recover.
In
this design, to ensure some timing margin, approximately 350ns, of the 500ns clock
period, have been allocated to the preamplifiers to recover from overdrive. Assuming
the preamplifier stages are identical, their output resistance, R., is constrained by
the overdrive recovery time and the settling requirements. This is shown in Equation
5.5, where the method of zero-value time-constants has been applied.
NRot(CL +0 CL2 + CL3) = 350ns
(5.5)
The maximum output resistance is derived using CL1, CL2, CL3, and N from above.
Accordingly, for a stage gain of 3-4, the minimum GM of each amplifier can be derived,
establishing the power consumption of the cascade.
94
Bias Current Optimization
The above result was derived under the assumption that the GM's and R0 st's of all
stages are equal. Since the time-constant of the first stage, which is loaded by the
largest noise limiting capacitor, likely dominates the delay of the cascade, reducing its
Rout can benefit overall performance. Specifically, reducing the overall time-constant,
Ttot, while keeping the total power constant requires increasing the GM of an earlier
stage, so that its Rout may be reduced, while decreasing the GM of a later stage.
Essentially, this corresponds to overall power-delay optimization, where the power is
constant, an the delay is minimized. In the case of the three-stage cascade, consider
increasing the transconductance of the first stage to Gm + aGM, and reducing the
transconductance of the third stage to Gm - aGM. The resulting change in timeconstant is given by Equation 5.6.
A-tot =
CLRot(G
Gm +aGm
1) + CL3 Rout (
G
- aGM
-
1)
(5.6)
The percentage change in the overall time-constant is plotted in Figure 5-21 for the
CL1, CL3,
and Rout values of this design. As shown, the time-constant is minimized
for a equal to 0.4. Although this optimization does not give the global minimum, it is
a tractable approach and gives a result that is practically as close. The preamplifier
bias currents are, thus, set accordingly.
Biasing Circuit
Figure 5-22 shows the biasing source employed to generate the preamplifier tail currents [36]. Here, MN1-2 are in weak-inversion, and MP1-2 are in strong-inversion to
improve the matching of the mirror. The current setting resistor is off-chip so that
the bias currents may be manually adjusted during testing. However, the required resistance is approximately 40kQ, which is amenable to integration if desired. Like the
preamplifiers, the biasing source is power gated so that it may be turned-off between
conversions. Additionally, during testing, the entire source can be disabled, to allow
an external biasing option through MP4. Finally, although it is likely not needed, a
95
Percentage Change in Time-Constant VS Changes in
II
:n
II
1510-
0
-~0
0
o
-5-10-15-20
0
0.2
0.4
0.6
0.8
1
Figure 5-21: Change in cascade time-constant with respect to fractional changes in
Gm.
start-up device, MN3, has been used in this design. Since the non-zero, equilibrium
current is quite low (-1pA), the difference in the leakage currents of MN1-2 (due to
their sizing ratio) should force the circuit to start up by itself.
5.2.2
Offset-Calibrating Latch
A simplified schematic of the offset calibrating latch is shown in Figure 5-23 below.
Here, MP1-MP2 form a regenerative load, MN1-MN2 form the input pair, and MN3MN4 form tail biasing sources, whose drains can be isolated. As described below,
this allows the differential structure (composed of MN1-MN4) to be configured as two
separate voltage-follower amplifiers. The remaining devices facilitate the calibration
operations.
Complete operation of this circuit occurs over two phases: an auto-zeroing phase
and a reset-resolve phase. The auto-zeroing phase coincides with auto-zeroing of the
preamplifiers and is used to calibrate the relative offsets of the voltage-followers. The
reset-resolve phase coincides with bit-cycling and allows successive latch decisions to
96
Off-chip
bias
VDD
E
ENABLE
MP4
SLCPMP3
MP1
MP2
N3
MN1
-Tail bias
MN2
Off-chip resistor
(40kn)
Figure 5-22: Preamplifier biasing source.
be made while enforcing offset cancelation.
Auto-Zero Phase
Here, operation of the latch during the auto-zeroing phase is considered. As mentioned, MN1-MN4 can be configured as voltage followers, thereby reflecting incremental differences in the input voltages to the source nodes of MN1-2.
The purpose of
the auto-zeroing phase is to eliminate the differential offset in these source voltages.
Figure 5-24 shows the relevant circuit elements. The gray devices are turned off by
driving the appropriate values onto their gates (through switches not shown). During
this time, it assumed that zero differential voltage, with the proper common-mode
value, is applied to the inputs. This is achieved using the biasing circuit described
later.
Initially, switches
Scscd, SdiffMd,
and Sfb are all closed. This biases MP7-8 and
MN3-4 while forcing the source voltages of MN1-MN2 (i.e. the follower outputs) to be
equal. If SdiffMd were open, the difference in the source voltages would be determined
by the Vcs's of MN 1-2, which depend on the devices' drain currents. Offsets in MN3-4
and MP7-8 would cause a difference in the drain currents, and offsets in MN1-2 would
97
V8
MP7
MPMP
mplk!
MP
O
- VOUr-
MP2
VOUr.C
MP4
MPS
MP
RSLV
VIN+1->
T
! --
MN1
MN2
1MN3
MN4
[-<VIN-
T
Figure 5-23: Simplified schematic of complete offset-calibrating latch.
cause VGS shifts. In this case, however, current flows through SdiffMd to equalize the
source voltages.
During the second part of the auto-zero phase, Scd and SdiffMd are opened.
Firstly, if the feedback connection through Sfb is ignored, this dramatically increases
the impedance at the drain of MN1-2 due to the resulting NMOS and PMOS cascodes.
Secondly, the current path through SdiffMd is eliminated, exposing all offsets by
changing the branch currents. A block diagram of the resulting structure is shown in
Figure 5-25. The feedback network is composed of a transconductor, gmn3,4, driving
the high impedance node at the drain of MN1-2,
Vhg.
This drain impedance is the
equivalent resistance, Re.. , of the parallel NMOS and PMOS cascodes. Here, the
transconductor current, ifb, is combined with the incremental offset current, i0 s, which
is caused by opening SdiffMd. The resulting current, Zer,, is multiplied by the output
resistance of the voltage-follower, Rfiiw,
"mp1,2on1,
.
which is approximately equal to ro3 ,4
The feedback loop attempts to minimize ierr and, therefore, attenuate
incremental changes in the voltage-follower outputs, Voutflwr.
98
_177
MP8
MPP7MP
7,
Vc,
F--OVd
-3r
SOc
RSLV
VN1
MN1
MN3
MN4
SdMid
|
VIN-
sd
I
soSL
Clock __
[N2
|
|
Auto-Zero, S
Sowd, SaMW
RSLV
Figure 5-24: Offset compensating latch during auto-zeroing.
Intuitively, the feedback loop can be thought of as means of enforcing drain currents in MN1-2 that are equal to those before opening SdiffMd.
Since the drain
currents determine the corresponding VGs's, the source voltages will return to their
original values. Specifically, opening SdiffMd causes incremental changes in the branch
currents. When these appear at the high-impedance drains of MN1-2, they result in
large voltage swings which are fed-back to the gates of MN3-4. Consequently, MN3-4
are rebiased so that the incremental voltage is eliminated. This requires canceling
the incremental current, returning the source voltages to their original values.
The calibration loop may also be analyzed using a small-signal circuit model. For
simplicity, the impedance of the PMOS cascode, composed of MP5-MP8, is assumed
to be infinite. The resulting right-half calibration circuit is shown in Figure 5-26,
where i0, represents the change in current caused by opening SdiffMd, and vca is the
incremental change in MN4's gate voltage. Once again, resulting changes in vout,flLwr
99
iOs
+
-- voutfll,
Rscd
Vhg
'err
+
If_
gmn3,4
Rmw
Figure 5-25: Block diagram of latch calibrating circuit
reflect errors in the desired calibration.
r.2
4
g2
i 0~
Vin-Vout OW
0
r04
9"
V.8,
Figure 5-26: Latch voltage-follower calibration circuit.
The following equations are derived from KCL and KVL analysis.
= VOS
of'
+ gm4vcal
VcaI = Vout,fllwr
+
(5.7)
(5.8)
Voutfllwrgm2ro2
From these, the error in the follower output voltage can be determined with respect
to iOs.
Vout,f Iwi
_=
r_4_________(__.9)
__
1 + gm4ro4 (1 +
gm 2 ro 2 )
gm4 9m 2 ro
2
(5.9)
Now, to estimate i0.,, a Thevenin equivalent of the voltage follower outputs can be
considered. Figure 5-27 shows the resulting structure, where the output impedance
is approximately equal to
1
,
if ro,
2
are large and the drain impedances are low.
Note, the drain impedances before opening Sc8 cd should be considered here. Then,
i,, can be approximated by Equation 5.10, where v, 8 is the uncalibrated, half-circuit
voltage-follower offset voltage.
100
1/gm1
Vfilwrjcd/
+
1/gm2
1OS
_
VfIrwrid+Vos
Figure 5-27: Latch voltage-follower equivalent circuit during first half of auto-zeroing
phase.
ios = gm 2 vos
(5.10)
Using Equation 5.9, the follower offset voltage, after calibration, is given by Equation
5.11, where, as shown, the uncalibrated offset is attenuated by an amount near the
intrinsic gain.
Voutfl
=
vOS
(5.11)
gm4ro2
Figure 5-28 shows the simulated waveforms observed during the auto-zeroing
phase.
Here, 3a- offset voltages have been applied to each pair of devices in the
latch circuit by placing an ideal voltage source in series with one of the gates. The
voltage sources have been applied so as to give the worst-case, overall offset.
As
shown, during the second part of this phase, when Sc.cd and Sdiff Md open, the gate
voltages of MN3-4 get re-biased such that the outputs of the voltage-followers converge. Note, at the end of this phase, the voltage-follower outputs are not exactly
equal, differing by approximately 1mV.
Reset-Resolve Phase
Here, operation of the latch during the reset-resolve phase is considered.
Figure
5-29 shows the relevant circuit elements. Once again, the gray devices are turned
off by driving the appropriate values onto their gates (through switches not shown).
Additionally, during this phase, RSLV is high, and the parallel NMOS and PMOS
devices, MN5-6 and MP5-6, effectively short their source-drain connections.
While Clock is high, the sources of MN1 and MN2 are de-coupled, and their
101
Auto-Zeroing Switches
)
0)0.5
0
> 0
3 .4
S osod'
e Sdif
S Md
- b
3.6
3.8
4
4.2
I MN3-4 Gate Voltages ,
4.4
4. 6
0.44
a)
0)0.42
0
>
0.4
-
4
-oi-oe-
3 .4
3.6
-Follower
--
3.8
4
4.2
Ouput Voltages,
-
-
4.4
4.6
,0.155
a) 0.15
-
-
t 0.145
-
I I I a
0
0.14
3 .4
-
...
3.6
3.8
4
time ([t s)
*
I
4.2
4.4
4.6
Figure 5-28: Latch circuit waveforms during the auto-zeroing phase.
voltages are determined by VIN+ - VGS,MN1 and VIN- - VGS,MN2,
respectively. Of
course, VGS,MN1 and VGS,MN2 are set by the bias currents, which were calibrated to
result in equal source voltages for zero differential inputs. To understand the behavior
of the regenerative loads, MP3-4 should initially be ignored. Since Saux and
closed, positive feedback is disabled, and the voltages generated across
Srgnrt
Crgnrtl,2
are
hold
MP1-2 at a stable bias condition for the given branch currents and device offsets.
However, at the falling clock edge, Sa
and
Srgnrt
open, and SdiffMd closes.
If
the source voltages of MN1-2 were initially equal (which only occurs for the zerodifferential input condition), the branch currents will remain unchanged, preserving
metastability in MP1-2. However, any difference in the source voltages will cause a
perturbation in the branch currents and trigger regeneration in MP1-2. Note, Sa,, is
an auxiliary switch [37], which is delayed with respect to Srgnrt, to prevent positive
feedback until the charge injection errors from the Srnt switches are equalized.
A practical problem in the circuit described above originates from the finite r's
102
VB
Crggvn
Cg1sC
tii~
Sc,
Vour+C<
->VoUTr
LiI'
Vc$~(:Q..
TN5
V N+
MP4
MP2
MP
MP3
....
....
MW
RLV
MNI
MN2
[-cVIN-
SA~
MN4
MN3
Clock~
Sx, Srgnrt
|
Saux
SdfflMd
Vo,
Vout.
RSLV
Figure 5-29: Offset compensating latch during reset-resolve phase.
of MN1-2.
Proper operation of the voltage-followers, requires that the drains of
MN1-2 be subject to a low impedance. Voltage swings on these nodes will cause
incremental changes in the portion of the branch currents passing through the devices'
r0 's as opposed to their gm generators. Consequently, their VGS's will deviate form
the calibrated values. MP3-4, which are initially diode-connected, provide a low
impedance path while the circuit stabilizes. Then, during regeneration, the diodeconnections are broken, enabling strong positive feedback.
Figure 5-30 shows the simulated waveforms observed during the reset-resolve
phase. Once again, 3a- offset voltages have been applied to each pair of devices,
in the directions resulting in worst-case overall offset. An input differential signal
of i1.5mV is successfully resolved. Note, while clock is high, the outputs are not
103
exactly equal. This is due to the offsets in MP1-4, which cause different voltages to
be generated across
Crgnrt,2-
Clock
00.5
0
>0
7.8
8
8.2
~0.414
8.4
8.6
8.8
9
Diffqrantial lnput
9.2
9.4
9.6
I
-~~
IN+
--
0)0.412
0
>
0.41
-,-,-,-,LatchOutptI
-I-
7.8
V
8
1
8.2
I
I
8.4
II
I
-
a)
8.6
8.8
Latch Output
f
9
M
9.2
a
7.8
8
8.2
9.6
I
iOUT+
-~~
00.5
0
> 0
9.4
"
-
8.4
8.6
8.8
time (g s)
9
9.2
OUT-
9.4
9.6
Figure 5-30: Latch circuit waveforms during the reset-resolve phase.
Biasing
Two bias voltages are needed within the latch circuit. The first, Vscd, is simply at
ground. MP5-6 are biased in moderate-inversion, leaving over 500mV for the VDS's
of the load devices, MP1-4 and MP7-8. Additionally, MN1-4 are all in weak-inversion
and have a VDS,sat of slightly more than 1O0mV. The branch currents (as well as the
nominal drain voltages of MN1-2 during auto-zeroing) are set by the relative sizing of
MN3-4 and MP7-8. In this implementation, branch currents of approximately 1.5pA
are used. The VGS of MN3-4 is approximately 400mV, so that MP7-8 are in stronginversion making the biasing less sensitive to supply variations. During reset-resolve,
the nominal drain voltages of MN1-2 are set by the diode loads, MP3-4.
The second bias voltage, VB is generated using the replica circuit shown in Figure
104
5-31.
Here, MP9-10, which replicate the regenerative and diode loads, are active
during the reset-resolve phase, and MP12 is active during the auto-zeroing phase.
In addition, to VB, this circuit generates the bias VCM-IN which is an appropriate
common-mode voltage for the inputs. Consequently, it is used to set the DC bias of
the last, auto-zeroed preamplifier stage.
MP10
MP9
MP12
RSLV
VCM-IN
7
MN7
MN8
Figure 5-31: Replica biasing circuit for latch.
Both the latch currents, and the biasing circuit currents, are turned off between
conversions to yield linear power savings with respect to reduced sampling rate. Although the branch currents of the replica biasing structure can be scaled back compared to those used in the active latch, there is practical limitation associated with
this approach.
Reducing the sizes of devices in the biasing circuit degrades their
matching characteristics. Since the current levels are quite low and the devices are
in weak-inversion, additional offsets can lead to complete inactivation. Consequently,
current levels have not been further reduced in the biasing circuit.
Implementation Analysis
Several implementation issues associated with the latch circuit are worth noting.
First, the only switches that introduce charge injection error are ccd and Sfb. However, since they are used to bias static nodes, large gate capacitors (Ccscd, CA
105
),
as
well as dummy switches, can be used to minimize this effect. The injection errors
from Srgnrt and S,, are equalized by the auxiliary switch Sa..
Finally, Sdiff Md, which
actually triggers the regeneration, does so by shorting two nodes. Consequently, the
possibility of false regeneration due to residual mismatch in charge injection is naturally avoided. This is a particularly beneficial feature of the latch circuit.
During the reset-resolve phase, the regenerative load is initially stabilized by
breaking the positive feedback. However, as mentioned in [28], the finite "on" resistance of the switches may not allow the positive feedback to be fully broken, resulting in instability. Care, in this regard, is particularly required for low-voltage
implementations.
Finally, the feedback structure used during auto-zeroing can also be subject to
instability if parasitics are not properly managed. After the Scscd switches are open,
each branch of the latch may be thought of as a high-gain cascode amplifier whose
output is fed-back to its input through Sfb. Although the resulting high-gain amplifier
is a single-stage structure, the branch currents are quite low, resulting in low gm's for
MN1-2. Consequently, their sources present a relatively high impedance. Excessive
parasitics on these nodes, or additional capacitances, which may be added to smoothout transient spikes, can degrade the phase margin of the amplifier. Figure 5-32 plots
the gain and phase of the amplifier for the case where no filtering capacitance has
been added and the case where 400fF of filtering capacitance has been added. As
shown, the phase margin degrades considerably in the filtered case. Note, Cfb is the
compensation capacitor in this loop. Its value has also been reduced in the filtered
case shown in Figure 5-32.
5.2.3
Latch Level Restorer
The latch circuit described above does not achieve full-swing outputs. Although, it
is possible to reach VDD, output voltages below 250mV can not be generated since
MP3-4 remain on despite regeneration. So, the level-restorer circuit, shown in Figure
5-33, is used to generate full-swing digital outputs.
Here, depending on the latch outputs, one of the PMOS input devices, MP1 or
106
Gain
20
-
M.:.............~.......
0--
No Filtering
Filtering
.
.
0. .. .. .........................................
-10
103
10
Xi
10
10
10
108
Phase
0
No Filtering
Filtering
--
-50.
-.-
-100.-
.-
-
.-
.-
phas
-150..Degraded
:margin:
-200.
103
104
10
10
Frequency (Hz)
10
10
Figure 5-32: Gain and phase of filtered and unfiltered auto-zeroing calibration circuit.
MP4, will turn on when Clock goes low. The corresponding NMOS, MN2 or MN4,
whose gate was initially discharged, will turn on. The other NMOS will, dynamically,
remain off. This circuit is robust, as it requires VLATCH+ and VLATCH- to only swing
slightly more than VTp1,4, in order to generate full-swing digital outputs. The signals
corresponding to the 8 bit and 12 bit paths are ANDed together at this point, to
drive the control signal of the SAR state machine. Waveforms showing the operation
of the level restorer circuits are given in Figure 5-34. As shown, the full rail digital
signals are derived for latch outputs of less than 400mV.
5.3
SAR Circuit Design
The SAR state machine is the digital block that controls the conversion cycle by
generating purging, auto-zeroing, sampling, and bit-cycling signals at the appropriate
times. In this, low-speed, design, the SAR imposes minimal delay with respect to the
target clock frequency. As a result, a standard cell implementation has been leveraged.
107
VL AT CH+- =-I
VDD
MP
Clock
VLATCH-
m--- 4
VL AT CH-
MP3
VDD
Cockf
VLATCH+
MP2
6
-UTMP5
C7ok?:DOUT
DOUT
C1ok
MNI
MN2
MN3
MN4
Figure 5-33: Latch level restoring circuit.
Clock
a>
>0.5
0
8
8.5
--
9
9.5
Latch Outputs
'
---
%
-
0.5
0
LATCH+
LATCH-
t
-
9.5
10
0
8
8.5
9
Level Restorer Outputs
-OUT
-
=-
a
0.
>
0
8
8.5
time ( t s)
9
9.5
10
Figure 5-34: Latch level restorer waveforms.
The core state logic, in this SAR, is a simple shift register, which makes up the
top row of flip-flops shown in Figure 5-35. The conversion is initiated by an activehigh pulse, CNVRT, which sets the first flip-flop in the shift register and resets the
remaining flip-flops (the reset of lower flip-flops is not shown). In all cases, the flipflops are set or reset asynchronously, as the clock is internally gated (as described
108
in Section 5.4) to minimize power consumption between conversions. Following the
CNVRT pulse, however, the clock is enabled, and the SRx signals of the shift register
are successively asserted, enabling their associated logic.
CNVRT
PREB
a_
CLR
CLR
CR1
SRIO
S9
PREB
PREB
SR8
_
CLOCK
MTSTBL
CMPRTRDONE
CMPRTR
OB
PREB
OB
'
r
0B
-
r
o
toco
r
0
Figure 5-35: SAR state machine circuit.
The initial signals, enforcing the purging, auto-zeroing, sampling, and MSB bitcycling phases are synchronous, and are derived in a straight-forward manner from
the associated shift register signal. The remaining bit-cycling signals are self-timed
using the comparator outputs. The corresponding logic, which must be able to recover
from comparator metastability, is described below. Additionally, the logic to enable
resolution scaling is also described below.
Self-Timing Logic
The comparator evaluates while CLOCK is low. Self-timed bit-cycling allows the
subsequent bit phase to begin immediately after a decision is made. Consequently,
the shift register flip-flops, associated with bit-cycling, are triggered on the negative
clock edge.
The comparator provides pseudo-complementary outputs, which are both precharged high, in the level-restorers, before the latch resolves. A comparator decision
109
can then be detected by simply NAND'ing the outputs. This derives CMPRTRDONE,
which is gated with the SRx signals to assert preset on the appropriate bit-cycling
flip-flop. The rising BCYCLx signal is used to clock the previous bit-cycling flipflop, which, accordingly, stores at "1" or "0" depending on the comparator decision.
Comparator Metastabiliy Detector
However, in the scheme described above, if the comparator fails to make a decision,
the entire bit-cycling process is stalled. To recover from such metastability conditions,
the circuit in Figure 5-36a is used. Here, the CMPRTR-DONE signal is registered
at the rising-edge of CLOCK. At this point, a comparator decision should have
been made. If it has not, however, the MTSTBL signal gets asserted and enforces
bit-cycling.
MTSTBL_RST
CNVRT
CMPRTROUT
TSTBL_RST
PREB
MPRTRDON
CMPRTROUT
R11
0
0B
MTSTBL
10
YCL_11
-CYCL_10
TSTBL
TSTBL
*
SR9
CYCL_9
TSTBL
CLOCK
(a)
(b)
Figure 5-36: Metastability recovery circuits (a)Metastability detector (b)Metastbility
reset.
Since metastability is detected at the rising clock edge, but bit-cycling logic is
enabled by falling-edge SRx signals, MTSTBL must be reset before erroneously
affecting the next bit. This is done by asynchronously asserting the flip-flop's clear
signal using the logic shown in Figure 5-36b. Here, the BCYCLEV signal, which
was just asserted by MTSTBL, propagates back to generate the reset.
Resolution and Sampling Rate Scaling
Scaling the ADC resolution from 12 bits to 8 bits requires bypassing the last four
shift register flip-flops. Figure 5-37 shows the logic associated with the last flip-flop
in the shift register, which is used to enable assertion of the SLEEP (once again,
110
reset of the lower flip-flop is not shown). The SLEEP signal indicates the end of
the conversion cycle. It is used internally to power gates all of the active circuitry as
well as to gate the ADC clock. Similar logic is used to bypass one of the shift register
flip-flops associated with auto-zeroing, since only one preamplifier exists in the 8 bit
comparator path.
CNVRT
12BITMD
CLR
00
S9R4
SRO
CLOCK
MTSTBL
CMPRTR DONE
PREB
0
SLEEP
OB-
Figure 5-37: Circuitry supporting resolution scaling. SLEEP signal is used to enforce
power-gating.
5.4
Clock Manager
To minimize the power consumed between ADC conversions, the internal clock signal
is gated as shown in Figure 5-38. The inverters, driving CLOCK and CLOCK have
been sized with cosideration to the internal clock load.
CLOCK
SLEEPCLOCK
CLOCKEXT-
Figure 5-38: Internal clock gating circuitry.
111
5.5
Charge Pump and Voltage Multiplier
To increase the overdrive of NMOS analog switches, the charge pump circuit shown
in Figure 5-39 is used. An unloaded output voltage of
2
VDD
-
VTN1
is generated.
With loading, the output level depends on the relative size of Cpump and the load
capacitance.
Consequently, Cpump has been sized differently for the auto-zeroing
switch drivers in the comparator and the input switch drivers in the DAC.
VDO
MNI
MPI
CBYPA-
BAKBIAS
BYPASS
:OUT
MN2
IN
Figure 5-39: Charge pump circuit to generate voltages beyond VDD
In the implementation shown, the junction implants of the PMOS device can be
forward biased if the voltage of its bulk remains at VDD. To avoid this, a separate
charge pump can be used to derive the bulk voltage, BAKBIAS [38. In this design,
the Dickson voltage multiplier, shown in Figure 5-40, is used [39]. Since it uses only
NMOS devices, its junctions are not at risk of being forward biased. The steady-state
output voltage of this circuit is given by Equation 5.12.
BAKBIAS
= VDD
+
VDD
Cboost
-
3
VTN
CbSt + Ccntri
Thus the desired bulk bias is achieved by setting the ratio of Cboost to
approximately 1.
(5.12)
Ccftri
to
Figure 5-41 shows a simulation of this circuit during startup.
As shown, BAKBIAS is continually pumped higher each clock cycle, reaching a
steady value beyond VDD (1v).
112
MNI
MN3
MN2
CLOCK
CLOCK=
CLOCKG
CbO.l,.
cc.I
..
Cto(Jt
BAKBIAS
cenf
Figure 5-40: NMOS Dickson voltage multiplier [39].
Clock Signals
1
-
-
-
-
-
- '- -'
'---
CLK
LR -
a>
0)0.5
I -- 1
0
)
- - -U
2
-. -
- - -J
4
-,
- -U
6
8
6
8
0
BAKBIAS
,1.5
)
1
-F
0.5
0
0
2
4
time (ji s)
Figure 5-41: Voltage muliplier simulation.
113
10
Chapter 6
Testing and Characterization
The low-power ADC was fabricated in a 0.18prm CMOS process. We acknowledge
Nation Semiconductor for providing the fabrication services.
a 0.5mm pitch TQFP package.
Figure 6-1.
It was packaged in
A micrograph of the entire test chip is shown in
It includes two complete ADCs, as well as a separate layout of the
offset calibrating latch. The first ADC, is the full design described in this document.
The second ADC uses a standard, sense-amplifier based latch [40], instead of the
experimental one. The additional latch layout allows controlled characterization of
offset.
Including pads, the test chip occupies an area of 2mm x 2mm. Figure 6-2
shows an annotated micrograph of the full ADC with the offset calibrating latch. It
occupies a total area of 900pm x 700pim.
6.1
Test Setup
Figure 6-3 shows the test setup and equipment used to characterize the ADC. The
Audio Precision System One signal source was used to generate an ultra low-distortion
sine wave [41]. It provides fully-balanced, differential outputs, which can be floated
and set to the desired common-mode voltage. A Tektronix PS280 power supply is
used for this purpose. A Tektronix TLA7NA3 Logic Analyzer module samples the
digital output of the ADC, and a Tektronix TLA7PG2 generates the clock signal and
conversion pulse. An additional PS280 power supply is used to power the ADC I/O
115
Figure 6-1: Micrograph of fabricated test chip.
A k
F
900um
Figure 6-2: Micrograph of full ADC with offset calibrating latch.
116
drivers. Finally, a Keithley 6517A electrometer is used to power the ADC core as
well as take accurate current measurements.
Tektronix
PS280
Keithley
6517A
0 Power
Core ?ower
Audio Precision
System One
Analog
Input
J
_L
r--]_
ADC
(under test)
Tektronix
STLA7NA3
InputDigital
__pu
Common-Mode
Convert Pulse
CTektronix
C k
Tektronix
PS280
TLA 7PG2
Tektronix TLA715
(mainframe)
Figure 6-3: ADC Test setup.
A custom printed-circuit board was designed and fabricated to facilitate testing
the ADC. The four layer PCB uses two signal layers and two power/ground layers
to make the board connections. On-board switches allow configuration of the ADC's
resolution, and on-board potentiometers and biasing circuits allow adjustment of bias
currents and voltages. A picture of the test board is shown in Figure 6-4.
The complete ADC, with offset canceling latch, is functional at the target sampling
rate. The biasing resistors require no adjustment beyond their expected, simulated
values. In 12 bit mode, the circuit operates with a 2MHz clock, and, in 8 bit mode,
it operates with a 4MHz clock, allowing a sampling rate of up to 200kS/s. The entire
ADC operates from a 1V supply, as expected. Note, these parameters will be adjusted
to characterize the maximum and optimum performance points of the ADC beyond
expectations.
117
Figure 6-4: ADC Test PCB photograph.
6.2
Characterization
This section describes the specific tests performed on the ADC. Additionally, results
are presented along with some brief analysis. All of the tests used here are prescribed
by the IEEE Standard 1241, Test Methods for Analog-to-Digital Converters [42].
6.2.1
Static Linearity
A variety of tests exist for extracting the static transfer characteristics of an ADC.
The code density test involves deriving the digital output code histogram associated
with a low-frequency sinusoidal input [43]. Since sine functions are well characterized
mathematically, the ideal code density histogram is well known and can be compared
with that observed. Thus, linearity errors can be quantified.
The code density test was conducted using a full-swing, differential sinusoidal
input with amplitude of 1V. The sampling rate of the ADC was 1OOkS/s, and the
118
frequency of the input signal was 111.381Hz. To test the 12 bit mode, approximately
four million samples were taken (30 records each with a size of 131,072). Figure 6-5
shows the resulting code density histogram. Here, no bins are empty, suggesting a
very low likely-hood for missing codes. Further, the offset of the ADC, determined
using the method prescribed in [421, is approximately 830p-V.
X 104
12
Code Density histogram
108 -2
IL
6 -
04
0420
0
1000
2000
3000
4000
Code
Figure 6-5: Code density histogram of ADC in 12 bit mode.
From the code density histogram, the INL and DNL can be determined. Figure
6-6 shows these with respect to the output code. The maximum INL is +0.68LSB/0.56LSB, while the maximum DNL is +0.58LSB/-0.66LSB. The INL plot has a sawtooth characteristic with a period of 64 (6 bits). This is a manifestation of imperfect
sub-DAC interpolation, and is likely caused by a small error in the prediction of its
top-plate parasitic capacitance (as described in Section 5.1.2). The peak value of the
saw-tooth, however, is only 0.2LSB, confirming that compensation of the sub-DAC
transmission gain was quite effective. Abrupt changes in the INL are also observed
at the 1024 and 3072 code transitions, indicating mismatch in the MSB/2 capacitor
(i.e. C4 in Figure 5-16b).
Recall that the largest capacitors were arranged in an
attempt to equalize their edge-coupling to active-capacitance ratio. This ratio for
119
C4, although much improved compared to the conventional layout, is most poorly
matched. As a result, small corresponding INL changes are observed. Nonetheless,
the static linearity of the ADC is quite good, well within t1LSB.
DNL
1
0.5
M
C/)
_j
L ALA~jW'
-.
.Ak
-N
0
-0.5
-1
0
500
1000
1500
2000
2500
3000
3500
4000
2500
3000
3500
4000
Code
INL
1
0.51
mj
0
-0.5
-1
0
500
1000
1500
2000
Code
Figure 6-6: DNL and INL of ADC in 12 bit mode.
Figure 6-7 shows the histogram corresponding to the ADC in 8 bit mode, and
Figure 6-8 shows the DNL and INL. Here, the sampling rate is 200kS/s, and the
input frequency is, once again, set to 111.381Hz. The maximum INL is
+0.19LSB/-
0.16LSB, while the maximum DNL is +0.16LSB/-0.14LSB
6.2.2
Dynamic Noise and Linearity
The dynamic performance of the ADC is also characterized by means of tone testing. The signal-to-noise-plus-distortion ratio (SNDR) is derived by varying the input
frequency from DC to one-half the sampling rate, so that the Nyquist performance
120
6
x 10 4
Code Density histogram
5
c4
C)
=3
2
_-.2h6,16010)
1
0
0
50
100
Codi
150
200
250
Figure 6-7: Code density histogram of ADC in 8 bit mode.
DNL
1
0.5
M
C/)
-j
0
-0.5
-1
)
50
100 Code 150
0.5
Cl)
_j
250
INL
1
M
200
l
il''IIl) 1111lll11111111il W
-i
0
-0.5
-1
0
50
100
150
200
250
Code
Figure 6-8: DNL and INL of ADC in 8 bit mode.
of the ADC may be evaluated. The resulting output, at each frequency, is used to
derive a least-squares fit to an ideal sinusoid. The RMS error between the output
and the fit quantifies the noise and distortion [42]. The resulting SNDR can be used,
121
as in Equation 6.1, to express the effective number of bits (ENOB) achieved by the
ADC.
ENOB
=
SNDR(dB) - 1.76
6.02
(6.1)
Figure 6-9 shows the ENOB of this ADC with respect to the input frequency. In 12
bit mode, the ADC samples at 1OOkS/s and achieves an ENOB of 10.55 bits (65.3dB
SNDR) operating at its Nyquist rate. The SNDR is fairly consistent over the input
frequency range. In the 8 bit mode, the ADC samples at 200kS/s and achieves an
ENOB of 7.96 bits (49.8dB SNDR) at its Nyquist rate.
ENOB VS Input Frequency
12
EU
U
*
-U- 12B Mode
8B Mode
~n
10
84
En0
z
6
w
4
2
0
0
-
-
-
-
20
40
60
80
100
Input Frequency (kHz)
Figure 6-9: ENOB versus input frequency for the ADC in 12 bit mode and 8 bit
mode.
In 8 bit mode, the accuracy of the ADC is nearly ideal. The loss of precision in 12
bit mode can be analyzed with the aide of an FFT. Figure 6-10 shows an FFT of the
ADC output for an input tone of frequency 47.3kHz, which is near half the sampling
rate. The
3 rd
5 th,
and 7 th harmonics are all visible. From the plot, the spurious-free
dynamic range (SFDR) is 71dB.
The combined power of the harmonics in Figure 6-10 is approximately -70.4dB
122
FFT
0-20
-40-
-
-603rd Harmonic (-71dB)
-80-
5th Harmonic (-80dB)
7th Harmonic (-89dB)
-100
-120
0
10
20
40
30
50
Frequency (kHz)
Figure 6-10: FFT of ADC output with 47.3kHz input tone.
with respect to the fundamental (i.e. -10logio(10 1
+10 1 -0 + 10
)). This suggests
that a modest portion of the observed degradation in SNDR is due to harmonic
distortion. Since no even-order harmonics are prominent, the source of the distortion
must effect the positive and negative signal paths similarly. Thus, mismatch in the
DAC capacitors, which is uncorrelated in the positive and negative arrays, is not a
likely source. Further, good matching of the DAC capacitors was confirmed by the
INL and DNL tests, and it is not dependant on input frequency. The most likely
source is the non-linearity in the resistance of the CMOS input switch. In simulation,
the resulting power of the distortion introduced by the sample-and-hold circuit is
-69dB with respect to the fundamental. This was measured by a applying a 50kHz
input signal to the distributed circuit consisting of six input switches and six binary
weighted capacitors. An ideal sinusoid was fit to the output voltage, and the meansquared power of the error was determined.
123
6.3
Power Consumption
At the highest 12 bit performance point, corresponding to 1OOkS/s, the ADC core (not
including I/O) consumes 25puW from the 1V supply. At the highest 8 bit performance
point, corresponding to 200kS/s, the ADC core consumes 39pW from the 1V supply.
The power consumption in 8 bit mode is higher than expected and is currently under
investigation. In both 12 bit and 8 bit modes, the linear power scaling with respect
to sampling rate is observed as expected. Figure 6-11 shows the power consumption
versus sampling rate, where it can be seen that the power consumption approaches
zero for very low sampling rates.
Power VS Sampling Rate
40
-E- 12B Mode
- . 8B Mode
35.
30-
Af
25
ifN
20-
o1510F
5
50
100
150
200
Sampling Rate (kS/s)
Figure 6-11: ADC power consumption with respect to sampling rate.
The power consumption in 12 bit mode matches quite well with simulations. Table
6.1 shows the measured and simulated power consumption of the constituent blocks
in this design.
124
Block(s)
Simulated Power
Measured Power
SAR, Switch Matrices
8.7pW
8.4pW
Charge Pumps
0.39pW
0.38p1W
Pre-Amplifiers
4.9p1W
5.8pW
Latch
3.9pW
5.2pW
DAC
5.9pW
5.3pW
Total
23.8pW
25pW
Table 6.1: Simulated and measured power consumption of ADC blocks.
6.4
Comparision Study
The power consumption of an ADC may be normalized by its effective dynamic
range and speed, to derive a figure-of-merit (FOM) for comparing a broad range of
implementations. The FOM commonly used is shown in Equation 6.2.
FOM =
P
2
fP2 ENOB
Here, P is the power consumption of the ADC, and
fin
(6.2)
is in input frequency at which
the ENOB is measured. For the ADC presented, the FOM is equal to 167fJ/conversion
step in the 12 bit mode. Figure 6-12 plots the FOM of previously demonstrated
implementations against their resolution. As shown, this design is the most efficient
known to the author, and, so far as Nyquist rate converters, of at least 12 bits, are
concerned, the FOM is over five times better than previous implementations.
In addition to good efficiency, this ADC achieves low absolute power consumption.
Figure 6-13 plots the power consumption of previously demonstrated SAR ADCs
against the input bandwidth they can digitize, while Figure 6-14 plots their power
consumption against resolution. Architecture comparison in Section 1.2 suggested
that SAR ADCs are able to achieve the lowest absolute power. At the 12 bit level
however, their power consumption increased faster than other architectures (namely
oversampling ADCs). As shown, the increase in power consumption of this 12 bit
design, compared with low-resolution (8 bit), micro-power solutions, is modest.
125
FOM I
x
*
Resolution
0
x AL
x~
X
xx
Ax
xA
C,,
C-
12
Flash
SAR
x Pipelined
A AE
*
o
)
x
0810-
x
A
0
L-
A
A
0
10-13L
6
8
O-*
This Work
12
14
10
16
18
Resolution (Bits)
Figure 6-12: Figure-of-merit of this ADC compared with previous implementations
(data courtesy B. Ginsburg, MIT).
126
Power of SAR ADCs VS Input Frequency
0
0
0
coo0
10-2
00
0
0
10-4
0-
0-0
This Work
0
10~6
10
104
102
108
Input Frequency (Hz)
Figure 6-13: Power consumption of SAR ADCs with respect to input frequency (data
courtesy B. Ginsburg, MIT).
Power of SAR ADCs VS Resolution
0
00
10-2
8
@
a)
10~0-
Work
0-This
10-6
[
6
8
10
12
14
16
Resolution (Bits)
Figure 6-14: Power consumption of SAR ADCs with respect to resolution (data
courtesy B. Ginsburg, MIT).
127
6.5
Summary
Table 6.2 summarizes the performance and features of the ADC.
8 Bit Mode
12 Bit Mode
Process
0.18pm CMOS, National Semiconductor
Area
900pm X 700pm
Voltage Supply
1V
Clock Frequency
4MHz
2MHz
Resolution
8 Bits
12 Bits
Maximum Sampling Rate
200kS/s
1 00kS/s
Minimum Sampling Rate
OS/s
OS/s
Power Consumption
1 9pW @ 100kS/s
25pW @ 100kS/s
SNDR (at Nyquist)
49.7dB (fin=100Hz)
65.3dB (fin=50Hz)
ENOB (at Nyquist)
7.96 Bits (fin=100Hz)
10.55 Bits (fin=50Hz)
SFDR (at Nyquist)
63.2dB (fin=100Hz)
71dB (fin=50Hz)
Table 6.2: ADC performance summary.
128
Chapter 7
Discussions and Future Work
A Nyquist rate ADC, operating from a 1V supply, was presented. The SAR architecture, which allows for a mostly passive implementation, was leveraged to achieve
micro-power operation. Additionally, the selected architecture enabled efficient power
management, allowing the power consumption to scale linearly as the sampling rate
varied between 0 and 1OOkS/s. For further power savings, 8 bit or 12 bit operating
modes could be selected dynamically.
Improvements in the efficiency of the converter were achieved by employing a variety of techniques. The low supply voltage significantly reduced the overall power
consumption of the ADC. Although 1V, 12 bit designs have previously been demonstrated [44][45], achieving a high SNDR at these voltage levels has shown be exceedingly difficult. Specifically, the low voltage imposes severe restrictions on analog
implementation. Most notably, in this design, the performance of analog switches was
degraded, amplifier gain enhancement methods (such as cascoding) were restricted,
and the dynamic range of noise-limited stages was reduced. The effect of these drawbacks was largely offset by a comparator implementation that relied on efficient regenerative amplification. To make this implementation viable, an offset calibrating
circuit was developed. Further, the power consumption of the charge redistribution
DAC was minimized by employing a fully capacitive structure that draws no static
current. The elements were sized aggressively, but within matching limitations. Layout and transmission gain compensation techniques were required to minimize the
129
ensuing sensitivity to parasitics.
The following sections analyze the benefits of the techniques applied and look
ahead to improvements that can be made to enhance the ADC subsystem further.
Many of the possibilities for future work focus on the ADC performance and features,
however, others also consider optimizations at higher system level.
7.1
Effects of Applied optimizations
Generally speaking, it's difficult to quantify the precise effect of the individual optimizations applied. Nonetheless, a rough analysis of the power improvements achieved
as a result of the specific techniques can be considered.
First, designing the ADC to operate from a 1V supply, instead of 1.8V, which is
the nominal limit for this technology, has a predictable advantage. Specifically, the
power consumption of all blocks reduces by at least a linear factor of 1.8. In the case
of the digital state machine and the charge redistribution DAC, quadratic reduction
is expected. With consideration to Table 6.1, the power consumption with a 1.8V
supply would be approximately 65pW. Although an increased supply voltage can ease
thermal noise limitations, only the first comparator preamplifier would benefit. As a
result, this estimate of power savings from reduced supply voltage is reasonable.
Second, without self-timed bit-cycling, the power consumption of the comparator
preamplifiers increases due to stringent settling requirements. As mentioned in Section 5.2.1, 350ns has been allocated for preamplifier settling. The remainder of the
clock period is consumed by logic delay, DAC settling, and latch resolution. Without
self-timed bit-cycling, the preamplifiers would be required to settle in approximately
150ns. Accordingly, the power consumption of the cascade would increase by a factor
of 350ns to 14pW.
Third, the low offset regenerative latch reduces preamplifier power consumption
by easing the linear gain requirement in the comparator. Without calibration, a latch
offset of approximately 50mV can be expected.
Since the simulated offset of the
calibrated latch used here is approximately 1.5mV (as shown in Section 5.2.2), an
130
additional gain of roughly 30 is required. This can be achieved efficiently using a
second, three stage cascade, identical to the existing preamplifiers. The additional
contribution to the preamplifier chain's time-constant is dependant on fixed parasitic
output capacitance, not noise limitations. Accordingly, the resulting total time constant is approximately 85ns, instead of 55ns in the original case. Since the number of
stages has doubled, the preamplifier power consumption increases by a factor of 28
in order to restore the previous settling characteristic. In this case, the preamplifiers
consume approximately 18paW.
The cumulative benefit of all of these techniques can be estimated. In the case
where the offset-canceling latch is replaced with linear gain stages, the increase in
preamplifier power is countered somewhat by reduced latch offset requirements. For
instance, simulations show that, at the desired speed, a non-calibrating, sense amplifier latch consumes a third the power of the offset-calibrating latch. Consequently,
preamplifier power would increase to approximately 18puW, but latch power would decrease to 1.7puW. Without self-timed bit-cycling, the preamplifier power consumption
would increase by an additional factor of 30,, to 42W. Finally, if the power supply
were increased to 1.8V, the entire ADC would consume 124pW. Other techniques,
such as sub-DAC transmission gain adjustment, which enables an aggressively sized
capacitive DAC implementation, also provide power savings in this design. Nonetheless, based on the figure-of-merit of previous work, 124pW is inline with the power
consumption expected for an ADC having the precision and speed of this design.
7.2
Future Work
This section examines further optimizations that might improve the power efficiency,
dynamic linearity, and scalability of the ADC. Additionally, the possibility of adding
post-processing capability to ADC to improve system efficiency is considered.
131
7.2.1
Digital Optimization
Although the digital standard cells were easily fast enough for this design, they did
not result in the most power efficient implementation for the SAR state machine.
Specifically, non-minimum sized devices were often used unnecessarily. Additionally,
during the conversion process transitions in the digital blocks occur fairly infrequently,
and in a highly deterministic manner. Consequently, the logic can be optimized to
ensure minimum activity.
7.2.2
Programmable On-Chip Post-Filtering
As mentioned in Section 1.1, the ADC may over-sample the input data to ease antialiasing filter requirements. This requires that the digital output be appropriately
filtered and decimated before further processing. If the ADC is not integrated with
the subsequent DSP, it is beneficial to implement the decimation filter on the ADC
chip. This will minimize the bandwidth on the heavily loaded off-chip drivers. Of
course, to maintain scalability in the effective sampling rate, the digital filter might
also be programmable
7.2.3
Resolution Scalable DAC
Section 4.2.2 discussed the challenges associated with achieving efficient scalability
in the DAC. In this design, no special techniques were employed to overcome the
parasitic loading imposed by MSB capacitors as the resolution is reduced.
A fu-
ture design might investigate de-coupling the inactive MSB capacitors using reliable,
charge-pump boosted switches.
7.2.4
Active Input Switch
Section 6.2.2 considered the distortion contributed by the sample-and-hold input
switch. Based on simulation, it was determined that the linearity of the ADC would
have benefited from some active biasing to reduce the input dependant variation in
132
its resistance. A variety of constant-VGS switch biasing techniques exist and may be
employed in future versions of this design.
133
Appendix A
ADC Fundamentals
This chapter examines fundamentals of the analog-to-digital conversion process. Since
modern ADC architectures and implementations make use of a plethora of new technologies and circuit techniques, it is worth examining the impact these have on the
signal processing characteristics of the converter.
This chapter serves to place the
goals of the design efforts pursued, during the development of this ADC, into a system context.
Section A.1 develops an ideal model of the ADC as a signal processing unit.
Section A.2 analyzes the effect of practical non-idealities on that model.
Finally,
Section A.3 examines the physical constraints associated with ADC implementation.
A.1
Linear Signal Processing
ADCs perform a highly non-linear function.
Converting a continuous-time (CT),
analog signal into a discrete-time (DT), digital representation involves quantization
and sampling. Nonetheless, it is valuable to model an ADC as a linear block, at least
partially, so that well-understood, linear signal processing theory may be applied to
data-conversion systems. The following sections develop that model. A characteristic
voltage associated with ADCs, know as the LSB voltage, will frequently be referred
to. This specifies the smallest voltage differences resolvable. Specifically, it is defined
as !,
where Vrej is the supported full-scale input voltage, and N is the number of
135
bits output by the ADC.
A.1.1
Ideal ADC Model
Figure A-1 shows an ideal model of an ADC. Here, V, represents the quantized signal,
and Vet is the final digital output. The operation of quantization is modeled by the
addition of an error signal, V,
to the input signal, V,. In this sense, all ideal ADCs
introduce error. Specifically, this error is called quantization error or quantization
noise.
Vn t.
VIN
Vout
+
X
VXAL
Impulse train
to discrete
sequence
N
n
t
t
Figure A-1: Ideal model of an ADC.
Quantization noise is explored further in the next subsection. However, notice,
due to abrupt changes at the quantization boundaries, V has a very wide bandwidth.
In particular, V, is the sum of Vi, and VqrL. While Vi may be bandlimited, V, is not.
As a result, when the Vq, portion of V, is subsequently sampled, aliased components
will fold into the baseband, defining a noise floor.
A.1.2
Quantization Noise
In general, the quantization noise signal, Vqri, is dependant on the input signal. Further, this dependence is highly non-linear. However, if the input signal varies rapidly,
with a peak value larger than an LSB voltage, some approximations may be made
regarding the quantization noise appearing at the ADC output. In particular, V ,
136
can be treated as a random variable with an equal probability density between the
values -
LSB
equal to
,
and LSB. In this case, the RMS value of the quantization error, Vqr, is
[46].
As mentioned in Chapter 6, sinusoids are typically used to characterize ADCs. In
such cases, the maximum signal-to-noise ratio (SNR) of the ADC is given by Equation
A.1, where the amplitude of the sinusoid is
SNR
ref
v'2
2V2oo(i~
201ogl0 ( 2 N ~)(A.
1)
From this relation, the SNR (in dB) is approximately equal to 6.02N + 1.76, where
N is the resolution of the ADC.
A.2
Non-Ideal ADC Model
Practical ADCs introduce error in addition to quantization noise. The main categories
of errors observed in an ADC are offset, gain-error, linearity error, and random noise.
Offset and gain error are typically easy to correct, but they may effect the SNR
slightly by degrading the full-scale input range. Linearity errors depend on the input,
and as a result are not easy to correct. In the case of sinusoidal inputs, linearity errors
manifest themselves as harmonic spurs in the frequency domain. The power of the
spurs corresponds to the distortion introduced by the ADC, and it may added to the
power of the other noise sources to quantify the signal-to-noise-plus-distortion ratio
(SNDR), which expresses the total error. Random noise, typically originating in the
constituent physical devices of analog circuits, does not manifest itself as spurious
noise. Instead, it, along with quantization noise, contributes to the noise floor of the
converter. The following subsections consider the effect of practical error sources on
the ADC model.
137
A.2.1
Effective Resolution
By applying a simple redefinition, the ideal ADC model developed earlier can account
for practical errors. In particular, all errors present in the converter, in addition to
inherent quantization, can be referenced back to the quantization noise signal. If the
actual SNDR is known, the following relation, derived from Equation A.1, can be
used to determine the effective number of bits (ENOB) of the ADC.
ENOB
=
SNDR(dB) - 1.76
6.02
(A.2)
(A2
As a result, non-idealities in a real ADC, degrade the effective resolution of the
conversion beyond the finite resolution determined by the number of output bits.
A.2.2
Random Noise in SAR ADCs
Determining the SNDR of an ADC involves deriving the mean-squared error between
its input signal (in digital representation) and its output signal. Thus, SNDR doesn't
explicitly say anything about how the measured error appears, in terms of deviation
of the actual ADC output code form the ideal digital output code.
The effect of random noise on the output code of a SAR ADC is analyzed in
[23]. Here, it is shown that, although random noise at the comparator input may be
presumed to be Gaussian, the distribution of resulting output codes is not Gaussian.
The probability of any code depends on the joint probability of each bit in that code.
For example if the five LSBs of the ideal output code are 01000 (8), an output code of
10000 (16) may be more likely than 01111 (15), since it relies on an erroneous decision
on only the 5 th bit rather than all of the 4 th to 1" bits. Although, it is true that an
error on the 5 th bit is less likely than one on the lower bits, the overall probability
may be higher. As a result, the likelihood of a particular code does not necessarily
decrease monotonically from that of the ideal code.
138
A.3
Performance Normalization
Three critical parameters associated with ADCs are sampling rate, resolution, and
power consumption.
This section examines the relationship between these, which
Section A.3.1 examines the power cost of
is rooted in inherent circuit tradeoffs.
increasing the sampling rate of an ADC. Section A.3.2 examines the power cost of
increasing resolution. Finally, Section A.3.3 uses the previous relations to rationalize
a widely used figure-of-merit (FOM) for evaluating ADCs.
A.3.1
Sampling Rate
Generally speaking, a linear power-speed relationship exists in both digital and analog
circuits. In the case of digital circuits, this can be seen in Equation A.3, where a is
the switching activity factor, CL is the load capacitance, VDD is the supply voltage,
fclk is the clock frequency, and d is the duty cycle (i.e. ratio of time the circuit
is actively processing) [24]. Often, d is combined with a and may be considered a
specific parameter associated with switching activity.
Pdig
=
aCLVJDfclkd
(A.3)
Additional forms of power consumption, namely direct-path power and leakage power,
are also present.
However, these typically represent a smaller portion of the total
power consumption. In the case of analog circuits, we can consider, as an example,
a simple single stage amplifier. Here, the required gain, A, and bandwidth, f-MB,
are given by the following expressions, where GM is the amplifier's transconductance,
and R0 ,t is the amplifier's output resistance.
A = GMRout
1
f-3B =
I
27rRout CL
139
(A.4)
(A.5)
For a simple differential pair implementation, the amplifier's Gm coincides with the
transconductance of the input devices, gm,
current,
bis,
and can be expressed in terms of bias
, electron charge, q, subthreshold slope, n, Boltzmann's constant, k,
and absolute temperature, T (note, this relationship is true in the weak-inversion
regime [18] where efficiency is highest).
gM =
Ibiasq
nkT
(A.6)
Panaq
nkTVDD
_
Combining these results, the power consumption can be expressed as in Equation
A.7, where its proportional dependence on signal frequency is shown.
Pana =
2WfnkTVDDCLAf- 3 dB
(A.7)
q
Although the results above were derived with consideration to specific examples,
they, in fact, appear quite generally. The key point to infer, is that increasing the
sampling rate of an ADC, which requires the constituent analog and digital circuits
to process faster, inflicts a proportional increase in power.
A.3.2
Resolution
Resolution quantifies the loss in precision, due to noise, whether that noise be from
quantization error or other non-idealities. Dynamic range is defined as the ratio of
maximum signal power to the minimum signal power when the SNR has degraded
to unity. Note that signal power, at unity SNR, is equal to the accumulated power
of all noise sources.
The ability of an ADC to resolve a higher number of bits is
ultimately limited by intrinsic device noise in the analog circuits.
To characterize
the power-resolution relationship in analog circuits, the effect of thermal noise, on
limiting dynamic range, can, once again, be analyzed for a simple one stage amplifier.
Equation A.8 relates dynamic range, DR, to the power of a full-swing sine wave,
and the noise power, v2.
V
2
AMP
2'
noV2
DR =
-
2V20
140
(A.8)
The value of vt2 is given by -y
, where - is the equivalent number of noise sources
in the amplifier and CL is the load capacitance. Then, by applying Equation A.4,
Equation A.6, and Equation A.5, we get the following expression.
DR =
VmpPanaq
4lrn-y(kT) 2 AVDDf- 3 dB
(A.9)
This results shows that power consumption in analog circuits is directly proportional
to dynamic range. Extrapolating to ADCs, where dynamic range is exponentially
related to resolution (namely 2 N, where N is the number of bits), power consumption
can be expected to vary exponentially with the number of bits to be resolved.
A.3.3
Figure of Merit
Based on the power-sampling rate and power-resolution relationships developed above,
the power consumption of an ADC can be normalized. The figure-of-merit (FOM),
shown in Equation A.10, was suggested to allow comparison of different ADC architectures and implementations.
FOM=
P(.
2fIN2ENOB
Here, P is the power consumption of the converter,
fIN
0
(A.10)
is the input signal frequency,
and ENOB is the effective resolution at that frequency. Note, fIN has been multiplied by two to relate the input signal frequency to the Nyquist rate. A comprehensive
survey of ADCs, using a similar metric, confirms that the linear speed, and exponential resolution, normalizations are appropriate for comparing a broad range of designs
[47].
141
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